256Mb LPSDR SDRAM
NT6SM16M16AG NT6SM8M32AK
26
R1.3 Nanya Technology, Inc., reserves the right to change products or
specifications without notices. 2009 NTC. All rights reserved.
Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit M3 as above
figure. The ordering of access within a burst is determined by the burst length, burst type, and the starting column address. The burst
length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. The burst
length is defined by bits M0-M2. Burst length options include 1, 2, 4, 8 or continuous locations are available for both the sequential
and the interleaved burst types. The continuous page burst is used in conjunction with the BURST TERMINATE command to
generate arbitrary BLs. Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the BL is effectively selected. All accesses for that burst
take place within this block, meaning that the burst will wrap when a boundary is reached. The block is uniquely selected by A1–Ai
when BL = 2, by A2–Ai when BL = 4, and by A3–Ai when BL = 8, where Ai is the most significant column address bit for a given
configuration. The remaining (least significant) address bits are used to specify the starting location within the block. The
programmed BL applies to both READ and WRITE bursts. Accesses within a given burst may be programmed to be either sequential
or interleaved via the standard mode register, and the burst type is selected via bit M3.
Burst Type and Burst Order
Burst Length Starting Column Address
A3, A2,A1,A0
Burst type = Sequential
3 = 0 Burst type = Interleaved
A3 = 1
0000 0,1 0,1
0001 1,0 1,0
0000 0,1,2,3 0,1,2,3
0001 1,2,3,0 1,0,3,2
0010 2,3,0,1 2,3,0,1
0011 3,0,1,2 3,2,1,0
0000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7
0001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6
0010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5
0011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4
0100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3
0101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2
0110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1
0111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0
Continuous n = A0~An/9/8 (location 0-y) Cn, Cn+1, Cn+2, …, Cn-1, Cn… Not supported
2
4
8
CAS Latency (CL)
The CAS Latency, or READ latency is the delay, in clock cycles, between the registration of a Read command and the availability of
the first bit of output data. The latency can be set to two or three clocks. CAS Latency is defined by bit A6~A4 in the standard mode
register. If a READ command is registered at a clock edge n, and the CAS latency is m clocks, the first data element will be valid by
clock edge n+m. The DQ start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access
times are met, the data is valid by clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with
future versions may result.