Motorola's PowerPC 603™ an d PowerPC 604™ RI SC Microprocessor: the C4/Ceramic-ball-gri d A rray Interconnect Technol ogy;
Kromann, Gerke, Huang page 1 of 9
Motorola's PowerPC 603™ and PowerPC 604™ RISC Microprocessor:
the C4/Ceramic-ball-grid Array Interconnect Technology
Gary B. Kromann, David Gerke, Wayne Huang
Advanced Packaging Technology
6501 William Cannon Dr., OE55
Semiconductor Products Sector
Austin, Texas 78735
Abstract - The Motorola PowerPC 603 and PowerPC 604
microprocessors are available in the 21mm controlled-
collapsed-chip-connection/ceramic-ball-grid-array single-
chip package (C4/CBGA). This paper will introduce the
C4/CBGA interconnect technology and address the
following: 1) the PCB land definition and board
preparation requirements, 2) the ball-grid-array to board
assembly methods, 3) the electrical design considerations,
4) the heat transfer mechanism and thermal control
options, and 5) the CBGA-to-PCB testing and reliability.
NOMENCLATURE
AF = acceleration factor
T
maxl, f = highest Ton temperature (K); lab, field
¨7l, f = Ton - Toff; lab, field
f
l, f = thermal cycling frequency; # of cycles;
lab, field must be at least 6 per day
Q
c = die power, W
Θjc = die junction-to-case resistance,°C/W
Θjl = die junction-to-lead (i.e., ball)
resistance, °C/W
Θja = die junction-to-a mbient resistance, °C/W
INTRODUCTION
PowerPC 603 and Power PC 604 RISC Micr opr ocessors
The scaleable PowerPC™ microprocessor family (Figure
1), jointly developed by Apple, IBM, and Motorola, is
being designed into high-performance cost-effective
computers (including notebooks, desktops, workstations,
and servers). The PowerPC microprocessor family ranges
from the PowerPC 601™ microprocessor to the PowerPC
620™ microprocessor. The PowerPC 603 microprocessor
is a low-power implementation of the PowerPC Reduced-
Instruction-Set-Computer (RISC) architecture. The
PowerPC 604 m icropr ocessor is a 32-bit impleme ntation of
the PowerPC architecture, and is software and bus
compatible w ith the PowerPC 601 a nd PowerPC 603
3URGXFWLRQ'DWH
603
Power Users and Business Workstations
Application Servers and Technical Workstations
Notebooks and Energy-Efficient Desktops
PowerPC 620
Microprocessor
PowerPC 601
Microprocessor
PowerPC 604 Microprocessor
PowerPC 603 Microprocessor
Figure 1. The PowerPC Microprocessor Family.
micr oproce ssors. Both the M otorola Pow erPC 603 and
PowerPC 604 microprocessors are available in the 21mm
controlled-collapsed-chip-connection/ceramic-ball-grid-
array single-chip package (C4/CBGA) (Figure 2) [1,2].
Objective
In this paper we wish to address the following topics: 1)
the C4/CBGA interconnect technology, 2) the PCB land
definition and board preparation requirements, 3) the
CBGA package-to-board assembly method, 4) the
electrical design considerations, 5) the heat transfer
mechanism s and the rma l control options, and 6) the CBGA
package-to-printed-circuit-board testing and reliability.
BACKGROUND
First-level Interconnect Technology: C4-Ceramic-Ball-
Grid Array Package
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The use of C4 die on a CBGA interconnect technology
offer s significant reduction in both the signal delay and the
microelectronics packaging volume [3-5]. Figure 2 shows
the salient features of the C4/CBGA interconnect
technology. The C4 interconnection provides both the
Chip w/C4
CBGA joint
Encapsulant
Ceramic Substrate
Heat Sink
Heat Sink Attach
Printed-circuit
Board
Figure 2. C4/Ceramic-Ball-Grid Array: Exploded Cross-
sectional Vie w with Optional Heat Sink (not
to scale).
electrical and the mechanical connections for the die to the
ceramic substrate. After the C4 solder bumps are reflowed
epoxy (encapsulant) is under-filled between the die and the
substrate. Under-fill material is commonly used on large
high-power die; however, this is not a requirem ent of the
C4 technology. The package substrate is a 21mm
multilayer-cofired ceramic for both the PowerPC 603 and
the PowerPC 604 microprocessor. The package-to-board
interconnection is by an array of orthogonal 90/10
(lead/tin) solder balls on 1.27 mm pitch. During assembly
of the C4/CBGA package to the board, the high-melt balls
do not collapse. To optimize the availability of wiring
tracks or "escapes" in the next-level interconnect (e.g.,
printed-circuit board), the signals are primarily located in
the outer rows of the package ball array; while, the
power/grounds are located in the interior region of the
package.
Second-level Interconnect Technology: Land Definition
Printed-circuit board (PCB) layouts recommended for use
have the surface mount pad diameter specified at 0.72mm
(28.5 mils) +/-0.038mm (1.5 mils). Two suggested land
patterns ( re fe rr ed to a s a "dog bone" ) ar e shown in Figur e 3
with solder-mask-defined pads and non-solder-mask-
defined pads. Due to etching of copper surface features,
0.69mm (27 m il) minim um diam et er me asur ed at the top of
the copper pad for a non-solder-mask-defined pad is
suggested. Either hot-air-solder-level coated (HASL) or
benzotriazole passivation over copper can be used
successfully due to the 1.27mm (50 mil) pitch BGA
footprint.
BOARD-LEVEL ASSEMBLY
CBGA packages can be attached to boards using standard
SMT assembly techniques. Both clean and no-clean, rosin-
based, 63/37 Sn/Pb solder pastes yield acceptable results.
The paste can be screened onto the PCBs using a 0.20mm
(8 mil) thick stencil, with 0.84mm (33 mil) apertures.
copper solder mask
a
b
Figure 3. BGA land patterns a) solder mask-defined,
b) copper-etched featur e.
Component placement can be accomplished by low-cost,
semiautomatic placement equipment. An acceptable
method can be as simple as using split screen optics and
manual placement for low volumes of packages with high
yields. A more practical method for moderate volumes
would involve programming a pick and place machine to
pick up CBGA from a standard shipping tray and place the
component into a vibratory centering fixture. Following
the centering process, a vacuum nozzle would be used to
place it onto the pre-programmed PCB site. Placement
accuracy of up to approximately 1 pad diameter will yield
acceptable results due to the self centering effects of the
molten solder.
Populated PCBs can be reflowed in a conventional
convection or infra-red (IR) furnace. During reflow profile
development, thermocouples should be attached at interior
and exterior leads to verify temperatures across a CBGA.
CBGA solde ring tempe ratures should ge nerally peak in the
range of 214 to 223°C. The ramp-up and cool-down
gradients below 2°C/second, and a dwell time above
liquidus should be mainta ined for about 75 seconds.
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ELECTRICAL CHARACTERISTICS
The total system electrical noise is influenced by the
electrical characteristics of the package, as was discussed
extensively in [6]. That is, the chip drivers, package
parasitics and loadings in the PCB impact the total
electrical noise. Electrical performance simulations that
used a 3D resistance-inductance-capacitance (RLC)
param etr ic m odeling optim ization study w er e c omplete d on
the PowerPC 603 and PowerPC 604 microprocessor
C4/CBGA package (to include the impact on printed-
circuit board routability) [7,8]. This section discusses
electrical package performance inhibitors, package
characteristics, and the system applications of the
C4/CBGA pac kage f or the Powe rP C 603 and Powe r PC 604
microprocessors.
Package Performance Inhibitors
Package parasitics in high performance systems have a
direct affect on the system performance. There are three
primary areas that negatively affect performance in a
package: impedance mismatches, crosstalk, and
simultaneously switching outputs.
Impedance mismatch and crosstalk are controlled by the
inclusion of reference planes. This addition coupled with
controlling the dielectric thickness and line width controls
the impedance and minimizes the coupling between
adjacent lines. Simultaneous Switching Noise (SSN) is a
function of three conditions: 1) the number of switching
outputs, 2) the transition time (relating to di/dt) of these
outputs, and 3) the package power/ground path inductance .
The appropriate number of package power/ground
connections is affected by the number of ground
connections to the device and the distance to the system
ground. Since the PowerPC™ 604 microprocessor uses
C4/CBGA technology, the power and ground connections
are maximized, and the electrical path from the device to
the system power and ground are kept to a minimum.
The PowerPC™ 604 microprocessor has a 64-bit external
data path. T his wide data path slow s the bus rate; however,
this is at the expe nse of incr easing the num ber of sw itching
signals. This increase causes the net current requirement
for a data path event to approximately double when
compared to a 32-bit external data path. T his doubling will
cause the current though the power/gr ound path inductance
to also double. The eff ect of doubling the c urrent will ca use
an increase in SSN.
To understand the data bus switching noise mechanism, an
earlie r version of the RISC chip w ith same number of data
bus lines was used as a test vehicle. The chip was
packaged in the 25 mm CBGA, and assembled on an
application board. A special test pattern was written to
identify the impact of: 1) the driver switching skew, 2)
linearity of the noise level as a function of the number of
switching drivers, 3) the percentage of the total noise
contribution from switching noise, and 4) the crosstalk
noise. The results have shown a linear increase in driver
switching noise; for example, the noise doubles when 64
drivers are switched versus 32. Experimental measure-
ments also showed negligible crosstalk noise from the
CBGA package.
The SSN was monitor ed on the quiet line , by switching all
the lines of the data path (active lines) except one (quiet
line). The active lines are switched from an all high state to
an all low state (data shows the falling edge to be worst
than the rising edge). The quiet line was held low.
Simulations for the PowerPC 604 microprocessor have
shown SSN value s below the noise budget of 0.7 V.
Electrical Socketing
In recent years the personal computer industry has used
sockets extensively for high performance microprocessors.
The disadvantage of using a socket for high performance
systems is the incr ease in the powe r and ground inducta nce.
Currently, two types of BGA sockets are available. These
two types of sockets use different imbedded conductors.
One uses solid metal conductors while the other uses gold
filaments (similar in construction to steel wool). These
conductors electrically connect the solder balls of the
CBGA package to the PCB.
The BGA sockets currently available contain relatively
small inductance from the package solder ball to the
printed-circuit board. One might expect the power and
ground path inductance to increase by 3-7%. This is
primarily because the distance is small. The small
inductance will have little impact on the signal electrical
performance.
HEAT TRANSFER MECHANISMS AND THERMAL
CONTROL OPTIONS
Primary H eat Transfer Path: Attache d Heat Sink
To increase the thermal dissipation capability of this
technology, a heat sink may be mate d to the silicon [9,10] .
In this C4/CBGA package, the silicon chip is exposed;
therefore, the package "case" is the top of the silicon
(Figure 2). For cases with an attached heat sink, the
primar y heat transfer path is as follows: heat gene rated on
the active side (ball) of the chip is conducted through the
silicon, then through the heat sink attach material and
finally to the heat sink where it is removed by natural or
forced-air convection. The junction-to-ambient resistance
is then,
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Θja = Θjc + Θ heat sink attach + Θ heat sink (1)
The silicon thermal resistance is quite small. That is, the
die junction-to-case thermal resistance is 0.075°C/W and
0.033 °C/W for the PowerPC 603 and PowerPC 604
microprocessors; respectively. Therefore, for a first-order
analysis the temperature drop in the silicon may be
neglected. Thus, the heat sink attach material and the heat
sink conduction/convective thermal resistances are the
dominant terms.
Alternate Heat Transfer Path: Conduction to the PCB
The internal-package conduction resistance terms for the
alternate heat transfer path is the contribution of: C4,
under-fill, package substrate, package leads/balls. For a
one-dimensional model, the die junction-to-lead thermal
resistance is:
Θjl = 1/(1/ΘC4 + 1/Θunder-fill) + Θ package + Θlead (2)
The results of 3D modeling predicted the die junction-to-
lead thermal resistance was 3.4 °C/W and 2.2 °C/W, for the
PowerPC 603 and PowerPC 604 microprocessors;
respectively.
For lower-power microprocessors, the use of a heat sink
may not be necessary. This path alone may be adequate
for low-power chips, however, it is a function of the board
population and the system -leve l boundary conditions. Heat
conducted through the silicon may be convectively
remove d to the a mbient air. In addition, a second parallel
heat f low path exists by conduction, thr ough the C4 bumps
and the epoxy under-fill, to the ceramic substrate for
further convection cooling off the edges. Then from the
ceramic substrate heat is conducted via the leads/balls to
the next-level interconnect; whereupon the primary mode
of heat transfer is by convection and/or radiation.
Thermal Enhancement Options: Forced-air Cooling
and Heat Sink O p tions
Computational fluid dynamics (CFD) methods were used
to solve the steady-state conjugate heat transfer problem
using a commercially-available software which uses the
finite-volume method [11]. The calculation domain was
subdivided into cuboidal volumes. A progression in grid
refinement was performed, until grid independent
temperatures were achieved. A CBGA with a C4 thermal
test die was utilized for model validation. Modeled and
measur ed r esults we re found to a gree w ithin approxima tely
a 10% diffe rence over the range f rom na tural c onvection to
4 m/s. Once the models of the test vehicle were validated,
other models were generated for the PowerPC 603 and
PowerPC 604 microprocessors. The worst-case power
dissipation for the PowerPC 603 mic roprocessor is 3 watts,
while the PowerPC 604 microprocessors is 13 watts [1,2].
Then models were run for moderate air velocity, with the
package mounted to a one-signal layer printed-circuit
board with no heat sink which concurs with SEMI
standards [12].
For the case when no heat sink was present for an air
velocity of 1 m/s, the die-junction temperature rise above
ambient is 60 °C f or the PowerP C 603 micropr ocessor and
50
100
150
200
250
012345
PowerPC 603 Microprocessor (3 W)
PowerPC 604 Microprocessor (13 W)
Airflow Velocity (m/s)
Figure 4. Model Results f or the Power PC 603 and
PowerPC 604 M icroprocessor (at 3 and
13 watts; respectively) Temperature Rise
above the Loca l Ambient with No Heat Sink.
40
80
120
160
200
012345
Heat Sink #1, Pin-fin (10.5 cm^3)
Heat Sink #2, Pin-fin (23.8 cm^3)
Heat Sink #3, Stamped (84.1 cm^3)
Heat Sink #4, Pin-fin (45.0 cm^3)
Heat Sink #5, Bi-directional (36.7 cm^3)
Heat Sink #6, Fan-sink (38.3 cm^3)
Airflow Velocity (m/s)
Figure 5. Model Results f or the Pow er PC 604 Micr o-
processor (13 watts) Die-junction temperature
Rise for Various Heat Sink Options: Adiabatic
Board.
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is 205 °C for the PowerPC 604 micropr ocessor (F igure 4).
Typical die-junction temperatures should be maintained
betwee n 85 a nd 110 °C. T he te mpe ra tur e of the a ir c ooling
the component greatly depends upon the ambient inlet air
temperature and the air temperature rise within the
computer cabinet before it reaches the component. A
computer cabinet inlet-air temperature may range from 30
to 40°C. The air temperature rise within a cabinet may be
in the range of 5 to 10°C. Thus, the allowa ble die-junction
component tem perature r ise above ambient ca n range from
35 to 75 °C.
Clearly, the temperature rise for the PowerPC 604
microprocessor is too high and thermal enhancements are
required. First, the internal-package thermal conduction
paths were examined. The junction-to-case is silicon and
its contribution to the overall heat transfer path is less than
1%. Thus, for the PowerPC 604 microprocessor, the
addition of extended-surface heat sinking was the next
consideration. For an adiabatic-board case, commercially-
available heat sinks were modeled and the temperature rise
for the 13 watt PowerPC 604 microprocessor is shown in
Figure 5. This graph may be used as an initial selection
guide f or a variety of boundary conditions. Let us assume ,
for most computer systems in an office environment, a 60
°C die-junction c omponent te mperature r ise above ambient
is typical. Thus, three of the heat sinks would meet this
criteria at 1 m/s of air velocity. If air velocity is increased
further to 2 m/s, then five of the heat sinks meet this
criteria. Of the passive heat sinks designs, the bi-
directional offers the best thermal performance, for its
relatively small spatial volume. The integral-fan pin-fin
heat sink which promotes impingement airflow offers the
best thermal performance; however, being an active device
it require s external power. In addition, a system's designer
might need to consider a "fail safe" thermal-control system
in the event of a fan failure.
Board-level Component Population Considerations
Thermal performance data presented thus far has been for a
single com ponent mounted to a one- signal layer car d. The
next consider ation is the boa rd- leve l inter action e ff ec ts of
similarly powered neighboring components. That is,
board-level thermal flux would rise with increasing
component population, thereby limiting the ability of the
PCB to a ct as a he at sink. As a case study let us consider
various component population configurations for the
PowerPC 603 microprocessor. For the case of a single
component mounted to one-signal layer card, the die-
junction temperature rise is approximately 50 °C (Figure
6). For the data presented in Figure 6, the PowerPC 603
microprocessor had a 3 watt power dissipation and an air
velocity of 2 m/s, with no hea t sink.
Now let us consider, the f ully populated case with all nine
components (at 3 wa tts), the c enter com ponent tempe ratur e
rise is approximately 135 °C. Notice that even if the
center component is not powered, the die-junction
component temperature rise is 90°C, due to heating from
adjacent neighbors. This example demonstrates the need
for microelectronics thermal engineers to conduct board-
level and system-level thermal simulations to accurately
predict component operating temperatures. In addition,
due to the complex nature of heat transfer mechanisms, any
models should be e mpirica lly validated.
0
40
80
120
160
single 3x1 Array 3x1 Off 3x3 Array 3x3 Off
Unpowered Component
Powered Component (3W)
PowerPC 603 Microprocessor (C4/CBGA) Test Orientation
Figure 6. Model Results f or the Populate d Board Cases,
Intera ction Eff ects of the PowerP C 603 Micro-
processor (3 watts) Tempe rature Rise above the
Local Ambient with No Heat Sink.
CBGA-TO-BOARD SOLDER JOINT RELIABILITY
PCB Test Vehicle Description
The printed- ci rc uit boards use d to evalua te CBG A-to- boar d
solder joint reliability testing, were 1.57m m (62 mils) thick
FR-4 four-layer boards with two one-ounce copper planes
in the center to simula te power and gr ound, and half-ounc e
copper on the top and bottom for signal layer s. The sur face
mount pad diameter averaged 0.74mm (29 mils). The
target diameter tolerance was 0.72mm (28.5 mils) +/-
0.038mm (1.5 mils) (Figure 3).
The BGA footprint used in this study for both package
sizes was designed to be used in conjunction with a daisy
chain package (without die) to detect opens. Each CBGA
site had two testable chains, representing high-DNP and
low-DNP joints.
Each substrate was designed to mate to the PCB dual-
daisy-chain pattern so that each interconnection element
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between the substra te a nd PCB (ball) could be continuously
monitored electrically. Each PCB had eight CBGAs. A
gold-plated edge connector on each board provided 18
connections (2 commons and 16 signals), allowing two
individual nets to be monitored on each part. Hot-air-
solder-level (HASL) PCB finish was evaluated.
PCBs were characterized to have a glass-transition
temperature (Tg) of 118°C minimum and a thermal-
expansion coefficient of 21 ppm/°C in the array site (18
ppm/°C in the base material) [14].
CBGA Reliability Test Vehicle Description
Substrates (21mm and 25mm) used to study CBGA solder
joint reliability were designed to mate to a PCB so that
each connection to the PCB was monitored continuously
during therm al c ycle testing. T he da isy-cha in patte rn on the
substrate has connections made without using a C4 chip;
therefore, a co-fired conductor layer is used to provide the
interconnections. This technique is preferred for
independent testing of the CBGA joints over others
because it isolates the board interconnections (and not the
other connections internal to the package).
Solder Joint Fatigue Accelerated Testing Methodology
Accelerated air-to-air temperature cycle testing for CBGA
joints were cycled over a range of 20°C to 80°C (at 3
cycles per hour) for the 25mm packages [14] and 0°C to
100°C (at 1.5 cycles pe r hour) for the 21mm packages.
There were 40 CBGAs in each test cell. A minimum of
four minutes dwell time at the temperature extremes was
applied to allow creep/stress relaxation. To avoid thermal
shock in the joints, the ramp rate was limited to less than
20°C/minute. The temperature cycling testing was
consistent with IP C-SM-785 [15].
Electrical current was applied to the test nets, and each net
was polled every ten seconds for resistance increases. A
failure was defined as a resistance increase IRU
0.20µs. The recommended failure criteria was IRU
>1µs [15]; therefore, the criteria used was more
conservative. An event had to occur ten times within ten
percent of the cycle number of the first occurrence to be
considered a valid failure.
To characterize the thermal test chamber, boards
(thermocoupled at the joint under test) w ere stra tegically
placed to monitor test temperature. Up to nine
thermocouples were used to characterize a test chamber.
Temperature variation from package to package was kept
under 2°C at the dwell temperatures. Throughout thermal
cycling, digital and chart recorders tracked test
temperatures of the air and solder joints.
When 50 percent of the nets in a given cell failed, the
CBGAs in that cell were removed from the test. After
visual inspection at 40 times, selected samples were
crosssectioned and polished. Sorted data from accelerated
temperature cycling (ATC) tests were entered into
statistical analysis software. Log-normal graphs were
genera ted to determine N50 ( number of cycles in whic h 50
perce nt of the population of a given cell fa il).
C4/CBGA-to-Board Reliability
For illustrative purposes, the fatigue-life results of the
25mm CBGA tested from 20°C to 80°C is presented in
Figure 7 and is compared to 0°C to 100°C for both
25mm[16] and 21mm substrates. The CBGA wear-out
mechanism follows a log-normal distribution. Final
separation is characterized as a primary crack propagating
through the eutec tic solder at the PCB side of the high-lead
ball as ver i fied by cross-sectioning [17] .
The purpose of accelerated-temperature-cycle testing is to
compare the m ec hanica l and the ele ctr ica l robustne ss of the
assembly when subjected to a thermal cyclical
environment. Correlation to the accelerated temperature
cycle testing and actual field use can be made by use of
daisy-chain test vehicles and the application of a modified
Coffin-Manson relationship [18]. Acceleration factors can
be calculated to predict field-life cycles from the
accelerated-stress test results.
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.01
.1
1
5
10
20
30
50
70
80
90
95
99
99.9
99.99
200 1032000 5000500 104
102
0 to 100° C - 25mm [16 ]
20000 50000 105
25 to 55°C, proje cti on - 2 5mm
25 to 55°C, proje cti on - 2 1mm
Cummulative
Package
Failure s, %
Number of Cycles to Fi rst Package F ai lure
20 to 80°C - 25mm [14]
0 to 100° C - 21mm
20 to 80°C - 25mm [16]
3.2 X 2.2 X
Figure 7. CBGA fatigue life distributions (log-normal) for and 25mm substrates air-to-air temperature cycled from 20°C-
80°C and 0°C to 100°C compared to predictions m ade for the two te mperatur e cycle conditions using E quation 3.
Also, 21mm CBGA data for 0°C to 100°C is shown. Projections for a field examples are also shown for each
substrate size.
The version of the Coffin-Manson equation typically used
for CBGAs has been previously described[14]. For solder
interconne ctions of a fi xed geom et ry, the stra in ter m c an be
reduced to a delta temperature term, ¨7ZKLFKFRPSULVHV
each thermal cycle as illustrated in equation 3.
AF = [¨7l/¨7f]1.9(ff/fl)1/3exp[1414(1/Tmaxf - 1/Tmaxl)] (3)
The acceleration factor (AF) is simply a multiplier applied
to a known set of data to predict the failure rate of the
condition. In the case of 25°C-55°C and 20°C-80°C, the
AF (or multiplier) is 2.2X (assumptions for this calculation
will be presented in a later sub-section). In other words, the
fatigue life of the smaller ¨7LVWLPHVORQJHUWKDQ WKH
20°C-80°C c ase. Typically, the 50% f ail value is a pplied to
the AF factor to translate between failure distributions
(Figure 7).
In conside ration of the system-leve l thermal de sign options
presented, the ¨7VSUHVHQWHGLQWKLVVHFWLRQDUHFRQVLGHUHG
to be typical upper bounds that may be expected during
product use, 25 - 55°C [13]. Thermal excursions occur
through tur n-on/turn-off cycles of compute r systems. The
greatest reliability concern in the C4/CBGA packaging
technology is solder fatigue in the CBGA joints during
these thermal excursions [5]. Small ¨7V DVVRFLDWHG ZLWK
the interconnect joint equate to longer life when compared
to large ¨7V7KHUHIRUH thermal management design can
influence the solder joint temperature rise (¨7V
CBGA Solder Fatigue Life Projections
Predictions for typical computer applications were
projected by using accelerated test data and the method
described as follows: a) failure distributions, such as those
from Figure 7 were extrapolated down to the 0.01%
(100ppm) and 0.1% (1000ppm) levels, b) the number of
cycles to failure at those levels were noted, c) the number
of cycles was then multiplied by an acceleration factor
(Equation 3) for the temperature range of interest.
The fatigue life estimates described above are generally
thought to be very conservative for the solder joints
studied. The assumptions are: 1) on the average, the system
would be turned on and off up to 6 times per day [Coffin-
Manson 24 hour pe riod] and 2) the syste m would be cycled
over the full thermal excursion each and every time the
system was turned on.
The ma ximum solder fa tigue dam a ge f re quenc y that c an be
applied for most desktop office environment operating
temperatures is 1 on-off cycle every 4 hours (i.e., 6 per 24
hours). This is due to the solder requiring time to stress
relax at both temperature extremes (full on and full off)
generated in the office environment. During the course of
an ave rage work da y, which is ge nera lly considere d to be 8
to 10 hours long it is probable then to accumulate
maximum fatigue damage by having 2 evenly spaced on-
off cycles. Cycles occurring more frequently do not
accumulate as much damage per cycle as the above
describe d situation. Mor e fre quent cycling, w hile higher in
total number of cycles, do not necessarily accumulate more
solder fatigue dam age than a low number of long cycles.
The above m ethod was utilized to make pr edictions for the
PowerPC 603 and PowerPC 604 microprocessors both
using 21mm CBGA packages. These predictions are
shown in Figure 8. T he a ssumptions use d for Figure 8 we re
calculated to be consistent with [15]. Failure rates of
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100ppm (0.01% cumulative package failures) are plotted
and failure rates of 1000ppm (0.1% cumulative package
failures) can be easily calculated by multiplying the
100ppm number of c ycles by 1. 3.
ÆT (¡C) - Solder Joint Temperature Defined by Power On-Off
1
X
P
E
H
U
R
I
3
R
Z
H
U
2
Q
2
I
I
&
\
F
O
H
V
)RUSSPPXOWLSO\E\;
End-of-Life defined as 100ppm. Toff = 25¡C.
Figure 8. 21mm CBGA Solder Fatigue Field Life
Projections. Each cycle is assumed to represent the full temperature excursion.
Figure 8 shows the solder joint fatigue life for the 21mm
ceramic ball-grid-array (CBGA), the package for the
PowerPC 603 and PowerPC 604 microprocessors to be
over 10,000 cycles for an average full on/off cycle ¨7RI
20°C. For a desktop computer application turned on and
off on the average of one time per day, the equivalent
fatigue life would be over 27 years for the 21mm CBGA.
A 'wor st' case desktop situation, as describe d above would,
with 2 on-off cycles per work day would yield over 10
years
SUMMARY AND CONCLUSIONS
The following conclusions are noted:
• Assembly of C4/CBGA packages may be done with
common SMT equipment and offers very low assembly
defect yields when compared to similar leaded quad-flat-
pack tec hnology.
• The electrical package parasitics (RLC) are improved
with the C4/CBGA when compared to similar leaded quad-
flat-pack wire-bond te chnology.
• For airfl ow velocities f rom 1 to 2 m/ s, the Power PC 603
microprocessor, may not require heat sinking; however,
heat sinking may be required if the PCB board has high
thermal loading.
• The PowerPC 604 microprocessor will require heat
sinking to maintain its die-junction temperature less than
100 °C. Of the passive he at sinks de signs the bi-dire ctional
offered the best thermal performance for its spatial volume.
Note, due to silicon die fragility any heat sink attach
material m ust be structurally compliant. Finally, the board-
level component population and system airflow are the
other ther mal control ke y factors.
• It was estimated that the solder fatigue life of a 21mm
CBGA at an average on-off ¨7 RI & WR EH RYHU
years. Small ¨7V DVVRFLDWHG ZLWK WKH LQWHUFRQQHFW MRLQW
equate to longer life when compared to large ¨7V
Therefore, thermal management design can influence the
solder joint temperature rise (¨7V 'XH WR HIILFLHQW
designs, high power devices were found to have relatively
cool board temperatures.
ACKNOWLEDGMENTS
The authors wish to acknowledge the contribution of the
Advanced Packaging Technology team and the PowerPC
RISC microprocessor produc t team.
REFERENCES
[1] PowerPC 604 RISC Microprocessor Technical
Summary, Motorola, 1994.
[2] PowerPC 603 RISC Microprocessor User's Manual,
IBM/Motorola, 1994.
[3] Motorola Customer Version of "C4 Product Design
Manual-Volume I: Chip and Wafer Design," Motorola C4
Product Design Center, A ustin, TX, 1993.
[4] Keith DeHaven and Joel Dietz ; "Controlled Collapse
Chip Connection (C4) - An Enabling Technology",
Proceedings of the 44th Electronic Components &
Technology Conference, Washington, D.C., May 1 -4,
1994, pp. 1 - 6.
[5] G. Kromann, D Gerke and Wayne Huang, "A Hi-
Density C4/CBGA Interconnect Technology for a CMOS
Microprocessor," Proceedings of the 44th Electronic
Components & Te chnology Conf er enc e, Washington, D.C.,
May 1 - 4, 1994, pp. 22 - 27.
[6] David P. LaPotin, Toufie R. Mazzawy and Martin L.
White, "Early Package Analysis: Considerations and Case
Study," Computer, pp. 30-39, April 1993.
[7] Wayne Huang, Hector Astrain, Yutaka Doi, Mali
Mahalingham "Electrical Characterization of a Multilayer
Ceramic Chip Carrier with Meshed Power and Ground
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Planes," Proc. of International Symposium on
Microelec t ronics, ISHM, pp. 282-287, Nov. 1993.
[8] Wayne Huang and Jim Casto, "CBGA Package Design
for C4 PowerPC™ Microprocessor Trade-off between
Substrate Routability and Performance," Proc. of 44th
IEEE ECTC, pp. 88-93, May 1994.
[9] Gary B. Kromann, "Thermal Modeling and
Experimental Characterization of the C4/Surface-Mount-
Array Interconnect Technologies", Proceedings of the 44th
Electronic Components & Technology Conference,
Washington, D.C., May 1 -4, 1994, pp. 395 - 402.
[10] Gary B. Kromann, "Thermal Management of a
C4/Ceramic-Ball-Grid Array: The Motorola PowerPC
603™ and PowerPC 604™ RISC Microprocessors",
Interpack-95; March 1995.
[11] FLOTHERM® User's Guide, Verision 1.4; Flomerics
Limited; Surrey, England, 1993
[12] Semiconductor Equipment and Material International,
"Packaging Volume 4" , 1991.
[13] R.D. Gerke and G. Kromann, "The Effect of Solder-
Joint Temperature Rise on Ceramic-Ball-Grid Array to
Board Interconnection Reliability: The Motorola PowerPC
603™ and PowerPC 604™ Microprocessors and MPC105
Bridge/Me mory Controller"; Inter pa ck-95; Mar ch 1995.
[14] R.D. Gerke, "Ceramic Solder-Grid-Array
Interconnection Reliability Over a Wide Temperature
Range," Proceedings of NEPCON/West '94, Anaheim, CA,
Februa ry 27 - March 4, 1994, pp 1087 - 1094.
[15] IPC- SM-785, "Guidelines for Accelerated Reliability
Testing of Surface Mount Technology," Institute for
Interconnection and Packaging Electronic Circuits,
Lincolnwood, IL .
[16] T. Caulfield, J.A. Benenati and J. Acocella, "Surface
Mount Array Interconnections for High I/O MCM-C to
Card Assembles" Proceedings of the 1993 International
Confere nce and Exhibition on M ultichip Modules, Denver,
CO, 1993, pp.320-325.
[17] D.R. Banks, T.E. Burnette, R.D. Gerke, E. Mammo
and Shyam Mattay, "Reliability Comparison of Two
Metallurgies for Ceramic Ball Grid Array", Proceedings of
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Denver, CO, A pril 1993, pp.320- 325.
[18] K.C. Norris and A.H. Landzberg, "Reliability of
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Research of Research and Development, May, 1969,
pp.266-271.
APPENDIX
Table 1. PowerPC 603 and Pow erPC 604 RISC Microprocessor s [1,2]
Microprocessor Transistors Performance Power Die CBGA
Substrate CB GA
Substrate
SPECint92/ Dissipation Size Size Leads
SPECfp92 (watt) (mm) (mm)
PowerPC 603 1.6 million 75/85 3 @80 MHz (Full) 7.5x11.5 21x21 255
PowerPC 604 3.6 million 160/165 13 @100 MHz 12.4x15.8 21x21 255
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Table 2. C4/CBGA Internal-Package Thermal Conduction Resistance (3D model results) [10]
Thermal Resistance PowerPC603 Microprocessor PowerPC 604 Microprocessor
Die Junction- to-Case 0.075 °C/W 0.0329 °C/W
Die Junction- to-Lead 3.4 °C/W 2.2 °C/W
FLOTHERM is a registered trademark of Flomerics Limited.
PowerPC, PowerPC 601, PowerPC 603, PowerPC 604, and PowerPC 620 are trademarks of International Business Machines Corporation and are used by Motorola, Inc. under
license from International Business Machines Corporation.
Motorola, Inc., 1996. All rights reserved.
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