1
®
FN3183.4
ICL7673
Automatic Battery Back-Up Switch
The Intersil ICL7673 is a monolithic CMOS battery backup
circuit that offers unique performance advantages over
conventional means of switching to a backup supply. The
ICL7673 is intended as a low-cost solution for the switching
of systems between two power supplies; main and battery
backup. The main application is keep-alive-battery power
switching for use in volatile CMOS RAM memory systems
and real time clocks. In many applications this circuit will
represent a low insertion voltage loss between the supplies
and load. This circuit features low current consumption, wide
operating voltage range, and exceptionally low leakage
between inputs. Logic outputs are provided that can be used
to indicate which supply is connected and can also be used
to increase the power switching capability of the circuit by
driving external PNP transistors.
Pinouts
ICL7673 (SOIC, PDIP)
TOP VIEW
Features
• Automatically Connects Output to the Greater of Either
Input Supply Voltage
• If Main Power to External Equipment is Lost, Circuit Will
Automatically Connect Battery Backup
• Reconnects Main Power When Restored
• Logic Indicator Signaling Status of Main Power
• Low Impedance Connection Switches
• Low Internal Power Consumption
• Wide Supply Range: . . . . . . . . . . . . . . . . . . . 2.5V to 15V
• Low Leakage Between Inputs
• External Transistors May Be Added if Very Large
Currents Need to Be Switched
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• On Board Battery Backup for Real-Time Clocks,
Timers, or Volatile RAMs
• Over/Under Voltage Detector
• Peak Voltage Detector
• Other Uses:
- Portable Instruments, Portable Telephones, Line
Operated Equipment
Functional Block Diagram
Ordering Information
PART
NUMBER
TEMP. RANGE
(°C) PACKAGE
PKG.
DWG. #
ICL7673CPA 0 to 70 8 Ld PDIP E8.3
ICL7673CPAZ
(See Note)
0 to 70 8 Ld PDIP*
(Pb-free)
E8.3
ICL7673CBA 0 to 70 8 Ld SOIC (N) M8.15
ICL7673CBA-T 8 Ld SOIC (N) Tape and Reel M8.15
ICL7673CBAZA
(See Note)
0 to 70 8 Ld SOIC (N)
(Pb-free)
M8.15
ICL7673CBAZA-T
(See Note)
0 to 70 8 Ld SOIC (N)
(Pb-free)
M8.15
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
VO
VS
SBAR
GDN
1
2
3
4
8
7
6
5
VP
NC
PBAR
NC
P1
P2
VS
GND
PBAR
SBAR
VO
+
-
VP
VP > VS, P1 SWITCH ON AND PBAR SWITCH ON
VS > VP, P2 SWITCH ON AND SBAR SWITCH ON
Data Sheet July 22, 2005
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 1999-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN3183.4
July 22, 2005
Absolute Maximum Ratings Thermal Information
Input Supply (VP or VS) Voltage . . . . . . . . . . . . GND - 0.3V to +18V
Output Voltages PBAR and SBAR . . . . . . . . . . . GND - 0.3V to +18V
Peak Current
Input VP (at VP = 5V) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . 38mA
Input VS (at VS = 3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
PBAR or SBAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150mA
Operating Conditions
Temperature Range:
ICL7673C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Thermal Resistance (Typical, Note 2) θJA (°C/W) θJC (°C/W)
PDIP Package* . . . . . . . . . . . . . . . . . . 150 N/A
Plastic SOIC Package . . . . . . . . . . . . . 180 N/A
Maximum Storage Temperature. . . . . . . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering, 10sec). . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Derate above 25°C by 0.38mA/°C.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TA = 25°C Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Input Voltage VPVS = 0V, ILOAD = 0mA 2.5 - 15 V
VSVP = 0V, ILOAD = 0mA 2.5 - 15 V
Quiescent Supply Current I+ VP = 0V, VS = 3V, ILOAD = 0mA - 1.5 5 µA
Switch Resistance P1 (Note 1) rDS(ON)P1 VP = 5V, VS = 3V, ILOAD = 15mA - 8 15 Ω
At TA = +85°C - 16 - Ω
VP = 9V, VS = 3V, ILOAD = 15mA - 6 - Ω
VP = 12V, VS = 3V, ILOAD = 15mA - 5 - Ω
Temperature Coefficient of Switch
Resistance P1
TC(P1) VP = 5V, VS = 3v, ILOAD = 15mA - 0.5 - %/°C
Switch Resistance P2 (Note 1) rDS(ON)P2 VP = 0V, VS = 3V, ILOAD = 1mA - 40 100 Ω
At TA = +85°C - 60 - Ω
VP = 0V, VS = 5V, ILOAD = 1mA - 26 - Ω
VP = 0V, VS = 9V, ILOAD = 1mA - 16 - Ω
Temperature Coefficient of Switch
Resistance P2
TC(P2) VP = 0V, VS = 3V, ILOAD = 1mA - 0.7 - %/°C
Leakage Current (VP to VS)I
L(PS) VP = 5V, VS = 3V, ILOAD = 10mA - 0.01 20 nA
At TA = +85°C - 35 - nA
Leakage Current (VP to VS)I
L(SP) VP = 0V, VS = 3V, ILOAD = 10mA - 0.01 50 nA
at TA = +85°C - 120 - nA
Open Drain Output Saturation Voltages VOPBAR VP = 5V, VS = 3V, ISINK = 3.2mA, ILOAD = 0mA - 85 400 mV
At TA = 85°C - 120 - mV
VP = 9V, VS = 3V, ISINK = 3.2mA, ILOAD = 0mA - 50 - mV
VP = 12V, VS = 3V, ISINK = 3.2mA
ILOAD = 0mA
-40- mV
Open Drain Output Saturation Voltages VOSBAR VP = 0V, VS = 3V, ISINK = 3.2mA, ILOAD = 0mA - 150 400 mV
at TA = +85°C - 210 - mV
VP = 0V, VS = 5V, ISINK = 3.2mA ILOAD = 0mA - 85 - mV
VP = 0V, VS = 9V, ISINK = 3.2mA ILOAD = 0mA - 50 - mV
ICL7673
3FN3183.4
July 22, 2005
Output Leakage Currents of PBAR and
SBAR
ILPBAR VP = 0V, VS = 15V, ILOAD = 0mA - 50 500 nA
at TA = +85°C - 900 - nA
ILSBAR VP = 15V, VS = 0V, ILOAD = 0mA - 50 500 nA
at TA = +85°C - 900 - nA
Switchover Uncertainty for Complete
Switching of Inputs and Open Drain
Outputs
VP - VSVS = 3V, ISINK = 3.2mA, ILOAD = 15mA - ±10 ±50 mV
NOTE:
3. The Minimum input to output voltage can be determined by multiplying the load current by the switch resistance.
Electrical Specifications TA = 25°C Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Typical Performance Curves
FIGURE 1. ON-RESISTANCE SWITCH P1 AS A FUNCTION OF
INPUT VOLTAGE VP
FIGURE 2. ON-RESISTANCE SWITCH P2 AS A FUNCTION OF
INPUT VOLTAGE VS
FIGURE 3. SUPPLY CURRENT AS A FUNCTION OF SUPPLY
VOLTAGE
FIGURE 4. PBAR OR SBAR SATURATION VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT
100
10
102 46810121416
ILOAD = 15mA
ON-RESI STANCE P1 (Ω)
INPUT VOLTAGE VP (V)
ON-RESISTANCE P2 (Ω)
INPUT VOLTAGE VS
100
10
10246810
ILOAD = 1mA
SUPPLY CURRENT (µA)
-40°C
25°C
85°C
1
0.8
0.6
0.4
0.2
02 46 810121416
SUPPLY VOLTAGE (V)
OUTPUT SATURATION VOLTAGE (V)
5
4
3
2
1
0 40 80 120 140 180
VO = 3V
OUTPUT CURRENT (mA)
VO = 5V VO = 9V
VO = 12V
VO = 15V
ICL7673
4FN3183.4
July 22, 2005
Detailed Description
As shown in the Functional Diagram, the ICL7673 includes a
comparator which senses the input voltages VP and VS. The
output of the comparator drives the first inverter and the
open-drain N-Channel transistor PBAR. The first inverter
drives a large P-Channel switch, P1, a second inverter, and
another open-drain N-Channel transistor, SBAR. The second
inverter drives another large P-Channel switch P2. The
ICL7673, connected to a main and a backup power supply,
will connect the supply of greater potential to its output. The
circuit provides break-before-make switch action as it
switches from main to backup power in the event of a main
power supply failure. For proper operation, inputs VP and VS
must not be allowed to float, and, the difference in the two
supplies must be greater than 50mV. The leakage current
through the reverse biased parasitic diode of switch P2 is
very low.
Output Voltage
The output operating voltage range is 2.5V to 15V. The
insertion loss between either input and the output is a
function of load current, input voltage, and temperature. This
is due to the P-Channels being operated in their triode
region, and, the ON-resistance of the switches is a function
of output voltage VO. The ON-resistance of the P-Channels
have positive temperature coefficients, and therefore as
temperature increases the insertion loss also increases. At
low load currents the output voltage is nearly equal to the
greater of the two inputs. The maximum voltage drop across
switch P1 or P2 is 0.5V, since above this voltage the body-
drain parasitic diode will become forward biased. Complete
switching of the inputs and open-drain outputs typically
occurs in 50µs.
Input Voltage
The input operating voltage range for VP or VS is 2.5V to
15V. The input supply voltage (VP or VS) slew rate should be
limited to 2V per microsecond to avoid potential harm to the
circuit. In line-operated systems, the rate-of-rise (or fall) of
the supply is a function of power supply design. For battery
applications it may be necessary to use a capacitor between
the input and ground pins to limit the rate-of-rise of the
supply voltage. A low-impedance capacitor such as a
0.047µF disc ceramic can be used to reduce the rate-of-rise.
Status Indicator Outputs
The N-Channel open drain output transistors can be used to
indicate which supply is connected, or can be used to drive
external PNP transistors to increase the power switching
capability of the circuit. When using external PNP power
transistors, the output current is limited by the beta and
thermal characteristics of the power transistors. The
application section details the use of external PNP
transistors.
Applications
A typical discrete battery backup circuit is illustrated in Figure
6. This approach requires several components, substantial
printed circuit board space, and high labor cost. It also
consumes a fairly high quiescent current. The ICL7673
battery backup circuit, illustrated in Figure 7, will often replace
such discrete designs and offer much better performance,
higher reliability, and lower system manufacturing cost. A
trickle charge system could be implemented with an additional
resistor and diode as shown in Figure 8. A complete low
power AC to regulated DC system can be implemented using
the ICL7673 and ICL7663S micropower voltage regulator as
shown in Figure 9.
IS LEAKAGE CURRENT
INPUT VP (V)
02456 81012
1mA
100mA
10nA
1nA
1000pA
10pA
1pA
ILOAD = 10mA
VS = 0V
85°C
25°C
FIGURE 5. IS LEAKAGE CURRENT VP TO VS AS A
FUNCTION OF INPUT VOLTAGE
+5V
PRIMARY
DC POWER
GND
NiCAD
BATTERY
STACK
VO
+5V OR
+3V
STATUS
INDICATOR
FIGURE 6. DISCRETE BATTERY BACKUP CIRCUIT
ICL7673
5FN3183.4
July 22, 2005
Applications for the ICL7673 include volatile semiconductor
memory storage systems, real-time clocks, timers, alarm
systems, and over/under the voltage detectors. Other
systems requiring DC power when the master AC line supply
fails can also use the ICL7673.
A typical application, as illustrated in Figure 12, would be a
microprocessor system requiring a 5V supply. In the event of
primary supply failure, the system is powered down, and a
3V battery is employed to maintain clock or volatile memory
data. The main and backup supplies are connected to VP
and VS, with the circuit output VO supplying power to the
clock or volatile memory. The ICL7673 will sense the main
supply, when energized, to be of greater potential than VS
and connect, via its internal MOS switches, VP to output VO.
The backup input, VS will be disconnected internally. In the
event of main supply failure, the circuit will sense that the
backup supply is now the greater potential, disconnect VP
from VO, and connect VS.
Figure 11 illustrates the use of external PNP power
transistors to increase the power switching capability of the
circuit. In this application the output current is limited by the
beta and thermal characteristics of the power transistors.
If hysteresis is desired for a particular low power application,
positive feedback can be applied between the input VP and
open drain output SBAR through a resistor as illustrated in
Figure 12. For high power applications hysteresis can be
applied as shown in Figure 13.
The ICL7673 can also be used as a clipping circuit as
illustrated in Figure 14. With high impedance loads the
circuit output will be nearly equal to the greater of the two
input signals.
VPVO
VSGND
Pbar
8
2
1
6
VO
+5V OR +3V
RI
STATUS
INDICATOR
LITHIUM
BATTERY
GND
+5V
PRIMARY
SUPPLY
4
+
-
FIGURE 7. ICL7673 BATTERY BACKUP CIRCUIT
VPVO
VSGND
8
2
1VO
+5V OR +3V
RECHARGEABLE
BATTERY
GND
+5V
PRIMARY
SUPPLY
4
RC
+
-
FIGURE 8. APPLICATION REQUIRING RECHARGEABLE
BATTERY BACKUP
FIGURE 9. POWER SUPPLY FOR LOW POWER PORTABLE AC TO DC SYSTEMS
FIGURE 10. TYPICAL MICROPROCESSOR MEMORY APPLICATION
FUSE
120/240
VAC
BRIDGE
RECTIFIER
BATTERY
STACK
GND
VO
VS
VP
18
24
28
46
STEPDOWN
TRANSFORMER
R3
R2
R1
C1
D1+
-
ICL7673
BATTERY
BACK-UP
ICL7663
REGULATOR
POWER
FAIL
DETECTOR MICROPROCESSOR
VOLATILE
RAM
INTERRUPT SIGNAL
ICL7673
BACKUP CIRCUIT
+5V
MAIN
POWER
VO
VP
VS
+
-
ICL7673
6FN3183.4
July 22, 2005
FIGURE 11. HIGH CURRENT BATTERY BACKUP SYSTEM
FIGURE 12. LOW CURRENT BATTERY BACKUP SYSTEM WITH HYSTERESIS
FIGURE 13. HIGH CURRENT BACKUP SYSTEM WITH HYSTERESIS
EXTERNAL
EQUIPMENT
VO
GND
8
23
6
VP
VS
NC
P-
S-
1
PNP
PNP
MAIN
SUPPLY
3V
BACKUP
SUPPLY
+
-
(NOTE 4)
NOTE 4. > 1MW
R3
R4
R1
R2
ICL7673
VO
GND
8
23
VP
VSS-
MAIN
SUPPLY
+
-
BATTERY
BACKUP
RS
RF
ICL7673
GNDGND
EXTERNAL
EQUIPMENT
1
4
8
23
6
VP
VS
NC
P-
S-
PNP
PNP
MAIN
SUPPLY
BACKUP
SUPPLY
RS
RF
R2
R4
R1
R3
ICL7673
+V
SUPPLY
GND
MAIN
+
-
ICL7673
7
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3183.4
July 22, 2005
FIGURE 14. CLIPPLING CIRCUITS
VP
VS
VO
GND
VS
VO
VP
ICL7673
ICL7673
