DS2505 DS2505 16K bit Add-Only Memory FEATURES * 16384 bits Electrically Programmable Read Only Memory (EPROM) communicates with the economy of one signal plus ground * Unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit CRC tester) assures absolute traceability because no two parts are alike PIN ASSIGNMENT TO-92 DALLAS DS2505 TSOC PACKAGE GND DATA NC 1 2 3 6 5 4 NC NC NC TOP VIEW * Built-in 3.7 X 4.0 X 1.5 mm multidrop controller ensures compatibility with other MicroLANTM products * EPROM partitioned into sixty-four 256-bit pages for SIDE VIEW randomly accessing packetized data records See Mech. Drawings Section 1 2 NC * Device is an "add only" memory where additional data GND tected to prevent tampering DATA * Each memory page can be permanently write-pro- can be programmed into EPROM without disturbing existing data * Architecture allows software to patch data by superseding an old page in favor of a newly programmed page * Reduces control, address, data, power, and program- 3 BOTTOM VIEW See Mech. Drawings Section ming signals to a single data pin * Directly connects to a single port pin of a microprocessor and communicates at up to 16.3k bits per second * 8-bit family code specifies DS2505 communications requirements to reader * Presence detector acknowledges when the reader first applies voltage * Low cost TO-92 or 6-pin TSOC surface mount package * Reads over a wide voltage range of 2.8V to 6.0V from -40C to +85C; programs at 11.5V to 12.0V from -40C to +85C ORDERING INFORMATION DS2505 DS2505P DS2505T DS2505V TO-92 Package 6-pin TSOC Package Tape & Reel version of DS2505 Tape & Reel version of DS2505P SILICON LABEL DESCRIPTION The DS2505 16k bits Add-Only Memory identifies and stores relevant information about the product to which it is associated. This lot or product specific information can be accessed with minimal interface, for example a single port pin of a microcontroller. The DS2505 consists of a factory-lasered registration number that 020998 1/23 DS2505 includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (0BH) plus 16k bits of user- programmable EPROM. The power to program and read the DS2505 is derived entirely from the 1-WireTM communication line. Data is transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return. The entire device can be programmed and then write-protected if desired. Alternatively, the part may be programmed multiple times with new data being appended to, but not overwriting, existing data with each subsequent programming of the device. Note: Individual bits can be changed only from a logical 1 to a logical 0, never from a logical 0 to a logical 1. A provision is also included for indicating that a certain page or pages of data are no longer valid and have been replaced with new or updated data that is now residing at an alternate page address. This page address redirection allows software to patch data and enhance the flexibility of the device as a standalone database. The 48-bit serial number that is factory- lasered into each DS2505 provides a guaranteed unique identity which allows for absolute traceability. The TO-92 and TSOC packages provide a compact enclosure that allows standard assembly equipment to handle the device easily for attachment to printed circuit boards or wiring. Typical applications include storage of calibration constants, maintenance records, asset tracking, product revision status and access codes. OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS2505. The DS2505 has three main data components: 1) 64-bit lasered ROM, 2) 16384-bits EPROM Data Memory, and 3) 704-bits EPROM Status Memory. The device derives its power for read operations entirely from the 1-Wire communication line by storing energy on an internal capacitor during periods of time when the signal line is high and continues to operate off of this "parasite" power source during the low times of the 1-Wire line until it returns high to replenish the parasite (capacitor) supply. During programming, 1-Wire communication occurs at normal voltage levels and then is pulsed momentarily to the programming voltage to cause the selected EPROM bits to be programmed. The 1-Wire line must be able to provide 12 volts and 10 milliamperes to adequately program the EPROM portions of the part. Whenever programming voltages are present on the 1-Wire line a special high voltage detect circuit within the DS2505 generates an internal logic signal to indicate this condition. The hierarchical structure of 020998 2/23 the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the four ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM. These commands operate on the 64-bit lasered ROM portion of each device and can singulate a specific device if many are present on the 1-Wire line as well as indicate to the bus master how many and what types of devices are present. The protocol required for these ROM Function Commands is described in Figure 8. After a ROM Function Command is successfully executed, the memory functions that operate on the EPROM portions of the DS2505 become accessible and the bus master may issue any one of the five Memory Function Commands specific to the DS2505 to read or program the various data fields. The protocol for these Memory Function Commands is described in Figure 5. All data is read and written least significant bit first. 64-BIT LASERED ROM Each DS2505 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See Figure 3.) The 64-bit ROM and ROM Function Control section allow the DS2505 to operate as a 1-Wire device and follow the 1-Wire protocol detailed in the section "1-Wire Bus System". The memory functions required to read and program the EPROM sections of the DS2505 are not accessible until the ROM function protocol has been satisfied. This protocol is described in the ROM functions flow chart (Figure 8). The 1-Wire bus master must first provide one of four ROM function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, or 4) Skip ROM. After a ROM function sequence has been successfully executed, the bus master may then provide any one of the memory function commands specific to the DS2505 (Figure 5). The 1-Wire CRC of the lasered ROM is generated using the polynomial X8 + X5 + X4 + 1. Additional information about the Dallas Semiconductor 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards. The shift register acting as the CRC accumulator is initialized to zero. Then starting with the least significant bit of the family code, one bit at a time is shifted in. After the eighth bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all zeroes. DS2505 DS2505 BLOCK DIAGRAM Figure 1 PARASITE POWER 1-WIRE BUS DATA 1-WIRE FUNCTION CONTROL PROGRAM VOLTAGE DETECT MEMORY FUNCTION CONTROL 64-BIT LASERED ROM 8-BIT SCRATCHPAD 16-BIT CRC GENERATOR 16K BIT EPROM (64 PAGES OF 32 BYTES) 88 EPROM STATUS BYTES 020998 3/23 DS2505 HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 BUS MASTER 1-WIRE BUS OTHER DEVICES DS2505 COMMAND LEVEL: 1-WIRE ROM FUNCTION COMMANDS (SEE FIGURE 9) DS2505-SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE 6) AVAILABLE COMMANDS: DATA FIELD AFFECTED: READ ROM MATCH ROM SEARCH ROM SKIP ROM 64-BIT ROM 64-BIT ROM 64-BIT ROM N/A WRITE MEMORY 16K BIT EPROM WRITE STATUS EPROM STATUS BYTES READ MEMORY 16K BIT EPROM READ STATUS EPROM STATUS BYTES EXTENDED READ DATA 16K BIT EPROM 64-BIT LASERED ROM Figure 3 8-Bit CRC Code MSB 020998 4/23 LSB 48-Bit Serial Number MSB LSB 8-Bit Family Code (0BH) MSB LSB DS2505 16384-BITS EPROM The memory map in Figure 4 shows the 16384-bit EPROM section of the DS2505 which is configured as sixty-four pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when programming the memory. Data is first written to the scratchpad and then verified by reading an 16-bit CRC from the DS2505 that confirms proper receipt of the data and address. If the buffer contents are correct, a programming voltage should be applied and the byte of data will be written into the selected address in memory. This process insures data integrity when programming the memory. The details for reading and programming the 16384-bit EPROM portion of the DS2505 are given in the Memory Function Commands section. EPROM STATUS BYTES In addition to the 16384 bits of data memory the DS2505 provides 704 bits of Status Memory accessible with separate commands. The EPROM Status Bytes can be read or programmed to indicate various conditions to the software interrogating the DS2505. The first eight bytes of the EPROM Status Memory (addresses 000 to 007H) contain the Write Protect Page bits which inhibit programming of the corresponding page in the 16384-bit main memory area if the appropriate write protection bit is programmed. Once a bit has been programmed in the Write Protect Page section of the Status Memory, the entire 32 byte page that corresponds to that bit can no longer be altered but may still be read. The next eight bytes of the EPROM Status Memory (addresses 020 to 027H) contain the Write Protect bits which inhibit altering the Page Address Redirection Byte corresponding to each page in the 16384-bit main memory area. The following eight bytes within the EPROM Status Memory (addresses 040 to 047H) are reserved for use by the iButton operating software TMEX. Their purpose is to indicate which memory pages are already in use. Originally, all of these bits are unprogrammed, indicating that the device does not store any data. As soon as data is written to any page of the device under control of TMEX, the bit inside this bitmap corresponding to that page will be programmed to 0, marking this page as used. These bits are application flags only and have no impact on the internal logic of the DS2505. The next sixty-four bytes of the EPROM Status Memory (addresses 100H to 13FH) contain the Page Address Redirection Bytes which indicate if one or more of the pages of data in the 16384-bit EPROM section have been invalidated by software and redirected to the page address contained in the appropriate redirection byte. The hardware of the DS2505 makes no decisions based on the contents of the Page Address Redirection Bytes. These additional bytes of Status EPROM allow for the redirection of an entire page to another page address, indicating that the data in the original page is no longer considered relevant or valid. With EPROM technology, bits within a page can be changed from a logical 1 to a logical 0 by programming, but cannot be changed back. Therefore, it is not possible to simply rewrite a page if the data requires changing or updating, but with space permitting, an entire page of data can be redirected to another page within the DS2505 by writing the one's complement of the new page address into the Page Address Redirection Byte that corresponds to the original (replaced) page. This architecture allows the user's software to make a "data patch" to the EPROM by indicating that a particular page or pages should be replaced with those indicated in the Page Address Redirection Bytes. To leave an authentic audit trail of data patches, it is recommended to also program the write protect bit of the Page Address Redirection Byte, after the page redirection is programmed. Without this protection, it is still possible to modify the Page Address Redirection Byte, making it point to a different memory page than the true one. If a Page Address Redirection Byte has a FFH value, the data in the main memory that corresponds to that page is valid. If a Page Address Redirection Byte has some other hex value, the data in the page corresponding to that redirection byte is invalid, and the valid data can now be found at the one's complement of the page address indicated by the hex value stored in the associated Page Address Redirection Byte. A value of FDH in the redirection byte for page 1, for example, would indicate that the updated data is now in page 2. The details for reading and programming the EPROM status memory portion of the DS2505 are given in the Memory Function Commands section. The Status Memory address range of the DS2505 extends from 000 to 13FH. The memory locations 008H to 01FH, 028H to 03FH, 048H to 0FFH and 140H to 020998 5/23 DS2505 7FFH are physically not implemented. Reading these locations will usually result in FFH bytes. Attempts to write to these locations will be ignored. If the bus master sends a starting address higher than 7FFH, the five most significant address bits are set to zeros by the internal circuitry of the chip. This will result in a mismatch between the CRC calculated by the DS2505 and the CRC calculated by the bus master, indicating an error condition. DS2505 MEMORY MAP Figure 4 8-BIT SCRATCHPAD STARTING ADDRESS 0000H 32-BYTE FINAL STORAGE EPROM PAGE 0 32-BYTE FINAL STORAGE EPROM PAGE 1 0020H 16K BIT EPROM 0040H 07E0H 32-BYTE FINAL STORAGE EPROM REDIRECTION BYTES BIT MAP OF USED PAGES WRITE-PROTECT BITS REDIRECTION BYTES PAGE 63 WRITE-PROTECT BITS DATA MEMORY 88 BYTES STATUS MEMORY STATUS MEMORY MAP 8 BYTES 000H BIT 0 OF ADDRESS 000H=WRITE-PROTECT OF PAGE 0. ETC. WRITE-PROTECT BITS DATA MEMORY RESERVED 007H 008H 01FH 020H WRITE-PROTECT BITS OF REDIRECTION BYTES RESERVED 11 PAGES OF 8 BYTES EACH 027H 028H 03FH 040H BIT MAP OF USED PAGES 047H 048H RESERVED FOR FUTURE EXTENSIONS 0FFH REDIRECTION BYTES 100H * * * * 13FH 020998 6/23 ADDRESS 100H=PAGE ADDRESS REDIRECTION BYTE FOR PAGE 0, ETC. DS2505 MEMORY FUNCTION COMMANDS The "Memory Function Flow Chart" (Figure 5) describes the protocols necessary for accessing the various data fields within the DS2505. The Memory Function Control section, 8-bit scratchpad, and the Program Voltage Detect circuit combine to interpret the commands issued by the bus master and create the correct control signals within the device. A three-byte protocol is issued by the bus master. It is comprised of a command byte to determine the type of operation and two address bytes to determine the specific starting byte location within a data field. The command byte indicates if the device is to be read or written. Writing data involves not only issuing the correct command sequence but also providing a 12 volt programming voltage at the appropriate times. To execute a write sequence, a byte of data is first loaded into the scratchpad and then programmed into the selected address. Write sequences always occur a byte at a time. To execute a read sequence, the starting address is issued by the bus master and data is read from the part beginning at that initial location and continuing to the end of the selected data field or until a reset sequence is issued. All bits transferred to the DS2505 and received back by the bus master are sent least significant bit first. READ MEMORY [F0H] The Read Memory command is used to read data from the 16384-bits EPROM data field. The bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. With every subsequent read data time slot the bus master receives data from the DS2505 starting at the initial address and continuing until the end of the 16384-bits data field is reached or until a Reset Pulse is issued. If reading occurs through the end of memory space, the bus master may issue sixteen additional read time slots and the DS2505 will respond with a 16-bit CRC of the command, address bytes and all data bytes read from the initial starting byte through the last byte of memory. This CRC is the result of clearing the CRC generator and then shifting in the command byte followed by the two address bytes and the data bytes beginning at the first addressed memory location and continuing through to the last byte of the EPROM data memory. After the CRC is received by the bus master, any subsequent read time slots will appear as logical 1s until a Reset Pulse is issued. Any reads ended by a Reset Pulse prior to reaching the end of memory will not have the 16-bit CRC available. Typically a 16-bit CRC would be stored with each page of data to insure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (See Book of DS19xx iButton Standards, Chapter 7 for the recommended file structure to be used with the 1-Wire environment.) If CRC values are imbedded within the data, a Reset Pulse may be issued at the end of memory space during a Read Memory command. READ STATUS [AAH] The Read Status command is used to read data from the EPROM Status data field. The bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. With every subsequent read data time slot the bus master receives data from the DS2505 starting at the supplied address and continuing until the end of an eight-byte page of the EPROM Status data field is reached. At that point the bus master will receive a 16-bit CRC of the command byte, address bytes and status data bytes. This CRC is computed by the DS2505 and read back by the bus master to check if the command word, starting address and data were received correctly. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. Note that the initial pass through the Read Status flow chart will generate a 16-bit CRC value that is the result of clearing the CRC generator and then shifting in the command byte followed by the two address bytes, and finally the data bytes beginning at the first addressed memory location and continuing through to the last byte of the addressed EPROM Status data page. The last byte of a Status data page always has an ending address of xx7 or xxFH. Subsequent passes through the Read Status flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the new data bytes starting at the first byte of the next page of the EPROM Status data field. This feature is provided since the EPROM Status information may change over time making it impossible to program the data once and include an accompanying CRC that will always be valid. Therefore, the Read Status command supplies a 16-bit CRC that is based on and always is consistent with the current data stored in the EPROM Status data field. 020998 7/23 DS2505 MEMORY FUNCTION FLOW CHART Figure 5 MASTER TX MEMORY FUNCTION COMMAND F0h READ MEMORY ? AAh READ STATUS ? N Y Y BUS MASTER TX TA1 (T7:T0) BUS MASTER TX TA1 (T7:T0) BUS MASTER TX TA2 (T15:T8) BUS MASTER TX TA2 (T15:T8) DS2505 SETS MEMORY ADDRESS = (T15:T0) DS2505 SETS STATUS ADDRESS = (T15:T0) Y Y BUS MASTER RX DATA FROM DATA MEMORY BUS MASTER RX DATA FROM STATUS MEMORY Y BUS MASTER TX RESET ? DS2505 INCREMENTS ADDRESS COUNTER N N BUS MASTER TX RESET ? Y N N END OF PAGE ? END OF DATA MEMORY ? N DS2505 INCREMENTS ADDRES5 COUNTER Y Y BUS MASTER TX RESET ? BUS MASTER RX CRC16 OF COMMAND, ADDRESS, DATA (1ST PASS) CRC16 OF DATA (SUBSEQUENT PASSES) Y N N BUS MASTER TX RESET BUS MASTER RX CRC16 OF COMMAND, ADDRESS, DATA CRC CORRECT ? DS2505 CLEARS CRC GENERATOR Y END OF STATUS MEMORY ? Y BUS MASTER TX RESET ? Y Y N BUS MASTER RX 1'S 020998 8/23 BUS MASTER TX RESET ? N DS2505 TX PRESENCE PULSE BUS MASTER RX 1'S N DS2505 MEMORY FUNCTION FLOW CHART (cont'd) Figure 5 A5h EXTENDED READ MEMORY ? N TO WRITE COMMANDS Y BUS MASTER TX TA1 (T7:T0) BUS MASTER TX TA2 (T15:T8) DS2505 SETS MEMORY ADDRESS = (T15:T0) Y BUS MASTER RX REDIR. BYTE LEGEND: BUS MASTER RX CRC16 OF COMMAND, ADDRESS, REDIR. BYTE (1ST PASS) CRC16 OF REDIR. BYTE (SUBSEQUENT PASSES) DECISION MADE BY THE MASTER CRC CORRECT ? N BUS MASTER TX RESET Y DECISION MADE BY DS2505 BUS MASTER RX DATA FROM DATA MEMORY BUS MASTER TX RESET ? DS2505 INCREMENTS ADDRESS COUNTER N Y N END OF PAGE ? Y BUS MASTER RX CRC16 OF PRECEDING PAGE OF DATA CRC CORRECT ? DS2505 INCREMENTS ADDRESS COUNTER N N BUS MASTER TX RESET END OF MEMORY ? Y BUS MASTER TX RESET ? Y DS2505 TX PRESENCE PULSE N BUS MASTER RX 1'S 020998 9/23 DS2505 MEMORY FUNCTION FLOW CHART (cont'd) Figure 5 0Fh WRITE MEMORY ? 55h WRITE STATUS ? N Y Y BUS MASTER TX TA1 (T7:T0) BUS MASTER TX TA1 (T7:T0) BUS MASTER TX TA2 (T15:T8) BUS MASTER TX TA2 (T15:T8) BUS MASTER TX DATA BYTE (D7:D0) BUS MASTER TX DATA BYTE (D7:D0) BUS MASTER RX CRC16 OF COMMAND, ADDRESS, DATA (1ST PASS) CRC16 OF ADDRESS, DATA (SUBSEQUENT PASSES) BUS MASTER RX CRC16 OF COMMAND, ADDRESS, DATA (1ST PASS) CRC16 OF ADDRESS, DATA (SUBSEQUENT PASSES) N CRC CORRECT ? N Y N Y CRC CORRECT ? BUS MASTER TX PROGRAM PULSE BUS MASTER TX PROGRAM PULSE DS2505 COPIES SCRATCHPAD TO DATA EPROM DS2505 COPIES SCRATCHPAD TO STATUS EPROM BUS MASTER RX BYTE FROM EPROM BUS MASTER RX BYTE FROM EPROM N EPROM BYTE = DATA BYTE ? EPROM BYTE = DATA BYTE ? Y END OF DATA MEMORY ? Y N END OF STATUS MEMORY ? N DS2505 INCREMENTS ADDRESS COUNTER DS2505 LOADS NEW ADDRESS INTO CRC GENERATOR BUS MASTER TX RESET Y Y MASTER TX RESET N DS2505 INCREMENTS ADDRESS COUNTER MASTER TX RESET DS2505 LOADS NEW ADDRESS INTO CRC GENERATOR DS2505 TX PRESENCE PULSE 020998 10/23 DS2505 After the 16-bit CRC of the last EPROM Status data page is read, the bus master will receive logical 1s from the DS2505 until a Reset Pulse is issued. The Read Status command sequence can be ended at any point by issuing a Reset Pulse. EXTENDED READ MEMORY [A5H] The Extended Read Memory command supports page redirection when reading data from the 16384-bit EPROM data field. One major difference between the Extended Read Memory and the basic Read Memory command is that the bus master receives the Redirection Byte first before investing time in reading data from the addressed memory location. This allows the bus master to quickly decide whether to continue and access the data at the selected starting page or to terminate and restart the reading process at the redirected page address. A non-redirected page is identified by a Redirection Byte with a value of FFH (see description of EPROM Status Bytes). If the Redirection Byte is different than this, the master has to complement it to obtain the new page number. Multiplying the page number by 32 (20H) results in the new address the master has to send to the DS2505 to read the updated data replacing the old data. There is no logical limitation in the number of redirections of any page. The only limit is the number of available memory pages within the DS2505. In addition to page redirection, the Extended Read Memory command also supports "bit-oriented" applications where the user cannot store a 16-bit CRC with the data itself. With bit-oriented applications the EPROM information may change over time within a page boundary making it impossible to include an accompanying CRC that will always be valid. Therefore, the Extended Read Memory command concludes each page with the DS2505 generating and supplying a 16-bit CRC that is based on and therefore always consistent with the current data stored in each page of the 16384-bit EPROM data field. After having sent the command code of the Extended Read Memory command, the bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. By sending eight read data time slots, the master receives the Redirection Byte associated with the page given by the starting address. With the next sixteen read data time slots, the bus mas- ter receives a 16-bit CRC of the command byte, address bytes and the Redirection Byte. This CRC is computed by the DS2505 and read back by the bus master to check if the command word, starting address and Redirection Byte were received correctly. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is correct, the bus master issues read time slots and receives data from the DS2505 starting at the initial address and continuing until the end of a 32-byte page is reached. At that point the bus master will send sixteen additional read time slots and receive a 16-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte to the last byte of the current page. With the next 24 read data time slots the master will receive the Redirection Byte of the next page followed by a 16-bit CRC of the Redirection Byte. After this, data is again read from the 16384-bit EPROM data field starting at the beginning of the new page. This sequence will continue until the final page and its accompanying CRC are read by the bus master. The Extended Read Memory command provides a 16-bit CRC at two locations within the transaction flow chart: 1) after the Redirection Byte and 2) at the end of each memory page. The CRC at the end of the memory page is always the result of clearing the CRC generator and shifting in the data bytes beginning at the first addressed memory location of the EPROM data page until the last byte of this page. The CRC received by the bus master directly following the Redirection Byte, is calculated in two different ways. With the initial pass through the Extended Read Memory flow chart the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator, followed by the two address bytes and the Redirection Byte. Subsequent passes through the Extended Read Memory flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the Redirection Byte only. After the 16-bit CRC of the last page is read, the bus master will receive logical 1s from the DS2505 until a Reset Pulse is issued. The Extended Read Memory command sequence can be exited at any point by issuing a Reset Pulse. 020998 11/23 DS2505 WRITE MEMORY [0FH]/SPEED WRITE MEMORY [F3] The Write Memory command is used to program the 16384-bit EPROM data field. The bus master will follow the command byte with a two byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of data (D7:D0). A 16-bit CRC of the command byte, address bytes, and data byte is computed by the DS2505 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. The highest starting address within the DS2505 is 07FFH. If the bus master sends a starting address higher than this, the five most significant address bits are set to zero by the internal circuitry of the chip. This will result in a mismatch between the CRC calculated by the DS2505 and the CRC calculated by the bus master, indicating an error condition. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is correct, a programming pulse (12 volts on the 1-Wire bus for 480 s) is issued by the bus master. Prior to programming, the entire unprogrammed 16384-bit EPROM data field will appear as logical 1s. For each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the selected byte of the 16384-bit EPROM will be programmed to a logical 0 after the programming pulse has been applied at that byte location. After the 480 s programming pulse is applied and the data line returns to the idle level, the bus master issues eight read time slots to verify that the appropriate bits have been programmed. The DS2505 responds with the data from the selected EPROM address sent least significant bit first. This byte contains the logical AND of all bytes written to this EPROM data address. If the EPROM data byte contains 1s in bit positions where the byte issued by the master contained 0s, a Reset Pulse should be issued and the current byte address should be programmed again. If the DS2505 EPROM data byte contains 0s in the same bit positions as the data byte, the programming was successful and the DS2505 will automatically increment its address counter to select the next byte in the 16384-bit EPROM data field. The new two-byte address will also be loaded into the 16-bit CRC generator as a starting value. The bus master will issue the next byte of data using eight write time slots. 020998 12/23 As the DS2505 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the current address and the result is a 16-bit CRC of the new data byte and the new address. After supplying the data byte, the bus master will read this 16-bit CRC from the DS2505 with sixteen read time slots to confirm that the address incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the Write Memory command sequence must be restarted. If the CRC is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. Note that the initial pass through the Write Memory flow chart will generate a 16-bit CRC value that is the result of shifting the command byte into the CRC generator, followed by the two address bytes, and finally the data byte. Subsequent passes through the Write Memory flow chart due to the DS2505 automatically incrementing its address counter will generate a 16-bit CRC that is the result of loading (not shifting) the new (incremented) address into the CRC generator and then shifting in the new data byte. For both of these cases, the decision to continue (to apply a program pulse to the DS2505) is made entirely by the bus master, since the DS2505 will not be able to determine if the 16-bit CRC calculated by the bus master agrees with the 16-bit CRC calculated by the DS2505. If an incorrect CRC is ignored and a program pulse is applied by the bus master, incorrect programming could occur within the DS2505. Also note that the DS2505 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected EPROM byte. The decision to continue is again made entirely by the bus master, therefore if the EPROM data byte does not match the supplied data byte but the master continues with the Write Memory command, incorrect programming could occur within the DS2505. The Write Memory command sequence can be ended at any point by issuing a Reset Pulse. To save time when writing more than one consecutive byte of the DS2505's data memory it is possible to omit reading the 16-bit CRC which allows verification of data and address before the data is copied to the EPROM memory. This saves 16 time slots or 976 s for every byte to be programmed. This speed-programming mode is accessed with the command code F3H instead of 0FH. It follows basically the same flow chart as the DS2505 Write Memory command, but skips sending the CRC immediately preceding the program pulse. This command should only be used if the electrical contact between bus master and the DS2505 is firm since a poor contact may result in corrupted data inside the EPROM memory. WRITE STATUS [55H]/SPEED WRITE STATUS [F5] The Write Status command is used to program the EPROM Status data field. The bus master will follow the command byte with a two byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of status data (D7:D0). A 16-bit CRC of the command byte, address bytes, and data byte is computed by the DS2505 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received. If the CRC read by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated. If the CRC received by the bus master is correct, a programming pulse (12 volts on the 1-Wire bus for 480 s) is issued by the bus master. Prior to programming, the EPROM Status data field will appear as logical 1s. For each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the selected byte of the EPROM Status data field will be programmed to a logical 0 after the programming pulse has been applied at that byte location. After the 480 s programming pulse is applied and the data line returns to the idle level, the bus master issues eight read time slots to verify that the appropriate bits have been programmed. The DS2505 responds with the data from the selected EPROM Status address sent least significant bit first. This byte contains the logical AND of all bytes written to this EPROM Status Byte address. If the EPROM Status Byte contains 1s in bit positions where the byte issued by the master contained 0s, a Reset Pulse should be issued and the current byte address should be programmed again. If the DS2505 EPROM Status byte contains 0s in the same bit positions as the data byte, the programming was successful and the DS2505 will automatically increment its address counter to select the next byte in the EPROM Status data field. The new two-byte address will also be loaded into the 16-bit CRC generator as a starting value. The bus master will issue the next byte of data using eight write time slots. As the DS2505 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the current address and the result is a 16-bit CRC of the new data byte and the new address. After supplying the data byte, the bus master will read this 16-bit CRC from the DS2505 with sixteen read time slots to confirm that the address incremented properly and the data byte was received correctly. If the CRC is incorrect, a Reset Pulse must be issued and the Write Status command sequence must be restarted. If the CRC is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. Note that the initial pass through the Write Status flow chart will generate a 16-bit CRC value that is the result of shifting the command byte into the CRC generator, followed by the two address bytes, and finally the data byte. Subsequent passes through the Write Status flow chart due to the DS2505 automatically incrementing its address counter will generate a 16-bit CRC that is the result of loading (not shifting) the new (incremented) address into the CRC generator and then shifting in the new data byte. For both of these cases, the decision to continue (to apply a program pulse to the DS2505) is made entirely by the bus master, since the DS2505 will not be able to determine if the 16-bit CRC calculated by the bus master agrees with the 16-bit CRC calculated by the DS2505. If an incorrect CRC is ignored and a program pulse is applied by the bus master, incorrect programming could occur within the DS2505. Also note that the DS2505 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected EPROM byte. The decision to continue is again made entirely by the bus master, therefore if the EPROM data byte does not match the supplied data byte but the master continues with the Write Status command, incorrect programming could occur within the DS2505. The Write Status command sequence can be ended at any point by issuing a Reset Pulse. To save time when writing more than one consecutive byte of the DS2505's status memory it is possible to omit reading the 16-bit CRC which allows verification of data and address before the data is copied to the EPROM memory. This saves 16 time slots or 976 s for every byte to be programmed. This speed-programming 020998 13/23 DS2505 mode is accessed with the command code F5H instead of 55H. It follows basically the same flow chart as the Write Status command, but skips sending the CRC immediately preceding the program pulse. This command should only be used if the electrical contact between bus master and the DS2505 is firm since a poor contact may result in corrupted data inside the EPROM status memory. 1-WIRE BUS SYSTEM The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances, the DS2505 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signalling (signal type and timing). A 1-Wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards. Hardware Configuration The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an open drain connection or 3-state outputs. The DS2505 is an open drain part with an internal circuit equivalent to that shown in Figure 6. The bus master can be the same equivalent circuit. If a bidirectional pin is not available, separate output and input pins can be tied together. The bus master requires a pull-up resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in Figures 7a and 7b. The value of the pull-up resistor should be approximately 5k for short line lengths. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3k bits per second. If the bus master is also required to perform programming of the EPROM por- 020998 14/23 tions of the DS2505, a programming supply capable of delivering up to 10 milliamps at 12 volts for 480 s is required. The idle state for the 1-Wire bus is high. If, for any reason, a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 120 s, one or more of the devices on the bus may be reset. Transaction Sequence The sequence for accessing the DS2505 via the 1-Wire port is as follows: * Initialization * ROM Function Command * Memory Function Command * Read/Write Memory/Status INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS2505 is on the bus and is ready to operate. For more details, see the "1-Wire Signalling" section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the four ROM function commands. All ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in Figure 8): Read ROM [33H] This command allows the bus master to read the DS2505's 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can be used only if there is a single DS2505 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result). DS2505 DS2505 EQUIVALENT CIRCUIT Figure 6 RX DATA 5 A TYP. TX 100 MOSFET GROUND BUS MASTER CIRCUIT Figure 7 12V A) OPEN DRAIN VDD VDD BUS MASTER 10k DS5000 OR 8051 EQUIVALENT 10k 5k S D OPEN DRAIN PORT PIN S RX VP0300L OR VP0106N3 OR BSS110 D TO DATA CONNECTION OF DS2505 2N7000 D TX D PGM 2N7000 470 pF S CAPACITOR ADDED TO REDUCE COUPLING ON DATA LINE DUE TO PROGRAMMING SIGNAL SWITCHING S 2N7000 B) STANDARD TTL VDD BUS MASTER VDD TTL-EQUIVALENT PORT PINS 5k 12V (10 mA min.) PROGRAMMING PULSE TO DATA CONNECTION OF DS2505 RX TX 5k 020998 15/23 DS2505 ROM FUNCTIONS FLOW CHART Figure 8 MASTER TX RESET PULSE DS2505 TX PRESENCE PULSE MASTER TX ROM FUNCTION COMMAND 33h READ ROM COMMAND N 55h MATCH ROM COMMAND F0h SEARCH ROM COMMAND N Y Y Y DS2505 TX BIT 0 DS2505 TX FAMILY CODE 1 BYTE MASTER TX BIT 0 DS2505 TX BIT 0 MASTER TX BIT 0 N BIT 0 MATCH? N BIT 0 MATCH? Y Y DS2505 TX SERIAL NUMBER 6 BYTES DS2505 TX CRC BYTE DS2505 TX BIT 1 DS2505 TX BIT 1 MASTER TX BIT 1 MASTER TX BIT 1 N BIT 1 MATCH? N BIT 1 MATCH? Y Y DS2505 TX BIT 63 MASTER TX BIT 63 DS2505 TX BIT 63 MASTER TX BIT 63 BIT 63 MATCH? N N Y Y MASTER TX MEMORY FUNCTION COMMAND (SEE FIGURE 5) 020998 16/23 BIT 63 MATCH? N CCh SKIP ROM COMMAND Y N DS2505 Match ROM [55H] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS2505 on a multidrop bus. Only the DS2505 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus. required to begin any communication with the DS2505 is shown in Figure 9. A reset pulse followed by a presence pulse indicates the DS2505 is ready to accept a ROM command. The bus master transmits (TX) a reset pulse (tRSTL, minimum 480 s). The bus master then releases the line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pull-up resistor. After detecting the rising edge on the data pin, the DS2505 waits (tPDH, 15-60 s) and then transmits the presence pulse (tPDL, 60-240 s). Skip ROM [CCH] This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pull-downs will produce a wired-AND result). Search ROM [F0H] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their 64-bit ROM codes. The search ROM command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The ROM search process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the ROM in one device. The remaining number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a ROM search, including an actual example. 1-Wire Signalling The DS2505 requires strict protocols to insure data integrity. The protocol consists of five types of signalling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, Read Data and Program Pulse. All these signals except presence pulse are initiated by the bus master. The initialization sequence Read/Write Time Slots The definitions of write and read time slots are illustrated in Figure 10. All time slots are initiated by the master driving the data line low. The falling edge of the data line synchronizes the DS2505 to the master by triggering a delay circuit in the DS2505. During write time slots, the delay circuit determines when the DS2505 will sample the data line. For a read data time slot, if a "0" is to be transmitted, the delay circuit determines how long the DS2505 will hold the data line low overriding the 1 generated by the master. If the data bit is a "1", the device will leave the read data time slot unchanged. PROGRAM PULSE To copy data from the 8-bit scratchpad to the EPROM Data or Status Memory, a program pulse of 12 volts is applied to the data line after the bus master has confirmed that the CRC for the current byte is correct. During programming, the bus master controls the transition from a state where the data line is idling high via the pull-up resistor to a state where the data line is actively driven to a programming voltage of 12 volts providing a minimum of 10 mA of current to the DS2505. This programming voltage (Figure 11) should be applied for 480 s, after which the bus master returns the data line to an idle high state controlled by the pull-up resistor. Note that due to the high voltage programming requirements for any 1-Wire EPROM device, it is not possible to multi-drop non-EPROM based 1-Wire devices with the DS2505 during programming. An internal diode within the non-EPROM based 1-Wire devices will attempt to clamp the data line at approximately 8 volts and could potentially damage these devices. 020998 17/23 DS2505 INITIALIZATION PROCEDURE "RESET AND PRESENCE PULSES" Figure 9 MASTER TX "RESET PULSE" MASTER RX "PRESENCE PULSE" tRSTH VPULLUP VPULLUP MIN VIH MIN VIL MAX 0V tRSTL tPDL tR tPDH RESISTOR 480 s < tRSTL < * 480 s < tRSTH < (includes recovery time) 15 s < tPDH < 60 s 60 s < tPDL < 240 s MASTER DS2505 * In order not to mask interrupt signalling by other devices on the 1-Wire bus, tRSTL + tR should always be less than 960 s. READ/WRITE TIMING DIAGRAM Figure 10 Write-one Time Slot tSLOT VPULLUP VPULLUP MIN VIH MIN DS2505 SAMPLING WINDOW VIL MAX 0V tLOW1 15 s 60 s RESISTOR 60 s < tSLOT < 120 s 1 s < tLOW1 < 15 s MASTER 1 s < tREC < DS2505 020998 18/23 tREC DS2505 READ/WRITE TIMING DIAGRAM (cont'd) Figure 10 Write-zero Time Slot tREC tSLOT VPULLUP VPULLUP MIN VIH MIN DS2505 SAMPLING WINDOW VIL MAX 0V 15 s 60 s tLOW0 60 s < tLOW0 < tSLOT < 120 s 1 s < tREC < Read-Data Time Slot tSLOT tREC VPULLUP VPULLUP MIN VIH MIN MASTER SAMPLING WINDOW VIL MAX 0V tSU tRELEASE tLOWR tRDV 60 s < tSLOT < 120 s 1 s < tLOWR < 15 s 0 < tRELEASE < 45 s RESISTOR MASTER 1 s < tREC < tRDV = 15 s tSU < 1 s DS2505 PROGRAM PULSE TIMING DIAGRAM Figure 11 VPP VPULLUP tRP tFP GND NORMAL 1-Wire COMMUNICATION ENDS >5 s 480 s >5 s tDP tPP tDV NORMAL 1-Wire COMMUNICATION RESUMES LINE TYPE LEGEND: Bus master active high (12V @ 10 mA) Resistor pull-up 020998 19/23 DS2505 CRC GENERATION With the DS2505 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is a 8-bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2505 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRC is: X8 + X5 + X4 + 1. This 8-bit CRC is received in the true (non- inverted) form when reading the ROM of the DS2505. It is computed once at the factory and lasered into the ROM. The other CRC is a 16-bit type, generated according to the standardized CRC16-polynomial function X16 + X15 + X2 + 1. This CRC is used to safeguard user-defined EPROM data when reading data memory or status memory. It is the same type of CRC as is used with NV RAM based iButtons to safeguard data packets of the iButton File Structure. In contrast to the 8-bit CRC, the 16-bit CRC is always returned in the complemented (inverted) form. A CRC-generator inside the DS2505 chip (Figure 12) will calculate a new 16-bit CRC at every situation shown in the command flow chart of Figure 5. The DS2505 provides this CRC-value to the bus master to validate the transfer of command, address, and data to and from the bus master. When reading the data memory of the DS2505 with the Read Memory command, the 16-bit CRC is only transmitted as the end of the memory is reached. This CRC is generated by clearing the CRC generator, shifting in the command, low address, high address and every data byte starting at the first addressed memory location and continuing until the end of the implemented data memory is reached. When reading the status memory with the Read Status command, the 16-bit CRC is transmitted when the end of each 8-byte page of the status memory is reached. At the initial pass through the Read Status flow chart the 16-bit CRC will be generated by clearing the CRC generator, shifting in the command byte, low address, high address and the data bytes beginning at the first addressed memory location and continuing until the last byte of the addressed EPROM Status data page is reached. Subsequent passes through the Read Status 020998 20/23 flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the new data bytes starting at the first byte of the next page of the EPROM Status data field and continuing until the last byte of the page is reached. When reading the data memory of the DS2505 with the Extended Read Memory command, there are two situations where a 16-bit CRC is transmitted. One 16-bit CRC follows each Redirection Byte, another 16-bit CRC is received after the last byte of a memory data page is read. The CRC at the end of the memory page is always the result of clearing the CRC generator and shifting in the data bytes beginning at the first addressed memory location of the EPROM data page until the last byte of this page. With the initial pass through the Extended Read Memory flow chart the 16-bit CRC value is the result of shifting the command byte into the cleared CRC generator, followed by the two address bytes and the Redirection Byte. Subsequent passes through the Extended Read Memory flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in the Redirection Byte only. When writing to the DS2505 (either data memory or status memory), the bus master receives a 16-bit CRC to verify the correctness of the data transfer before applying the programming pulse. With the initial pass through the Write Memory/Status flow chart the 16-bit CRC will be generated by clearing the CRC-generator, shifting in the command, address low, address high and the data byte. Subsequent passes through the Write Memory/ Status flow chart due to the DS2505 automatically incrementing its address counter will generate an 16-bit CRC that is the result of loading (not shifting) the new (incremented) address into the CRC generator and then shifting in the new data byte. The comparison of CRC values and decision to continue with an operation are determined entirely by the bus master. There is no circuitry on the DS2505 that prevents a command sequence from proceeding if the CRC stored in or calculated by the DS2505 does not match the value generated by the bus master. For more details on generating CRC values including example implementations in both hardware and software, see the Book of DS19xx iButton Standards. DS2505 CRC-16 HARDWARE DESCRIPTION AND POLYNOMIAL Figure 12 Polynomial = X16 + X15 + X2 + 1 1ST STAGE X0 2ND STAGE 3RD STAGE X1 9TH STAGE X2 10TH STAGE X9 X3 11TH STAGE X10 4TH STAGE 12TH STAGE X11 5TH STAGE X4 13TH STAGE X12 6TH STAGE X5 14TH STAGE X13 7TH STAGE X6 8TH STAGE X7 15TH STAGE X14 X8 16TH STAGE X15 X16 CRC OUTPUT INPUT DATA 020998 21/23 DS2505 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.5V to +12.0V -40C to +85C -55C to +125C 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS PARAMETER (VPUP=2.8V to 6.0V; -40C to +85C) SYMBOL MIN VIH 2.2 Logic 0 VIL -0.3 Output Logic Low @ 4 mA VOL Output Logic High VOH VPUP Input Load Current IL 5 Operating Charge QOP Programming Voltage @ 10 mA VPP 11.5 PARAMETER SYMBOL MIN Data (1-Wire) CIN/OUT Logic 1 TYP MAX UNITS NOTES V 1, 6 +0.8 V 1, 10 0.4 V 1 6.0 V 1, 2 A 3 7, 8 30 nC 12.0 V MAX UNITS NOTES 800 pF 9 (tA = 25C) CAPACITANCE TYP AC ELECTRICAL CHARACTERISTICS PARAMETER (VPUP=2.8V to 6.0V; -40C to +85C) SYMBOL MIN Time Slot tSLOT 60 Write 1 Low Time tLOW1 Write 0 Low Time tLOW0 Read Data Valid Release Time MAX UNITS 120 s 1 15 s 60 120 s tRDV tRELEASE TYP s exactly 15 0 15 45 s 1 s Read Data Setup tSU Recovery Time tREC 1 s Reset Time High tRSTH 480 s Reset Time Low s tRSTL 480 Presence Detect High tPDHIGH 15 60 s Presence Detect Low 240 s tPDLOW 60 Delay to Program tDP 5 s Delay to Verify tDV 5 s Program Pulse Width tPP 480 s Program Voltage Rise Time tRP 0.5 5.0 s Program Voltage Fall Time tFP 0.5 5.0 s 020998 22/23 NOTES 5 4 DS2505 NOTES: 1. All voltages are referenced to ground. 2. VPUP = external pull-up voltage. If VPUP is lower than 3.0V the first byte read (any read command) may not reproduce the correct memory contents. Therefore, under low voltage conditions, it is recommended to set either the most significant bit or all five most significant bits of TA2 to 1. Internal circuitry of the chip will force these five bits back to zero before they are shifted in the address counter and CRC generator. 3. Input load is to ground. 4. An additional reset or communication sequence cannot begin until the reset high time has expired. 5. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1 s of this falling edge and will remain valid for 14 s minimum. (15 s total from falling edge on 1-Wire bus.) 6. VIH is a function of the external pull-up resistor and VPUP. 7. 30 nanocoulombs per 72 time slots @ 5.0V. 8. At VCC=5.0V with a 5k pullup to VCC and a maximum time slot of 120 s. 9. Capacitance on the data pin could be 800 pF when power is first applied. If a 5k resistor is used to pull up the data line to VCC, 5 s after power has been applied the parasite capacitance will not affect normal communications. 10. Under certain low voltage conditions VILMAX may have to be reduced to as much as 0.5V to always guarantee a presence pulse. 020998 23/23