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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT PD16740 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES) The PD16740 is a source driver for TFT-LCDs capable of dealing with displays with 256 gray scales. Data input is based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,700,000 colors by output of 256 values -corrected by an internal D/A converter and 11 external power modules. Because the output dynamic range is as large as VSS2 + 0.1 V to Vref - 0.1 V, level inversion operation of the LCD's common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 8-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. The D/A converter, which incorporates a digital offset circuit, is suitable for an LCD panel in which liquid crystal transmittance in positive and negative polarities is different. Assuring a maximum clock frequency of 40 MHz when driving at 3.0 V, this driver is applicable to SXGA and XGA-standard TFT-LCD panels. FEATURES * CMOS level input * 384-output channel * Input of 8 bits (gradation data) by 6 dots * Capable of outputting 256 values by means of 11 external power modules and a D/A converter (C-DAC) * Logic Part Power Supply Voltage (VDD1) : 3.3 0.3 V * Driver Part Power Supply Voltage (VDD2) : 8.5 0.5 V * High-speed data transfer: fMAX. = 40 MHz (internal data transfer speed when operating at VDD1 = 3.0 V) * Output dynamic range VSS2 + 0.1 V to Vref - 0.1 V * Apply for dot-line inversion, n-line inversion and column line inversion * Output voltage polarity reverse is possible (POLA) * Input data reverse function is incorporated (POLB) ORDERING INFORMATION Part Number Package PD16740N-xxx TCP (TAB package) Remark The TCP's external shape is custom-order item. Users are requested to consult with a NEC sales representative. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S12930EJ1V0DS00 (1st edition) Date Published May 1999 NS CP(K) Printed in Japan 1998,1999 PD16740 1. BLOCK DIAGRAM STHR R,/L CLK STHL VDD1 (3.3 V) VSS1 64-bit bidirectional shift register C1 C2 D00 - D07 D10 - D17 D20 - D27 D30 - D37 D40 - D47 D50 - D57 POLB DWsel C63 C64 Data register STB Latch VDD2 (8.5 V) Level shifter VSS2 INH POLA V0 - V9 Vref D/A converter & Output buffer S1 S2 S383 S384 Remark /xxx indicates active low signal. 2 Data Sheet S12930EJ1V0DS00 PD16740 2. PIN CONFIGURATION ( PD16740N-xxx xxx) xxx VSS2 VDD2 V8 V6 V4 V2 V0 R,/L D50 D51 D52 D53 D54 D55 D56 D57 D40 D41 D42 D43 D44 D45 D46 D47 D30 D31 D32 D33 D34 D35 D36 D37 POLB POLA STB INH STHL DWsel VDD1 CLK VSS1 STHR D20 D21 D22 D23 D24 D25 D26 D27 D10 D11 D12 D13 D14 D15 D16 D17 D00 D01 D02 D03 D04 D05 D06 D07 V1 V3 V5 V7 V9 Vref VDD2 VSS2 S384 S383 S382 Copper Foil Surface S3 S2 S1 Remark This figure does not specify the TCP package. Data Sheet S12930EJ1V0DS00 3 PD16740 3. PIN FUNCTIONS Pin Symbol Pin Name Description S1 to S384 Driver output The D/A converted 64/256-gray-scale analog voltage is output. D00 to D07 Display data The display data is input in either a 48-bit width of 8-bit gray-scale data x 6 dots (2 pixels) or in a 36-bit width of 6-bit gray-scale data x 6 dots (2 pixels). D10 to D17 In 8-bit input: DX7: MSB, DX0: LSB D20 to D27 In 6-bit input: DX7: MSB, DX2: LSB D30 to D37 In 6-bit input (DWsel = L), the Dn0 and Dn1 pins are fixed to low in the IC. Therefore, be sure to leave them open on TCP. D40 to D47 D50 to D57 DWsel 6-/8-bit input control This pin switches the bit width of the display data between 6 bits and 8 bits. DWsel = H: 8-bit input DWsel = L: 6-bit input This pin is pulled down internally. R,/L Shift direction control input These refer to the start pulse input/output pins when driver ICs are connected in cascade. The shift directions of the shift registers are as follows. R,/L = H(Right shift) : STHR (input) S1 S384 STHL (output) R,/L = L (Left shift) : STHL (input) S384 S1 STHR (output) STHR Right shift start pulse input/output Start pulse I/O pin at cascade connection. The display data is acquired when the STHL Left shift start pulse input/output Right shift : STHR is input. STHL is output. CLK Shift clock input Refers to the shift register's shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 64th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. Start pulse high level is read at rising edge of CLK, start to load the display data from next rising edge of CLK. Also, after start pulse input and CLK input 66 pulses, it stops to load the display data and it makes contents of shift register clear at rising edge of STB. STB Latch input After the contents of data register is transferred to a latch at a rising edge and is cleared, operation of analog output voltage for output voltage is started. INH Inhibit input At the falling edge complete calculation of analog output voltage, and output the high level is read at the rising edge of CLK. Left shift : STHL is input. STHR is output. voltage appointed by display data. POLA Polarity input This signal is read at the rising edge of latch signal and determines the output voltage polarity to reference voltage of each output pin. POLA = L : Pins with even number are negative output. Pins with odd number are positive output. POLA = H : Pins with even number are positive output. Pins with odd number are negative output. POLB Data inversion By inputting a switching signal to this pin, this pin enables the data whose polarity is reversed to be read. POLB = H : Acquires with displayed data reversed POLB = L : Acquires raw displayed data Vref Reference power supply V0 to V9 -corrected power supplies This terminal is the input reference power supply need to calculation output. Please refer to 4. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE. Input the -corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. Vref - 0.1 V V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VSS2 + 0.1 V Vref - 0.1 V V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 VSS2 + 0.1 V During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. 4 VDD1 Logic power supply 3.3 V 0.3 V VDD2 Driver power supply 8.5 V 0.5 V VSS1 Logic ground Grounding VSS2 Driver ground Grounding Data Sheet S12930EJ1V0DS00 PD16740 Cautions 1. The power start sequence must be VDD1 logic input VDD2 Vref V0 to V9 in that order. Reverse this sequence to shut down. Be sure to observe this power sequence even during a transition period. 2. To stabilize the supply voltage, please be sure to insert each 0.1 F, 0.47 F bypass capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 F is also advised between the corrected power supply terminals (V0, V1, V2, ***, V9) and VSS2. 3. This IC employs the C-DAC circuit to control gray-scale generation. The -corrected voltage is sampled between the rising of the STB signal and the rising of the INH signal, and the corrected voltage is output from the driver output pin two or three clocks after the INH signal falls. That is, each gray-scale voltage is determined by sampling -corrected voltage. At this time, a large transient current flows instantly into the -corrected power supply pin. Therefore, when inputting -corrected voltage and -corrected reference voltage, an operational amplifier is recommended to reduce the input impedance of this pin. In addition to this, the voltage to be input to this pin needs to be stabilized. When a switching signal with high frequency is input to the -corrected power supply pin, the application voltage becomes unstable and display may be abnormal. For details of the output timing, refer to 9. SWITCHING CHARACTERISTICS WAVEFORM. 4. When this product is used as a 6-bit driver (DWsel = L), the wiring for the Dn1 and Dn2 (lower 2 bits of display data) pins must be left open on the TCP, since they are forcibly short-circuited to VSS1 in the IC. Data Sheet S12930EJ1V0DS00 5 PD16740 4. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE 4.1 Calculation of output voltage in 8-bit input (DWsel = H, Vref - 0.1 V V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VSS2 + 0.1 V ) Gray Binary Scale 6 Input Data Output Voltage DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 S2n-1 (POLA=H), S2n (POLA=L) Output Voltage S2n(POLA=H),S2n-1(POLA=L) 0 00H 0 0 0 0 0 0 0 0 2Vref - {V8+(V9 - V8) x 31/32} V8+(V9-V8) x 31/32 1 01H 0 0 0 0 0 0 1 1 2Vref - {V8+(V9 - V8) x 30/32} V8+(V9-V8) x 30/32 30 1EH 0 0 0 1 1 1 1 0 2Vref - {V8+(V9 - V8) x 1/32} V8+(V9-V8) x 1/32 31 1FH 0 0 0 1 1 1 1 1 2Vref - V8 V8 32 20H 0 0 1 0 0 0 0 0 2Vref - {V7+(V8 - V7) x 31/32} V7+(V8-V7) x 31/32 33 21H 0 0 1 0 0 0 1 1 2Vref - {V7+(V8 - V7) x 30/32} V7+(V8-V7) x 30/32 62 3EH 0 0 1 1 1 1 1 0 2Vref - {V7+(V8 - V7) x 1/32} V7+(V8-V7) x 1/32 63 3FH 0 0 1 1 1 1 1 1 2Vref - V7 V7 64 40H 0 1 0 0 0 0 0 0 2Vref - {V6+(V7 - V6) x 31/32} V6+(V7-V6) x 31/32 65 41H 0 1 0 0 0 0 1 1 2Vref - {V6+(V7 - V6) x 30/32} V6+(V7-V6) x 30/32 94 5EH 0 1 0 1 1 1 1 0 2Vref - {V6+(V7 - V6) x 1/32} V6+(V7-V6) x 1/32 95 5FH 0 1 0 1 1 1 1 1 2Vref - V6 V6 96 60H 0 1 1 0 0 0 0 0 2Vref - {V5+(V6 - V5) x 31/32} V5+(V6-V5) x 31/32 97 61H 0 1 1 0 0 0 1 1 2Vref - {V5+(V6 - V5) x 30/32} V5+(V6-V5) x 30/32 126 7EH 0 1 1 1 1 1 1 0 2Vref - {V5+(V6 - V5) x 1/32} V5+(V6-V5) x 1/32 127 7FH 0 1 1 1 1 1 1 1 2Vref - V5 V5 128 80H 1 0 0 0 0 0 0 0 2Vref - {V4+(V5 - V4) x 31/32} V4+(V5-V4) x 31/32 129 81H 1 0 0 0 0 0 1 1 2Vref - {V4+(V5 - V4) x 30/32} V4+(V5-V4) x 30/32 158 9EH 1 0 0 1 1 1 1 0 2Vref - {V4+(V5 - V4) x 1/32} V4+(V5-V4) x 1/32 159 9FH 1 0 0 1 1 1 1 1 2Vref - V4 V4 160 A0H 1 0 1 0 0 0 0 0 2Vref - {V3+(V4 - V3) x 31/32} V3+(V4-V3) x 31/32 161 A1H 1 0 1 0 0 0 1 1 2Vref - {V3+(V4 - V3) x 30/32} V3+(V4-V3) x 30/32 190 BEH 1 0 1 1 1 1 1 0 2Vref - {V3+(V4 - V3) x 1/32} V3+(V4-V3) x 1/32 191 BFH 1 0 1 1 1 1 1 1 2Vref - V3 V3 192 C0H 1 1 0 0 0 0 0 0 2Vref - {V2+(V3 - V2) x 31/32} V2+(V3-V2) x 31/32 193 C1H 1 1 0 0 0 0 1 1 2Vref - {V2+(V3 - V2) x 30/32} V2+(V3-V2) x 30/32 222 DEH 1 1 0 1 1 1 1 0 2Vref - {V2+(V3 - V2) x 1/32} V2+(V3-V2) x 1/32 223 DFH 1 1 0 1 1 1 1 1 2Vref - V2 V2 224 E0H 1 1 1 0 0 0 0 0 2Vref - {V1+(V2 - V1) x 31/32} V1+(V2-V1) x 31/32 225 E1H 1 1 1 0 0 0 1 1 2Vref - {V1+(V2 - V1) x 30/32} V1+(V2-V1) x 30/32 254 FEH 1 1 1 1 1 1 1 0 2Vref - {V1+(V2 - V1) x 1/32} V1+(V2-V1) x 1/32 255 FFH 1 1 1 1 1 1 1 1 2Vref - V0 V0 Data Sheet S12930EJ1V0DS00 PD16740 4.2 Curved line of output voltage in 8-bit input (DWsel = H, POLA = H, Vref - 0.1 V V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VSS2 + 0.1 V) VDD2 0.1 V S2n Vref V0 V1 V2 S2n-1 V3 V4 V5 V6 V7 V8 V9 0.1 V VSS2 00 H 1F H 3F H 5F H 7F H 9F H BF H DF H FE H FF H Input data (HEX) Data Sheet S12930EJ1V0DS00 7 PD16740 4.3 Calculation of output voltage in 6-bit input (DWsel = L, Vref - 0.1 V V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VSS2 + 0.1 V ) Gray Binary Scale 8 Input Data Output Voltage DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 S2n-1 (POLA=H), S2n (POLA=L) Output Voltage S2n(POLA=H),S2n-1(POLA=L) 0 00H 0 0 0 0 0 0 0 0 2Vref - {V8+(V9 - V8) x 7/8} V8+(V9-V8) x 7/8 1 01H 0 0 0 0 0 1 0 0 2Vref - {V8+(V9 - V8) x 6/8} V8+(V9-V8) x 6/8 6 06H 0 0 0 1 1 0 0 0 2Vref - {V8+(V9 - V8) x 1/8} V8+(V9-V8) x 1/8 7 07H 0 0 0 1 1 1 0 0 2Vref - V8 V8 8 08H 0 0 1 0 0 0 0 0 2Vref - {V7+(V8 - V7) x 7/8} V7+(V8-V7) x 7/8 9 09H 0 0 1 0 0 1 0 0 2Vref - {V7+(V8 - V7) x 6/8} V7+(V8-V7) x 6/8 14 0EH 0 0 1 1 1 0 0 0 2Vref - {V7+(V8 - V7) x 1/8} V7+(V8-V7) x 1/8 15 0FH 0 0 1 1 1 1 0 0 2Vref - V7 V7 16 10H 0 1 0 0 0 0 0 0 2Vref - {V6+(V7 - V6) x 7/8} V6+(V7-V6) x 7/8 17 11H 0 1 0 0 0 1 0 0 2Vref - {V6+(V7 - V6) x 6/8} V6+(V7-V6) x 6/8 22 16H 0 1 0 1 1 0 0 0 2Vref - {V6+(V7 - V6) x 1/8} V6+(V7-V6) x 1/8 23 17H 0 1 0 1 1 1 0 0 2Vref - V6 V6 24 18H 0 1 1 0 0 0 0 0 2Vref - {V5+(V6 - V5) x 7/8} V5+(V6-V5) x 7/8 25 19H 0 1 1 0 0 1 0 0 2Vref - {V5+(V6 - V5) x 6/8} V5+(V6-V5) x 6/8 30 1EH 0 1 1 1 1 0 0 0 2Vref - {V5+(V6 - V5) x 1/8} V5+(V6-V5) x 1/8 31 1FH 0 1 1 1 1 1 0 0 2Vref - V5 V5 32 20H 1 0 0 0 0 0 0 0 2Vref - {V4+(V5 - V4) x 7/8} V4+(V5-V4) x 7/8 33 21H 1 0 0 0 0 1 0 0 2Vref - {V4+(V5 - V4) x 6/8} V4+(V5-V4) x 6/8 38 26H 1 0 0 1 1 0 0 0 2Vref - {V4+(V5 - V4) x 1/8} V4+(V5-V4) x 1/8 39 27H 1 0 0 1 1 1 0 0 2Vref - V4 V4 40 28H 1 0 1 0 0 0 0 0 2Vref - {V3+(V4 - V3) x 7/8} V3+(V4-V3) x 7/8 41 29H 1 0 1 0 0 1 0 0 2Vref - {V3+(V4 - V3) x 6/8} V3+(V4-V3) x 6/8 46 2EH 1 0 1 1 1 0 0 0 2Vref - {V3+(V4 - V3) x 1/8} V3+(V4-V3) x 1/8 47 2FH 1 0 1 1 1 1 0 0 2Vref - V3 V3 48 30H 1 1 0 0 0 0 0 0 2Vref - {V2+(V3 - V2) x 7/8} V2+(V3-V2) x 7/8 49 31H 1 1 0 0 0 1 0 0 2Vref - {V2+(V3 - V2) x 6/8} V2+(V3-V2) x 6/8 54 36H 1 1 0 1 1 0 0 0 2Vref - {V2+(V3 - V2) x 1/8} V2+(V3-V2) x 1/8 55 37H 1 1 0 1 1 1 0 0 2Vref - V2 V2 56 38H 1 1 1 0 0 0 0 0 2Vref - {V1+(V2 - V1) x 7/8} V1+(V2-V1) x 7/8 57 39H 1 1 1 0 0 1 0 0 2Vref - {V1+(V2 - V1) x 6/8} V1+(V2-V1) x 6/8 63 3EH 1 1 1 1 1 0 0 0 2Vref - {V1+(V2 - V1) x 1/8} V1+(V2-V1) x 1/8 64 3FH 1 1 1 1 1 1 0 0 2Vref - V0 V0 Data Sheet S12930EJ1V0DS00 PD16740 4.4 Curved line of output voltage in 6-bit input (DWsel = L, POLA = H, Vref - 0.1 V V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VSS2 + 0.1 V) VDD2 0.1 V S2n Vref V0 V1 V2 S2n-1 V3 V4 V5 V6 V7 V8 V9 0.1 V VSS2 00 H 07 H 0F H 17 H 1F H 20 H 2F H 30 H 3E H 3F H Input data (HEX) Data Sheet S12930EJ1V0DS00 9 PD16740 5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN The reference power supply of the D/A converter is made up of a capacitance ladder circuit, which minimizes current flow into the - corrected power supply pins. However, in the LCD driver of previous R-DAC systems the resistance ratio between the - corrected power supply pins was set to be identical to the - corrected voltage ratio used for an actual LCD panel. Such a function is not available in this product. Therefore, - corrected voltage directly becomes D/A converter reference power voltage in the IC. Determine - corrected voltage based on the data of characteristics of a LCD panel described in 4. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE. 6. INPUT FORMAT OF DISPLAY DATA Data format : 8/6 bits x 2 RGBs (6 dots) Input width : 48/36 bits (2-pixel data) (1) R,/L = H (Right shift) Output S1 S2 S3 S4 xxx S383 S384 Data D00 to D05/07 D10 to D15/17 D20 to D25/27 D30 to D35/37 xxx D40 to D45/47 D50 to D55/57 (2) R,/L = L (Left shift) Output S1 S2 S3 S4 xxx S383 S384 Data D00 to D05/07 D10 to D15/17 D20 to D25/27 D30 to D35/37 xxx D40 to D45/47 D50 to D55/57 7. RELATIONSHIP BETWEEN STB, POL, AND OUTPUT WAVEFORM The output buffer consists of an operational amplifier circuit that does not perform recharge operation. Therefore, driver output current IVOH is the charging current to the LCD, and IVOL is the discharging current. STB INH POL S2n-1 Selected voltage of V0 to V4 Selected voltage of V0 to V4 Selected voltage of V5 to V9 S2n Selected voltage of V5 to V9 Hi-Z 10 Selected voltage of V0 to V4 Hi-Z Data Sheet S12930EJ1V0DS00 Selected voltage of V5 to V9 Hi-Z PD16740 8. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = +25C, VSS1 = VSS2 = 0 V) Parameter Symbol Ratings Unit Logic Part Power Supply Voltage VDD1 -0.5 to + 5.0 V Driver Part power Supply Voltage VDD2 -0.5 to + 10.0 V Logic Part Input Voltage VI1 -0.5 to VDD1 + 0.5 V Driver Part Input Voltage VI2 -0.5 to VDD2 + 0.5 V Logic Part Output Voltage VO1 -0.5 to VDD1 + 0.5 V Driver Part Output Voltage VO2 -0.5 to VDD2 + 0.5 V Operating Temperature Range TA -10 to +75 C Storage Temperature Range Tstg -55 to +125 C Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Recommended Operating Range (TA = -10 to +75C, VSS1 = VSS2 = 0 V) Parameter Symbol MIN. TYP. MAX. Unit Logic Part Supply Voltage VDD1 3.0 3.3 3.6 V Driver Part Supply Voltage VDD2 8.0 8.5 9.0 V VO VSS2 + 0.1 VDD2 - 0.1 V V0 to V9 VSS2 + 0.1 Vref - 0.1 V 5.0 V Driver Part Output Voltage Range -Corrected Voltage -Corrected Reference Power Supply Vref Maximum Clock Frequency fMAX. 0.5 VDD2 40 Data Sheet S12930EJ1V0DS00 MHz 11 PD16740 Electrical Characteristics (TA = -10 to + 75C, VDD1 = 3.3 V 0.3 V, VDD2 = 8.5 V 0.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. High-Level Input Voltage VIH CLK,STB,R,/L,INH,POLA,POLB, Low-level Input Voltage VIL Input Leak Current IIL MAX. Unit 0.7 VDD2 VDD2 V D00 to D07, D10 to D17, D20 to D27, VSS2 0.3 VDD2 V D30 to D37, D40 to D47, D50 to D57 -1.0 +1.0 A High-Level Output Voltage VOH STHR (STHL), IOH = -1.0 mA Low-level Output Voltage VOL STHR (STHL), IOL = +1.0 mA Driver Output Current IVOH VDD1 = 3.3 V , INH = 0 V, (VDD2 = 8.5 V) VOUT = 7.9 V , VO = 8.4 V IVOL VO Output Voltage Deviation VDD1 - 0.5 V -90 VSS1 + 0.5 V -40 mA Note VDD1 = 3.3 V , INH = 0 V, VOUT = 0.6 V , VO = 0.1 V TYP. 40 90 mA Note VDD1 = 3.3 V , VDD2 = 8.5 V, VOUT = 0.5 / 3.0 / 5.0 / 8.0 V 18 25 mV Note Logic Part Dynamic Current Consumption I DD1 VDD1 = 3.3 V, with no load 1.2 4.0 mA Driver Part Dynamic Current Consumption I DD2 VDD2 = 8.5 V, with no load 4.0 12.0 mA Note VOUT indicates application voltage to output pins. V0 indicates output voltage to output pins. Caution For logic part dynamic current consumption, the TYP. value is based on the condition while the screen is displayed in entirely dark or entirely light and the MAX. value is based on the condition while the screen is displayed in chess board pattern. Switching Characteristics (TA = -10 to +75C, VDD1 = 3.3 V 0.3 V, VDD2 = 8.5 V 0.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition Start Pulse Delay Time tPLH1 CL = 10 pF, CLK STHL (STHR) Driver Output Delay Time tPLH2 VDD2 = 8.5 V, tPLH3 RL = 5.0 k, tPHL2 CL = 35 pF x 2 VO = 0.1 V 8.4 V VO = 8.4 V 0.1 V tPHL3 Input Capacitance 12 MIN. TYP. MAX. Unit 2 4.3 20 ns 2.8 6.0 s 9.1 12.0 s 1.6 6.0 s 9.0 12.0 s CI1 TA = +25C , STHR (STHL), V0 to V9,Vref 8 15 pF CI2 TA = +25C, STHR(STHL), V0 to V9, Except Vref 6 10 pF Data Sheet S12930EJ1V0DS00 PD16740 Timing Requirement (TA = -10 to +75C, VDD1 = 3.3 V 0.3 V, VSS1 = VSS2 = 0 V) Parameter Clock Pulse Width Symbol Condition MIN. TYP. MAX. Unit PWCLK 25 ns Clock Pulse High Period PWCLK(H) 8 ns Clock Pulse Low Period PWCLK(L) 8 ns STB Pulse Width PWSTB 1 CLK INH Pulse Width PWINH 1 CLK Data Setup Time tSETUP1 4 ns Data Hold Time tHOLD1 0 ns Start Pulse Setup Time tSETUP2 4 ns Start Pulse Hold Time tHOLD2 0 ns POLB Setup Time tSETUP3 4 ns POLB Hold Time tHOLD3 0 ns STB Pulse Rise Timing tSRT1 1 CLK Start Pulse Rise Timing tSRT2 1 CLK tIRT 1 s INH Rise Timing CLK-INH Time tCLK-INH CLK INH 4 ns INH-CLK Time tINH-CLK INH CLK 4 ns POLA-STB Time tPOLA-STB POLA or STB 4 ns CLK-STB Time tCLK-STB CLK STB 4 ns STB-CLK Time tSTB-CLK STB CLK 4 ns Data Sheet S12930EJ1V0DS00 13 tr tf VDD1 90% CLK 1 2 3 64 65 66 512 513 1 2 3 4 10% VSS1 tSETUP2 tHOLD2 tCLK-STB tSTB-CLK VDD1 STHR (1st Dr.) VSS1 tSRT2 tSETUP1 tHOLD1 VDD1 Dn0 to Dn7 INVALID D 1 - D6 D7 D12 D373 D378 D379 D384 D385 D390 D3061 D3066 D3067 D3072 INVALID D1 - D6 INVALID D7 D12 D13 D18 D19 D24 VSS1 tSETUP3 tHOLD3 VDD1 POLB INVALID INVALID INVALID VSS1 tPLH1 Data Sheet S12930EJ1V0DS00 VDD1 STHL (1st Dr.) VSS1 tPLH1 VDD1 STHL (8th Dr.) VSS1 tSRT1 PWSTB tINH- tINH- CLK STB CLK tCLK- tCLK- INH INH VDD1 VSS1 tPOLA-STB VDD1 POLA VSS1 tIRT PWINH VDD1 INH VSS1 tPLH3 Hi-Z 9. SWITCHING CHARACTERISTICS WAVEFORM (In case of XGA drive) PWCLK(H) (Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.) 14 PWCLK(L) PWCLK tPLH2 Target voltage 0.1 VDD2 VOUT 8-bit accuracy tPHL3 PD16740 tPHL2 PD16740 10. RECOMMENDED SOLDERING CONDITIONS The following conditions must be met for soldering conditions of the PD16740. Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. xxx : TCP (TAB package) PD16740N-xxx Mounting Condition Thermocompression Caution Mounting Method Condition Soldering Heating tool 300 to 350C: heating for 2 to 3 seconds: pressure 100 g (per solder) ACF (Adhesive Conductive Film) Temporary bonding 70 to 100C: pressure 3 to 8 kg/cm : time 3 to 5 secs. 2 Real bonding 165 to 180C: pressure 25 to 45 kg/cm : time 30 to 40 secs. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.) 2 To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more packaging methods at a time. Data Sheet S12930EJ1V0DS00 15 PD16740 [MEMO] 16 Data Sheet S12930EJ1V0DS00 PD16740 [MEMO] Data Sheet S12930EJ1V0DS00 17 PD16740 [MEMO] 18 Data Sheet S12930EJ1V0DS00 PD16740 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S12930EJ1V0DS00 19 PD16740 Reference Documents NEC Semiconductor Device Reliability / Quality Control System (C10983E) Quality Grades to NEC's Semiconductor Devices (C11531E) * The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8