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MOS INTEGRATED CIRCUIT
µ
µµ
µ
PD16740
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 256-GRAY SCALES)
Document No. S12930EJ1V0DS00 (1st edition)
Date Published May 1999 NS CP(K)
Printed in Japan
DATA SHEET
1998,1999
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
The
µ
PD16740 is a source driver for TFT-LCDs capable of dealing with displays with 256 gray scales. Data input
is based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,700,000
colors by output of 256 values
γ
-corrected by an internal D/A converter and 11 external power modules. Because
the output dynamic range is as large as VSS2 + 0.1 V to Vref – 0.1 V, level inversion operation of the LCD’s common
electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line
inversion when mounted on a single side, this source driver is equipped with a built-in 8-bit D/A converter circuit
whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. The D/A
converter, which incorporates a digital offset circuit, is suitable for an LCD panel in which liquid crystal transmittance
in positive and negative polarities is different. Assuring a maximum clock frequency of 40 MHz when driving at 3.0 V,
this driver is applicable to SXGA and XGA-standard TFT-LCD panels.
FEATURES
• CMOS level input
• 384-output channel
• Input of 8 bits (gradation data) by 6 dots
• Capable of outputting 256 values by means of 11 external power modules and a D/A converter (C-DAC)
• Logic Part Power Supply Voltage (VDD1) : 3.3 ± 0.3 V
• Driver Part Power Supply Voltage (VDD2) : 8.5 ± 0.5 V
• High-speed data transfer: fMAX. = 40 MHz (internal data transfer speed when operating at VDD1 = 3.0 V)
• Output dynamic range VSS2 + 0.1 V to Vref – 0.1 V
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output voltage polarity reverse is possible (POLA)
• Input data reverse function is incorporated (POLB)
ORDERING INFORMATION
Part Number Package
µ
PD16740N-××× TCP (TAB package)
Remark The TCP’s external shape is custom-order item. Users are requested to consult with a NEC sales
representative.
Data Sheet S12930EJ1V0DS00
2
µ
µµ
µ
PD16740
1. BLOCK DIAGRAM
64-bit bidirectional shift register
C
1
C
2
C
63
C
64
Data register
D/A converter
&
Output buffer
S
1
S
2
S
383
S
384
STB
D
00
-
D
07
D
10
-
D
17
D
20
-
D
27
D
30
-
D
37
D
40
-
D
47
D
50
-
D
57
POLB
STHR STHL
V
DD1
(3.3 V)
V
SS1
Latch
Level shifter V
DD2
(8.5 V)
V
SS2
DW
sel
R,/L
CLK
INH
POLA
V
0
-
V
9
V
ref
Remark /xxx indicates active low signal.
Data Sheet S12930EJ1V0DS00 3
µ
µµ
µ
PD16740
2. PIN CONFIGURATION (
µ
µ µ
µ
PD16740N-×××
××××××
×××)
S384
S383
VSS2 S382
VDD2
V8
V6
V4
V2
V0
R
,
/L
D50
D51
D52
D53
D54
D55
D56
D57
D40
D41
D42
D43
D44
D45
D46
D47
D30
D31
D32
D33
D34
D35
D36
D37
POLB
POLA
STB
INH
STHL
DWsel
VDD1
CLK
VSS1
STHR
D20
D21
D22
D23
D24
D25
D26
D27
D10
D11
D12
D13
D14
D15
D16
D17
D00
D01
D02
D03
D04
D05
D06
D07
V1
V3
V5
V7
V9
Vref
VDD2 S3
VSS2 S2
S1
Surface
Copper Foil
Remark This figure does not specify the TCP package.
Data Sheet S12930EJ1V0DS00
4
µ
µµ
µ
PD16740
3. PIN FUNCTIONS
Pin Sy m bol Pin Name Descript i on
S1 to S384 Driver output The D/A converted 64/256-gray-scal e anal og voltage is output.
D00 to D07
D10 to D17
D20 to D27
D30 to D37
D40 to D47
D50 to D57
Display data The display data is input in ei ther a 48-bit width of 8-bit gray-sc ale data × 6 dots (2
pixels ) or i n a 36-bi t width of 6-bi t gray-scale data × 6 dots (2 pixels).
In 8-bit input: DX7: MSB, DX0: LSB
In 6-bit input: DX7: MSB, DX2: LSB
In 6-bit i nput (DWsel = L), the Dn0 and Dn1 pins are fixed t o low in the I C. Therefore,
be sure to leave them open on TCP.
DWsel 6-/8-bit input control This pin switches the bit wi dth of the di s pl ay data between 6 bi ts and 8 bit s .
DWsel = H: 8-bit input
DWsel = L: 6-bit input
This pin is pulled down int ernal l y.
R,/L Shift di rection c ontrol input These refer to the start pulse input/output pi ns when driver I Cs are connected i n
casc ade. The shift di rections of the shi f t regist ers are as fol l ows .
R,/L = H(Right shift) : STHR (input) → S1 → S384 → STHL (output)
R,/L = L (Left shi ft) : S T HL (i nput) → S384 → S1 → STHR (output)
STHR Right shift start pul se
input/output
STHL Left shift start pulse
input/output
Start pul se I/O pi n at cascade connection. The dis pl ay data is acquired when the
high level i s read at the ri sing edge of CLK.
Right shift : STHR is input. STHL is output.
Left shift : STHL is input. STHR is output.
CLK Shift clock i nput Refers to the shif t regist er’ s shif t clock i nput. The dis pl ay data is i nc orporated into
the data regis ter at the ri sing edge.
At the ri sing edge of t he 64t h clock after the start pulse input, the start pul se output
reaches t he hi gh l ev el , thus becoming the start pul se of the nex t-level dri ver.
Start pul se high level i s read at ris i ng edge of CLK, s tart to l oad t he di splay dat a
from next ri sing edge of CLK .
Also, after start puls e i nput and CLK input 66 pulses, i t stops to load the display
data and it m akes cont ents of shift regi ster clear at rising edge of STB.
STB Latch input After the content s of data regi ster is transferred t o a l atch at a ri s i ng edge and i s
cleared, operat i on of analog output voltage f or out put volt age i s start ed.
INH Inhibit input At the f alling edge complete calculation of analog output voltage, and output the
voltage appoi nt ed by displ ay data.
POLA Polarity input This si gnal i s read at the ri s i ng edge of latc h signal and determ i nes the output
voltage pol ari t y to reference volt age of each output pi n.
POLA = L : Pins with even number are negat i ve output. Pins with odd number are
positive output.
POLA = H : Pins with even number are pos i tive out put . Pins wi t h odd number are
negative out put.
POLB Data inversion By input ting a switching s i gnal t o this pin, this pi n enabl es the data whos e pol ari ty
is reversed to be read.
POLB = H : Acquires wi th displayed data reversed
POLB = L : Acquires raw di splayed dat a
Vref Reference power suppl y This term i nal i s the input ref erence power supply need to calc ul ation output.
Please ref er to 4. REL ATIONSHIP BETWE E N INPUT DATA AND OUT P UT
VOLTAGE VALUE.
V0 to V9
γ
-correct ed power s uppl i es Input the
γ
-correct ed power s uppl i es from out side by us i ng operational ampli fier.
Make sure to maintain the following relationships.
Vref – 0.1 V ≥ V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 ≥ V6 ≥ V7 ≥ V8 ≥ V9 ≥ VSS2 + 0.1 V
Vref – 0.1 V ≥ V9 ≥ V8 ≥ V7 ≥ V6 ≥ V5 ≥ V4 ≥ V3 ≥ V2 ≥ V1 ≥ V0 ≥ VSS2 + 0.1 V
During the gray scale v ol t age output, be sure to keep t he gray scal e l evel power
supply at a const ant level.
VDD1 Logic power suppl y 3.3 V ± 0.3 V
VDD2 Driver power supply 8.5 V ± 0.5 V
VSS1 Logic ground Grounding
VSS2 Driver ground Grounding
Data Sheet S12930EJ1V0DS00 5
µ
µµ
µ
PD16740
Cautions 1. The power start sequence must be VDD1 →
→→
→ logic input →
→→
→ VDD2 →
→→
→ Vref →
→→
→ V0 to V9 in that order.
Reverse this sequence to shut down. Be sure to observe this power sequence even during a
transition period.
2. To stabilize the supply voltage, please be sure to insert each 0.1
µ
µ µ
µ
F, 0.47
µ
µ µ
µ
F bypass
capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A
converter, insertion of a bypass capacitor of about 0.01
µ
µ µ
µ
F is also advised between the
γ
γγ
γ
-
corrected power supply terminals (V0, V1, V2, ···, V9) and VSS2.
3. This IC employs the C-DAC circuit to control gray-scale generation. The γ
γγ
γ-corrected voltage is
sampled between the rising of the STB signal and the rising of the INH signal, and the γ
γγ
γ-
corrected voltage is output from the driver output pin two or three clocks after the INH signal
falls. That is, each gray-scale voltage is determined by sampling γ
γγ
γ-corrected voltage. At this
time, a large transient current flows instantly into the γ
γγ
γ-corrected power supply pin. Therefore,
when inputting γ
γγ
γ-corrected voltage and γ
γγ
γ-corrected reference voltage, an operational amplifier
is recommended to reduce the input impedance of this pin. In addition to this, the voltage to be
input to this pin needs to be stabilized.
When a switching signal with high frequency is input to the γ
γγ
γ-corrected power supply pin, the
application voltage becomes unstable and display may be abnormal. For details of the output
timing, refer to 9. SWITCHING CHARACTERISTICS WAVEFORM.
4. When this product is used as a 6-bit driver (DWsel = L), the wiring for the Dn1 and Dn2 (lower 2
bits of display data) pins must be left open on the TCP, since they are forcibly short-circuited to
VSS1 in the IC.
Data Sheet S12930EJ1V0DS00
6
µ
µµ
µ
PD16740
4. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
4.1 Calculation of output voltage in 8-bit input
(DWsel = H, Vref – 0.1 V ≥ V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 ≥ V6 ≥ V7 ≥ V8 ≥ V9 ≥ VSS2 + 0.1 V )
0
1
30
31
32
33
62
63
64
65
94
95
96
97
126
127
128
129
158
159
160
161
190
191
192
193
222
223
224
225
254
255
D
X7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D
X5
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D
X3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
X4
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
X6
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
00H
01H
1EH
1FH
20H
21H
3EH
3FH
40H
41H
5EH
5FH
60H
61H
7EH
7FH
80H
81H
9EH
9FH
A0H
A1H
BEH
BFH
C0H
C1H
DEH
DFH
E0H
E1H
FEH
FFH
D
X2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
X1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
D
X0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V
8
+(V
9
-V
8
) x 31/32
V
8
+(V
9
-V
8
) x 30/32
V
8
+(V
9
-V
8
) x 1/32
V
8
V
7
+(V
8
-V
7
) x 31/32
V
7
+(V
8
-V
7
) x 30/32
V
7
+(V
8
-V
7
) x 1/32
V
7
V
6
+(V
7
-V
6
) x 31/32
V
6
+(V
7
-V
6
) x 30/32
V
6
+(V
7
-V
6
) x 1/32
V
6
V
5
+(V
6
-V
5
) x 31/32
V
5
+(V
6
-V
5
) x 30/32
V
5
+(V
6
-V
5
) x 1/32
V
5
V
4
+(V
5
-V
4
) x 31/32
V
4
+(V
5
-V
4
) x 30/32
V
4
+(V
5
-V
4
) x 1/32
V
4
V
3
+(V
4
-V
3
) x 31/32
V
3
+(V
4
-V
3
) x 30/32
V
3
+(V
4
-V
3
) x 1/32
V
3
V
2
+(V
3
-V
2
) x 31/32
V
2
+(V
3
-V
2
) x 30/32
V
2
+(V
3
-V
2
) x 1/32
V
2
V
1
+(V
2
-V
1
) x 31/32
V
1
+(V
2
-V
1
) x 30/32
V
1
+(V
2
-V
1
) x 1/32
V
0
2V
ref
– {V
8
+(V
9
– V
8
) x 31/32}
2V
ref
– {V
8
+(V
9
– V
8
) x 30/32}
2V
ref
– {V
8
+(V
9
– V
8
) x 1/32}
2V
ref
– V
8
2V
ref
– {V
7
+(V
8
– V
7
) x 31/32}
2V
ref
– {V
7
+(V
8
– V
7
) x 30/32}
2V
ref
– {V
7
+(V
8
– V
7
) x 1/32}
2V
ref
– V
7
2V
ref
– {V
6
+(V
7
– V
6
) x 31/32}
2V
ref
– {V
6
+(V
7
– V
6
) x 30/32}
2V
ref
– {V
6
+(V
7
– V
6
) x 1/32}
2V
ref
– V
6
2V
ref
– {V
5
+(V
6
– V
5
) x 31/32}
2V
ref
– {V
5
+(V
6
– V
5
) x 30/32}
2V
ref
– {V
5
+(V
6
– V
5
) x 1/32}
2V
ref
– V
5
2V
ref
– {V
4
+(V
5
– V
4
) x 31/32}
2V
ref
– {V
4
+(V
5
– V
4
) x 30/32}
2V
ref
– {V
4
+(V
5
– V
4
) x 1/32}
2V
ref
– V
4
2V
ref
– {V
3
+(V
4
– V
3
) x 31/32}
2V
ref
– {V
3
+(V
4
– V
3
) x 30/32}
2V
ref
– {V
3
+(V
4
– V
3
) x 1/32}
2V
ref
– V
3
2V
ref
– {V
2
+(V
3
– V
2
) x 31/32}
2V
ref
– {V
2
+(V
3
– V
2
) x 30/32}
2V
ref
– {V
2
+(V
3
– V
2
) x 1/32}
2V
ref
– V
2
2V
ref
– {V
1
+(V
2
– V
1
) x 31/32}
2V
ref
– {V
1
+(V
2
– V
1
) x 30/32}
2V
ref
– {V
1
+(V
2
– V
1
) x 1/32}
2V
ref
– V
0
Gray Binary Input Data Output Voltage Output Voltage
Scale S
2n
(POLA=H),S
2n–1
(POLA=L)
S
2n–1
(POLA=H), S
2n
(POLA=L)
Data Sheet S12930EJ1V0DS00 7
µ
µµ
µ
PD16740
4.2 Curved line of output voltage in 8-bit input
(DWsel = H, POLA = H, Vref – 0.1 V ≥ V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 ≥ V6 ≥ V7 ≥ V8 ≥ V9 ≥ VSS2 + 0.1 V)
V
DD2
0.1 V
V
1
V
3
V
5
V
7
V
ref
V
0
V
2
V
4
V
6
0.1 V
V
SS2
1F
H00
H3F
H5F
H7F
H9F
HBF
HDF
HFF
H
Input data (HEX)
V
9
V
8
FE
H
S
2
n
S
2
n
–1
Data Sheet S12930EJ1V0DS00
8
µ
µµ
µ
PD16740
4.3 Calculation of output voltage in 6-bit input
(DWsel = L, Vref – 0.1 V ≥ V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 ≥ V6 ≥ V7 ≥ V8 ≥ V9 ≥ VSS2 + 0.1 V )
0
1
6
7
8
9
14
15
16
17
22
23
24
25
30
31
32
33
38
39
40
41
46
47
48
49
54
55
56
57
63
64
D
X7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D
X5
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D
X3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
X4
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
X6
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
00H
01H
06H
07H
08H
09H
0EH
0FH
10H
11H
16H
17H
18H
19H
1EH
1FH
20H
21H
26H
27H
28H
29H
2EH
2FH
30H
31H
36H
37H
38H
39H
3EH
3FH
D
X2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D
X1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D
X0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V
8
+(V
9
-V
8
) x 7/8
V
8
+(V
9
-V
8
) x 6/8
V
8
+(V
9
-V
8
) x 1/8
V
8
V
7
+(V
8
-V
7
) x 7/8
V
7
+(V
8
-V
7
) x 6/8
V
7
+(V
8
-V
7
) x 1/8
V
7
V
6
+(V
7
-V
6
) x 7/8
V
6
+(V
7
-V
6
) x 6/8
V
6
+(V
7
-V
6
) x 1/8
V
6
V
5
+(V
6
-V
5
) x 7/8
V
5
+(V
6
-V
5
) x 6/8
V
5
+(V
6
-V
5
) x 1/8
V
5
V
4
+(V
5
-V
4
) x 7/8
V
4
+(V
5
-V
4
) x 6/8
V
4
+(V
5
-V
4
) x 1/8
V
4
V
3
+(V
4
-V
3
) x 7/8
V
3
+(V
4
-V
3
) x 6/8
V
3
+(V
4
-V
3
) x 1/8
V
3
V
2
+(V
3
-V
2
) x 7/8
V
2
+(V
3
-V
2
) x 6/8
V
2
+(V
3
-V
2
) x 1/8
V
2
V
1
+(V
2
-V
1
) x 7/8
V
1
+(V
2
-V
1
) x 6/8
V
1
+(V
2
-V
1
) x 1/8
V
0
2V
ref
– {V
8
+(V
9
– V
8
) x 7/8}
2V
ref
– {V
8
+(V
9
– V
8
) x 6/8}
2V
ref
– {V
8
+(V
9
– V
8
) x 1/8}
2V
ref
– V
8
2V
ref
– {V
7
+(V
8
– V
7
) x 7/8}
2V
ref
– {V
7
+(V
8
– V
7
) x 6/8}
2V
ref
– {V
7
+(V
8
– V
7
) x 1/8}
2V
ref
– V
7
2V
ref
– {V
6
+(V
7
– V
6
) x 7/8}
2V
ref
– {V
6
+(V
7
– V
6
) x 6/8}
2V
ref
– {V
6
+(V
7
– V
6
) x 1/8}
2V
ref
– V
6
2V
ref
– {V
5
+(V
6
– V
5
) x 7/8}
2V
ref
– {V
5
+(V
6
– V
5
) x 6/8}
2V
ref
– {V
5
+(V
6
– V
5
) x 1/8}
2V
ref
– V
5
2V
ref
– {V
4
+(V
5
– V
4
) x 7/8}
2V
ref
– {V
4
+(V
5
– V
4
) x 6/8}
2V
ref
– {V
4
+(V
5
– V
4
) x 1/8}
2V
ref
– V
4
2V
ref
– {V
3
+(V
4
– V
3
) x 7/8}
2V
ref
– {V
3
+(V
4
– V
3
) x 6/8}
2V
ref
– {V
3
+(V
4
– V
3
) x 1/8}
2V
ref
– V
3
2V
ref
– {V
2
+(V
3
– V
2
) x 7/8}
2V
ref
– {V
2
+(V
3
– V
2
) x 6/8}
2V
ref
– {V
2
+(V
3
– V
2
) x 1/8}
2V
ref
– V
2
2V
ref
– {V
1
+(V
2
– V
1
) x 7/8}
2V
ref
– {V
1
+(V
2
– V
1
) x 6/8}
2V
ref
– {V
1
+(V
2
– V
1
) x 1/8}
2V
ref
– V
0
Gray Binary Input Data Output Voltage Output Voltage
Scale S
2n
(POLA=H),S
2n–1
(POLA=L)
S
2n–1
(POLA=H), S
2n
(POLA=L)
Data Sheet S12930EJ1V0DS00 9
µ
µµ
µ
PD16740
4.4 Curved line of output voltage in 6-bit input
(DWsel = L, POLA = H, Vref – 0.1 V ≥ V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 ≥ V6 ≥ V7 ≥ V8 ≥ V9 ≥ VSS2 + 0.1 V)
V
DD2
0.1 V
V
1
V
3
V
5
V
7
V
ref
V
0
V
2
V
4
V
6
0.1 V
V
SS2
07
H00
H0F
H17
H1F
H20
H2F
H30
H3F
H
Input data (HEX)
V
9
V
8
3E
H
S
2
n
S
2
n
–1
Data Sheet S12930EJ1V0DS00
10
µ
µµ
µ
PD16740
5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
The reference power supply of the D/A converter is made up of a capacitance ladder circuit, which minimizes
current flow into the
γ
- corrected power supply pins. However, in the LCD driver of previous R-DAC systems the
resistance ratio between the
γ
- corrected power supply pins was set to be identical to the
γ
- corrected voltage ratio
used for an actual LCD panel. Such a function is not available in this product. Therefore,
γ
- corrected voltage
directly becomes D/A converter reference power voltage in the IC. Determine
γ
- corrected voltage based on the data
of
γ
characteristics of a LCD panel described in 4. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT
VOLTAGE VALUE.
6. INPUT FORMAT OF DISPLAY DATA
Data format : 8/6 bits × 2 RGBs (6 dots)
Input width : 48/36 bits (2-pixel data)
(1) R,/L = H (Right shift)
Output S1S2S3S4xxx S383 S384
Data D00 to D05/07 D10 to D15/17 D20 to D25/27 D30 to D35/37 xxx D40 to D45/47 D50 to D55/57
(2) R,/L = L (Left shift)
Output S1S2S3S4xxx S383 S384
Data D00 to D05/07 D10 to D15/17 D20 to D25/27 D30 to D35/37 xxx D40 to D45/47 D50 to D55/57
7. RELATIONSHIP BETWEEN STB, POL, AND OUTPUT WAVEFORM
The output buffer consists of an operational amplifier circuit that does not perform recharge operation. Therefore,
driver output current IVOH is the charging current to the LCD, and IVOL is the discharging current.
STB
POL
S
2n–1
S
2n
Selected voltage of V
0
to V
4
Hi-Z
Hi-Z
Hi-Z
INH
Selected voltage of V
0
to V
4
Selected voltage of V
5
to V
9
Selected voltage of V
5
to V
9
Selected voltage of V
0
to V
4
Selected voltage of V
5
to V
9
Data Sheet S12930EJ1V0DS00 11
µ
µµ
µ
PD16740
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°C, VSS1 = VSS2 = 0 V)
Parameter Symbol Ratings Unit
Logic Part Power Supply V ol tage VDD1 –0.5 to + 5. 0 V
Driver Part power Supply Voltage VDD2 –0.5 to + 10.0 V
Logic Part Input Vol t age VI1 –0.5 to V DD1 + 0.5 V
Driver Part Input Vol t age VI2 –0.5 to V DD2 + 0. 5 V
Logic Part Output Vol t age VO1 –0.5 to V DD1 + 0.5 V
Driver Part Output Vol t age VO2 –0.5 to V DD2 + 0. 5 V
Operating Temperature Range TA–10 t o +75 °C
Storage Temperat ure Range Tstg –55 to +125 °C
Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily,
the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values
exceeding which the product may be physically damaged. Be sure to use the product within the
range of the absolute maximum ratings.
Recommended Operating Range (TA = –10 to +75°C, VSS1 = VSS2 = 0 V)
Parameter Symbol MIN. TYP. MAX. Unit
Logic Part Supply V ol t age VDD1 3.0 3.3 3.6 V
Driver Part Supply V ol t age V DD2 8.0 8.5 9.0 V
Driver Part Output Voltage Range VOVSS2 + 0.1 VDD2 – 0.1 V
γ
-Corrected Vol tage V0 to V9VSS2 + 0.1 Vref – 0.1 V
γ
-Corrected Reference Power Suppl y Vref 0.5 VDD2 5.0 V
Maximum Clock Frequency fMAX. 40 MHz
Data Sheet S12930EJ1V0DS00
12
µ
µµ
µ
PD16740
Electrical Characteristics (TA = –10 to + 75°C, VDD1 = 3.3 V ±
±±
±
0.3 V, VDD2 = 8.5 V ±
±±
±
0.5 V, VSS1 = VSS2 = 0 V)
Parameter Symbol Condition MIN. TYP. MAX. Unit
High-Level I nput Voltage VIH 0.7 VDD2 VDD2 V
Low-level I nput Voltage VIL VSS2 0.3 VDD2 V
Input Leak Current IIL
CLK,STB,R,/L,INH,POLA,POLB,
D00 to D07, D10 to D17, D20 to D27,
D30 to D37, D40 to D47, D50 to D57 −1.0 +1.0
µ
A
High-Level Out put Voltage VOH STHR (S T HL), IOH = −1.0 mA VDD1 − 0.5 V
Low-level Out put Voltage VOL STHR (S T HL), IOL = +1.0 mA VSS1 + 0.5 V
IVOH VDD1 = 3.3 V , INH = 0 V,
VOUT = 7.9 V , VO = 8.4 V Note
−90 −40 mA
Driver Output Current
(VDD2 = 8.5 V)
IVOL VDD1 = 3.3 V , INH = 0 V,
VOUT = 0.6 V , VO = 0.1 V Note
40 90 mA
Output Vol tage Deviat i on ∆VOVDD1 = 3.3 V , VDD2 = 8. 5 V,
VOUT = 0.5 / 3.0 / 5.0 / 8.0 V Note
±18 ±25 mV
Logic Part Dynami c Current
Consumption
I DD1 VDD1 = 3.3 V, wi th no load 1.2 4.0 mA
Driver Part Dynami c Current
Consumption
I DD2 VDD2 = 8.5 V, wi th no load 4.0 12.0 mA
Note VOUT indicates application voltage to output pins. V0 indicates output voltage to output pins.
Caution For logic part dynamic current consumption, the TYP. value is based on the condition while the
screen is displayed in entirely dark or entirely light and the MAX. value is based on the condition
while the screen is displayed in chess board pattern.
Switching Characteristics (TA = –10 to +75°C, VDD1 = 3.3 V ±
±±
±
0.3 V, VDD2 = 8.5 V ±
±±
±
0.5 V, VSS1 = VSS2 = 0 V)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Start Pulse Delay Time tPLH1 CL = 10 pF, CLK → STHL (S T HR) 2 4.3 20 ns
tPLH2 2.8 6.0
µ
s
tPLH3
VO = 0.1 V → 8.4 V
9.1 12.0
µ
s
tPHL2 1.6 6.0
µ
s
Driver Output Del ay Time
tPHL3
VDD2 = 8.5 V,
RL = 5.0 kΩ,
CL = 35 pF x 2 VO = 8.4 V → 0.1 V
9.0 12.0
µ
s
CI1 TA = +25°C , STHR (S T HL), V 0 to V9,Vref 815pFInput Capaci tance
CI2 TA = +25°C, STHR(S T HL), V0 to V9,
Except Vref
610pF
Data Sheet S12930EJ1V0DS00 13
µ
µµ
µ
PD16740
Timing Requirement (TA = –10 to +75°C, VDD1 = 3.3 V ±
±±
±
0.3 V, VSS1 = VSS2 = 0 V)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Clock P ul se Width P WCLK 25 ns
Clock Pulse Hi gh Period PWCLK(H) 8ns
Clock Pulse Low Period PWCLK(L) 8ns
STB Pulse Width PWSTB 1CLK
INH Pulse Width PWINH 1CLK
Data Setup Time tSETUP1 4ns
Data Hold Ti m e tHOLD1 0ns
Start P ul s e Setup Time tSETUP2 4ns
Start Pulse Hold Time tHOLD2 0ns
POLB Set up Ti m e tSETUP3 4ns
POLB Hold Time tHOLD3 0ns
STB Pulse Rise Timing tSRT1 1CLK
Start Pulse Rise Timing t SRT2 1CLK
INH Rise T iming tIRT 1
µ
s
CLK-INH Time tCLK-INH CLK ↑ → INH ↓4ns
INH-CLK Ti m e tINH-CLK I NH ↑ → CLK ↑4ns
POLA-STB Time tPOLA-STB POLA ↑ or ↓ → STB ↑4ns
CLK-STB Time tCLK-STB CLK ↑ → STB ↑4ns
STB-CLK Time tSTB-CLK STB ↑ → CLK ↑4ns
Data Sheet S12930EJ1V0DS00
14
µ
µµ
µ
PD16740
9. SWITCHING CHARACTERISTICS WAVEFORM (In case of XGA drive)
(Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.)
VDD1
VSS1
t
SETUP2
POLB
Dn0 to Dn7
V
OUT
CLK
STHR
(1st Dr.)
STHL
(1st Dr.)
STHL
(8th Dr.)
STB
POLA
INH
t
HOLD1
t
SETUP1
t
PLH1
t
PLH1
t
SRT2
PWSTB
PWINH
t
SRT1
t
POLA-STB
t
IRT
Hi-Z
t
PHL3
t
PLH3
t
PHL2
t
PLH2
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
t
HOLD3
t
SETUP3
t
HOLD2
PWCLK(L) PWCLK
t
r
90%
10%
t
f
1
D1 - D6D7 -
D12 D373 -
D378 D379 -
D384 D385 -
D390 D3061 -
D3066 D3067 -
D
3072
D19 -
D24
D1 - D6
512 513
2656631234
64
INVALID INVALIDINVALID
INVALIDINVALIDINVALID
t
CLK-STB
t
STB-CLK
t
CLK-
INH
t
I
NH-
CLK
PWCLK(H)
VDD1
VSS1
D7 -
D12 D13 -
D18
Target voltage ± 0.1 VDD2
8-bit accuracy
t
CLK-
INH
t
I
NH-
CLK
Data Sheet S12930EJ1V0DS00 15
µ
µµ
µ
PD16740
10. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met for soldering conditions of the
µ
PD16740.
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.
µ
µ µ
µ
PD16740N-×××
××××××
××× : TCP (TAB package)
Mounting Condition Mounting Method Condition
Soldering
Heating tool 300 to 350°C: heating for 2 to 3 seconds: pressure 100 g (per
solder)
Thermocompression
ACF
(Adhesive
Conductive Film)
Temporary bonding 70 t o 100° C: pressure 3 to 8 kg/c m2 : time 3 to 5 secs.
Real bonding 165 to 180°C: pressure 25 to 45 kg/c m 2 : time 30 to 40 secs.
(When using the ani sotropy c onductiv e film S UM I ZAC1003 of Sum i t om o
Bakeli t e, Ltd.)
Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF
manufacturing company. Be sure to avoid using two or more packaging methods at a time.
Data Sheet S12930EJ1V0DS00
16
µ
µµ
µ
PD16740
[MEMO]
Data Sheet S12930EJ1V0DS00 17
µ
µµ
µ
PD16740
[MEMO]
Data Sheet S12930EJ1V0DS00
18
µ
µµ
µ
PD16740
[MEMO]
Data Sheet S12930EJ1V0DS00 19
µ
µµ
µ
PD16740
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
µ
µµ
µ
PD16740
Reference Documents
NEC Semiconductor Device Reliability / Quality Control System (C10983E)
Quality Grades to NEC’s Semiconductor Devices (C11531E)
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
