128K x 8 Static RAM
CY62128V Family
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 27, 2000
amily
Features
• Low vol t age rang e:
—2.7V–3.6V (CY6 2128V)
—2.3V–2.7V (CY6 2128V25)
—1.6V–2.0V (CY6 2128V18)
• Low active power and standb y power
• Easy memory e xpansion with CE and OE fe atures
• TTL-compatible inputs and outp uts
• Autom atic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The CY621 28V fami ly i s composed of three high- per formanc e
CMOS static RAMs organized as 131,072 words by 8 bits.
Easy memory expansion is provided by an active LOW Chip
En able (CE1), an active HIGH Chip Enable (CE2), an active
LOW Output Enable (OE) and three-state drivers. These de-
vices have an automatic power-down feature, reducing the
power consumption by over 99% when deselected. The
CY62128V family is available in the standard 450-mil-wide
SOIC, 32-lead TSOP-I, and STSOP packages.
Writing to the device is accomplished by taking Chip Enable
one (CE1) and Write Enable (WE) inputs LOW and the Chip
Enable two ( C E2) input HIGH. Data on the eight I/O pins (I/O0
through I/O7) is t hen written into the location specified on the
address pins (A0 through A16).
Reading from the device is accomplished by taking Chip En-
able one (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable two (CE2) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/ O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
14
15
Logic Block Diagram Pin Configurations
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
CE
2
I/O1
I/O2
I/O3
512x256x8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A11
A13
A12
A
A10
CE
1
A
A16
A9
62128V-1
62128V-2
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top View
SOIC
12
13
29
32
31
30
16
15 17
18
GND
A16
A14
A12
A7
A6
A5
A4
A3
WE
VCC
A15
A13
A8
A9
I/O7
I/O6
I/O5
I/O4
A2
NC
I/O0
I/O1
I/O2
CE1
OE
A10
I/O3
A1
A0
A11
CE2
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9OE
TSOP I / STSOP
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE1
A11
A517
18
8
9
10
11
12
13
14
15
16
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9OE
TSOP I
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE1
A11
A517
18
8
9
10
11
12
13
14
15
16
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
(not to scale)
Top View
Reverse Pinout
62128V-3 62128V-4
CY62128V Family
2
Maximum Ratings
(Above which the useful l ife may be impaired. For user gui de-
li nes, not tes ted.)
Storage Temperat ure ... .. ......... ...... ......... ....–65°C to +15 0 °C
Ambient Temperature with
Power Applied.............................................–55°C to +12 5 °C
Supply Voltage to Ground Potential
(Pi n 2 8 to Pi n 14). .. ... ....... ..... ....... ..... ........ .... . –0.5V to +4.6V
DC Voltag e Appli ed to Output s
in High Z State[1]....................................–0.5V to VCC + 0.5V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage...... .. .. ............. .. .. ............. .. >2001V
(per MIL- STD-883, Method 3015 )
Latch-Up Curr ent. .................................. .............. .. . >200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 1.6V to 3.6V
Industrial –40°C to +85°C 1.6V to 3.6V
Product Portfolio
VCC Range
Power Dissipati on (Comme rcial)
Operati ng (ICC)Standby (ISB2)
Product Min. Typ.[2] Max. Speed Typ.[2] Maximum Typ.[2] Maximum
CY62128V 2.7V 3.0V 3.6V 55, 70 ns 20 mA 40 mA 0.4 µA100 µA (XL = 10 µA)
CY62128V25 2.3V 2.5V 2.7V 100 ns 15 mA 20 mA 0.3 µA50 µA (LL = 12 µA)
CY62128V18 1.6V 1.8V 2.0V 200 ns 10 mA 15 mA 0.3 µA30 µA (LL = 10 µA)
Electrical Characteristics Over the Ope rating Range
CY62128V-55/70
Parameter Description Test Conditions Min. Typ.[2] Max. Unit
VOH Output HIGH Vo ltage VCC = Min., IOH = –1.0 mA 2.4 V
VOL Ou tput LOW Volt age VCC = Min., IOL = 2.1 mA 0.4 V
VIH Input HIGH Voltage 2 VCC
+0.5V V
VIL Input LOW Voltage –0.5 0.8 V
IIX Input Load Curre nt GND < VI < VCC –1±1 +1 µA
IOZ Outpu t Leakage Current GND < VO < VCC, Output Disabled –1±1 +1 µA
ICC VCC Operating Supply
Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
Com’l,
70 ns L20 40 mA
LL, XL 20 40
Ind’l,
55 ns LL 23 50
Ind’l,
70 ns L20 40
LL 20 40
ISB1 Auto matic C E
Power-Down Current —
TTL In puts
Max. VCC, CE > VIH,
VIN > VIH or
VIN < VIL, f = fMAX
Com’l,
70 ns L15 300 µA
LL, XL 15 300
Coml,
55 ns LL 17 350
Ind’l L 15 300
LL 15 300
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ., TA = 25°C.
CY62128V Family
3
ISB2 Auto matic C E
Power-Down Current —
CMOS Inputs
Max. VCC,
CE > VCC – 0.3V
VIN > VCC – 0.3V
or VIN < 0.3V, f = 0
Com’l L 0.4 100 µA
LL 15 µA
XL 10 µA
Ind’l L 100 µA
LL 30 µA
Electrical Characteristics Over the Ope rating Range
CY62128V-55/70
Parameter Description Test Conditions Min. Typ.[2] Max. Unit
Electrical Characteristics Over the Ope rating Range
CY62128V25-100 CY62128V18-200
Parameter Description Test Conditions Min. Typ.[2] Max. Min. Typ.[2] Max. Unit
VOH Output HIGH Vo ltage VCC = Min ., I OH = –0.1 mA 2.4 0.8*
VCC V
VOL Ou tput LOW Volt age VCC = Min ., I OL = 0.1 mA 0.4 0.2 V
VIH Input HIGH Voltage 2 VCC
+0.5 0.7*
VCC VCC
+0.3 V
VIL Input LOW Voltage –0.5 0.8 –0.5 0.3*
VCC V
IIX Input Load Curre nt GND < VI < VCC –1±1 +1 –1±0.1 +1 µA
IOZ Outpu t Leakage Current GND < VO < VCC, Output
Disabled –1±1 +1 –1±0.1 +1 µA
ICC VCC Operating Supply
Current VCC = Ma x .,
IOUT = 0 mA,
f = fMAX = 1/tRC
L15 20 10 15 mA
LL
ISB1 Auto matic C E
Power-Down Current —
TTL In puts
Max. VCC, CE > VIH,
VIN > VIH or
VIN < VIL, f = fMAX
L15 300 5100 µA
LL
ISB2 Auto matic C E
Power-Down Current —
CMOS Inputs
Max. VCC,
CE > VCC – 0. 3 V
VIN > VCC – 0.3V
or VIN < 0.3V, f = 0
L0.4 50 0.4 30 µA
LL 12 10 µA
Indust’l Temp Range LL 24 20 µA
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capac it ance TA = 25°C, f = 1 MHz,
VCC = 3.0V 6pF
COUT Output Capacitance 8pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
CY62128V Family
4
AC Test Loads and Waveforms
1.8V
VCC
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
<5ns <5ns
OUTPUT V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
62128V–562128V–6
RTH
R1
Parameters 3.3V 2.5V 1.8V Unit
R1 1213 15909 10800 Ohms
R2 1378 4487 4154 Ohms
RTH 645 3500 3000 Ohms
VTH 1.75V 0.55V 0.50V Volts
Data Reten ti o n C h ar acter i stics (Ov er the Operating Range)
Parameter Description Conditions[4] Min. Typ.[2] Max. Unit
VDR VCC f o r Data R etentio n 1.6 V
ICCDR Data Retention Current Com’l L VCC = 2V
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
No input may exceed
VCC+0.3V
0.4 10 µA
LL,
XL 10 µA
Ind’l L 20 µA
LL 20 µA
tCDR[3] Chip Desel ect to Data Retention Time 0ns
tROper ati on Recovery Time tRC ns
Data Retention Waveform
Note:
4. No input may exceed VCC+0.3V.
C62128V–7
1.8V1.8V
tCDR
VDR >1.6 V
DATA RETENTION MODE
tR
CE
VCC
CY62128V Family
5
Data Retention Current Graph (for “L” version only)
Switching Characteristics Ov er the Operating Range[5]
62128V-55 62128V-70 62128V25-100 62128V18-200
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cyc le Ti m e 55 70 100 200 ns
tAA Address to Data Valid 55 70 100 200 ns
tOHA Dat a Hold f rom Address Change 510 10 10 ns
tACE CE LOW to Data Valid 55 70 100 200 ns
tDOE OE LOW to Data Valid 20 35 75 125 ns
tLZOE OE LOW to Low Z[6] 10 10 10 10 ns
tHZOE OE HIGH to High Z[6, 7] 20 25 50 75 ns
tLZCE CE LO W to Low Z[6] 10 10 10 10 ns
tHZCE CE HIGH to High Z[6, 7] 20 25 50 75 ns
tPU CE LOW to Power -Up 0 0 0 0 ns
tPD CE HIGH to Power-Down 55 70 100 200 ns
WRITE CY CL E[8 , 9 ]
tWC Write Cycle Time 55 70 100 200 ns
tSCE CE LO W to Write End 45 60 100 190 ns
tAW Address Set-Up to Write End 45 60 100 190 ns
tHA Address Hold from Write End 0 0 0 0 ns
tSA Address Set-Up to Write Star t 0 0 0 0 ns
tPWE WE P u l s e W idth 45 55 90 125 ns
tSD Data S et -U p to Write End 25 30 60 100 ns
tHD Data Hold from Write End 0 0 0 0 ns
tHZWE WE LOW to Hi gh Z[6, 7] 20 25 50 100 ns
tLZWE WE H IGH to Lo w Z[6] 5 5 10 15 ns
5. Test conditions assume signal transition time of 5 ns or less timing reference le vels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100- pF load c apa citance .
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is le ss th an t LZOE, and tHZWE is l ess than t LZWE for any given device.
7. tHZOE, tHZCE, and tHZWE are s pecified wi th CL = 5 pF as in pa rt (b) of AC Test Loads. Transition is me asured ±200 mV from s teady- state v ol tage.
8. The internal write time of the memory is defined by the overlap of CE 1 LO W , CE2 HIGH, and WE LOW. CE1 and WE signals must be LO W and CE2 HIGH to initiate a
write and eithe r signal can terminate a write by goin g HIGH. The data i nput set- up and hold timi ng should be r eferenc ed to the rising edge of the s ignal that te rminates the write.
9. The minimum write cycle time for write cycle #3 (WE control led, OE LO W) is the s um of tHZWE and t SD.
SUPPLY VOLTAGE (V)
DATA RETENTION
CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
T=25°C
1.6
2.6
3.6
(µA)
40
30
20
10
0
50
60
70
80
A
CY62128V Family
6
Switching Wavefor ms
Read Cycle No. 2 (OE Controll ed)[11, 12]
Write Cycle No. 1 (CE1 or CE2 Controlled)[13,14]
Notes:
10. Device is continuously selected. OE, CE = VIL, CE2=VIH.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE1 trans ition LOW and CE2 trans ition H IGH.
13. Data I/O is high impedance if OE = VIH.
14. If CE1 goes HIGH or CE2 goes L OW s imultane ous ly with W E HI GH, the output remai ns in a hi gh-impedanc e state.
Read Cycle No.1
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
62128V–8
[10, 11]
62128V-9
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
OE
CE1
ICC
ISB
IMPEDANCE
ADDRESS
CE2
DATA OUT
VCC
SUPPLY
CURRENT
62128V-10
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE1
ADDRESS
CE2
WE
DATA I/O
CY62128V Family
7
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
Note:
15. During this period, the I/Os are in output state and input signals should not be applied.
Switching Wavefor ms (cont inued)
62128V-11
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tSCE
tWC
tHZOE
DATAIN VALID
CE1
ADDRESS
CE2
WE
DATA I/O
OE
NOTE 15
Truth Table
CE1CE2OE WE I/O0–I/O7Mode Power
H X X X Hi gh Z Power-Down Standby (ISB)
X L X X High Z Power-Down Standby (ISB)
L H L H Data Out Read Active (ICC)
L H X L Data In Write Activ e (I CC)
L H H H High Z Selected, Outputs Disab led Ac ti ve (ICC)
CY62128V Family
8
Ordering Information
Speed
(ns) Orderi ng Code Package
Name P ackage Type Operating
Range
55 CY62128VLL-55ZAI ZA32 32-Lead STSOP Type 1 Industrial
70 CY62128VL-70SC S34 32-Lead 450- M il SO IC Commercial
CY62128VLL-70SC S34
CY62128VL-70ZC Z32 32-Lead TSOP Type 1
CY62128VLL-70ZC Z32
CY62128VXL-70ZC Z32
CY62128VL-70ZAC ZA32 32-Lead STSOP Type 1
CY62128VLL-70ZAC ZA32
CY62128VL-70ZRC ZR32 32-Lead Rev erse TSOP 1
CY62128VLL-70ZRC ZR32
70 CY62128VL-70SI S34 32-Lead 450- M il SO IC Industrial
CY62128VLL-70SI S34
CY62128VL-70ZI Z32 32-Lead TSOP Type 1
CY62128VLL-70ZI Z32
CY62128VL-70ZAI ZA32 32-Lead STSOP Type 1
CY62128VLL-70ZAI ZA32
CY62128VL-70ZRI ZR32 32-Lead Rev erse TSOP 1
CY62128VLL-70ZRI ZR32
100 CY62128V25L-100SC S34 32-Lead 450- M il SO IC Commercial
CY62128V25LL-100SC S34
CY62128V25L-100ZC Z32 32-Lead TSOP Type 1
CY62128V25LL-100ZC Z32
CY62128V25L-100ZAC ZA32 32-Lead STSOP Type 1
CY62128V25LL-100ZAC ZA32
CY62128V25L-100ZRC ZR32 32-Lead Reverse TSO P 1
CY62128V25LL-100ZRC ZR32
100 CY62128V25L-100SI S34 32-Lead 450- M il SO IC Industrial
CY62128V25LL-100SI S34
CY62128V25L-100ZI Z32 32-Lead TSOP Type 1
CY62128V25LL-100ZI Z32
CY62128V25L-100ZAI ZA32 32-Lead STSOP Type 1
CY62128V25LL-100ZAI ZA32
CY62128V25L-100ZRI ZR32 32-Lead Reverse TSO P 1
CY62128V25LL-100ZRI ZR32
200 CY62128V18L-200SC S34 32-Lead 450- M il SO IC Commercial
CY62128V18LL-200SC S34
CY62128V18L-200ZC Z32 32-Lead TSOP Type 1
CY62128V18LL-200ZC Z32
CY62128V18L-200ZAC ZA32 32-Lead STSOP Type 1
CY62128V18LL-200ZAC ZA32
CY62128V18L-200ZRC ZR32 32-Lead Reverse TSO P 1
CY62128V18LL-200ZRC ZR32
CY62128V Family
9
Document #: 38-00547-B
200 CY62128V18L-200SI S34 32-Lead 450- M il SO IC Industrial
CY62128V18LL-200SI S34
CY62128V18L-200ZI Z32 32-Lead TSOP Type 1
CY62128V18LL-200ZI Z32
CY62128V18L-200ZAI ZA32 32-Lead STSOP Type 1
CY62128V18LL-200ZAI ZA32
CY62128V18L-200ZRI ZR32 32-Lead Reverse TSO P 1
CY62128V18LL-200ZRI ZR32
Ordering Information (continued)
Speed
(ns) Orderi ng Code Package
Name P ackage Type Operating
Range
Package D i ag r ams
32-Lead (450 MIL) Molded SOIC S34
51-85081-A
CY62128V Family
10
Package D i ag r ams (continued)
51-85056-C
32-Lead Thin Small Outline Package Z32
CY62128V Family
11
Package D i ag r ams (continued)
32-Lead Shrunk Thin Small Outline Package ZA32
51-85094-B
CY62128V Family
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it conv ey or imply any license under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package D i ag r ams (continued)
51-85089-B
32-Lead Reverse Thin Sm all Outline Package ZR32
