Product Specification PE42543 UltraCMOS(R) SP4T RF Switch 9 kHz-18 GHz Product Description The PE42543 is a HaRPTM technology-enhanced absorptive SP4T RF switch designed for use in Test/ ATE, microwave and other wireless applications. This broadband general purpose switch is a pin-compatible version of the PE42542 with faster switching time and settling time. It exhibits low insertion loss, high isolation and linearity performance from 9 kHz through 18 GHz. No blocking capacitors are required if DC voltage is not present on the RF ports. The PE42543 is manufactured on Peregrine's UltraCMOS(R) process, a patented variation of silicon-oninsulator (SOI) technology on a sapphire substrate. Peregrine's HaRP technology enhancements deliver high linearity and excellent harmonics performance. It is an innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Features HaRP technology-enhanced Fast settling time No gate and phase lag No drift in insertion loss and phase Fast switching time of 500 ns Low insertion loss 1.20 dB @ 3 GHz 2.30 dB @ 13.5 GHz 2.70 dB @ 16 GHz 3.20 dB @ 18 GHz High isolation 55 dB @ 3 GHz 32 dB @ 13.5 GHz 28 dB @ 16 GHz 25 dB @ 18 GHz ESD performance 2500V HBM on all pins Figure 1. Functional Diagram 150V MM on all pins 250V CDM on all pins Figure 2. Package Type 29-lead 4 4 mm LGA DOC-62642 Document No. DOC-12314-2 www.psemi.com (c)2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 14 PE42543 Product Specification Table 1. Electrical Specifications @ 25C (ZS = ZL = 50 ), unless otherwise noted Normal Mode1: VDD = 3.3V, VSS_EXT = 0V or Bypass Mode2: VDD = 3.4V, VSS_EXT = -3.4V Parameter Path Condition Min Operating frequency Typ 9k 0.70 1.20 1.65 2.10 2.30 2.70 3.20 Max Unit 18 G Hz 0.85 1.50 2.05 2.55 2.80 3.20 3.90 dB dB dB dB dB dB dB RFC-RFX 9 kHz-10 MHz 10-3000 MHz 3000-7500 MHz 7500-10000 MHz 10000-13500 MHz 13500-16000 MHz 16000-18000 MHz RFX-RFX 9 kHz-10 MHz 10-3000 MHz 3000-7500 MHz 7500-10000 MHz 10000-13500 MHz 13500-16000 MHz 16000-18000 MHz 80 53 46 41 36 31 27 90 55 48 43 38 33 29 dB dB dB dB dB dB dB Isolation RFC-RFX 9 kHz-10 MHz 10-3000 MHz 3000-7500 MHz 7500-10000 MHz 10000-13500 MHz 13500-16000 MHz 16000-18000 MHz 78 54 41 36 31 27 24 90 55 42 38 32 28 25 dB dB dB dB dB dB dB Return loss (active and common port) RFC-RFX 9 kHz-10 MHz 10-3000 MHz 3000-18000 MHz 22 15 14 dB dB dB RFX 9 kHz-18000 MHz 14 dB Fig. 4 dBm Insertion loss Isolation Return loss (terminated port) Input 0.1dB compression point3 RFC-RFX Input IP2 RFC-RFX 10-18000 MHz 113 dBm Input IP3 RFC-RFX 10-18000 MHz 59 dBm Settling time 50% CTRL to 0.05 dB final value 2 3 s Switching time 50% CTRL to 90% or 10% of final value 500 800 ns Notes: 1. Normal mode: connect VSS_EXT (pin 29) to GND (VSS_EXT = 0V) to enable internal negative voltage generator. 2. Bypass mode: use VSS_EXT (pin 29) to bypass and disable internal negative voltage generator. 3. The input 0.1dB compression point is a linearity figure of merit. Refer to Table 3 for the RF input power PMAX (50). (c)2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 14 Document No. DOC-12314-2 UltraCMOS(R) RFIC Solutions PE42543 Product Specification Figure 3. Pin Configuration (Top View) Table 3. Operating Ranges Symbol Min Supply voltage VDD 2.3 Supply current IDD Parameter Typ Max Unit 5.5 V 120 200 uA 3.4 5.5 V 50 80 uA -3.2 V 1 Normal mode (VSS_EXT = 0V) 2 Bypass mode (VSS_EXT = -3.4V) Supply voltage (VDD 3.4V for Table 1 full spec. compliance) VDD Supply current IDD 2.7 Negative supply voltage VSS_EXT -3.6 Negative supply current ISS -40 Digital input high (V1, V2) VIH 1.17 3.6 V Digital input low (V1, V2) VIL -0.3 0.6 V Fig. 4 30 dBm dBm Fig. 4 32 dBm dBm Fig. 4 20 dBm dBm +85 C -16 uA Normal or Bypass mode Table 2. Pin Descriptions Pin # Pin Name Description 1, 3-6, 8-11, 13-16, 18-21, 23, 25, 26 GND Ground 2 RF21 RF port 2 7 1 RF4 RF port 4 12 RFC1 RF common 17 RF31 RF port 3 22 1 RF1 RF port 1 24 VDD Supply voltage (nominal 3.3V) 27 V2 Digital control logic input 2 28 V1 Digital control logic input 1 29 VSS_EXT2 Pad GND RF input power, CW (RFC-RFX)3 9 kHz-27.5 MHz 27.5 MHz-18 GHz PMAX,CW RF input power, pulsed (RFC-RFX)4 9 kHz-27.5 MHz 27.5 MHz-18 GHz PMAX,PULSED RF input power into terminated ports, CW (RFX)3 9 kHz-18.8 MHz 18.8 MHz-18 GHz PMAX,TERM Operating temperature range TOP -40 +25 Notes: 1. Normal mode: connect VSS_EXT (pin 29) to GND (VSS_EXT = 0V) to enable internal negative voltage generator 2. Bypass mode: use VSS_EXT (pin 29) to bypass and disable internal negative voltage generator 3. 100% duty cycle, all bands, 50 4. Pulsed, 5% duty cycle of 4620 s period, 50 External VSS negative voltage control Exposed pad: Ground for proper operation Notes: 1. RF pins 2, 7, 12, 17, and 22 must be at 0 VDC. The RF pins do not require DC blocking capacitors for proper operation if the 0 VDC requirement is met. 2. Use VSS_EXT (pin 29) to bypass and disable internal negative voltage generator. Connect VSS_EXT (pin 29) to GND (VSS_EXT = 0V) to enable internal negative voltage generator. Document No. DOC-12314-2 www.psemi.com (c)2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 14 PE42543 Product Specification Table 4. Absolute Maximum Ratings Parameter/Condition Supply voltage Digital input voltage (V1, V2) Symbol Min Max Unit VDD -0.3 5.5 V VCTRL -0.3 3.6 V Fig. 4 33 dBm dBm Fig. 4 34 dBm dBm RF input power, CW (RFC-RFX)1 9 kHz-27.5 MHz 27.5 MHz-18 GHz PMAX,ABS RF input power, pulsed (RFC-RFX)2 9 kHz-27.5 MHz 27.5 MHz-18 GHz PMAX,PULSED RF input power into terminated ports, CW (RFX)1 9 kHz-18.8 MHz 18.8 MHz-18 GHz Storage temperature range 3 ESD voltage HBM, all pins 4 Switching Frequency PMAX,TERM TST -65 VESD,HBM Fig. 4 22 dBm dBm +150 C 2500 V ESD voltage MM , all pins VESD,MM 150 V ESD voltage CDM5, all pins VESD,CDM 250 V Notes: 1. 100% duty cycle, all bands, 50 2. Pulsed, 5% duty cycle of 4620 s period, 50 3. Human Body Model (MIL_STD 883 Method 3015) 4. Machine Model (JEDEC JESD22-A115) 5. Charged Device Model (JEDEC JESD22-C101) Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified. The PE42543 has a maximum 25 kHz switching rate when the internal negative voltage generator is used (pin 29 = GND). Switching frequency describes the time duration between switching events. Switching time is the duration between the point the control signal reaches 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. Optional External VSS Control (VSS_EXT) For proper operation, the VSS_EXT control pin must be grounded or tied to the VSS voltage specified in Table 3. When the VSS_EXT control pin is grounded, FETs in the switch are biased with an internal negative voltage generator. For applications that require the lowest possible spur performance, VSS_EXT can be applied externally to bypass the internal negative voltage generator. Spurious Performance The typical spurious performance of the PE42543 is -150 dBm when VSS_EXT = 0V (pin 29 = GND). If further improvement is desired, the internal negative voltage generator can be disabled by setting VSS_EXT = -3.4V. Table 5. Truth Table State V1 V2 RF1 on 0 0 RF2 on 1 0 RF3 on 0 1 RF4 on 1 1 Moisture Sensitivity Level Latch-Up Avoidance The Moisture Sensitivity Level rating for the PE42543 in the 29-lead 4 4 mm LGA package is MSL3. Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Hot-Switching Capability The maximum hot switching capability of the PE42543 is 20 dBm from 18.8 MHz to 18 GHz. The maximum hot switching capability below 18.8 MHz does not exceed the maximum RF CW terminated power, see Figure 4. Hot switching occurs when RF power is applied while switching between RF ports. (c)2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 14 Document No. DOC-12314-2 UltraCMOS(R) RFIC Solutions PE42543 Product Specification Figure 4a. Power De-rating Curve for 9 kHz-18 GHz @ 25C Ambient (50) 35 30 Input Power (dBm) 25 20 15 10 P0.1 dB Compression @ 25C Ambient Max. RF Input Power, Pulsed ( 26.0 MHz, 25C Ambient) 5 Max. RF Input Power, CW ( 26.0 MHz, 25C Ambient) Max. RF Input Power, CW & Pulsed (< 26.0 MHz, 25C Ambient) 0 Max. RF Terminated Power, CW @ 25C Ambient 5 Frequency (MHz) Figure 4b. Power De-rating Curve for 9 kHz-18 GHz @ 85C Ambient (50) 35 30 Input Power (dBm) 25 20 15 10 P0.1 dB Compression @ 85C Ambient Max. RF Input Power, Pulsed ( 27.5 MHz, 85C Ambient) 5 Max. RF Input Power, CW ( 27.5 MHz, 85C Ambient) Max. RF Input Power, CW & Pulsed (< 27.5 MHz, 85C Ambient) 0 Max. RF Terminated Power, CW @ 85C Ambient 5 Frequency (MHz) Document No. DOC-12314-2 www.psemi.com (c)2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 14 PE42543 Product Specification Typical Performance Data @ 25C and VDD = 3.3V (ZS = ZL = 50 ), unless otherwise noted Figure 5. Insertion Loss (RFC-RFX) Figure 6. Insertion Loss vs. Temp (RFC-RFX) (c)2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 14 Figure 7. Insertion Loss vs. VDD (RFC-RFX) Document No. DOC-12314-2 UltraCMOS(R) RFIC Solutions PE42543 Product Specification Typical Performance Data @ 25C and VDD = 3.3V (ZS = ZL = 50 ), unless otherwise noted Figure 8. RFC Port Return Loss vs. Temp Figure 9. RFC Port Return Loss vs. VDD Figure 10. Active Port Return Loss vs. Temp Figure 11. Active Port Return Loss vs. VDD Document No. DOC-12314-2 www.psemi.com (c)2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 14 PE42543 Product Specification Typical Performance Data @ 25C and VDD = 3.3V (ZS = ZL = 50 ), unless otherwise noted Figure 12. Terminated Port Return Loss vs. Temp (c)2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 14 Figure 13. Terminated Port Return Loss vs. VDD Document No. DOC-12314-2 UltraCMOS(R) RFIC Solutions PE42543 Product Specification Typical Performance Data @ 25C and VDD = 3.3V (ZS = ZL = 50 ), unless otherwise noted Figure 14. Isolation vs. Temp (RFX-RFX)* Figure 15. Isolation vs. VDD (RFX-RFX)* Note: * RF1 adjacent to RF3 RF2 adjacent to RF4 RF1 and RF3 opposite to RF2 and RF4 Document No. DOC-12314-2 www.psemi.com (c)2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 14 PE42543 Product Specification Typical Performance Data @ 25C and VDD = 3.3V (ZS = ZL = 50 ), unless otherwise noted Figure 16. Isolation vs. Temp (RFC-RFX, RF1 or RF2 Active)* Figure 17. Isolation vs. VDD (RFC-RFX, RF1 or RF2 Active)* Figure 18. Isolation vs. Temp (RFC-RFX, RF3 or RF4 Active)* Figure 19. Isolation vs. VDD (RFC-RFX, RF3 or RF4 Active)* Note: * RF1 adjacent to RF3 RF2 adjacent to RF4 RF1 and RF3 opposite to RF2 and RF4 (c)2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 14 Document No. DOC-12314-2 UltraCMOS(R) RFIC Solutions PE42543 Product Specification Evaluation Kit Figure 20. Evaluation Board Layout The SP4T switch evaluation board was designed to ease customer evaluation of Peregrine's PE42543. The RF common port is connected through a 50 transmission line via the SMA connector, J1. RF1, RF2, RF3 and RF4 ports are connected through 50 transmission lines via SMA connectors J4, J3, J2 and J5, respectively. A 50 through transmission line is available via SMA connectors J6 and J7, which can be used to de-embed the loss of the PCB. J13 provides DC and digital inputs to the device. The board is constructed of a four metal layer material with a total thickness of 62 mils. The top RF layer is Rogers 4360 material with a thickness of 32 mils and the r = 6.4. The middle layers provide ground for the transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 18 mils, trace gaps of 7 mils and metal thickness of 2.1 mils. For the true performance of the PE42543 to be realized, the PCB should be designed in such a way that RF transmission lines and sensitive DC I/O traces are heavily isolated from one another. High frequency insertion loss and return loss can be further improved by external series inductive tuning traces in the customer application board layout. For example, to improve 12-18 GHz performance, use ~180 pH for RFX ports and ~50 pH for RFC port. PRT-09205 Vector de-embed is recommended to more accurately calculate the performance of the DUT. Refer to Application Note 39 "Vector Deembedding of the PE42542 and PE42543 SP4T RF Switches" for additional information. The half thru line data file can be downloaded from Peregrine's website to facilitate the vector deembedding. Document No. DOC-12314-2 www.psemi.com (c)2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 14 PE42543 Product Specification Figure 21. Evaluation Board Schematic J13 VDD R6 DNI R8 0 OHM R7 0 OHM R1 DNI R2 DNI R3 DNI R4 DNI 1 3 5 7 9 11 13 1 3 5 7 9 11 13 2 4 6 8 10 12 14 2 4 6 8 10 12 14 R5 PE42543 GND RF1 GND GND GND GND RF3 GND 50 OHM 23 22 21 20 19 18 17 16 GND GND GND GND VSS 29 V1 28 V2 27 GND RF2 GND GND GND GND RF4 GND U1 50 OHM C3 C4 C5 C6 DNI DNI DNI DNI J4 J2 J7 C7 DNI 50 OHM J6 30 31 32 33 50 OHM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 J5 50 OHM GND GND GND RFC GND GND GND J3 TMGND 26 DGND 25 VDD 24 DNI THRU J1 50 OHM DOC-12327 CAUTION: Contains parts and assemblies susceptible to damage by electrostatic discharge (ESD). (c)2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 12 of 14 Document No. DOC-12314-2 UltraCMOS(R) RFIC Solutions PE42543 Product Specification Figure 22. Package Drawing 29-lead 4 4 mm LGA A PIN #1 CORNER 4.00 (2X) B 0.26x0.30 (x6) 0.20 x45 Chamfer 0.40 (x5) 0.40 0.33x0.34 (x18) 0.4684 0.4684 0.4284 0.30x0.30 (x5) 0.4284 0.4484 0.4484 0.4484 4.00 0.4484 0.4484 1.13 (x4) 1.13 (x4) 0.24 (x4) 0.24 (x4) 0.4684 0.4284 3.80 0.4484 1.13 0.4684 1.13 0.4284 0.4646 0.10 (x29) (2X) 0.4948 0.4484 0.24 (x4) 3.80 0.4684 0.700.05 0.910.10 0.4684 0.24 (x4) RECOMMENDED LAND PATTERN BOTTOM VIEW TOP VIEW 0.4484 Note: - Dimensions concerning Pad pitch are all mirrored across the Y-axis DOC-50743 SEATING PLANE SIDE VIEW C Figure 23. Top Marking Specification 42543 YYWW ZZZZZ = Pin 1 designator YYWW = Date code, last two digits of assembly year and work week ZZZZZ = Last five characters of the assembly lot code DOC-51207-2 Document No. DOC-12314-2 www.psemi.com (c)2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 13 of 14 PE42543 Product Specification Figure 24. Tape and Reel Drawing Table 6. Ordering Information Order Code Description Package Shipping Method PE42543A-X PE42543 SP4T RF switch 29-lead 4 4 mm LGA 500 units / T&R EK42543-02 PE42543 Evaluation kit Evaluation kit 1 / Box Sales Contact and Information For sales and contact information please visit www.psemi.com. Advance Information: The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. (c)2013-2014 Peregrine Semiconductor Corp. All rights reserved. Page 14 of 14 No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com. Document No. DOC-12314-2 UltraCMOS(R) RFIC Solutions