8
8
1
8
1
1
1
2
3
4 5
6
7
8
N/C
_
VCC
VE
VO
GND
+
N/C
VF
FEATURES
• Very high speed-10 MBit/s
• Superior CMR-10 kV/µs
• Double working voltage-480V
• Fan-out of 8 over -40°C to +85°C
• Logic gate output
• Strobable output
• Wired OR-open collector
• U.L. recognized (File # E90700)
DESCRIPTION
The 6N137, HCPL-2601/2611 single-channel and HCPL-2630/2631 dual-channel
optocouplers consist of a 850 nm AlGaAS LED, optically coupled to a very high
speed integrated photodetector logic gate with a strobable output. This output
features an open collector, thereby permitting wired OR outputs. The coupled
parameters are guaranteed over the temperature range of -40°C to +85°C. A
maximum input signal of 5 mA will provide a minimum output sink current of 13
mA (fan out of 8).
An internal noise shield provides superior common mode rejection of typically 10
kV/µs. The HCPL- 2601 and HCPL- 2631 has a minimum CMR of 5 kV/µs.
The HCPL-2611 has a minimum CMR of 10 kV/µs.
APPLICATIONS
• Ground loop elimination
• LSTTL to TTL, LSTTL or 5-volt CMOS
• Line receiver, data transmission
• Data multiplexing
• Switching power supplies
• Pulse transformer replacement
• Computer-peripheral interface
Input Enable Output
HHL
LHH
HLH
LLH
HNCL
LNCH
A 0.1 µF bypass capacitor must be connected between pins 8 and 5.
(See note 1)
TRUTH TABLE
(Positive Logic)
1
2
3
4 5
6
7
8
+
_
VF1
VCC
V01
V02
GND
VF2
_
+
HCPL-2630
HCPL-2631
6N137
HCPL-2601
HCPL-2611
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
2001 Fairchild Semiconductor Corporation
DS300202 7/9/01 1 OF 11 www.fairchildsemi.com
SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Max Units
Input Current, Low Level IFL 0 250 µA
Input Current, High Level IFH *6.3 15 mA
Supply Voltage, Output VCC 4.5 5.5 V
Enable Voltage, Low Level VEL 0 0.8 V
Enable Voltage, High Level VEH 2.0 VCC V
Low Level Supply Current TA-40 +85 °C
Fan Out (TTL load) N 8
Parameter Symbol Value Units
Storage Temperature TSTG -55 to +125 °C
Operating Temperature TOPR -40 to +85 °C
Lead Solder Temperature TSOL 260 for 10 sec °C
EMITTER
DC/Average Forward Single channel IF
50 mA
Input Current Dual channel (Each channel) 30
Enable Input Voltage Single channel VE5.5 V
Not to exceed VCC by more than 500 mV
Reverse Input Voltage Each channel VR5.0 V
Power Dissipation Single channel PI
100 mW
Dual channel (Each channel) 45
DETECTOR
Supply Voltage VCC 7.0 V
(1 minute max)
Output Current Single channel IO
50 mA
Dual channel (Each channel) 50
Output Voltage Each channel VO7.0 V
Collector Output Single channel PO
85 mW
Power Dissipation Dual channel (Each channel) 60
ABSOLUTE MAXIMUM RATINGS (No derating required up to 85°C)
* 6.3 mA is a guard banded value which allows for at least 20 % CTR degradation. Initial input current threshold value is 5.0 mA or less
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
www.fairchildsemi.com 2 OF 11 7/9/01 DS300202
SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611
AC Characteristics Test Conditions Symbol Min Typ** Max Unit
Propagation Delay Time (Note 4) (TA=25°C) TPLH
20 45 75 ns
to Output High Level (RL= 350 1, CL= 15 pF) (Fig. 12) 100
Propagation Delay Time (Note 5) (TA=25°C) TPHL
25 45 75 ns
to Output Low Level (RL= 350 1, CL= 15 pF) (Fig. 12) 100
Pulse Width Distortion (RL= 350 1, CL= 15 pF) (Fig. 12) TPHL-TPLH335ns
Output Rise Time (10-90%) (RL= 350 1, CL= 15 pF) tr50 ns
(Note 6) (Fig. 12)
Output Fall Time (90-10%) (RL= 350 1, CL= 15 pF) tf12 ns
(Note 7) (Fig. 12)
Enable Propagation Delay Time (IF= 7.5 mA, VEH = 3.5 V) tELH 20 ns
to Output High Level (RL= 350 1, CL= 15 pF) (Note 8) (Fig. 13)
Enable Propagation Delay Time (IF= 7.5 mA, VEH = 3.5 V) tEHL 20 ns
to Output Low Level (RL= 350 1, CL= 15 pF) (Note 9) (Fig. 13)
Common Mode Transient Immunity (TA=25°C) VCM= 50 V, (Peak)
(at Output High Level) (IF= 0 mA, VOH (Min.) = 2.0 V) CMHV/µs
6N137, HCPL-2630 (RL= 350 1) (Note 10) 10,000
HCPL-2601, HCPL-2631 (Fig. 14) 5000 10,000
HCPL-2611 VCM= 400 V 10,000 15,000
(RL= 350 1) (IF= 7.5 mA, VOL (Max.) = 0.8 V) 10,000
Common Mode 6N137, HCPL-2630 VCM= 50 V (Peak) CMLV/µs
Transient Immunity HCPL-2601, HCPL-2631 (TA=25°C) 5000 10,000
(at Output Low Level) (Note 11) (Fig. 14)
HCPL-2611 (TA=25°C) VCM= 400 V 10,000 15,000
SWITCHING CHARACTERISTICS (TA= -40°C to +85°C, VCC = 5 V, IF= 7.5 mA Unless otherwise specified.)
Parameter Test Conditions Symbol Min Typ** Max Unit
EMITTER (IF= 10 mA) VF
1.8 V
Input Forward Voltage TA=25°C 1.4 1.75
Input Reverse Breakdown Voltage (IR= 10 µA) BVR 5.0 V
Input Capacitance (VF= 0, f = 1 MHz) CIN 60 pF
Input Diode Temperature Coefficient (IF= 10 mA) VF/TA-1.4 mV/°C
DETECTOR 710
High Level Supply Current Single Channel (VCC = 5.5 V, IF= 0 mA) ICCH mA
Dual Channel (VE= 0.5 V) 10 15
Low Level Supply Current Single Channel (VCC = 5.5 V, IF= 10 mA) ICCL
913
mA
Dual Channel (VE= 0.5 V) 14 21
Low Level Enable Current (VCC = 5.5 V, VE= 0.5 V) IEL -0.8 -1.6 mA
High Level Enable Current (VCC = 5.5 V, VE= 2.0 V) IEH -0.6 -1.6 mA
High Level Enable Voltage (VCC = 5.5 V, IF= 10 mA) VEH 2.0 V
Low Level Enable Voltage (VCC = 5.5 V, IF= 10 mA) (Note 3) VEL 0.8 V
INDIVIDUAL COMPONENT CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (TA= -40°Cto +85°C Unless otherwise specified.)
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
DS300202 7/9/01 3 OF 11 www.fairchildsemi.com
SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611
Characteristics Test Conditions Symbol Min Typ** Max Unit
Input-Output (Relative humidity = 45%)
Insulation Leakage Current (TA = 25°C, t = 5 s) II-O 1.0* µA
(VI-O = 3000 VDC)
(Note 12)
Withstand Insulation Test Voltage (RH < 50%, TA = 25°C) VISO 2500 VRMS
(Note 12) ( t = 1 min.)
Resistance (Input to Output) (VI-O = 500 V) (Note 12) RI-O 1012 1
Capacitance (Input to Output) (f = 1 MHz) (Note 12) CI-O 0.6 pF
ISOLATION CHARACTERISTICS (TA= -40°C to +85°C Unless otherwise specified.)
** All typical values are at VCC = 5 V, TA= 25°C
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid tantalum
capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC and GND pins
of each device.
2. Each channel.
3. Enable Input - No pull up resistor required as the device has an internal pull up resistor.
4. tPLH - Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the 1.5 V
level on the LOW to HIGH transition of the output voltage pulse.
5. tPHL - Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the 1.5 V
level on the HIGH to LOW transition of the output voltage pulse.
6. tr - Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
7. tf - Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
8. tELH - Enable input propagation delay is measured from the 1.5 V level on the HIGH to LOW transition of the input voltage pulse
to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.
9. tEHL - Enable input propagation delay is measured from the 1.5 V level on the LOW to HIGH transition of the input voltage pulse
to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.
10. CMH - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state
(i.e., VOUT > 2.0 V). Measured in volts per microsecond (V/µs).
11. CML - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low output state
(i.e., VOUT < 0.8 V). Measured in volts per microsecond (V/µs).
12. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.
NOTES
DC Characteristics Test Conditions Symbol Min Typ** Max Unit
High Level Output Current (VCC = 5.5 V, VO= 5.5 V) IOH 100 µA
(IF= 250 µA, VE= 2.0 V) (Note 2)
Low Level Output Current (VCC = 5.5 V, IF= 5 mA) VOL .35 0.6 V
(VE= 2.0 V, ICL = 13 mA) (Note 2)
Input Threshold Current (VCC = 5.5 V, VO= 0.6 V, IFT 35mA
VE= 2.0 V, IOL = 13 mA)
TRANSFER CHARACTERISTICS (TA= -40°C to +85°C Unless otherwise specified.)
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
www.fairchildsemi.com 4 OF 11 7/9/01 DS300202
SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
DS300202 7/9/01 5 OF 11 www.fairchildsemi.com
Fig.1 Low Level Output Voltage vs. Ambient Temperature
TA - Ambient Temperature (˚C)
TA - Ambient Temperature (˚C)
TA - Ambient Temperature (˚C)
-40 -20 0 20 40 60 80
V
OL
-Low Level Output Voltage (V)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
IOL
= 16 mA
IF - Forward Current (mA)
Fig. 4 Low Level Output Current
vs. Ambient Temperature
-40 -20 0 20 40 60 80
I
OL
-
Low Level Output Current (mA)
20
25
30
35
40
45
50
IF
= 5 mA
IF = 10 mA
IF = 15 mA
Fig. 5 Input Threshold Current
vs. Ambient Temperature
-40 -20 0 20 40 60 80
I
FT
- Input Threshold Current (mA)
1
2
3
4
RL = 350 1
RL = 1k 1
RL = 4k 1
Fig. 6 Output Voltage vs. Input Forward Current
0123456
V
O
- Output Voltage (V)
0
1
2
3
4
5
6
RL = 350 1
RL = 1k 1
RL =4k 1
IOL
= 6.4 mA
IOL
= 9.6 mA
IOL
= 12.8 mA
Conditions:
IF = 5 mA
VE = 2 V
VCC
= 5.5V
Conditions:
VCC
= 5.0 V
VO
= 0.6 V
Fig. 2 Input Diode Forward Voltage
vs. Forward Current
VF - Forward Voltage (V)
0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
I
F
= Forward Current (mA)
0.001
0.01
0.1
1
10
16
30
Conditions:
VCC
= 5 V
VE = 2 V
VOL
= 0.6 V
Fig.3 Switching Time vs. Forward Current
IF - Forward Current (mA)
5 7 9 11 13 15
T
P
- Propagation Delay (ns)
0
20
40
60
80
100
120
VCC = 5 V
RL = 1 k (TPLH)
RL = 4 k1(TPLH)
RL = 350 1 (TPLH)
RL = 1 k1
RL = 4 k1
RL = 350 k1
(TPHL)
1
SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611
TYPICAL PERFORMANCE CURVES
Fig. 7 Pulse Width Distortion vs. Temperature
TA - Temperature (˚C) TA - Temperature (˚C)
-60 -40 -20 0 20 40 60 80 100
PWD - Pulse Width Distortion (ns)
0
20
40
60
80
RL = 4 k1
RL = 1 k1
RL = 350 1
F
Conditions:
I = 7.5 mA
VCC = 5 V
Fig. 8 Rise and Fall Time vs. Temperature
-60 -40 -20 0 20 40 60 80 100
Tr/Tf - Rise and Fall Time (ns)
0
100
200
300
400
500
600
LR = 4 k1(tr)
Conditions:
IF = 7.5 mA
VCC = 5 V
RL = 1 k1(tr)
RL = 350 1(tr)
RL = 1 k1
RL = 4 k1 (tf)
RL = 350 1
Fig. 9 Enable Propagation Delay vs. Temperature
TA-Temperature (˚C)
-60 -40 -20 0 20 40 60 80 100
TE-Enable Propagation Delay (ns)
0
20
40
60
80
100
120
RL = 4 k 1(TELH)
RL = 1 k 1(TELH)
RL = 350 1(TELH)
RL = 350 1
RL = 1 k 1
RL = 4 k 1
(TEHL)
]
Fig. 10 Switching Time vs. Temperature
TA-Temperature (˚C)
-60 -40 -20 0 20 40 60 80 100
TP-Propagation Delay (ns)
20
40
60
80
100
120
RL = 1 k 1TPLH
RL = 350 1TPLH
RL = 4 k 1TPLH
RL = 1 k 1
RL = 4 k 1
RL = 350 1
TPHL
Fig. 11 High Level Output Current
vs. Temperature
TA-Temperature (˚C)
-60 -40 -20 0 20 40 60 80 100
IOH-High Level Output Current (µA)
0
5
10
15
20
VCC = 5.5 V
Conditions:
VO = 5.5 V
VE = 2.0 V
IF = 250 µA
]
]
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
www.fairchildsemi.com 6 OF 11 7/9/01 DS300202
SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611
47
1
PHL
t
F
I = 7.5 mA
1.5 V
90%
10%
7.5 mA
+5V
1.5 V
3.0 V
1.5 V
3
2
1
4
8
7
6
5
4 5
Pulse
1
2
3
Generator
tr = 5ns
Z = 50
1
O
8
7
6
+5V
GND
PLH
t
I = 3.75 mA
F
Output
O
(V )
Input
(I )
F
Output
(V )
O
f
t
r
t
CC
V
Output
(V )
O
L
R
C
L
(I )
Input
F
Monitor
O
Z = 50
Pulse
Generator
tr = 5ns
1
(V )
E
Input
Monitor
GND
V
CC
O
(V )
Output
L
R
L
C
(V )
Output
O
Input
(V )
E
EHL
tt
ELH
bypass
.1 f
E
bypass
.1 f
E
Fig. 12 Test Circuit and Waveforms for tPLH, tPHL, trand tf.
Fig. 13 Test Circuit tEHL and tELH.
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
DS300202 7/9/01 7 OF 11 www.fairchildsemi.com
SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611
+5V
Peak
3
2
1
4
8
7
6
5
GND
V
CC
O
(V )
Output
350
1
V
CM
FF
V
A
B
Pulse Gen
I
F
CM
V
0V
O
V
5V Switching Pos. (A), I = 0
F
O
V (Max)
CM
0.5 V
O
VSwitching Pos. (B), I = 7.5 mA
F
H
CM
L
V (Min)
O
bypass
.1 f
E
Fig. 14 Test Circuit Common Mode Transient Immunity
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
www.fairchildsemi.com 8 OF 11 7/9/01 DS300202
SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
DS300202 7/9/01 9 OF 11 www.fairchildsemi.com
SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611
Package Dimensions (Through Hole)
0.200 (5.08)
0.140 (3.55)
0.100 (2.54) TYP
0.022 (0.56)
0.016 (0.41)
0.020 (0.51) MIN
0.390 (9.91)
0.370 (9.40)
0.270 (6.86)
0.250 (6.35)
3
0.070 (1.78)
0.045 (1.14)
241
56 78
0.300 (7.62)
TYP
0.154 (3.90)
0.120 (3.05)
0.016 (0.40)
0.008 (0.20)
15° MAX
PIN 1
ID.
SEATING PLANE
Package Dimensions (Surface Mount)
Lead Coplanarity : 0.004 (0.10) MAX
0.270 (6.86)
0.250 (6.35)
0.390 (9.91)
0.370 (9.40)
0.022 (0.56)
0.016 (0.41)
0.100 (2.54)
TYP
0.020 (0.51)
MIN
0.070 (1.78)
0.045 (1.14)
0.300 (7.62)
TYP
0.405 (10.30)
MIN
0.315 (8.00)
MIN
0.045 [1.14]
32 14
5678
0.016 (0.41)
0.008 (0.20)
PIN 1
ID.
Package Dimensions (0.4"Lead Spacing)
0.200 (5.08)
0.140 (3.55)
0.100 (2.54) TYP
0.022 (0.56)
0.016 (0.41)
0.004 (0.10) MIN
0.390 (9.91)
0.370 (9.40)
0.270 (6.86)
0.250 (6.35)
3
0.070 (1.78)
0.045 (1.14)
241
56 78
0.400 (10.16)
TYP
0.154 (3.90)
0.120 (3.05)
0.016 (0.40)
0.008 (0.20) 0° to 15°
PIN 1
ID.
SEATING PLANE
Recommended Pad Layout for
Surface Mount Leadform
0.070 (1.78)
0.060 (1.52)
0.030 (0.76)
0.100 (2.54)
0.295 (7.49)
0.415 (10.54)
NOTE
All dimensions are in inches (millimeters)
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
4.0 ± 0.1
Ø1.55 ± 0.05
User Direction of Feed
4.0 ± 0.1
1.75 ± 0.10
7.5 ± 0.1
16.0 ± 0.3
12.0 ± 0.1
0.30 ± 0.05
13.2 ± 0.2
4.90 ± 0.20
0.1 MAX 10.30 ± 0.20
10.30 ± 0.20
Ø1.6 ± 0.1
QT Carrier Tape Specifications (“D” Taping Orientation)
ORDERING INFORMATION
S .S Surface Mount Lead Bend
SD .SD Surface Mount; Tape and reel
W .W 0.4” Lead Spacing
Order
Entry
Option Identifier Description
www.fairchildsemi.com 10 OF 11 7/9/01 DS300202
SINGLE-CHANNEL DUAL-CHANNEL
6N137 HCPL-2630
HCPL-2601 HCPL-2631
HCPL-2611
MARKING INFORMATION
Reflow Profile
1
2
6
43 5
Definitions
1 Fairchild logo
2 Device number
3VDE mark (Note: Only appears on parts ordered with VDE
option – See order entry table)
4 Two digit year code, e.g., ‘03’
5 Two digit work week ranging from ‘01’ to ‘53’
6 Assembly package code
2601
T1YYXXV
• Peak reflow temperature: 225 C (package surface temperature)
• Time of temperature higher than 183 C for 60–150 seconds
• One time soldering reflow is recommended
215 C, 10–30 s
225 C peak
Time (Minute)
0
300
250
200
150
100
50
0
0.5 1 1.5 2 2.5 3 3.5 4 4.5
Temperature (°C)
Time above 183 C, 60–150 sec
Ramp up = 3 C/sec
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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