T6817 Dual Triple DMOS Output Driver with Serial Input Control Description The T6817 is a fully protected driver interface designed in 0.8-m BCDMOS technology. It is used to control up to 6 different loads by a microcontroller in automotive and industrial applications. Each of the 3 high-side and 3 Low-side drivers is capable to drive currents up to 600 mA. The drivers are freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the applications of H-bridges to drive DC motors. Protection is guaranteed in terms of short-circuit conditions, overtemperature, under- and overvoltage. Various diagnosis functions and a very low quiescent current in standby mode open a wide range of applications. Automotive qualification referring to conducted interferences, EMC protection and 2 kV ESD protection gives added value and enhanced quality for the exacting requirements of automotive applications. Features D Three high-side and three low-side drivers D Outputs short-circuit protected D Outputs freely configurable as switch, half bridge or H-bridge D Overtemperature prewarning and protection D Capable to switch all kinds of loads such as DC motors, bulbs, resistors, capacitors and inductors D 0.6 A continuous current per switch D Low-side: RDSon < 1.5 vs. total temperature range D High-side: RDSon < 2.0 vs. total temperature range D Very low quiescent current Is < 20 A in standby mode D Undervoltage and overvoltage protection D Various diagnosis functions such as shorted output, open load, overtemperature and power supply fail D Serial data interface D Daisy chaining possible D Loss of ground protection D SSO20 package Ordering Information Extended Type Number Package T6817-FP SSO20 Power package Rev. A2, 10-Jul-01 Remarks 1 (14) Preliminary Information T6817 Block Diagram HS3 HS2 HS1 12 14 16 Osc Fault Detect Fault Detect Vs Fault Detect 6 Vs DI CLK VS 2 4 S I S C T O L n. D u. n. u. n. u. n. u. n. u. n. u. Input Register CS INH 3 5 I N H S C D n. u. n. u. H S 2 L S 2 H S 1 L S 1 n. n. u. u. n. n. u. u. H S 3 L S 3 H S 2 L S 2 H S 1 OV- protection S R R Control logic Serial interface Output Register P S F L S 3 H S 3 7 VS UV- protection L T S P 1 Vcc Vcc 19 GND 1 P ower-on Reset DO GND 10 18 Vcc GND 11 Fault Detect Fault Detect Fault Detect Thermal protection GND 13 20 8 LS3 15 LS2 GND 17 LS1 Figure 1. Block diagram 2 (14) Rev. A2, 10-Jul-01 Preliminary Information T6817 Pin Description GND VCC DO 20 19 LS1 18 HS1 LS2 16 17 HS2 GND HS3 15 GND 14 13 12 11 6 7 8 9 10 VS VS LS3 Leadframe T6817 2 3 GND DI CS 1 4 5 CLK INH n.c. GND Figure 2. Pinning Pin Description Pin Symbol 1 GND Function 2 DI Serial data input; 5-V CMOS logic level input with internal pull-down; receives serial data from the control device, DI expects a 16-bit control word with LSB being transferred first 3 CS Chip-select input; 5-V CMOS logic level input with internal pull-up; low = serial communication is enabled, high = disabled 4 CLK Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) 5 INH Inhibit input; 5-V logic input with internal pull-down; low = standby, high = normal operating 6, 7 VS Power supply output stages HS1, HS2 and HS3 8 LS3 Low-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by active zenering; short-circuit protection; diagnosis for short and open load 9 n.c. Not connected 10 GND Ground, see Pin 1 11 GND Ground, see Pin 1 12 HS3 High-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by active zenering; short-circuit protection; diagnosis for short and open load 13 GND Ground, see Pin 1 14 HS2 High-side driver output 2; see Pin 12 15 LS2 Low-side driver output 2; see Pin 8 16 HS1 High-side driver output 1; see Pin 12 17 LS1 Low-side driver output 1; see Pin 8 18 DO Serial data output; 5-V CMOS logic level tristate output for output (status) register data; sends 16-bit status information to the mC (LSB is transferred first); output will remain tristated unless device is selected by CS = low, therefore, several ICs can operate on one data output line only. 19 VCC Logic supply voltage (5 V) 20 GND Ground, see Pin 1 Ground; reference potential; internal connection to Pin 10, 11, 13 and 20; cooling tab Rev. A2, 10-Jul-01 3 (14) Preliminary Information T6817 Functional Description Serial Interface CS DI SRR LS1 HS1 LS2 HS2 LS3 HS3 n.u. n.u. n.u. 0 1 2 3 4 5 6 7 8 9 TP SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 n.u. n.u. n.u. n.u. 10 n.u. 11 n.u. 12 OLD SCT SI 13 14 15 SCD INH PSF CLK DO n.u. n.u. n.u. Figure 3. Data transfer Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, Pin DO is in tristate condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Input Data Protocol Bit Input Register Function 0 SRR Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown in the output data register are set to low) 1 LS1 Controls output LS1 (high = switch output LS1 on) 2 HS1 Controls output HS1 (high = switch output HS1 on) 3 LS2 See LS1 4 HS2 See HS1 5 LS3 See LS1 6 HS3 See HS1 7 n.u. Not used 8 n.u. Not used 9 n.u. Not used 10 n.u. Not used 11 n.u. Not used 12 n.u. Not used 13 OLD Open load detection (low = on) 14 SCT Programmable time delay for short circuit and overvoltage shutdown (short circuit shutdown delay high / low = 100 ms / 12.5 ms, overvoltage shutdown delay high / low = 14 ms / 3.5 ms 15 SI Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digitalpart is still powered) After power-on reset, the input register has the following status: 4 (14) Rev. A2, 10-Jul-01 Preliminary Information T6817 Bit 15 (SI) Bit 14 (SCT) Bit 13 (OLD) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 (HS3) Bit 5 (LS3) Bit 4 (HS2) Bit 3 (LS2) Bit 2 (HS1) Bit 1 (LS1) Bit 0 (SRR) H H H n.u. n.u. n.u. n.u. n.u. n.u. L L L L L L L Output Data Protocol Bit Output (Status) Register Function 0 TP 1 Status LS1 Temperature prewarning: high = warning (overtemperature shut down see remark below) Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) 2 Status HS1 Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) 3 Status LS2 Description see LS1 4 Status HS2 Description see HS1 5 Status LS3 Description see LS1 6 Status HS3 Description see HS1 7 n.u. Not used 8 n.u. Not used 9 n.u. Not used 10 n.u. Not used 11 n.u. Not used 12 n.u. Not used 13 SCD Short circuit detected: set high, when at least one output is switched off by a short circuit condition 14 INH Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit (Pin 17). High = standby, low = normal operation 15 PSF Power supply fail: over- or undervoltage at Pin VS detected Remark: Bit 0 to 15 = high: overtemperature shutdown function for this output. If bit SI is set to low, the openload function is also switched off. Power Supply Fail In case of over- or undervoltage at Pin VS, an internal timer is started. When the over- or undervoltage delay time (tdOV/tdUV) programmed by the SCT bit is reached, the power supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal voltage is present again the outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input register. Open-Load Detection If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current IHS1-3, ILS1-3). If VVS-VHS1-3 or VLS1-3 is lower than the open-load detection threshold (open-load condition), the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the open-load Overtemperature Protection If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low, the state of TP appears at Pin DO. After the mC has read this information, CS is set high and the data transfer is interrupted without affecting the state of input and output registers. If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the outputs are disabled and all bits in the output register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, Tj switch on, and when a high has been written to the SRR bit in the input register. Rev. A2, 10-Jul-01 5 (14) Preliminary Information T6817 Thermal prewarning and shutdown threshold have hysteresis. Short-Circuit Protection The output currents are limited by a current regulator. Current limitation takes place when the overcurrent limitation and shutdown threshold (IHS1-3, ILS1-3) are reached. Simultaneously, an internal timer is started. The shorted output is disabled when during a permanent short the delay time (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-circuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled. Inhibit There are two ways to inhibit the T6817: 1. Set bit SI in the input register to zero 2. Switch Pin 5 (INH) to 0 V In both cases, all output stages are turned off but the serial interface stays active. The output stages can be activated again by bit SI = 1 and by Pin 5 (INH) switched back to 5 V. Absolute Maximum Ratings All values refer to GND pins Parameters Supply voltage Pins 6, 7 Supply voltage tt0.5 s; ISu-2 A Pins 6, 7 Supply voltage difference |VS_Pin6 - VS_Pin7| Supply current Pins 6, 7 Supply current t < 200 ms Pins 6,7 Logic supply voltage Pin 19 Input voltage Pin 5 Logic input voltage Pins 2 to 4 Logic output voltage Pin 18 Input current Pins 5, 2 to 4 Output current Pin 18 Output current Pins 8, 12, 14 to 17 Reverse conducting current (tPulse = 150 ms) Junction temperature range Storage temperature range Pins 12, 14, 16, towards Pins 6, 7 Symbol VVS VVS DVVS IVS IVS VVCC VINH VDI, VCS, VCLK VDO IINH, IDI, ICS, ICLK IDO ILS1 to ILS3 IHS1 to IHS3 IHS1 to IHS3 Value - 0.3 to 40 -1 150 1.4 2.6 -0.3 to 7 -0.3 to 17 -0.3 to VVCC + 0.3 -0.3 to VVCC + 0.3 -10 to +10 -10 to +10 Internal limited, see output specification 17 Unit V V mV A A V V V V mA mA Tj -40 to 150 -55 to 150 C C TSTG A Operating Range All values refer to GND pins Parameters Supply voltage Logic supply voltage Logic input voltage Serial interface clock frequency Junction temperature range 1) Test Conditions / Pins Pins 6, 7 Pin 19 Pin 2 to 4 and 5 Pin 4 Threshold for undervoltage detection 2) Symbol Min. VVS VVCC VINH, VDI, VCLK, VCS fCLK Tj VUV 1) 4.5 -0.3 -40 Typ. 5 Max. Unit 40 2) 5.5 VVCC 2 150 V V V MHz C Outputs disabled for VVS > VOV (threshold for overvoltage detection) 6 (14) Rev. A2, 10-Jul-01 Preliminary Information T6817 Thermal Resistance All values refer to GND pins Parameters Junction - pin Test Conditions / Pins Symbol Max. Unit RthJP 25 K/W RthJA 65 K/W Measured to GND Pins 1, 10, 11, 13 and 20 Junction ambient Min. Typ. Noise and Surge Immunity Parameters Test Conditions Value Level 4 1) Conducted interferences ISO 7637-1 Interference Suppression VDE 0879 Part 2 ESD (Human Body Model) ESD STM 5.1 - 1998 2 kV ESD (Machine Model) JEDEC EIA / JESD 22 - A115-A 150 V 1) Level 5 Test pulse 5: VSmax = 40 V Electrical Characteristics 7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. Parameters Test Conditions / Pins Symbol Quiescent current (VS) VVSt16 V, INH or bit SI = low Pins 6, 7 Quiescent current (VCC) Min. Typ. Max. Unit IVS 40 mA 4.5 VtVVCC t5.5 V, INH or bit SI = low Pin 19 IVCC 20 mA Supply current (VS) VVSt16 V normal operating, all output stages off, Pins 6, 7 IVS 1.2 mA Supply current (VS) VVS < 16 V normal operating, all output stages on, no load Pins 6, 7 IVS 10 mA Supply current (VCC) 4.5 V < VVCC < 5.5 V, normal operating Pin 19 IVCC 150 mA 45 kHz Current Consumption 0.8 Internal Oscillator Frequency Frequency (time-base for delay timers) fOSC 19 VVCC 3.4 3.9 4.4 V tdPor 30 95 160 ms VUV 5.5 7.0 V Over- and Undervoltage Detection, Power-On Reset Power-on reset threshold Power-on reset delay time Undervoltage detection threshold Pin 19 After switching on VVCC Pins 6, 7 Rev. A2, 10-Jul-01 7 (14) Preliminary Information T6817 Electrical Characteristics (continued) 7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. Parameters Test Conditions / Pins Undervoltage detection hysteresis Pins 6, 7 Undervoltage detection delay Symbol DVUV Max. 0.4 Unit V 7 21 ms 18.0 22.5 V Pins 6, 7 VOV Overvoltage detection hysteresis Pins 6, 7 DVOV Input register bit 14 (SCT) = high bit 14 (SCT) = low Typ. tdUV Overvoltage detection threshold Overvoltage detection delay Min. 1 tdOV tdOV 7 1.75 Thermal prewarning TjPWset 125 Thermal prewarning TjPWreset V 21 5.25 ms ms 145 165 C 105 125 145 C DTjPW 3 20 Thermal shutdown Tj switch off 150 170 190 C Thermal shutdown Tj switch on 130 150 170 C Thermal shutdown hysteresis DTj switch 3 20 Ratio thermal shutdown / thermal prewarning Tj switch off/ TjPW set 1.05 1.17 Ratio thermal shutdown / thermal prewarning Tj switch on/ TjPW reset 1.05 1.2 Thermal Prewarning and Shutdown Thermal prewarning hysteresis Output Specification (LS1 - LS3, HS1 - HS3) On resistance On resistance IOut = 600 mA Pins 8, 15 and 17 RDS OnL 1.5 W IOut = -600 mA Pins 12, 14 and 16 RDS OnH 2.0 W 60 V 10 mA ILS1-3 = 50 mA Pins 8, 15 and 17 Output leakage current VLS1-3 = 40 V all output stages off Pins 8, 15 and 17 ILS1-3 VHS1-3 = 0 V all output stages off Pins 12, 14 and 16 IHS1-3 Inductive shutdown energy Pins 8, 12, 14 to 17 Woutx Output voltage edge steepness Pins 8, 12, 14 to 17 dVLS1-3/dt dVHS1-3/dt 50 ILS1-3 650 Overcurrent limitation and shutdown threshold K 7.5 V < VVS < VOV Output clamping voltage Output leakage current K Pins 8, 15 and 17 VLS1-3 8 (14) 40 mA -10 15 mJ 200 400 mV/ms 950 1250 mA Rev. A2, 10-Jul-01 Preliminary Information T6817 Electrical Characteristics (continued) 7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. Parameters Overcurrent limitation and shutdown threshold Test Conditions / Pins Pins 12, 14 and 16 Symbol Min. Typ. Max. Unit IHS1-3 -1250 -950 -650 mA tdSd tdSd 70 8.75 100 12.5 140 17.5 ms ms Overcurrent shutdown delay time Input register bit 14 (SCT) = high bit 14 (SCT) = low Open load detection current Input register bit 13 (OLD) =low, output off Pins 8, 15 and 17 ILS1-3 60 200 mA Open load detection current Input register bit 13 (OLD) =low, output off Pins 12, 14 and 16 IHS1-3 -150 -30 mA ILS1-3 / IHS1-3 1.2 Open load detection current ratio Open load detection threshold Input register bit 13 (OLD) =low, output off Pins 8, 15 and 17 VLS1-3 0.6 4 V Open load detection threshold Input register bit 13 (OLD) =low, output off Pins 12, 14 and 16 VVSVHS1-3 0.6 4 V Output Switch on delay 1) RLoad = 1 kW tdon 0.5 ms Output Switch off delay 1) RLoad = 1 kW tdoff 1 ms Inhibit Input Input voltage low level threshold Pin 5 VIL Input voltage high level threshold Pin 5 VIH Hysteresis of input voltage Pin 5 VI Pin 5 Pull-down current VINH = VVCC 0.3 VVCC V 0.7 VVCC V 100 700 mV IPD 10 80 mA 0.3 VVCC Serial Interface - Logic Inputs DI, CLK, CS Input voltage low level threshold Pins 2-4 VIL Input voltage high level threshold Pins 2-4 VIH Hysteresis of input voltage Pins 2-4 VI V 0.7 VVCC V 50 500 mV Pull-down current Pin DI, CLK VDI, VCLK = VVCC Pins 2 and 4 IPDSI 2 50 mA Pull-up current Pin CS VCS= 0 V IPUSI -50 -2 mA 1) Pin 3 Delay time between rising edge of CS after data transmision and switch on/off output stages to 90% of final level Rev. A2, 10-Jul-01 9 (14) Preliminary Information T6817 Electrical Characteristics (continued) 7.5 V < VVS < VOV; 4.5 V < VVCC < 5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. Parameter Test Conditions / Pins Symbol Min. Typ. Max. Unit 0.5 V Serial Interface - Logic Output DO Output voltage low level IOL = 3 mA Pin 18 VDOL Output voltage high level IOL = -2 mA Pin 18 VDOH VVCC-1V Leakage current (tristate) VCS = VVCC, 0 VtVDOtVVCC IDO -10 V 10 mA Max. Unit Pin 18 Parameters Test Conditions Timing Chart No. Symbol Min. Typ. Serial Interface - timing DO enable after CS falling edge CDO = 100 pF 1 tENDO 200 ns DO disable after CS rising edge CDO = 100 pF 2 tDISDO 200 ns DO fall time CDO = 100 pF - tDOf 100 ns DO rise time CDO = 100 pF - tDOr 100 ns DO valid time CDO = 100 pF 200 ns 10 tDOVal CS setup time 4 tCSSethl 225 ns CS setup time 8 tCSSetlh 225 ns CS high time Input register Bit 14 (SCT) = high 9 tCSh 140 ms CS high time Input register Bit 14 (SCT) = low 9 tCSh 17.5 ms CLK high time 5 tCLKh 225 ns CLK low time 6 tCLKl 225 ns CLK period time - tCLKp 500 ns CLK setup time 7 tCLKSethl 225 ns CLK setup time 3 tCLKSetlh 225 ns DI setup time 11 tDIset 40 ns DI hold time 12 tDIHold 40 ns 10 (14) Rev. A2, 10-Jul-01 Preliminary Information T6817 1 2 CS DO 9 CS 4 7 CLK 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 x VCC, Low level = 0.3 x VCC Output DO: High level = 0.8 x VCC, Low level = 0.2 x VCC Figure 4. Serial interface timing diagram with chart numbers Rev. A2, 10-Jul-01 11 (14) Preliminary Information T6817 Application Circuit Vcc Trigger Enable HS3 HS2 12 HS1 14 16 Vs Osc Fault Detect Fault Detect DI 2 CLK mC 4 CS 3 INH 5 VS OV - protection S O H L H L H L S n. n. n. n. n. S S S S S S R S C L n. I T D u. u. u. u. u. u. 3 3 2 2 1 1 R Input Register Output Register Control logic Serial interface VS UV- protection P I S n. n. n. n. n. n. H L H L H L T S N C u. u. u. u. u. u. S S S S S S P F H D 3 3 2 2 1 1 P ower-on Reset DO 18 Vcc Vs 7 VBATT 13V Vcc Vcc Vcc 19 1 BYT41D Vs 6 + Fault Detect + Reset U5021M WATCHDOG Vcc 5V GND GND 10 GND 11 Fault Detect Fault Detect 8 Vcc LS3 Fault Detect 15 LS2 Thermal protection 17 GND 13 20GND LS1 Figure 5. Application circuit Application Notes It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: electrolythic capacitor C > 22 F in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IHSX (see: Absolut Maximum Ratings). Recommended value for capacitors at VCC: electrolythic capacitor C > 10 F in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to GND pins. 12 (14) Rev. A2, 10-Jul-01 Preliminary Information T6817 Package Information Package SSO20 5.7 5.3 Dimensions in mm 6.75 6.50 4.5 4.3 1.30 0.15 0.15 0.05 0.25 6.6 6.3 0.65 5.85 20 11 technical drawings according to DIN specifications 1 10 Rev. A2, 10-Jul-01 13 (14) Preliminary Information T6817 Ozone Depleting Substances Policy Statement It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.atmel-wm.com Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423 14 (14) Rev. A2, 10-Jul-01 Preliminary Information