1
FEATURES
APPLICATIONS
Upto11.3Gbps
DifferentialInputSignal TLK1102E
AC -
Coupling
TLK1102E
AC -
Coupling
Upto20-meter100 W
CableorEquivalent
BackplaneLink
100 WDifferential
PCBInterconnect
Upto20-meter100 W
CableorEquivalent
BackplaneLink
100 Differential
PCBInterconnect
100WDifferential
PCBInterconnect
100WDifferential
PCBInterconnect
W
DESCRIPTION
TLK1102E
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................................................................................................................................................................................................... SLLS958 – MARCH 2009
11.3-Gbps Dual-Channel Cable and PC Board Equalizer
•Surface Mount Small Footprint 4-mm × 4-mm24-Pin QFN Package23
•Dual-Channel Multi-Rate Operation up to11.3Gbps •Single 3.3V Supply•Two-Wire Serial Interface (with 8 Selectable •-40 ° C to 100 ° C Operation (Lead Temperature)Device Addresses) or Device Pin Control•Compensates for up to 30dB Loss on the
•High-Speed Links In Communication and DataReceive Side and up to 7dB Loss on the
SystemsTransmit Side at 5.65GHz
•Backplane, Daughtercard, and Cable•Adjustable Input Equalization Level
Interconnects for 10GE, 8GFC, 10GFC, 10G•Adjustable Output De-Emphasis: 0 - 7dB
SONET, SAS, SATA, and InfiniBand•Adjustable Input Bandwidth: 4.5 - 11GHz
•QSFP, SFP+, XFP, SAS, SATA, and InfiniBand•Adjustable CML Output Swing: 225 -
Active Cable Assemblies1200mV
p-p•Loss of Signal (LOS) Detection•Output Disable with Selectable Auto-SquelchFunction
•Output Polarity Switch•Excellent High Frequency Input and OutputReturn Loss
The TLK1102E is a versatile and flexible high-speed dual-channel equalizer for applications in digital high-speedlinks with data rates up to 11.3Gbps.
The TLK1102E can be configured in many ways through its two-wire serial interface, available through the SDAand the SCL pins, to optimize its performance. The configurable parameters include the output de-emphasissettable from 0 to 7dB, the output differential voltage swing settable from 225 to 1200mV
p-p
, the inputequalization level settable for 0 to 20 meters of 24-AWG twinaxial cable, 0 to 40 inches of FR-4 PCBinterconnect, or equivalent interconnect (see Table 1 ), the input filter bandwidth settable from 4.5 to 11GHz, andthe LOS (loss of signal) assert voltage level.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Spectra-Strip, SKEWCLEAR, XCede are registered trademarks of Amphenol Corporation.3SI is a trademark of Park Electrochemical Corporation.
PRODUCTION DATA information is current as of publication date.
Copyright © 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DESCRIPTION (CONTINUED)
TLK1102E
SLLS958 – MARCH 2009 ...................................................................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
Alternatively, the TLK1102E can be configured using its configuration pins in two modes selectable using theMODE pin. In Pin Control Mode 1 (see Figure 2 b), a common setting can be set for the two channels for theoutput de-emphasis level and the interconnect length using the DE pin and LN0, LN1 pins respectively. In PinControl Mode 2 (see Figure 2 c), those parameters can be set individually for the two channels using DEA, DEB,LNA, and LNB pins. In both modes only a common setting is available for the output voltage swing using theSWG pin. For Pin Control Mode 2 the typical LOS assert and de-assert voltage levels are fixed at 90mV
p-p
and150mV
p-p
respectively with 4.0dB hysteresis.
The outputs can be disabled using the DISA and DISB pins. The DISA/DISB pins and the LOSA/LOSB pins canbe connected together to implement an external output squelch function. The TLK1102E implements an internaloutput squelch function that can be enabled using the two-wire serial interface. In addition, a special fastauto-squelch function can be selected through the two-wire serial interface when needed to support SAS andSATA out-of-band (OOB) signals.
The POLA and POLB pins can be used to reverse the polarity of the OUTA+/OUTA- and OUTB+/OUTB – pinsrespectively.
The high input signal dynamic range ensures low jitter output signals even when overdriven with input signalswings as high as 1600mV
p-p
differential. The low-frequency cut-off is low enough to support low-frequencycontrol signals such as SAS and SATA OOB signals. The loss-of-signal detection and output disable functionsare carefully designed to meet SAS/SATA OOB signal timing constraints.
Table 1. Equalization Level Settings
TWO-WIRE SERIAL I/F MODEPIN MODE 1 PIN MODE 2CABLE LENGTH (meters)
(registers 3 and 6)(1.8dB/m loss at 5 GHz)
LN1 LN0 LNA / LNB EQ3 EQ2 EQ1 EQ0
0 – 2 GND GND GND 1 1 1 12 – 6 GND VCC GND 0 1 1 16 – 11 VCC GND 1.8 M Ωto GND 0 1 0 111 – 15 VCC VCC VCC 0 0 0 0
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BLOCK DIAGRAM
Output
Buffer
Output
Driver
50 W50 W
VCC
Power-On
Reset
BandgapVoltage
Referenceand
BiasCurrent
Generation
2-WireInterfaceand
ControlLogic
SDA
SCL
DISA
IN[B:A]+
IN[B:A]– OUT[B:A]–
OUT[B:A]+
SDA
SCL
DISA
Equalizer
Stage
InputBuffer
with
Selectable
Bandwidth
Offset
Cancellation
DISB
DISB
LossofSignal
Detection
LOS[B:A]
VCC
GND
MODE
MODE
CS
CS
RST
RST
50 W50 W
VCC
ADD0
ADD1
ADD0
ADD1
ADD2 ADD2
GeneralSettings
De-emphasis
OutputSwing
InputBandwidth
LOS AssertLevel
4-Bit
2 4-Bit´
2 7-Bit´
2 4-Bit´
2 7-Bit´
2 4-Bit´
2 1-Bit´
EqualizationLevel
LOSStatus
FastLOSControl
2 4-Bit´
2 1-Bit´
ControlSettings
TLK1102E
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................................................................................................................................................................................................... SLLS958 – MARCH 2009
A simplified block diagram of the TLK1102E is shown in Figure 1 for the two-wire serial interface control mode.This compact, low power, 11.3-Gbps dual-channel equalizer consists of a high-speed data path with an offsetcancellation block combined with an analog input threshold selection circuitry, a loss of signal detection block, atwo-wire interface with a control-logic block, a bandgap voltage reference, and a bias current generation block.
Figure 1. Simplified Block Diagram of the TLK1102E
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PACKAGE
7
19
13
18
12
124
6
TopView
Exposed ThermalPad
mustbesoldered
toGND
EP
INA+
INA-
GND
INB+
INB-
OUTA+
OUTA-
VCC
OUTB+
OUTB-
GND VCC
CS
SDA
SCL
MODE
DISB
LOSB
RST
ADD0
ADD1
ADD2
DISA
LOSA
(a) Two-WireSerialInterfaceControlMode
7
19
13
18
12
124
6
TopView
Exposed ThermalPad
mustbesoldered
toGND
EP
INA+
INA-
GND
INB+
INB-
OUTA+
OUTA-
VCC
OUTB+
OUTB-
GND VCC
DE
LOSL
POLB
MODE
DISB
LOSB
LN0
LN1
POLA
SWG
DISA
LOSA
(b)PinControlMode1
7
19
13
18
12
124
6
TopView
Exposed ThermalPad
mustbesoldered
toGND
EP
INA+
INA-
GND
INB+
INB-
OUTA+
OUTA-
VCC
OUTB+
OUTB-
GND VCC
DEA
DEB
POLB
MODE
DISB
LOSB
LNB
LNA
POLA
SWG
DISA
LOSA
(c)PinControlMode2
TLK1102E
SLLS958 – MARCH 2009 ...................................................................................................................................................................................................
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For the TLK1102E a small footprint 4-mm × 4-mm 24-pin QFN package is used, with a lead pitch of 0.5mm.Three pin-outs are available for this device as shown in Figure 2 . The pin-out in Figure 2 a is applicable for thecase where the device is setup to be controlled through the two-wire serial interface. The pin-outs in Figure 2 band Figure 2 c are applicable for the cases where the device is setup to be controlled through the deviceconfiguration pins. The MODE pin controls the pinout as described in the TERMINAL FUNCTIONS tables.
Figure 2. Pin-Out of the TLK1102E in a 4-mm × 4-mm 24-Pin QFN Package
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TERMINAL FUNCTIONS - TWO-WIRE SERIAL INTERFACE CONTROL MODE
TERMINAL FUNCTIONS - PIN CONTROL MODE 1
TLK1102E
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................................................................................................................................................................................................... SLLS958 – MARCH 2009
Pin descriptions for the TLK1102E in a 4-mm x 4-mm 24-pin QFN package when the device is set to becontrolled using the two-wire serial interface. This mode is selected through setting the MODE pin (pin 10) tohigh level.
PIN SYMBOL TYPE DESCRIPTION
1, 2 INA+, INA- analog-in First pair of differential data inputs. Each pin is on-chip 50 Ωterminated to VCC.3, 4 GND supply Circuit ground.5, 6 INB+, INB- analog-in Second pair of differential data inputs. Each pin is on-chip 50 Ωterminated to VCC.7 CS digital-in Chip Select pin. Disables the two-wire serial interface when set to low level. Internally pulled up.8 SDA digital-in/out Bidirectional serial data pin for the two-wire serial interface. Open drain. Connect to a 10k Ωpull-up resistor if used. Leave open if unused.9 SCL digital-in Serial clock pin for the two-wire serial interface. Connect to a 10k Ωpull-up resistor if used. Leaveopen if unused. Internally pulled up to VCC with a 500k Ωresistor.10 MODE three-state Device control mode select. Pull up to VCC for the two-wire serial interface control mode.11 DISB digital-in Disables CML output stage for OUTB+ and OUTB- when set to high level. Internally pulled down.12 LOSB digital-out High level indicates that the input signal amplitude on INB+/INB- is below the programmedthreshold level. Open drain. Requires an external 10k Ωpull-up resistor to VCC for properoperation.13, 14 OUTB-, OUTB+ analog-out Second pair of differential data outputs. Each pin is on-chip 50 Ωterminated to VCC.15, 16 VCC supply 3.3V ± 10% supply voltage.17, 18 OUTA-, OUTA+ analog-out First pair of differential data outputs. Each pin is on-chip 50 Ωterminated to VCC.19 LOSA digital-out High level indicates that the input signal amplitude on INA+/INA- is below the programmedthreshold level. Open drain. Requires an external 10k Ωpull-up resistor to VCC for properoperation.20 DISA digital-in Disables CML output stage for OUTA+ and OUTA- when set to high level. Internally pulled down.21, 22, ADD2, ADD1, digital-in Configurable least significant bits (ADD[2:0]) of the two-wire serial interface device address. The23 ADD0 fixed most significant bits (ADD[6:3]) of the 7-bit device address are 0101. The default address is0101100. These pins are internally pulled up. Pull down externally to invert the associated bits.24 RST digital-in Reset pin. Resets all the device digital circuits when set to high level. Internally pulled down.EP EP Exposed die pad (EP) must be grounded.
Pin descriptions for the TLK1102E in a 4-mm x 4-mm 24-pin QFN package when the device is set for Pin ControlMode 1. This mode is selected through setting the MODE pin (pin 10) to low level.PIN SYMBOL TYPE DESCRIPTION
1, 2 INA+, INA- analog-in First pair of differential data inputs. Each pin is on-chip 50 Ωterminated to VCC.3, 4 GND supply Circuit ground.5, 6 INB+, INB- analog-in Second pair of differential data inputs. Each pin is on-chip 50 Ωterminated to VCC.7 DE analog-in Output signal de-emphasis control. A 0 to 1.2-V controlling voltage on this pin adjusts outputde-emphasis on OUTA and OUTB pins from 0 to 7dB.8 LOSL analog-in LOS threshold control. A 0 to 0.7-V controlling voltage on this pin adjusts the LOS assert andde-assert levels on INA and INB pins.9 POLB digital-in Output data signal polarity select for OUTB+/OUTB- pins. Internally pulled up. Set to high levelor leave open for normal polarity. Set to low level for inverted polarity.10 MODE three-state Device control mode select. Tie to GND for pin control mode 1.11 DISB digital-in Disables CML output stage for OUTB+ and OUTB- when set to high level. Internally pulleddown.12 LOSB digital-out High level indicates that the input signal amplitude on INB+/INB- is below the programmedthreshold level. Open drain. Requires an external 10k Ωpull-up resistor to VCC for properoperation.13, 14 OUTB-, OUTB+ analog-out Second pair of differential data outputs. Each pin is on-chip 50 Ωterminated to VCC.15, 16 VCC supply 3.3V ± 10% supply voltage.17, 18 OUTA-, OUTA+ analog-out First pair of differential data outputs. Each pin is on-chip 50 Ωterminated to VCC.
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TERMINAL FUNCTIONS - PIN CONTROL MODE 2
TLK1102E
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PIN SYMBOL TYPE DESCRIPTION
19 LOSA digital-out High level indicates that the input signal amplitude on INA+/INA- is below the programmedthreshold level. Open drain. Requires an external 10k Ωpull-up resistor to VCC for properoperation.20 DISA digital-in Disables CML output stage for OUTA+ and OUTA- when set to high level. Internally pulleddown.21 SWG three-state OUTA, OUTB swing control. Tie to VCC for 1200mV
p-p
swing, tie to GND for 225mV
p-p
swing, orpull down with a 1.8M Ωresistor for 600mV
p-p
swing.22 POLA digital-in Output data signal polarity select for OUTB+/OUTB- pins. Internally pulled up. Set to high levelor leave open for normal polarity. Set to low level for inverted polarity.23, 24 LN1, LN0 digital-in Equalization level setting. Internally pulled up. Each pin supports two logic levels: high and low –four settings in the following low to high equalization order: LN1=LN0=0; LN1=0 LN0=1; LN1=1LN0=0; LN1=LN0=1EP EP Exposed die pad (EP) must be grounded.
Pin descriptions for the TLK1102E in a 4-mm x 4-mm 24-pin QFN package when the device is set for Pin ControlMode 2. This mode is selected through pulling down the MODE pin (pin 10) with a 1.8-M Ωresistor.PIN SYMBOL TYPE DESCRIPTION
1, 2 INA+, INA- analog-in First pair of differential data inputs. Each pin is on-chip 50 Ωterminated to VCC.3, 4 GND supply Circuit ground.5, 6 INB+, INB- analog-in Second pair of differential data inputs. Each pin is on-chip 50 Ωterminated to VCC.7 DEA analog-in Output signal de-emphasis control for OUTA. A 0 to 1.2-V controlling voltage on this pin adjustsoutput de-emphasis on OUTA+/OUTA- pins from 0 to 7dB.8 DEB analog-in Output signal de-emphasis control for OUTB. A 0 to 1.2-V controlling voltage on this pin adjustsoutput de-emphasis on OUTB+/OUTB- pins from 0 to 7dB.9 POLB digital-in Output data signal polarity select for OUTB+/OUTB- pins. Internally pulled up. Set to high levelor leave open for normal polarity. Set to low level for inverted polarity.10 MODE three-state Device control mode select. Pull down with a 1.8M Ωresistor for pin control mode 2.11 DISB digital-in Disables CML output stage for OUTB+ and OUTB- when set to high level. Internally pulleddown.12 LOSB digital-out High level indicates that the input signal amplitude on INB+/INB- is below the programmedthreshold level. Open drain. Requires an external 10k Ωpull-up resistor to VCC for properoperation.13, 14 OUTB-, OUTB+ analog-out Second pair of differential data outputs. Each pin is on-chip 50 Ωterminated to VCC.15, 16 VCC supply 3.3V ± 10% supply voltage.17, 18 OUTA-, OUTA+ analog-out First pair of differential data outputs. Each pin is on-chip 50 Ωterminated to VCC.19 LOSA digital-out High level indicates that the input signal amplitude on INA+/INA- is below the programmedthreshold level. Open drain. Requires an external 10k Ωpull-up resistor to VCC for properoperation.20 DISA digital-in Disables CML output stage for OUTA+ and OUTA- when set to high level. Internally pulleddown.21 SWG three-state OUTA, OUTB swing control. Tie to VCC for 1200mV
p-p
swing, tie to GND for 225mV
p-p
swing,or pull down with a 1.8M Ωresistor for 600mV
p-p
swing.22 POLA digital-in Output data signal polarity select for OUTB+/OUTB- pins. Internally pulled up. Set to high levelor leave open for normal polarity. Set to low level for inverted polarity.23 LNA three-state Equalization level setting. Supports three equalization settings. Tie to VCC for high setting, tieto GND for low setting, or pull down with 1.8M Ωresistor for medium setting. Internally tied toVCC/2.24 LNB three-state Equalization level setting. Supports three equalization settings. Tie to VCC for high setting, tieto GND for low setting, or pull down with 1.8M Ωresistor for medium setting. Internally tied toVCC/2.EP EP Exposed die pad (EP) must be grounded.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
TLK1102E
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................................................................................................................................................................................................... SLLS958 – MARCH 2009
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
V
CC
Supply voltage
(2)
-0.3 to 4.0 VV
IN+
, V
IN-
Voltage at INA+, INA-, INB+, INB-
(2)
0.5 to 4.0 VV
IO
Voltage at pin 7 to 11 and pin 20 to 24
(2)
-0.3 to 4.0 VV
IN,DIFF
Differential voltage between INA+ and INA-, and between INB+ and INB- ± 2.5 VI
IN+
, I
IN-
Continuous current at data inputs -25 to 25 mAI
OUT+
, I
OUT-
Continuous current at data outputs -35 to 35 mAI
LOS
Sink current at LOSA and LOSB outputs 25 mAESD ESD rating at all pins 2.5 kV (HBM)T
J,max
Maximum junction temperature 125 ° C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly. Functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute – maximum – rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network ground terminal.
MIN NOM MAX UNIT
V
CC
Supply voltage 2.95 3.3 3.6 VT
A
Operating lead temperature -40 100 ° CV
IH
CMOS input high voltage 2.1 VV
IL
CMOS input low voltage 0.7 V
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
CC
Supply voltage 2.95 3.3 3.6 V600mV
p-p
SWG setting (CML output current included) 170 230I
CC
Supply current mA1200mV
p-p
SWG setting (CML output current included) 225 290LOS high voltage I
SOURCE
= 50 µA; 10k ΩPull-up to V
CC
on LOSA or 2.4 VLOSB pinLOS low voltage I
SINK
= 10mA; 10k ΩPull-up to V
CC
on LOSA or LOSB 0.4 Vpin
Typical operating condition is at V
CC
= 3.3V and T
A
= 25 ° C. Over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Low frequency -3dB bandwidth With 0.1 µF input AC-coupling capacitors 30 50 kHz
BER < 10
-12
, K28.5 pattern at 11.3Gbps over a 10m28AWG cable including two SMA connectors (27dB lossat 5.65GHz),V
IN,MIN
Data input sensitivity 250 mV
p-pSWG = 600mV
p-p
setting, no de-emphasis, maximuminterconnect length setting. Voltage measured at theinput of the cable.
BER < 10
– 12
, K28.5 pattern at 11.3Gbps, K28.5 patternat 11.3Gbps over a 15m 24AWG cable including twoSMA connectors (29dB loss at 5.65GHz), SWG =V
IN,MAX
Data input overload 1600 mV
p-p600mV
p-p
setting, no de-emphasis, maximuminterconnect length setting. Voltage measured at theinput of the cable.
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AC ELECTRICAL CHARACTERISTICS (continued)Typical operating condition is at V
CC
= 3.3V and T
A
= 25 ° C. Over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIS = Low, SWG = Low, V
IN
= 400mV
p-p
,
150 225 350no de-emphasis, no interconnect loss.
Differential data output voltage DIS = Low, SWG = 600mV
p-p
setting, V
IN
= 400mV
p-p
,V
OD
400 600 800 mV
p-pswing no de-emphasis, no interconnect loss.
DIS = Low, SWG = High, V
IN
= 400mV
p-p
,
800 1200 1600no de-emphasis, no interconnect loss.
DIS = Low, SWG = Low, V
IN
= 400mV
p-p
,no de-emphasis, no interconnect loss, 50 Ωto VCC V
CC
-0.12 V
CC
-0.08 V
CC
-0.04output termination.
DIS = Low, SWG = 600mV
p-p
setting, V
IN
= 400mV
p-p
,V
CM,OUT
Data output common-mode voltage no de-emphasis, no interconnect loss, 50 Ωto VCC V
CC
-0.29 V
CC
-0.205 V
CC
-0.12 Voutput termination.
DIS = Low, SWG = High, V
IN
= 400mV
p-p
,no de-emphasis, no interconnect loss, 50 Ωto VCC V
CC
-0.65 V
CC
-0.45 V
CC
-0.25output termination.
DIS = Low, SWG = 600mV
p-p
setting, K28.5 pattern atV
CM,RIP
Common-mode output ripple 11.3Gbps, no interconnect loss, 600mV on DE pin, V
IN
= 2 5 mV
RMS1600mV
p-p
.
DIS = High, K28.5 pattern at 11.3Gbps, no interconnectV
OD,RIP
Differential output ripple 15 20 mV
p-ploss, V
IN
= 1600mV
p-p
.
K28.5 pattern at 11.3Gbps on both channels, nointerconnect loss,
0V
IN
= 400mV
p-p
, SWG = 600mV
p-p
setting, node-emphasis.DE Output de-emphasis dBK28.5 pattern at 11.3Gbps on both channels, nointerconnect loss,
7V
IN
= 400mV
p-p
, SWG = 600mV
p-p
setting, maximumde-emphasis level.
K28.5 pattern at 11.3Gbps on both channels, 10m28AWG cable (27dB loss at 5.65GHz),
8V
IN
= 400mV
p-p
, SWG = 600mV
p-p
setting, 600mV on DEpin, maximum interconnect length setting.DJ Deterministic jitter ps
p-pK28.5 pattern at 11.3Gbps on both channels, 15m24AWG cable (29dB loss at 5.65GHz),
12V
IN
= 400mV
p-p
, SWG = 600mV
p-p
setting, 600mV on DEpin, maximum interconnect length setting.
K28.5 pattern at 11.3Gbps on both channels, 10m28AWG cable (27dB loss at 5.65GHz),
1.2V
IN
= 400mV
p-p
, SWG = 600mV
p-p
setting, 600mV on DEpin, maximum interconnect length setting.RJ Random jitter ps
RMSK28.5 pattern at 11.3Gbps on both channels, 15m24AWG cable (29dB loss at 5.65GHz),
1.4V
IN
= 400mV
p-p
, SWG = 600mV
p-p
setting, 600mV on DEpin, maximum interconnect length setting.
Channel A: K28.5 pattern at 11.3Gbps, 15m 24AWGcable (29dB loss at 5.65GHz), V
IN
= 600mV
p-p
, Register2 = 10h (offset cancellation OFF), Register 3 = 01h(equalizer filter 1 OFF), Register 4 = 66h (680mVppoutput swing, 3.3dB output de-emphasis);JPXT Crosstalk jitter penalty 3 ps
p-pChannel B: Repeated 1010 pattern at 11.3Gbps, nointerconnect line loss, V
IN
= 600mV
p-p
, Register 6 = 10h(offset cancellation OFF), Register 7 = 0Fh (all equalizerfilters OFF), Register 8 = F6h (680mVpp output swing,7dB output de-emphasis);
20% to 80%, No interconnect line,t
R
Output rise time V
IN
= 400mV
p-p
, SWG = 600mV
p-p
setting, no 28de-emphasis
ps20% to 80%, no interconnect loss,t
F
Output fall time V
IN
= 400mV
p-p
, SWG = 600mV
p-p
setting, no 28de-emphasis
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................................................................................................................................................................................................... SLLS958 – MARCH 2009
AC ELECTRICAL CHARACTERISTICS (continued)Typical operating condition is at V
CC
= 3.3V and T
A
= 25 ° C. Over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0.01GHz < f < 4.1GHz See
(1)SDD11 Differential input return loss dB4.1GHz < f < 12.1GHz See
(2)
0.01GHz < f < 4.1GHz See
(1)SDD22 Differential output return loss dB4.1GHz < f < 12.1GHz See
(2)
0.01GHz < f < 7.5GHz See
(3)SCC22 Common-mode output return loss dB7.5GHz < f < 12.1GHz See
(4)
K28.5 Pattern at 11.3Gbps, no interconnect loss,
45 90LOSL = Open (also applies to Pin Control Mode 2)V
AS
LOS assert threshold voltage mV
p-pK28.5 Pattern at 11.3Gbps, no interconnect loss,
70 140V(LOSL) = 0.7V
K28.5 Pattern at 11.3Gbps, no interconnect loss,
150 300LOSL = Open (also applies to Pin Control Mode 2)V
DAS
LOS de-assert threshold voltage mV
p-pK28.5 Pattern at 11.3Gbps, no interconnect,
235 500V(LOSL) = 0.7V
LOS hysteresis 20log(V
DAS
/ V
AS
) 2.5 4.0 dB
T
AS/DAS
LOS assert/De-assert time 1/10 2/20 4/30 µs
K28.5 Pattern at 11.3Gbps, no interconnect loss,V
FAS
Fast LOS assert threshold voltage 150 mV
p-pReg 5/9 = 10111111b
Fast LOS de-assert threshold K28.5 Pattern at 11.3Gbps, no interconnect loss,V
FDAS
220 mV
p-pvoltage Reg 5/9 = 10111111b
Fast LOS hysteresis 20log(V
FDAS
/ V
FAS
) 3.3 dB
Fast auto-squelch mode, no interconnect loss, 600mV
p-pT
SQUELCH
Squelch time input swing, K28.5 pattern, 1.5Gbps, SWG = 600mV
p-p
5 nssetting. Time from input off to output voltage < 120mV
p-p
T
DIS
Disable response time 2 ns
T
SKEW
Channel-to-channel skew OUTB+/ OUTB – relative to OUTA+/OUTA – 2 ps
Latency from IN[B:A]+/ IN[B:A] – to OUT[B:A]+/OUT[B:A] – 165 ps
(1) Differential return loss given by SDD11, SDD22 = 12.3 - 13 log
10
(f/5.5), f in GHz(2) Differential return loss given by SDD11, SDD22 = 18 - 2 √f, f in GHz(3) Common-mode output return loss given by SCC22 = 12 - 2.8f, f in GHz(4) Common-mode output return loss given by SCC22 = 5.2 - 0.08f, f in GHz
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 9
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TWO-WIRE SERIAL INTERFACE AND CONTROL LOGIC
FUNCTIONAL DESCRIPTION
TLK1102E
SLLS958 – MARCH 2009 ...................................................................................................................................................................................................
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The TLK1102E uses a two-wire serial interface for digital control. The two circuit inputs, SDA and SCL, aredriven respectively by the serial data and serial clock from a microcontroller, for example. Both inputs require10k Ωpull-up resistors to VCC when used. For driving these inputs, an open-drain output is recommended.
The two-wire interface allows write access to the internal memory map to modify control registers and readaccess to read out control and status signals. The TLK1102E is a slave device only which means that it cannotinitiate a transmission itself; it always relies on the availability of the clock (SCL) signal for the duration of thetransmission. The master device provides the clock signal as well as the START and STOP commands. Theprotocol for a data transmission is as follows:1. START command2. 7-bit slave address (0101A
2
A
1
A
0
) followed by an eighth bit which is the data direction bit (R/W). A zeroindicates a WRITE and a 1 indicates a READ. The default slave address is 0101100. The A
2
, A
1
, and A
0address bits change with the status of the ADD2, ADD1, and ADD0 device pins, respectively. Those pins areinternally pulled up. Pulling down the ADD[2:0] pins changes the address to 0101011. Table 2 summarizesthe slave address settings:3. 8-bit register address4. 8-bit register data word5. STOP command
Table 2. Slave Address Settings
ADD2 ADDR1 ADDR0 SLAVE ADDRESS
0 0 0 01010110 0 1 01010100 1 0 01010010 1 1 01010001 0 0 01011111 0 1 01011101 1 0 01011011 1 1 0101100
Regarding timing, the TLK1102E is I
2
C-compatible. The typical timing is shown in Figure 3 and a complete datatransfer is shown in Figure 4 . Parameters for Figure 3 are defined in Table 3 .
Bus Idle: Both SDA and SCL lines remain HIGH
Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH,defines a START condition (S). Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGHdefines a STOP condition (P). Each data transfer is terminated with a STOP condition; however, if the master stillwishes to communicate on the bus, it can generate a repeated START condition and address another slavewithout first generating a STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited andis determined by the master device. The receiver acknowledges the transfer of data.
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Product Folder Link(s): TLK1102E
tBUF
tHDSTA
tr
tLOW
tHDDAT
tHIGH tf
tSUDAT tSUSTA
tHDSTA
tSUSTO
P S S P
SDA
SCL
S
SDA
SCL
P
1-7
SLAVE
ADDRESS
R/W ACK
8 9 8 9
REGISTER
ADDRESS
ACK
8 9
ACK
REGISTER
FUNCTION
1-7 1-7
TLK1102E
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................................................................................................................................................................................................... SLLS958 – MARCH 2009
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. Thetransmitter releases the SDA line and a device that acknowledges must pull down the SDA line during theacknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of theacknowledge clock pulse. Setup and hold times must be taken into account. When a slave-receiver does notacknowledge the slave address, the data line must be left HIGH by the slave. The master can then generate aSTOP condition to abort the transfer. If the slave-receiver does acknowledge the slave address but some timelater in the transfer cannot receive any more data bytes, the master must abort the transfer. This is indicated bythe slave generating the not acknowledge on the first byte to follow. The slave leaves the data line HIGH and themaster generates the STOP condition.
Figure 3. Two-Wire Serial Interface Timing Diagram.
Table 3. Two-Wire Serial Interface Timing Diagram Definitions
SYMBOL PARAMETER MIN MAX UNIT
f
SCL
SCL Clock frequency 400 kHzt
BUF
Bus free time between START and STOP conditions 1.3 µst
HDSTA
Hold time after repeated START condition. After this period, the first clock pulse is generated 0.6 µst
LOW
Low period of the SCL clock 1.3 µst
HIGH
High period of the SCL clock 0.6 µst
SUSTA
Setup time for a repeated START condition 0.6 µst
HDDAT
Data HOLD time 0 µst
SUDAT
Data setup time 100 nst
R
Rise time of both SDA and SCL signals 300 nst
F
Fall time of both SDA and SCL signals 300 nst
SUSTO
Setup time for STOP condition 0.6 µs
Figure 4. Two-Wire Serial Interface Data Transfer
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REGISTER MAPPING
TLK1102E
SLLS958 – MARCH 2009 ...................................................................................................................................................................................................
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The register mapping for read/write register addresses 0 (0x00) through 15 (0x0F) are shown in Table 4 toTable 19 .Table 20 describes the circuit functionality based on the register settings.
Table 4. Register 0x00 - General Device Settings
REGISTER ADDRESS 0x00
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
RESET PWRDOWN Reserved Reserved Reserved Reserved LOSRNG CHA_TRACK
Table 5. Register 0x01 – Reserved
REGISTER ADDRESS 0x01
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Table 6. Register 0x02 – Control A Control Settings
REGISTER ADDRESS 0x02
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
INOFF OUTOFF LOSOFF OCOFF Reserved SQUELCH POL DISABLE
Table 7. Register 0x03 – Control A Input Settings
REGISTER ADDRESS 0x03
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
BW3 BW2 BW1 BW0 EQ3 EQ2 EQ1 EQ0
Table 8. Register 0x04 – Channel A Output Settings
REGISTER ADDRESS 0x04
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DEEM3 DEEM2 DEEM1 DEEM0 AMP3 AMP2 AMP1 AMP0
Table 9. Register 0x05 – Channel A LOS Settings
REGISTER ADDRESS 0x05
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FAST LOSLVL6 LOSLVL5 LOSLVL4 LOSLVL3 LOSLVL2 LOSLVL1 LOSLVL0
Table 10. Register 0x06 – Channel B Control Settings
REGISTER ADDRESS 0x06
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
INOFF OUTOFF LOSOFF OCOFF Reserved SQUELCH POL DISABLE
Table 11. Register 0x07 – Channel B Input Settings
REGISTER ADDRESS 0x07
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
BW3 BW2 BW1 BW0 EQ3 EQ2 EQ1 EQ0
Table 12. Register 0x08 – Channel B Output Settings
REGISTER ADDRESS 0x08
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
DEEM3 DEEM2 DEEM1 DEEM0 AMP3 AMP2 AMP1 AMP0
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................................................................................................................................................................................................... SLLS958 – MARCH 2009
Table 13. Register 0x09 – Channel B LOS Settings
REGISTER ADDRESS 0x09
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FAST LOSLVL6 LOSLVL5 LOSLVL4 LOSLVL3 LOSLVL2 LOSLVL1 LOSLVL0
Table 14. Register 0x0A – Reserved
REGISTER ADDRESS 0x0A
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Table 15. Register 0x0B – Reserved
REGISTER ADDRESS 0x0B
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Table 16. Register 0x0C – Reserved
REGISTER ADDRESS 0x0C
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Table 17. Register 0x0D – Reserved
REGISTER ADDRESS 0x0D
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Table 18. Register 0x0E – Device Status
REGISTER ADDRESS 0x0E
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Reserved Reserved Reserved Reserved Reserved Reserved LOS_CHB LOS_CHA
Table 19. Register 0x0F – Reserved
REGISTER ADDRESS 0x0F
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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Table 20. Register Functionality
REGISTER BIT(s) NAME DESCRIPTION FUNCTION DEFAULT
0 7 RESET Software Reset Resets all registers 000000006 PWRDOWN Powerdown Set high to power down the device. In powerdownmode the the current consumption about 2.5mA5 - 2 Reserved
1 LOSRNG LOS Range Select Set to high to increase LOS detection sensitivity0 CHA_TRACK Channel A Tracking All settings from channel A will be used for bothMode channels, A and B1 7 Reserved 000000006 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 Reserved2 7 INOFF Channel A Input Off Set high to power down channel A input stages 000000006 OUTOFF Channel A Output Off Set high to power down channel A output driver andbuffer5 LOSOFF Channel A LOS Set high to power down channel A input signalDetector Off detector4 OCOFF Channel A Offset Disables channel A offset cancellation circuitCancellation Off3 Reserved
2 SQUELCH Channel A Squelch High activates channel A internal output squelchMode function1 POL Channel A Polarity Set to high to change polarity of channel A outputSwitch signal0 DISABLE Channel A Output Set to high to disable channel A output data andDisable keep common mode level3 7 BW3 Channel A Bandwidth 0000 - > highest bandwidth 00000000Select 3 (MSB) 1111 - > lowest bandwidth6 BW2 Channel A BandwidthSelect 25 BW1 Channel A BandwidthSelect 14 BW0 Channel A BandwidthSelect 0 (LSB)3 EQ3 Channel A EQ Filter Set to high to switch off channel A EQ filter 3Stage 3 Control (MSB)2 EQ2 Channel A EQ Filter Set to high to switch off channel A EQ filter 2Stage 2 Control1 EQ1 Channel A EQ Filter Set to high to switch off channel A EQ filter 1Stage 1 Control0 EQ0 Channel A EQ Filter Set to high to switch off channel A EQ filter 0Stage 0 Control (LSB)
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................................................................................................................................................................................................... SLLS958 – MARCH 2009
Table 20. Register Functionality (continued)
REGISTER BIT(s) NAME DESCRIPTION FUNCTION DEFAULT
4 7 DEEM3 Channel A Output 0000 - > no peaking 00000000De-emphasis 3 (MSB) 1111 - > highest peaking6 DEEM2 Channel A OutputDe-emphasis 25 DEEM1 Channel A OutputDe-emphasis 14 DEEM0 Channel A OutputDe-emphasis 0 (LSB)3 AMP3 Channel A Output 0000 - > 225mV
p-pAmplitude 3 (MSB) 1111- > 1200mV
p-papproximately 60mV
p-p
per step2 AMP2 Channel A OutputAmplitude1 AMP1 Channel A OutputAmplitude 10 AMP0 Channel A OutputAmplitude 0 (LSB)5 7 FAST Channel A Fast Signal Set to high to select fast signal detection mode on 00000000Detection Mode channel A6 LOSLVL6 Channel A LOS 0000000 - > Minimum LOS assert levelThreshold Level 6 1001100 - > Maximum LOS assert level(MSB) Settings out of the above range are not supported5 LOSLVL5 Channel A LOSThreshold Level 54 LOSLVL4 Channel A LOSThreshold Level 43 LOSLVL3 Channel A LOSThreshold Level 32 LOSLVL2 Channel A LOSThreshold Level 21 LOSLVL1 Channel A LOSThreshold Level 10 LOSLVL0 Channel A LOSThreshold Level 0(LSB)6 7 INOFF Channel B Input Off Set high to power down channel B input stages 000000006 OUTOFF Channel B Output Off Set high to power down channel B output driver andbuffer5 LOSOFF Channel B LOS Set high to power down channel B input signalDetector Off detector4 OCOFF Channel B Offset Disables channel B offset cancellation circuitCancellation Off3 Reserved
2 SQUELCH Channel B Squelch High activates channel B internal output squelchMode function1 POL Channel B Polarity Set to high to change polarity of channel B outputSwitch signal0 DISABLE Channel B Output Set to high to disable channel B output data andDisable keep common mode level
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Table 20. Register Functionality (continued)
REGISTER BIT(s) NAME DESCRIPTION FUNCTION DEFAULT
7 7 BW3 Channel B Bandwidth 0000 - > highest bandwidth 00000000Select 3 (MSB) 1111 - > lowest bandwidth6 BW2 Channel B BandwidthSelect 25 BW1 Channel B BandwidthSelect 14 BW0 Channel B BandwidthSelect 0 (LSB)3 EQ3 Channel B EQ Filter Set to high to switch off channel B EQ filter 3Stage 3 Control (MSB)2 EQ2 Channel B EQ Filter Set to high to switch off channel B EQ filter 2Stage 2 Control1 EQ1 Channel B EQ Filter Set to high to switch off channel B EQ filter 1Stage 1 Control0 EQ0 Channel B EQ Filter Set to high to switch off channel B EQ filter 0Stage 0 Control (LSB)8 7 DEEM3 Channel B Output 0000 - > no peaking 00000000De-emphasis 3 (MSB) 1111 - > highest peaking6 DEEM2 Channel B OutputDe-emphasis 25 DEEM1 Channel B OutputDe-emphasis 14 DEEM0 Channel B OutputDe-emphasis 0 (LSB)3 AMP3 Channel B Output 0000 - > 225mV
p-pAmplitude 3 (MSB) 1111- > 1200mV
p-papproximately 60mV
p-p
per step2 AMP2 Channel B OutputAmplitude1 AMP1 Channel B OutputAmplitude 10 AMP0 Channel B OutputAmplitude 0 (LSB)9 7 FAST Channel B Fast Signal Set to high to select fast signal detection mode on 00000000Detection Mode channel B6 LOSLVL6 Channel B LOS 0000000 = Minimum LOS assert levelThreshold Level 6 1001100 = Maximum LOS assert level(MSB) Settings outside the above range are not supported5 LOSLVL5 Channel B LOSThreshold Level 54 LOSLVL4 Channel B LOSThreshold Level 43 LOSLVL3 Channel B LOSThreshold Level 32 LOSLVL2 Channel B LOSThreshold Level 21 LOSLVL1 Channel B LOSThreshold Level 10 LOSLVL0 Channel B LOSThreshold Level 0(LSB)
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................................................................................................................................................................................................... SLLS958 – MARCH 2009
Table 20. Register Functionality (continued)
REGISTER BIT(s) NAME DESCRIPTION FUNCTION DEFAULT
10 7 Reserved 000000006 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 Reserved11 7 Reserved 000000006 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 Reserved12 7 Reserved 000000006 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 Reserved13 7 Reserved 000000006 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 Reserved14 7 Reserved 000000006 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 LOS_CHB LOS Channel B Indicates LOS at input channel B0 LOS_CHA LOS Channel A Indicates LOS at input channel A
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Table 20. Register Functionality (continued)
REGISTER BIT(s) NAME DESCRIPTION FUNCTION DEFAULT
15 7 Reserved 000000006 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 Reserved
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TYPICAL CHARACTERISTICS
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 1 23456789 10 11 12 13 14 15 16 17 18 19 20
f-Frequency-GHz
InsertionLoss-15m24AWGCable
InsertionLoss-10m28AWGCable
InsertionLoss-40inPCBLink
ReturnLoss-15m24AWGCable
ReturnLoss-10m28AWGCable
ReturnLoss-40inPCBLink
DifferentialS-parameterMagnitude-dB
TLK1102E
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................................................................................................................................................................................................... SLLS958 – MARCH 2009
Typical operating condition is at V
CC
= 3.3V and T
A
= 25 ° C, V
IN
= 400mV
p-p
(signal generator output), outputswing = 600mV
p-p
setting, no interconnect line at the output, and with default device settings (unless otherwisenoted). Optimum input equalization level and output de-emphasis settings were used for the cable and backplanemeasurements. Differential S-parameter characteristics of Spectra-Strip
®
SKEWCLEAR
®
EXD twinaxial cablesand a 40-inch N4000-13 SI™ backplane link with Amphenol XCede
®
backplane connectors used for themeasurements captured in this document are as shown in Figure 5 .
Figure 5. Typical Differential S-Parameter Characteristics of Twinaxial Cable and PCB Interconnect Lines
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 19
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DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT 12Gbps
InputVoltage
50mV/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
OutputVoltage
200mV/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
t – Time – 500ps/divt – Time – 40ps/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
t – Time – 500ps/divt – Time – 40ps/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
t – Time – 40ps/div t – Time – 500ps/div
InputInterconnect:15meters24AWGTwinaxialCable InputInterconnect:15meters24AWGTwinaxialCable
InputInterconnect:10meters28AWGTwinaxialCable InputInterconnect:10meters28AWGTwinaxialCable
InputInterconnect:40inchesBackplaneLink InputInterconnect:40inchesBackplaneLink
TLK1102E
SLLS958 – MARCH 2009 ...................................................................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
USING A K28.5 PATTERN
Figure 6. Equalizer Input and Output Signals with Different Interconnect Lines at 12Gbps
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DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT
InputVoltage
50mV/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
OutputVoltage
200mV/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
t – Time – 500ps/divt – Time – 40ps/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
t – Time – 500ps/divt – Time – 40ps/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
t – Time – 40ps/div t – Time – 500ps/div
InputInterconnect:15meters24AWGTwinaxialCable InputInterconnect:15meters24AWGTwinaxialCable
InputInterconnect:10meters28AWGTwinaxialCable InputInterconnect:10meters28AWGTwinaxialCable
InputInterconnect:40inchesBackplaneLink InputInterconnect:40inchesBackplaneLink
TLK1102E
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................................................................................................................................................................................................... SLLS958 – MARCH 2009
TYPICAL CHARACTERISTICS (continued)
11.3Gbps USING A K28.5 PATTERN
Figure 7. Equalizer Input and Output Signals with Different Interconnect Lines at 11.3Gbps
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 21
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DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT
InputVoltage
50mV/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
OutputVoltage
200mV/div
t – Time – 40ps/div
t – Time – 40ps/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
t – Time – 40ps/div
InputInterconnect:15meters24AWGTwinaxialCable
InputInterconnect:10meters28AWGTwinaxialCable
InputInterconnect:40inchesBackplaneLink
TLK1102E
SLLS958 – MARCH 2009 ...................................................................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
10.3125Gbps USING A PRBS 2
31
-1 PATTERN
Figure 8. Equalizer Input and Output Signals with Different Interconnect Lines at 10.3125Gbps.
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DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT
InputVoltage
50mV/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
OutputVoltage
200mV/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
t – Time – 500ps/divt – Time – 40ps/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
t – Time – 500ps/divt – Time – 40ps/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
InputVoltage
50mV/div
OutputVoltage
200mV/div
t – Time – 40ps/div t – Time – 500ps/div
InputInterconnect:15meters24AWGTwinaxialCable InputInterconnect:15meters24AWGTwinaxialCable
InputInterconnect:10meters28AWGTwinaxialCable InputInterconnect:10meters28AWGTwinaxialCable
InputInterconnect:40inchesBackplaneLink InputInterconnect:40inchesBackplaneLink
TLK1102E
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................................................................................................................................................................................................... SLLS958 – MARCH 2009
TYPICAL CHARACTERISTICS (continued)
8.5Gbps USING A K28.5 PATTERN
Figure 9. Equalizer Input and Output Signals with Different Interconnect Lines at 8.5Gbps.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 23
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VIN − Input Voltage − mVpp
0
2
4
6
8
10
12
14
16
18
0 300 600 900 1200 1500 1800
DJ − Residual Deterministic Jitter − ps
G002
15m 24AWG Twinaxial Cable
No Interconnect
40-Inch Backplane Link 10m 28AWG Twinaxial Cable
f − Frequency − GHz
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
0 2 4 6 8 10 12 14 16
Differential S11 − dB
G003
f − Frequency − GHz
−55
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
0 2 4 6 8 10 12 14 16
Differential S22 − dB
G004
VTH − LOS Threshold Voltage − mVpp G005
LOSL Pin Voltage − V
0
10
20
30
40
50
60
70
80
0 50 100 150 200 250 300
Register 5/9 Setting − dec
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Deassert (Pin Mode)
Assert (Pin Mode)
Deassert (2-Wire
Serial I/F Mode)
Assert (2-Wire
Serial I/F Mode)
LOS Hysteresis − dB
0
10
20
30
40
50
60
70
80
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1
Register 5/9 Setting − dec
G006
LOSL Pin Voltage − V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Pin Mode
2-Wire Serial I/F Mode
TLK1102E
SLLS958 – MARCH 2009 ...................................................................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)
RANDOM JITTER RESIDUAL DETERMINISTIC JITTERvs vsINPUT VOLTAGE (11.3Gbps, K28.5 Pattern, OC = OFF) INPUT VOLTAGE (11.3Gbps, K28.5 Pattern, OC = OFF)
Figure 10. Figure 11.
DIFFERENTIAL INPUT RETURN LOSS DIFFERENTIAL OUTPUT RETURN LOSSvs vsFREQUENCY FREQUENCY
Figure 12. Figure 13.
REGISTER 5/9 SETTING/LOSL PIN VOLTAGE REGISTER 5/9 SETTING/LOSL PIN VOLTAGEvs vsLOS THRESHOLD VOLTAGE LOS HYSTERESIS
Figure 14. Figure 15.
24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TLK1102E
Data Rate − GHz
0
20
40
60
80
100
120
140
160
180
0 2 4 6 8 10 12 14
VTH − LOS Threshold Voltage − mVpp
G008
LOS Hysteresis − dB
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
Hysteresis
Deassert
Assert
Data Rate − GHz
0
50
100
150
200
250
300
0 2 4 6 8 10 12 14
VTH − LOS Threshold Voltage − mVpp
G007
LOS Hysteresis − dB
2.5
3.5
4.5
5.5
6.5
7.5
8.5
Hysteresis
Deassert
Assert
TLK1102E
www.ti.com
................................................................................................................................................................................................... SLLS958 – MARCH 2009
TYPICAL CHARACTERISTICS (continued)
LOS THRESHOLD VOLTAGE/LOS HYSTERESIS LOS THRESHOLD VOLTAGE/LOS HYSTERESISvs vsDATA RATE (V(LOSL)=700mV) DATA RATE (V(LOSL)=OPEN)
Figure 16. Figure 17.
Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TLK1102E
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLK1102ERGER ACTIVE VQFN RGE 24 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLK1102ERGET ACTIVE VQFN RGE 24 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 2-Jun-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLK1102ERGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TLK1102ERGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLK1102ERGER VQFN RGE 24 3000 367.0 367.0 35.0
TLK1102ERGET VQFN RGE 24 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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