HFA3524IA - Intersil Corporation - Datasheet.Directory

File Number 4062.9

HFA3524

2.5GHz/600MHz Dual Frequency

Synthesizer

The Intersil 2.4GHz PRISM® chip set

is a hi ghly integrat ed six-ch ip s olution

f or RF m o dem s empl o ying D ir e ct

Sequence Spread Spectrum (DSSS)

signaling. The HFA3524 600MHz Dual Frequenc y

Synthesi zer is one of the si x chips in the PRISM chip set

(see the Typical Application Di agram).

The HFA3524 is a monolithic, in tegrated dual frequency

synthesizer, including prescaler , is to be used as a local

oscillator for RF and first IF of a dual conversi on tr ansceiver.

The HFA352 4 cont ains a dual m odul us prescaler. A 32/33 or

64/65 p resc aler can be se lected fo r t he RF synthesizer an d a

8/9 or a 16/1 7 pres caler can b e selected for the IF

synthesizer. Using a digital phase locked loop technique, the

HFA3524 can generate a very stable, low noise signal for the

RF and IF local oscillator. Serial data is transferred into the

HFA3524 via a three wire interface (Data, Enable, Clock).

Supply voltage can range from 2.7V to 5.5V. The HFA3524

features v ery low cur rent consumpt ion o f 13mA at 3V .

Features

• 2.7V to 5.5V Operation

• Low Current Consumptio n

• Selectable Powerdown Mode ICC = 1µA Typical at 3V

• Dual Modulus Prescaler, 32/33 or 64/65

• Selectable Charge Pump High Z State Mode

Applications

• Systems Targeting IEEE 802. 11 Standard

• PCMCIA Wireless Transceive r

• Wireless Loca l Area Network Modem s

• TDMA Packet Protocol Radios

• Part 15 Compliant Radio L inks

• Portabl e Battery Powered Equipment

Funct ional Block Diag ram

Ordering Information

PART

NUMBER TEMP.

RANGE (oC) PACKAGE PKG. NO.

HFA3524IA -40 to 85 20 Ld TSSOP M20.173

HFA3524IA96 -40 to 85 Tape and Reel

PRESCALER 15-BIT IF

N COUNTER

15-BIT IF

R COUNTER

15-BIT RF

R COUNTER

18-BIT RF

N COUNTER

OSC

PRESCALER

CHARGE

PUMP

fOUT

FASTLOCK

LOCK

DETECT

fIN IF

OSCIN

fIN RF

CLOCK

DATA

PHASE

COMP DO IF

PHASE

COMP

DO RF

FO/LD

CHARGE

PUMP

22-BIT DATA

MUX

Data Sheet January 2001

tle

()

tho

()

C-

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1- 888-INTERSIL o r 321-724-7143 |Intersi l (and design) is a regi stered trademark of In tersil Americas Inc.

PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.

NOT RECOMMENDED FOR NEW DESIGNS

REFER TO PRISM II, 11Mbps (FN4904)

or contact our Technical Support Center at

1-888-INTERSIL or www.intersil.com/tsc

Typical Application Diagram

For additional information on the PRISM chip set, see us on

the web http://www.intersil.com/ prism . The four-digit file numbers are shown in Typical Application

Diagram, and correspond to the approp ri ate circuit.

QUAD IF MODULATOR

RFPA

HFA3925

HFA3724

DSSS BASEBAND PROCESSOR

DATA TO MACCTRL

HSP3824

TUNE/SELECT

HFA3524

0o/90o

VCO

A/D

MAC-PHY

INTERFACE

802.11

VCO

HFA3624

UP/DOWN

CONVERTER A/D

(FILE# 4067) (FILE# 4064)

( FIL E # 40 62)

(FILE# 40 66)

(FIL E# 4132)

PRISM CHIP SET FILE #4063

DPSK

DEMOD

DPSK

MOD.

DE-

SPREAD

HFA3424 (NOTE)

(FILE# 4131)

NOTE: Requi red for systems targeting 802.11 sp ecifications.

TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HFA352

CCA

RXI

RXQ

RSSI

TXI

TXQ

³÷ 2

DUAL SYNTHESIZER

HFA3524

Pinout

HFA3524 (TSSOP)

TOP VIEW

Pin Descr iption s

NUMBER PIN NAME I/O DESCRIPTION

CC1 - Power supply voltage input. Input may range from 2.7V to 5.5V. VCC1 mu st equa l VCC2. Bypass

capacitors should be placed as close as possible to this pin and be connected directly to the ground

plane.

P1 - Power Supply for RF charge pump. Must be > VCC.

O RF O Internal charge pump output. For connection to a loop filter for driving the input of an external VCO.

4 GND - Ground.

IN RF I RF prescaler input. Smal l signal in put from the VCO.

IN RF l RF pres ca le r comp li me ntar y input . A bypa ss cap aci tor sh ould be pl a ced as clo se a s po ssi bl e to t his

pin and be connected directly to the ground plane. Capacitor is optional with some loss of sensitivity.

7 GND - Ground.

8OSC

IN I Osc il la to r in put. Th e in pu t h as a VCC/2 input threshold and can be driven from an external CMOS

or TTL logic gate.

9 GND - Ground.

10 FO/LD O Multiplexed output of the RF/lF programmable or reference dividers, RF/lF lock detect signals and

Fastlock mode. CMOS output (see P rogrammable Modes).

11 Clock I High impedance CMOS Clock input. Data for the various counters is clocked in on the rising edge,

into the 22-bit shift register.

12 Data l Binary serial data input. Data entered MSB first. The last two bits are the control bits. High

im pedance CMOS input .

13 LE l L oad enabl e CMOS input. When LE goes HIGH, data stored in the shift registers is loaded into one

of the 4 appropriate latches (control bit dependent).

14 GND - Ground.

15 fIN IF I IF prescaler complimentary input. A bypass capacitor should be placed as close as possible to

this pin and be connected directly to the ground plane. Capacitor is optional with some loss of

sensitivity.

16 fIN IF I IF prescaler input. Small signal input from the VCO.

17 GND - Ground.

18 DO IF O IF charge pump output. For connection to a loop filter for driving the input of an external VCO.

19 VP2 - Pow er Sup pl y for IF charg e pum p. Must be >VCC.

20 VCC2 - Power supply voltage input Input may range from 2.7V to 5.5V. VCC2 must equal VCC1. Bypass

capacitors should be placed as close as possible to this pin and be connected directly to the ground

plane.

VCC1

VP1

DO RF

GND

fIN RF

OSCIN

GND

FO/LD

VCC2

DO IF

GND

fIN IF

VP2

fIN IF

GND

DATA

CLOCK

HFA3524

Block Diagram

LOCK DETECT/

FASTLOCK

MULTIPLEXER

fOUT/

LOCK

DETECT

RF CHARGE PUMP

1X 4X

VCC1 1

VP1 2

GND 4

DO RF

RF PRESCALER

32/33 OR 64/65

CONTROL

SWALLOW

FR 1

FP 1

PHASE

DETECTOR

fIN RF 5

GND 7

fIN RF

(RF) 18-BIT N-LATCH

LATCH

1-BIT P1

PWDN

1-BIT RF

15-BIT R1 LATCH5-BIT MODE LATCH

LOCK

DETECT

IF IF CHARGE PUMP

4X1X VCC2

VP2

GND

DO IF

15-BIT (IF)

N-COUNTER

PROGRAMMABLE

IF PRESCALER

8/9 OR 16/17

CONTROL

SWALLOW

FR 2

FP 2 PHASE

DETECTOR

-fIN IF

GND

fIN IF

(IF) 15-BIT N-LATCH LATCH

1-BIT P2 PWDN

1-BIT IF

PROGRAMMABLE 15-BIT

(R2) REFERENCE COUNTER

OSCIN 8

GND 9

15-BIT R2 LATCH5-BIT MODE LATCH

FOLD

DECODE

LATCH

20-BIT SHIFT REGISTER

18-BIT (RF)

N-COUNTER

PROGRAMMABLE

PROGRAMMABLE 15-BIT

(R1) REFERENCE COUNTER

CONTROL

2-BIT

LATCH

13 LE

12 DATA

11 CLOCK

NOTES:

1. VCC1 supplies power to the RF prescaler, N-counter and phase detector. VCC2 supplies power to the IF prescaler, N-counter and phase detector,

RF and IF R-co unters along with the OSCIN buffer and all digita l circuitry. VCC1 and VCC2 are separated by a diode and must be run at the

s ame volt age level.

2. VP1 and VP2 can be run independently as long as VP ≥ VCC.

HFA3524

Absolute Maximum Ratings Thermal Information

Power Supply Voltage

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

VP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

Voltage on Any Pin with GN D = 0 V (VI). . . . . . . . . . . -0.3V to +6.5V

Ope rat i ng Condi tio ns

Power Supply Voltage

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

VP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC to +5.5V

Te mp eratu r e (T A). . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Maximum Storage Temperature Range (TS). . . . . . -55oC to 15 0oC

Maximum Lead Temperature (Soldering 4s) (TL) . . . . . . . . . .260oC

(TSSOP - Lead Tips Only)

CAUTIO N: S tresses abov e those l isted i n “ A bsolute Max imum Ra ting s” ma y cause per manen t dam age to th e de vice. This is a s tress on l y rating and ope ration of th e

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is me asured with the componen t mounted on an evaluation PC board in free air.

Electrical Speci fications VCC = 3.0V, VP = 3.0V, -40oC < TA < 85oC, Unless Otherwise Specified

PARAMETE R SYMBOL TEST CONDITIONS

HFA3524

UNITSMIN TYP MAX

Power Supply Current ICC

RF + IF VCC = 2.7V to 5.5V - 13 - m A

RF Only VCC = 2.7V to 5.5V - 10 - m A

Powe rdown Current ICC-PWDN VCC = 3.0V - 1 25 µA

Operating Frequency fIN RF 0.5 - 2.5 GHz

Operating Frequency fIN IF 45 - 600 MHz

Oscillator Frequency fOSC 5-44MHz

Maximum Phase Detector

Frequency fφ10 - - MHz

RF Input Sensitivity PfIN RF VCC = 3.0V -15 - +4 dBm

VCC = 5.0V -10 - +4 dBm

IF Input Sensitivity PfIN IF VCC = 2.7V to 5.5V -10 - +4 dBm

Oscillator Sensitivity VOSC OSCIN 0.5 - - VP-P

High Level Input Voltage VIH (Note) 0.8VCC -- V

Low Level Input Voltage VIL (Note) - - 0.2VCC V

High Level Input Current IIH VIH = VCC = 5.5V (Note) -1.0 - 1.0 µA

Low Level Input Current IIL VIL = 0V, VCC = 5.5V (Note) -1.0 - 1.0 µA

Oscilla tor Input Cur rent IIH VIH = VCC = 5.5V - - 100 µA

Oscilla tor Input Cur rent IIL VIL = 0V, VCC = 5.5V -100 - - µA

High Le vel Output Voltage VOH IOH = -500µAV

CC -0.4 - - V

High Le vel Output Voltage VOH IOH = -1mA --- V

Low Le vel Ou tp ut Volt a ge VOL IOL = 500µA--0.4V

Low Le vel Ou tp ut Volt a ge VOL IOL = 1mA --- V

Data to Clock Set Up Time tCS See Data Input Timing 50 - - ns

Data to Clock Hold Time tCH See Data Input Timing 10 - - ns

Clock Pulse Width High t CWH See Data Input Timing 50 - - ns

Clock Pulse Width Low tCWL See Data Input Timing 50 - - ns

Clock to Load Enable Set Up Time tES See Data Input Timing 50 - - ns

Load Enable Pulse Width tEW See Data Input Timing 50 - - ns

NO TE: Cl oc k , Da ta an d LE do es not inc lud e fIN RF, fIN IF and O SCIN.

HFA3524

Charge Pump Spec ifications VCC = 3.0 V, VP = 3.0V, -40oC < TA < 85oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS

HFA3524

UNITSMIN TYP MAX

Charge Pump Output Curren t IDO-SOURCE VDO = VP/2, ICPO = HIGH (Note 4) - -5.0 - mA

IDO-SINK VDO = VP/2, ICPO = HIGH (Note 4) - 5.0 - mA

IDO-SOURCE VDO = VP/2, ICPO = LOW (Note 4) - -1.25 - mA

IDO-SINK VDO = VP/2, ICPO = LOW (Note 4) - 1.25 - mA

Charge Pump High Z State Current IDO - HIGH Z 0.5V ≤ VDO ≤ VP - 0. 5, - 40 oC < T < 85oC-2.5 - 2.5 nA

CP Sink vs Sour ce Mismatch (Note 5) IDO-SINK vs IDO-

SOURCE VDO = VP/2, TA = 25oC-310%

CP Current vs Voltage (Note 6) IDO vs VDO 0.5V ≤ VDO ≤ VP - 0.5, T < 25oC - 10 15 %

CP Current vs Temperature (Note 7) IDO vs T VDO = VP/2, -40oC < T < 85oC-10-%

NOTES:

4. S e e Pr o gr a mm a ble Mo de s f or ICPO description.

5. IDO vs VDO = Charge Pump Output Current magnitude variation vs Voltage =

[1/2 •{ |I1| - |I3|}]/[1/2 • {|I1| + |I3|}] • 100% and [1/2 • |I4| - |I6|]/[1/ 2 • {|I4| + |I6|}] • 100% .

6. IDO-SINK vs IDO-SOURCE = Charge Pump Output Current Sink vs Source Mismatch = [|I2| - |I5|]/[1/2 • {|I2| + |I5|}] • 100%.

7. IDO vs TA = Charge Pump Output Current magnitude variation vs Temperature =

[|I2 at temp| - |I2 at 25oC|]/|I2 at 25oC| • 100% and [|I5 at temp| - |I5 at 25 oC|]/|I5 at 25oC| • 100%.

I1 = CP sink curre nt at VDO = VP - ∆V

I2 = CP sink curre nt at VDO = VP/2

I3 = CP sink curre nt at VDO = ∆V

I4 = CP source current at VDO = VP - ∆V

I5 = CP source current at VDO = VP/2

I6 = CP source current at VDO = ∆VFIGURE 1. CHARGE PUMP CURRENT SPECIFICATION DEFINI TIONS

CURRENT (mA)

VOLTAGE

OFFSET ∆V

∆V

VP/2 VP-∆VV

∆VDO VOLTAGE

100pF

2.2µF

39K

CLOCK

DATA

FOLD

PC PARALLEL

PORT

HP5385A

FREQUENCY

COUNTER

2.7V 5.0V

100pF 2.2µF

fIN

VCC

OSCIN

0Ω

0.01µF

100pF

13dB

ATTN

SMHU 835.8011.52

SIGNAL GENERATOR

10MHz EXT REF OUT

RF 50Ω

12K

FIGURE 2. RF SENSI TIVITY TEST BLOCK DIAGRAM

HFA3524

Typica l HFA3524 Performance Curves

FIGURE 3. ICC vs VCC FIGURE 4. IDO HIGH Z STATE vs DO VOLTAGE

FIGURE 5. CHARGE PUMP CURRENT vs DO VOLTAGE

ICP = HIGH FIGURE 6. CHARGE PUMP CURRENT vs DO VOLTAGE

ICP = LOW

NOTE: See charge pump current specification definitions.

FIGURE 7. CHARGE PUMP CURRENT VARIATION FIGURE 8. SINK vs SOURCE MISMATCH vs DO VOLTAGE

ICC (mA)

VCC (V)

2.5 3.0 3.5 4.0 4.5 5.0 5.5

11 T = 40 oC

T = 85 oC

T = 25 oC

IDO HIGH Z STATE (pA)

DO VOLTAGE (V)

1500

0123456

1250

1000

750

500

250

-250

-500

T = 90oC

T = 70oC

T = 25 oC

DO VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

-2

-4

-6

DO CURRENT (mA)

VP = 5.5V

VP = 2.7V

VP = 5.5VVP = 2.7V

DO VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.5

2.0

1.5

1.0

0.5

-0.5

-1.0

-2.0

DO CURRENT (mA)

-1.5

5.0

VP = 5.5V

VP = 2.7V

VP = 5.5VVP = 2.7V

VP = 3.0V

SINK

SOURCE

VP = 5.0V

VOLTAGE OFFSET (V)

0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5

VARIATION (%)

VP = 5.0V

DO VOLTAGE (V)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

-25

MISMATCH (%)

-5

-10

-15

-20

VP = 3.0V

HFA3524

Marker 1 = 1G Hz, Real = 101, Im aginary = -144

Marker 2 = 2GHz, Real = 37, Imaginary = -54

Marker 3 = 3GHz, Real = 22, Imaginary = -2

Marker 4 = 500MHz , Re al = 209, Imaginar y = -232

FIGURE 9. RF INPUT IMPEDANCE

Marker 1 = 100MHz, Real = 58 9, Imag inary = -209

Marker 2 = 200MHz, Real = 44 0, Imag inary = -286

Marker 3 = 300MHz, Real = 32 6, Imag inary = -287

Marker 4 = 500MHz, Real = 20 2, Imag inary = -234

FIGURE 10. IF INPUT IMPEDANCE

FIGURE 11. RF SEN SIT IVI TY vs FREQU E NC Y FIGURE 12. IF INPUT SENSI TIV ITY vs FREQ UENC Y

FIGURE 13. OSCILLATOR INPUT SENSITIVITY vs FREQUENCY

Typica l HFA3524 Performance Curves (Continue d)

VCC = 2.7V TO 5.5V,

fIN = 0. 5GHz TO 3GHz

VCC = 2.7V TO 5.5V,

fIN = 10MHz TO 1000MHz

FREQUENCY (MHz)

1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000

-10

-15

-20

-25

-30

-35

SENSITIVITY (dBm)

-40

-45

VCC = 5.5V

VCC = 2.7V

SENSITIVITY (dBm)

FREQUENCY (MHz)

-10

0 100 200 300 400 500 600

-15

-20

-25

-30

-35

-40

-45

-50

VCC = 5.5V

VCC = 2.7V

FREQUENCY (MHz)

0 1020304050

-10

-20

-40

SENSIT IVITY (dBm)

-30

VCC = 5.5V

-60

VCC = 2.7V

-50

0.200

0.063

0.020

0.006

0.002

SENSITIVITY (VPP)

HFA3524

Functional Description

The simplified block diagram in Figur e 14 shows the 22-bit

data regist er, two 1 5-bit R Coun ter s and t he 1 5-bit and 18- bit

N Counters (inte rmediate latches are not shown). The data

stream is clocked (on the ri sing edge of Clock) into the

DATA input , MSB fir st. The last two bits are the Contr ol Bus.

The DATA is transferred into the counters as follows:

Programmable Reference Dividers (IF and RF R Counters)

If t he Contr ol Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22- bit shift register in to a la tch which sets the

15-bi t R Counter. Serial data format is shown below.

CONTROL BITS

DATA LOCATIONC1 C2

0 0 IR R Counter

0 1 RF R Counter

1 0 IF N Counter

1 1 RF N Counter

LSB

↓MSB

↓

C1 C2 R

10 R

11 R

12 R

13 R

14 R

15 R

16 R

17 R

18 R

19 R

15-BI T PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)

DIVIDE

RATIO R

15 R

14 R

13 R

12 R

11 R

10 R

3 000000000000011

4 000000000000100

• •••••••••••••••

32767111111111111111

NOTES:

8. Divide ratios less than 3 are prohibited.

9. D i vi de ra tio : 3 to 32 76 7.

10. R1 to R15: These b its select the div ide ratio of the programma ble reference divider.

11. Data is shifted in MSB first.

PRESCALER 15-BIT IF

N COUNTER

15-BIT IF

R COUNTER

15-BIT RF

R COUNTER

18-BIT RF

N COUNTER

OSC

PRESCALER

CHARGE

PUMP

fOUT

FASTLOCK

LOCK

DETECT

fIN IF

OSCIN

fIN RF

CLOCK

DATA

PHASE

COMP DO IF

PHASE

COMP

DO RF

FO/LD

CHARGE

PUMP

22-BIT DATA

MUX

FIGURE 14. SIMPLIFIED BLOCK DIAGRAM

(C ontrol bits) Divide ratio of the reference divider, R Program Mo des

HFA3524

Programm ab le Divide (N Counter)

The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control

Bits are 10 or 11 (10 for IF counter and 11 for RF count er) data is transferred from the 22-bit shift register into a 4-bit or 7-bit latch

(which sets the Swallow ( A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Seri al data

format is shown bel ow. For the IF N counter bit s 5, 6, and 7 are don’t care bi ts. The RF N co unter does no t have don’t care bits.

7-Bit Swallow Counter Divide Ratio (A Counter) Pulse Swallow Function

Programmable Modes

Several modes of operation can be programmed with bits

R16-R19 i ncludi ng the phas e det ector polar i ty, charge pum p

High Z State and the outp ut of the FO/LD pin. The prescaler

and powerdown modes are sel ected with bits N19 and N20.

The programmable m odes are shown in Table 1. Truth table

for the programmabl e modes and FO/LD out put are shown in

Table 2 and Table 3.

LSB

↓MSB

↓

C1 C2 N

10 N

11 N

12 N

13 N

14 N

15 N

16 N

17 N

18 N

19 N

(C ontrol bits) Divide ratio of the programmable divider, N Program

DIVIDE

RATIO A N

0 0000000

1 0000001

• •••••••

127 1111111

NOTES:

12. Divid e ratio 0 to 127.

13. B ≥ A.

DIVIDE

RATIO A N

0 XXX0000

1 XXX0001

• •••••••

15 XXX1111

X = Don’t car e condition.

11 -BIT PROGR AMMABLE COUNTER DIVIDE RATIO (B COUNTER

DIVIDE

RATIO B N

18 N

17 N

16 N

15 N

14 N

13 N

12 N

11 N

10 N

3 00000000011

4 00000000100

• •••••••••••

2047 11111111111

NOTES:

14. Divid e ratio 3 to 2047 (divide r atios less th an 3 are prohib ited).

15. B ≥ A.

fVCO = [(P x B) + A] x fOSC/R

fVCO:Output fr equency of external voltage controlled

oscillator (VCO)

B: Preset divide ratio of binary 11-bit programmable

counter (3 to 2047)

A: Preset div ide ratio of binary 7-bit swallow counter

(0 ≤ A ≤ 127 {RF}, 0 ≤ A ≤ 15 {IF} , A ≤ B)

fOSC:Output frequency of the external reference frequency

oscillator

R: Preset divide ratio of bina ry 15- bit programmable

referen ce counter (3 to 32767)

P: Preset modulus of dua l modulus prescaler

(for IF: P = 8 or 16; for RF: P = 32 or 64)

TABLE 1. PROGRAMMABLE MODES

C1 C2 R16 R17 R18 R19 R20

0 0 IF Phase

Detector Polarity IF ICPO IF DO

High Z IF LD IF FO

01RF Phase

Detector Polarity RF ICPO RF DO

High Z RF LD RF FO

C1 C2 N19 N20

1 0 IF Prescaler Powerdown IF

1 1 RF Prescaler Powerdown RF

HFA3524

Phase Detector Polarity

Depending upon VCO character istics, R16 bit should be set

accordingly, (see Figure 15).

• When VCO characteristics are positive like (1), R16

should be set HIGH.

• When VCO characteristics are negative like (2), R16

should be set LOW.

TABLE 2. MODE SELECT TRUTH TABLE

ΦD

POLARITY DO HIGH Z STATE (NOTE 16)

ICPO

PRESCALER RF

PRESCALER (NOTE 17)

POWERDOWN

0 Negative Normal Oper ation LOW 8/9 32/33 Power ed Up

1 Positi ve High Z State HIGH 16/17 64/65 Power ed Down

NOTES:

16. The ICPO LOW current state = 1/4 x ICPO HIGH current.

17. Activation of the IF PLL or RF PLL powerdown modes result i n the disablin g of the resp ective N counter d ivider and debi asing of its respective

fIN inputs (to a high impedance state). Powerdown forces the respective charge pump and phase comparator logic to a High Z State condition.

The R c ounter functionali ty does n ot become disabled un til both IF and RF powerdown bits are activated. The OSCIN pin reverts to a high im-

pedance state when this condition exists. The control register remains active and capable of loading and latching in data during all of the pow-

erdown modes.

TABLE 3. THE FO/LD (PIN 10) OUTPUT TRUTH TABLE

RF R [19]

(RF LD) IF R [19]

(IF LD) RF R [20]

(RF FO)IF R [20]

(IF FO)F

O OUTPUT STATE

0 0 0 0 Disabled (Note 18)

0 1 0 0 IF Lock Det ect (No te 19)

1 0 0 0 RF Lock Detect (Note 19 )

1 1 0 0 RF/IF Lock De tect (Note 19)

X 0 0 1 IF Reference Divider Output

X 0 1 0 RF Reference Divider Output

X 1 0 1 IF Programmable Divider Output

X 1 1 0 RF Pr ogrammable Divider Output

0 0 1 1 Fastlock (Note 20)

0 1 1 1 For Internal Use Only

1 0 1 1 For Internal Use Only

1 1 1 1 For Internal Use Only

1 1 1 1 Counter Reset (Note 21)

X = Don’t car e condition

NOTES:

18. When the FO/LD output is disabled, it is actively pulled to a low logic state.

19. Lock detect output provided to indic ate when the VCO fre quency is in “lock”. Wh en the loop is lock ed and a lo ck detect mode is selected , the

pins output is HIGH, with narrow pulses LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and IF are bo th lock ed .

20. The Fastlock mode utilizes the FO/LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation

of Fastlock occurs whenever the RF loop’s lc po magnitude bit #17 is selected HIGH (while th e #19 and #20 m ode bits are set for Fastlock).

21. The Cou nter Re se t mod e bi ts R1 9 a nd R 20 wh en acti va te d r ese t al l co un ter s. U p on r emo val of t he R es et b it s, t h e N cou nt er res umes counting

in “c lo se” al ig nm ent wit h the R count e r. ( The ma xi mu m err or is on e pre sca le r cy cle . ) I f th e Re se t bi ts ar e ac tiv at ed , th e R cou nt er is al so f or ce d

to Reset, al lowing smooth acquisition upon powering up.

(1)

(2)

VCO INPUT VOLTAGE

VCO OUTPUT FREQUENCY

FIGURE 15. VCO CHARACTERISTICS

HFA3524

DATA

CLOCK

N20: MSB

(R20: MSB)

N19

(R19)

tCS tEW

tES

(R8) (R7) (R6) (R1) CONTROL BIT: LSB

N10 N9 N1 CONTROL BIT: LSB

tCWL

tCWH

tCH

NOTES:

22. Parenthes is data indicates programmable referenc e divider data.

23. Data shifted into register on clock rising edge.

24. Data is shifted in MSB first.

Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of

0.6V/ns with amplitudes of 2.2V at VCC = 2.7V and 2.6V at VCC = 5.5V.

FIGURE 16. S ERIAL DATA INPUT TIMING

fR > fP fR = fP fR < fP fR < fP fR < fP

ZII I

NOTES:

25. Pha se difference detection range: -2π to +2π

26. The mi nimum width pump up and p ump dow n current pulses occur at th e DO pin when the loop is locked.

27. R16 = HIGH.

FIGURE 17. PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS

HFA3524

Typical Application Example

Typical Locked Detect Circuit

A lock detect circuit is needed in order to provide a steady

LOW si gnal when the PLL is in the locked state. A typical ci r-

cuit is shown in Figure 20.

100pF

0.01µF

100pF 0.01µF

VCC

VCC VPDO IF GND fIN IF

VCO

(NOTE 28) 10pF IF OUT

CLOCK

DATALEfIN IF

100pF

FROM

CONTROLLER

RIN (NOTE 29)

GND

GND FO/LD FO/LD

OSCIN

GND

100pF

fIN RFfIN RF

RIN

(NOTE 29)

GNDDO RFVCC VP

CRYSTAL OSCILLATOR

INPUT

100pF

0.01µF

100pF

VCC

0.01µF

VCO

(NOTE 28)

10pF

RF OUT

51Ω

(NOTE 30)

NOTES:

28. VCO is assumed AC coupled.

29. RIN inc rea ses imp ed an ce so that VCO ou tp ut po w er is pr o vi ded to th e lo ad ra th er t ha n the P LL . Typi ca l va lu es a re 10Ω to 2 00 Ω de pe ndin g on

the VCO power level. fIN RF impedanc e range s from 40 Ω to 100Ω. fIN IF impe dances ar e higher.

30. 50Ω termination is often used on test boards to allow use of external reference oscillator. For most typical products a CMOS clock is use d and

no terminatin g resistor is required. O SCIN may be AC or DC c oupled. AC coupling is recomm ended beca use the in put circuit provides its own

bias (see Figure 16).

31. Proper use of grounds and bypass capacitors is esse ntial to achi eve a high level of performance. Crosstalk betwe en pins ca n be re duced by

c areful board layout.

32. This is a static sensitive device. It should be handled only at static free work stations.

FIGURE 18.

20 19 18 17 16 15 14 13 12 11

12345678910

HFA3524

OSCIN

100kΩ

FIGURE 19.

FIGURE 20.

VCC

LD 33K 0.01µF

10K

MMBT200 LOCK

DETECT

100K

HFA3524

Application Information

A block diagram of the basic phase locked loop is shown in

Figure 21.

Loop Gain Equations

A linear control system model of the phase feedback fo r a

PLL in th e locked st ate is shown in Fi gure 22 . The open loop

gain i s the produc t of the phase comparator gain (Kφ), t he

VCO gain (KVCO/s), and the loop f il ter gain Z(s) divided by

the gain of the feed back counter modul us (N). The passive

loop filt er configuration used is displayed in Figure 23, while

the complex impedance of the filter is given in Equation 2.

The time constants which det ermine the pole and zero

frequencies of the filter transfer function can be defi ned as:

and

The 3rd order PLL Open Loop Gain can be calcul ated in

terms of frequency, ω, t he filter time const ants T1 and T2,

and the design constants Kφ, KVCO, and N.

From Equation 3 we can see that the phase term will be

dependent on the single pole and zero such that the phase

margin is determined in Equati on 5.

A plot of the magnitude and phase of G(s) H(s) for a stable

loop, is sh own in Figure 24 with a solid t race. The parameter

φP shows the amount of ph ase margin t hat ex ists at th e point

the gain drops below zero (the cutoff f requency wp of the

loop). In a critically damped system, the amount of phase

margin would be approximately 45 degrees.

If we were now to redefine the cut off frequency, wp’, as

double the frequency which gave us our original loop

bandwidth, wp, the loop response time would be

approximately halved. Because the filter attenuation at the

comparison frequency also diminishes, the spurs would have

increased by approximately 6dB. In the proposed Fastlock

sch e me, th e h igh er spu r lev el s an d w ide r loo p f il te r c ond i ti on s

would exist only during the initial lock-on phase - just long

enough to reap the benefits of locking faster. The objective

would be to open up the loop bandwidth but not introduce any

additional complications or compromises related to our

original design criteria. We would ideally like to momentarily

shift the curve of Figure 24 over to a different cutoff frequency,

illustrated by the dotted line, without affecting the relative

open loop gain and phase relationships. To maintain the

same gain/phase relationship at twice the original cutoff

frequency, other terms in the gain and phase Equations 4 and

5 will have to compensate by the corresponding “1/w” or 1/w2”

factor. Examination of Equations 3 and 5 indicates the

damping resistor variable R2 could be chosen to compensate

the “w” terms for the phase margin. This implies that another

resistor of equal value to R2 will need to be switched in

fOUT

VCO

LOOP

Z(s)

CHARGE

PUMP

FILTER

PHASE

DETECTOR

φR

φP

1/N

MAIN

DIVIDER

REFERENCE

FREQUENCY

fREF

FREQUENCY

SYNTHESIZER

1/R

REFERENCE

DIVIDER

CRYSTAL

REFERENCE

fIN

FIGURE 21 . BASIC CHARGE PUMP PHASE LOCKED LOOP

KVCO

Z(s)

Kφ

1/N

∑

ΘE

ΘR

ΘI

+ΘO

FIGURE 22. PLL LINEAR MODEL

VCODO

FIGURE 23. PASSIVE LOOP FILTER

(EQ. 1)

Open loop gain H(s) G(s) ΘIΘE

⁄==

Kφ Z(s) K VCO Ns⁄=

Zs() sC2 R2•()1+

s2C1 C2 R2••()sC1 sC2++

-----------------------------------------------------------------------------------= (EQ. 2)

T1 R2 C1 C2•

C1 C2+

----------------------•=(EQ. 3A)

T2 R2 C2•=(EQ. 3B)

Gs() Hs()•s = j w •

KφKVCO 1jωT2•+()•–

ω2C1 N 1 jωT1•+()•

-------------------------------------------------------------------T1

-------•=(EQ. 4)

φω() tan 1–ωT2•()tan 1–ωT1•()–180o

+= (EQ. 5)

HFA3524

parallel with R2 during the initial lock period. We must also

insure that the magnitude of the open loop gain, H(s)G(s) is

equ al to ze ro at wp’ = 2w p. KVCO, Kφ, N, or t he ne t pro du ct o f

these terms can be changed by a factor of 4, to counteract the

w2 term present in the denominator of Equation 3. The Kφ

term was chosen to complete the transformation because it

can readily be switched between 1X and 4X values. This is

accomplished by increasing th e char ge pump outp ut cu rrent

from 1mA in the standard mode to 4mA in Fastlock.

F ast l ock Circui t I m p lement ation

A diagr am of the Fast lock sc heme as impl ement ed in In tersil

Corporations HFA3524 PLL is shown in Figure 25. When a

new freque ncy is loaded, and the RF IcpO bit is set high, t he

charge pump circuit receives an input to deliver 4 times the

normal current per unit phase error while an open drain

NMOS on chip device swit ches in a second R2 resistor

element to ground. The user c alculates the loop filte r

comp onent values for th e normal stea dy state

considerations . The devic e configurat ion ensures that as

long as a second id enti cal damping resistor is wire d in

appropriately, t he loop will l ock faster without any additional

stabilit y considerati ons to account for. Once locked on the

correct frequency, the user can return the PLL to stand ard

low noi se operation by sendi ng an instruction wit h the RF

IcpO bit set low. This tr ansit ion does not affect the cha rge on

the l oop f ilter capacitors and is enact ed sy nchronous with

the charge pump output. Thi s create s a nearl y seam less

change between Fastlock and standard mode.

PHASE

G(s) H(s)

-90

-180

FREQUENCY

0dB

GAIN

|<G(s) H(s)|

φP

ωPωP’ = 2ωP

φP’

FIGURE 24. OPEN LOOP RESPONSE BODE PLOT

RFOUT

VCO

LOOP FILTER

CHARGE

PUMP

PHASE

DETECTOR

φR

φP

1/N

DIVIDER MAIN

fIN

1/R

REFERENCE

DIVIDER

REFERENCE

CRYSTAL

FASTLOCK

1X 4X FOLD

R2’

FIGURE 25. FASTLOCK CIRCUIT IMPLEMENTATION

HFA3524