Rev. 1.3 2/18 Copyright © 2018 by Silico n Laboratories Si87xx
Si87xx
5KV LED EMULATOR INPUT, OPEN COLLECTOR
OUTPUT ISOLATORS
Features
Applications
Safety Regulatory Approvals
Description
The Si87xx isolators are pin-compatible, one-channel, drop-in
replacements for popular optocouplers with data rates up to 15 Mbps.
These devices isolate high-speed digital signals and offer performance,
reliability, and flexibility advantages not available with optocoupler
solutions. The Si87xx series is based on Silicon Labs' proprietary CMOS
isolation technology for low-power and high-speed operation and are
resistant to the wear-out effects found in optocouplers that degrade
performance with increasing temperature, forward current, and device
age. As a result, the Si87xx series offer longer service life and
dramatically higher reliability compared to optocouplers. Ordering options
include open collector output with and without integrated pull-up resistor
and output enable options.
Pin-compatible, drop-in upgrades for
popular high-speed digital
optocouplers
Performance and reliability
advantages vs. optocouplers
Resistant to temperature, age and
forward current effects
10x lower FIT rate for longer
service life
Higher common-mode transient
immunity: >50 kV/µs typical
Lower power and forward input
diode current
PCB footprint compatible with
optocoupler packaging
Wide range of product options
1 channel diode emulator input
3 to 30 V open collector output
Propagation delay 30 ns
Data rates dc to 15 Mbps
Up to 5000 VRMS isolation and 10 kV
surge protection
AEC-Q100 qualified
Wide operating temperature range
–40 to +125 °C
RoHS-compliant packages
SOIC-8 (Narrow body)
DIP8 (Gull-wing)
SDIP6 (Stretched SO-6)
Industrial automation
Motor controls and drives
Isolated switch mode power supplies
Isolated data acquisition
Test and measurement equipment
UL 1577 recognized
Up to 5000 Vrms for 1 minute
CSA component notice 5A
approval
IEC 60950-1, 60601-1
(reinforced insulation)
VDE certification conformity
VDE0884 Part 10
(basic/reinforced insulation)
CQC certification approval
GB4943.1
Patent pending
Pin Assignments:
See page 20
SOIC-8, DIP8
Open Collector Output
SDIP6
Open Collector Output
SOIC-8, DIP8
Open Collector Output
with 20 k Pull-up Resistor
SOIC-8, DIP8
Open Collector Output
with Output Enable
Si87xx
2 Rev. 1.3
Functional Block Diagram
Diode
Emulator
IF
A1
Output
Stage
(Open-Collector)
OUT
VDD
XMIT
GND
REC
C1
Si87xx
Rev. 1.3 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3. Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.1. Input Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.2. Output Circuit Design and Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . .17
5. Pin Descriptions (SOIC-8, DIP8) Open Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
6. Pin Descriptions (SOIC-8, DIP8) Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7. Pin Descriptions (SDIP6) Open Collector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
8. Pin Descriptions (SOIC-8, DIP8) 20 kW Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . .21
9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
10. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
11. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
12. Package Outline: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
13. Land Pattern: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
14. Package Outline: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
15. Land Pattern: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
16. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
16.1. Top Marking (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
16.2. Top Marking Explanation (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . .32
16.3. Top Marking (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
16.4. Top Marking Explanation (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
16.5. Top Marking (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
16.6. Top Marking Explanation (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Si87xx
4 Rev. 1.3
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
VDD Supply Voltage VDD 3—30V
Input Current
Si87xxA Devices
Si87xxB Devices
Si87xxC Devices
IF(ON)
(see Figure 1) 3
6
3
—
—
—
15
30
15
mA
mA
mA
Operating Temperature (Ambient) TA–40 — 125 °C
Table 2. Electrical Characteristics
VDD = 5 V; GND = 0 V; TA= –40 to +125 °C; typical specs at 25 °C; TJ= –40 to +140 °C
Parameter Symbol Test Condition Min Typ Max Unit
DC Parameters
Supply Voltage VDD (VDD–GND) 3 — 30 V
Supply Current IDD Output high or low (VDD = 5 to 30 V) — — 1.7 mA
Input Current Threshold IF(TH) Si87xxA devices
Si87xxB devices
Si87xxC devices
—
—
—
—
—
—
1.8
3.6
1.8
mA
mA
mA
Input Current Hystere-
sis
IHYS Si87xxA devices
Si87xxB devices
Si87xxC devices
—
—
—
0.17
0.34
0.17
—
—
—
mA
mA
mA
Input Forward Voltage
(OFF)
VF(OFF) Measured at ANODE with respect to
CATHODE.
—— 1V
Input Forward Voltage
(ON)
VF(ON) Measured at ANODE with respect to
CATHODE.
1.6 — 2.8 V
Input Capacitance CIf=100kHz
VF=0V,
VF=2V
—
—
15
15
—
—
pF
pF
Logic Low Output
Voltage
VOL I
OL =3mA, V
DD = 3.3 or 5 V
IOL =13mA, V
DD =5.5V
—
—
—
—
0.4
0.7
V
V
Logic High Output
Current
IOH VDD =V
OUT =5.5V
VDD =V
OUT =24V
—
—
—
—
0.5
1
µA
µA
Peak Output Current IOPK Peak DC collector current drive
(VDD =5V)
—50—mA
Output Low Impedance ROL ——54
Pull-up Resistor RPU Using internal pull-up — 20 — k
Enable High Min VEH 2—30V
Enable Low Max VEL ——0.8V
Enable High Current
Draw
IEH VDD =V
EH =5V — 20 — µA
Enable Low Current
Draw
IEL VDD =5V, V
EL = 0 V — –10 0 µA
Si87xx
Rev. 1.3 5
AC Switching Parameters (VDD =5V, R
L=350, CL= 15 pF)
Maximum Data Rate FDATA Si87xxA devices
Si87xxB devices
Si87xxC devices
DC
DC
DC
—
—
—
15
15
1
MBPS
MBPS
MBPS
Minimum Pulse Width MPW Si87xxA devices
Si87xxB devices
Si87xxC devices
66
66
1
—
—
—
—
—
—
ns
ns
µs
Propagation Delay
(Low-to-High)
tPLH CL= 15 pF using 350 pull-up — — 60 ns
Propagation Delay
(High-to-Low)
tPHL CL= 15 pF using 350 pull-up — — 60 ns
Pulse Width Distortion PWD | tPLH – tPHL |——20ns
Propagation Delay
Skew
tPSK(p-p) tPSK(P-P) is the magnitude of the dif-
ference in prop delays between dif-
ferent units operating at same supply
voltage, load, and ambient temp.
——20ns
Rise Time tRCL= 15 pF using 350 pull-up — 15 — ns
Fall Time tFCL= 15 pF using 350 pull-up — 5 — ns
Device Startup Time tSTART ——40µs
Common Mode
Transient Immunity
CMTI Output = low or high
VCM =1500V (See Figure 2)
IF= 3 mA for Si87xxA devices
IF= 6 mA for Si87xxB devices
IF= 3 mA for Si87xxC devices
20
35
20
35
50
35
—
—
—
kV/µs
kV/µs
kV/µs
Table 2. Electrical Characteristics (Continued)
VDD = 5 V; GND = 0 V; TA= –40 to +125 °C; typical specs at 25 °C; TJ= –40 to +140 °C
Parameter Symbol Test Condition Min Typ Max Unit
Si87xx
6 Rev. 1.3
Figure 1. Diode Emulator Model and I-V Curve
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25 30
AnodetoCathodeVoltage[V]
DiodeEmulatorInputCurrent[mA]
700
2.2 V
10
Anode
Cathode
ESD
Anode
Cathode
e
Si87xx
Rev. 1.3 7
Figure 2. Common Mode Transient Immunity Characterization Circuit
Oscilloscope
5 V
Isolated
Supply
VDD
VO
12 V
Supply
High Voltage
Surge Generator
Vcm Surge
Output
High Voltage
Differential
Probe
GND
Cathode
Anode
Input Signal
Switch
Input
Output
Isolated
Ground
267
348
Si87xx
Si87xx
8 Rev. 1.3
Table 3. Regulatory Information*
CSA
The Si87xx is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract
Number 232873.
60950-1: Up to 1000 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working
voltage.
60601-1: Up to 250 VRMS working voltage and 2 MOPP (Means of Patient Protection).
VDE
The Si87xx is certified according to VDE0884-10. For more details, see certificate 40037519.
VDE0884 Part 10: Up to 1414 Vpeak for reinforced insulation working voltage.
UL
The Si87xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si87xx is certified under GB4943.1-2011. For more details, see certificates CQC15001121489,
CQC15001121490, CQC15001121284, and CQC15001121315.
Rated up to 1000 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
*Note: Regulatory Certifications apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "9.Ordering Guide" on page 22.
Table 4. Insulation and Safety-Related Specifications
Parameter Symbol Test Condition Value Unit
SOIC-8 DIP8 SDIP6
Nominal External Air Gap
(Clearance) CLR 4.7 min 7.2 min 9.6 min mm
Nominal External Tracking
(Creepage) CPG 3.9 min 7.0 min 8.3 min mm
Minimum Internal Gap
(Internal Clearance) DTI 0.016 0.016 0.016 mm
Tracking Resistance CTI or
PTI IEC60112 600 600 600 V
Erosion Depth ED 0.031 0.031 0.057 mm
Resistance (Input-Output)* RIO 1012 1012 1012
Capacitance (Input-Output)* CIO f=1MHz 1 1 1 pF
*Note: To determine resistance and capacitance, the Si87xx is converted into a 2-terminal device. Pins 1–4 (1–3, SDIP6) are
shorted together to form the first terminal, and pins 5–8 (4–6, SDIP6) are shorted together to form the second terminal.
The parameters are then measured between these two terminals.
Si87xx
Rev. 1.3 9
Table 5. IEC 60664-1 Ratings
Parameter Test Condition Specification
SOIC-8 DIP8 SDIP6
Basic Isolation Group Material Group I I I
Installation
Classification
Rated Mains Voltages <
150 VRMS
I-IV I-IV I-IV
Rated Mains Voltages <
300 VRMS
I-IV I-IV I-IV
Rated Mains Voltages <
450 VRMS
I-III I-III I-IV
Rated Mains Voltages <
600 VRMS
I-III I-III I-IV
Rated Mains Voltages <
1000 VRMS
I-II I-II I-III
Table 6. VDE 0884-10 Insulation Characteristics*
Parameter Symbol Test Condition Characteristic Unit
SOIC-8 DIP8 SDIP6
Maximum Working
Insulation Voltage VIORM 630 891 1140 V peak
Input to Output Test
Voltage VPR
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm= 1 sec,
Partial Discharge < 5 pC)
1181 1671 2138 V peak
Transient Overvoltage VIOTM t = 60 sec 6000 6000 8000 V peak
Surge Voltage VIOSM
Tested per IEC 60065 with
surge voltage of 1.2 μs/50 μs
Si87xx tested with magnitude
6250 V x 1.6 = 10 kV
6250 6250 6250 V peak
Pollution Degree
(DIN VDE 0110, Table 1)
222
Insulation Resistance at
TS, VIO =500V RS>109>109>109
*Note: This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety
data is ensured by protective circuits. The Si87xx provides a climate classification of 40/125/21.
Si87xx
10 Rev. 1.3
Table 7. IEC Safety Limiting Values
Parameter Symbol Test Condition Max Unit
SOIC-8 DIP8 SDIP6
Case Temperature TS140 140 140 °C
Input Current ISJA = 110 °C/W (SOIC-8),
110 °C/W (DIP8),
105 °C/W (SDIP6),
VF= 2.8 V, TJ=140°C,
TA=25°C
370 370 390 mA
Output Power PS111W
Note: Maximum value allowed in the event of a failure; also see the thermal derating curve in Figures 3, 4, and 5.
Si87xx
Rev. 1.3 11
Figure 3. (SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per VDE0884 part 10
Figure 4. (DIP8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per VDE0884 part 10
Table 8. Thermal Characteristics
Parameter Symbol Typ Unit
SOIC-8 DIP8 SDIP6
IC Junction-to-Air Thermal
Resistance
JA 110 110 105 ºC/W
400
600
800
1000
1200
owerͲ Ps,InputCurrentͲ Is
Ps(mW)
Is(mA)
0
200
0 20406080100120140
OutputPo
TsͲ CaseTemperature(°C)
400
600
800
1000
1200
owerͲ Ps,InputCurrentͲ Is
Ps(mW)
Is(mA)
0
200
0 20406080100120140
OutputPo
TsͲ CaseTemperature(°C)
Si87xx
12 Rev. 1.3
Figure 5. (SDIP6) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per VDE0884 part 10
400
600
800
1000
1200
owerͲ Ps,InputCurrentͲ Is
Ps(mW)
Is(mA)
0
200
0 20406080100120140
OutputPo
TsͲ CaseTemperature(°C)
Si87xx
Rev. 1.3 13
Table 9. Absolute Maximum Ratings*
Parameter Symbol Min Max Unit
Storage Temperature TSTG –65 +150 °C
Operating Temperature TA–40 +125 °C
Junction Temperature TJ—+140°C
Average Forward Input Current
Si87xxA Devices
Si87xxB Devices
Si87xxC Devices
IF(AVG) —
—
—
15
30
15
mA
mA
mA
Peak Transient Input Current
(< 1 µs pulse width, 300 ps)
IFTR —1 A
Reverse Input Voltage VR—0.3 V
Supply Voltage VDD –0.5 36 V
Output Voltage VOUT –0.5 36 V
Enable Voltage VOUT –0.5 VDD+0.5 V
Output Sink Current ISINK —15mA
Average Output Current IO(AVG) —8mA
Peak Output Current (VDD =5V) I
OPK —75mA
Input Power Dissipation PI—90mW
Output Power Dissipation PO—50mW
Total Power Dissipation PT—140mW
Lead Solder Temperature (10 s) — 260 °C
HBM Rating ESD 3 — kV
Machine Model ESD 200 — V
CDM 500 — V
Maximum Isolation Voltage (1 s) SOIC-8 — 4500 VRMS
Maximum Isolation Voltage (1 s) DIP8 — 4500 VRMS
Maximum Isolation Voltage (1 s) SDIP6 — 6500 VRMS
*Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions specified in the operational sections of this data sheet.
Si87xx
14 Rev. 1.3
2. Functional Description
2.1. Theory of Operation
The Si87xx are pin-compatible, one-channel, drop-in replacements for popular optocouplers with data rates up to
15 Mbps. The operation of an Si87xx channel is analogous to that of an opto coupler, except an RF carrier is
modulated instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for the Si87xx is shown in Figure 6.
Figure 6. Simplified Channel Diagram
RF
OSCILLATOR
MODULATOR DEMODULATOR
AB
Semiconductor-
Based Isolation
Barrier
Transmitter Receiver
LED
Emulator
Output Stage
Open Collector
Si87xx
Rev. 1.3 15
3. Technical Description
3.1. Device Behavior
Truth tables for the Si87xx are summarized in Table 10.
3.2. Device Startup
During start-up, Output VO floats and its voltage level is determined by the external pull-up until VDD rises above
the UVLO+ threshold for a minimum time period of tSTART
. Following this, the output is low when the current flowing
from anode to cathode is > IF(ON). Device startup, normal operation, and shutdown behavior is shown in Figure 7.
Figure 7. Si87xx Operating Behavior (IF > IF(MIN) when VF > VF(MIN))
Table 10. Si87xx Truth Table Summary1
Input VDD EN2VO3
OFF > UVLO H HIGH
OFF > UVLO L HIGH
OFF < UVLO H HIGH
OFF < UVLO L HIGH
ON > UVLO H LOW
ON > UVLO L HIGH
ON < UVLO H HIGH
ON < UVLO L HIGH
Notes:
1. This truth table assumes VDD is powered. UVLO is typically 2.8 V.
2. Si8712 only.
3. The output voltage level is determined by the external pull-up supply.
IF
VO
VDD
tSTART tPLH tPHL
IF(ON) IHYS
UVLO+
Voltage level
determined by
external pull-up
supply
tPLH
VDDHYS
UVLO-
tSTART
Si87xx
16 Rev. 1.3
4. Applications
The following sections detail the input and output circuits necessary for proper operation of the Si87xx family.
4.1. Input Circuit Design
Opto coupler manufacturers typically recommend the circuits shown in Figures 8 and 9. These circuits are
specifically designed to improve opto-coupler input common-mode rejection and increase noise immunity.
Figure 8. Si87xx Input Circuit
Figure 9. High CMR Si87xx Input Circuit
The optically-coupled circuit of Figure 8 turns the LED on when the control input is high. However, internal
capacitive coupling from the LED to the power and ground conductors can momentarily force the LED into its off
state when the anode and cathode inputs are subjected to a high common-mode transient. The circuit shown in
Figure 9 addresses this issue by using a value of R1 sufficiently low to overdrive the LED, ensuring it remains on
during an input common-mode transient. Q1 shorts the LED off in the low output state, again increasing common-
mode transient immunity.
Some opto coupler applications recommend reverse-biasing the LED when the control input is off to prevent
coupled noise from energizing the LED. The Si87xx input circuit requires less current and has twice the off-state
noise margin compared to opto couplers. However, high CMR opto coupler designs that overdrive the LED (see
Figure 9) may require increasing the value of R1 to limit input current IF to its maximum rating when using the
Si87xx. In addition, there is no benefit in driving the Si87xx input diode into reverse bias when in the off state.
Consequently, opto coupler circuits using this technique should either leave the negative bias circuitry unpopulated
or modify the circuitry (e.g., add a clamp diode or current limiting resistor) to ensure that the anode pin of the
Si87xx is no more than –0.3 V with respect to the cathode when reverse-biased.
R1
1
2
3
4
Si87xx
Vdd
Open Drain or
Collector
Control
Input
ANODE
CATHODE
N/C
N/C
R1
1
2
3
4
Si87xx
Vdd
Control
Input
ANODE
CATHODE
N/C
N/C
Q1
Si87xx
Rev. 1.3 17
New designs should consider the input circuit configurations of Figure 10, which are more efficient than those of
Figures 8 and 9. As shown, S1 and S2 represent any suitable switch, such as a BJT or MOSFET, analog
transmission gate, processor I/O, etc. Also, note that the Si87xx input can be driven from the I/O port of any MCU
or FPGA capable of sourcing a minimum of 6 mA (see Figure 10B). Additionally, note that the Si87xx propagation
delay and output drive do not significantly change for values of IF between IF(MIN) and IF(MAX).
Figure 10. Si87xx Other Input Circuit Configurations
4.2. Output Circuit Design and Power Supply Connections
The speed of the open collector circuit is dependent upon the supply, VCC, the pullup resistor, RL, and the load
modeled by CL. Figure 11 illustrates three common circuit output configurations. For VDD = 5 V operation,
RL>350 is recommended to ensure proper VOL levels. For VDD = 30 V operation, RL > 2.1 kis recommended
to ensure proper VOL levels. If the enable pin is used (see Figure 11B) and two separate supplies power VDD and
the VO pullup resistor, the enable pin should be referenced to the VDD pin because VO cannot exceed VDD by more
than 0.5 V. Figure 11C illustrates a circuit using the internal 20 k resistor.
Note that GND can be biased at, above, or below ground as long as the voltage on VDD with respect to GND is a
maximum of 30 V. VDD decoupling capacitors should be placed as close to the package pins as possible. The
optimum values for these capacitors depend on load current and the distance between the chip and its power
source. It is recommended that 0.1 and 1 µF bypass capacitors be used to reduce high-frequency noise and
maximize performance. Opto replacement applications should limit their supply voltages to 30 V or less.
Figure 11. Si87xx Output Circuit Configurations
Si87xx
1
2
3
4
+5V
Control
Input
S1 N/C
ANODE
CATHODE
N/C
Si87xx
AB
R1
S2
4N/C
3CATHODE
2
MCU I/O
Port pin
ANODE
R1
1N/C
Si87xx
Si87xx
B
5
GND
6
VO
7
VE
8
VDD
0.1, 1 µF
EN
VCC1 3-30 V
RL
CL
VCC2 3-30 V
C
5
GND
6
VO
7
8
RL
CL
0.1, 1 µF
VCC 3-30 V
VL
VDD
Si87xx
A
5
GND
6
VO
7
VE
8
VDD
RL
CL
0.1, 1 µF
EN
VCC 3-30 V
Si87xx
18 Rev. 1.3
5. Pin Descriptions (SOIC-8, DIP8) Open Collector
Figure 12. Pin Configuration
Table 11. Pin Descriptions (SOIC-8, DIP8) Open Collector
Pin Name Description
1 NC* No connect.
2 ANODE Anode of LED emulator. VO follows the signal applied to this input with respect to the
CATHODE input.
3 CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input.
4 NC* No connect.
5 GND External MOSFET source connection and ground reference for VDD. This terminal is typically
connected to ground but may be tied to a negative or positive voltage.
6V
OOutput signal.
7 NC* No connect.
8V
DD Output-side power supply input referenced to GND (30 V max).
*Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be
connected to the ground plane.
Si87xx
Rev. 1.3 19
6. Pin Descriptions (SOIC-8, DIP8) Output Enable
Figure 13. Pin Configuration
Table 12. Pin Descriptions (SOIC-8, DIP8) Output Enable
Pin Name Description
1 NC* No connect.
2 ANODE Anode of LED emulator. VO follows the signal applied to this input with respect to the
CATHODE input.
3 CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input.
4 NC* No connect.
5 GND External MOSFET source connection and ground reference for VDD. This terminal is typically
connected to ground but may be tied to a negative or positive voltage.
6V
OOutput signal.
7V
EOutput enable. Tied to VDD to enable output.
8V
DD Output-side power supply input referenced to GND (30 V max).
*Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be
connected to the ground plane.
Si87xx
20 Rev. 1.3
7. Pin Descriptions (SDIP6) Open Collector
Figure 14. Pin Configuration
Table 13. Pin Descriptions (SDIP6) Open Collector
Pin Name Description
1 ANODE Anode of LED emulator. VO follows the signal applied to this input with respect to the
CATHODE input.
2 NC* No connect.
3 CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input.
4 GND External MOSFET source connection and ground reference for VDD. This terminal is typically
connected to ground but may be tied to a negative or positive voltage.
5V
OOutput signal.
6V
DD Output-side power supply input referenced to GND (30 V max).
*Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be
connected to the ground plane.
Si87xx
Rev. 1.3 21
8. Pin Descriptions (SOIC-8, DIP8) 20 k Pull-Up Resistor
Figure 15. Pin Configuration
Table 14. Pin Descriptions (SOIC-8, DIP8) 20 k Pull-Up Resistor
Pin Name Description
1 NC* No connect.
2 ANODE Anode of LED emulator. VO follows the signal applied to this input with respect to the
CATHODE input.
3 CATHODE Cathode of LED emulator. VO follows the signal applied to ANODE with respect to this input.
4 NC* No connect.
5 GND External MOSFET source connection and ground reference for VDD. This terminal is typically
connected to ground but may be tied to a negative or positive voltage.
6V
OOutput signal.
7V
LOutput Pull-Up Load. Tie to VO to enable load.
8V
DD Output-side power supply input referenced to GND (30 V max).
*Note: No Connect. These pins are not internally connected. To maximize CMTI performance, these pins should be
connected to the ground plane.
Si87xx
22 Rev. 1.3
9. Ordering Guide
Table 15. Si87xx Ordering Guide1,2,3
New Ordering
Part Number
(OPN)
Ordering Options
Input/Output
Configuration Dat a Rate
(Cross Reference) Insulation
Rating Temp Range Pkg Type
Open Collector Output (Available in SOIC-8, DIP8, and SDIP6)
Si8710AC-B-IS LED input
Open collector output
15 Mbps
ACPL-W611,
PS9303L2
(Functional Match)
3.75 kVrms –40 to +125 °C SOIC-8
Si8710BC-B-IS High CMTI LED input
Open collector output
15 Mbps
ACPL-W611,
PS9303L2
(Functional Match)
3.75 kVrms –40 to +125 °C SOIC-8
Si8710CC-B-IS LED input
Open collector output
1Mbps
ACPL-W611,
PS9303L2
(Functional Match)
3.75 kVrms –40 to +125 °C SOIC-8
Si8710AC-B-IP LED input
Open collector output
15 Mbps
HCPL-4502 3.75 kVrms –40 to +125 °C DIP8/GW
Si8710BC-B-IP High CMTI LED input
Open collector output
15 Mbps
HCPL-4502 3.75 kVrms –40 to +125 °C DIP8/GW
Si8710CC-B-IP LED input
Open collector output
1Mbps
HCPL-4502 3.75 kVrms –40 to +125 °C DIP8/GW
Si8710AD-B-IS LED input
Open collector output
15 Mbps
ACPL-W611,
PS9303L2
5.0 kVrms –40 to +125 °C SDIP6
Si8710BD-B-IS High CMTI LED input
Open collector output
15 Mbps
ACPL-W611,
PS9303L2
5.0 kVrms –40 to +125 °C SDIP6
Si8710CD-B-IS LED input
Open collector output
1Mbps
ACPL-W611,
PS9303L2
5.0 kVrms –40 to +125 °C SDIP6
Notes:
1. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry
standard classifications.
2. “Si” and “SI” are used interchangeably.
3. AEC-Q100 qualified.
Si87xx
Rev. 1.3 23
Open Collector Output with 20 k Pullup Resistor (Available in SOIC-8 and DIP8)
Si8711AC-B-IS
LED input
Open collector output
with integrated pullup
15 Mbps
HCPL-4506
(Functional Match)
3.75 kVrms –40 to +125 °C SOIC-8
Si8711BC-B-IS
High CMTI LED input
Open collector output
with integrated pullup
15 Mbps
HCPL-4506
(Functional Match)
3.75 kVrms –40 to +125 °C SOIC-8
Si8711CC-B-IS
LED input
Open collector output
with integrated pullup
1Mbps
HCPL-4506
(Functional Match)
3.75 kVrms –40 to +125 °C SOIC-8
Si8711AC-B-IP
LED input
Open collector output
with integrated pullup
15 Mbps
HCPL-4506 3.75 kVrms –40 to +125 °C DIP8/GW
Si8711BC-B-IP
High CMTI LED input
Open collector output
with integrated pullup
15 Mbps
HCPL-4506 3.75 kVrms –40 to +125 °C DIP8/GW
Si8711CC-B-IP
LED input
Open collector output
with integrated pullup
1Mbps
HCPL-4506 3.75 kVrms –40 to +125 °C DIP8/GW
Table 15. Si87xx Ordering Guide1,2,3 (Continued)
New Ordering
Part Number
(OPN)
Ordering Options
Input/Output
Configuration Dat a Rate
(Cross Reference) Insulation
Rating Temp Range Pkg Type
Notes:
1. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry
standard classifications.
2. “Si” and “SI” are used interchangeably.
3. AEC-Q100 qualified.
Si87xx
24 Rev. 1.3
Open Collector Output with Output Enable (Available in SOIC-8 and DIP8)
Si8712AC-B-IS
LED input
Open collector output
with enable
15 Mbps
HCPL-261x/260x
(Functional Match)
3.75 kVrms –40 to +125 °C SOIC-8
Si8712BC-B-IS
High CMTI LED input
Open collector output
with enable
15 Mbps
HCPL-261x/260x
(Functional Match)
3.75 kVrms –40 to +125 °C SOIC-8
Si8712CC-B-IS
LED input
Open collector output
with enable
1Mbps
HCPL-261x/260x
(Functional Match)
3.75 kVrms –40 to +125 °C SOIC-8
Si8712AC-B-IP
LED input
Open collector output
with enable
15 Mbps
HCPL-261x/260x 3.75 kVrms –40 to +125 °C DIP8/GW
Si8712BC-B-IP
High CMTI LED input
Open collector output
with enable
15 Mbps
HCPL-261x/260x 3.75 kVrms –40 to +125 °C DIP8/GW
Si8712CC-B-IP
LED input
Open collector output
with enable
1Mbps
HCPL-261x/260x 3.75 kVrms –40 to +125 °C DIP8/GW
Table 15. Si87xx Ordering Guide1,2,3 (Continued)
New Ordering
Part Number
(OPN)
Ordering Options
Input/Output
Configuration Dat a Rate
(Cross Reference) Insulation
Rating Temp Range Pkg Type
Notes:
1. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry
standard classifications.
2. “Si” and “SI” are used interchangeably.
3. AEC-Q100 qualified.
Si87xx
Rev. 1.3 25
10. Package Outline: 8-Pin Narrow Body SOIC
Figure 16 illustrates the package details for the Si87xx in an 8-pin narrow-body SOIC package. Table 16 lists the
values for the dimensions shown in the illustration.
Figure 16. 8-Pin Narrow Body SOIC Package
Table 16. 8-Pin Narrow Body SOIC Package Diagram Dimensions
Symbol Millimeters
Min Max
A1.351.75
A1 0.10 0.25
A2 1.40 REF 1.55 REF
B0.330.51
C0.190.25
D4.805.00
E3.804.00
e 1.27 BSC
H5.806.20
h0.250.50
L0.401.27
08
Si87xx
26 Rev. 1.3
11. Land Pattern: 8-Pin Narrow Body SOIC
Figure 17 illustrates the recommended land pattern details for the Si87xx in an 8-pin narrow-body SOIC. Table 17
lists the values for the dimensions shown in the illustration.
Figure 17. 8-Pin Narrow Body SOIC Land Pattern
Table 17. 8-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 5.40
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Si87xx
Rev. 1.3 27
12. Package Outline: DIP8
Figure 18 illustrates the package details for the Si87xx in a DIP8 package. Table 18 lists the values for the
dimensions shown in the illustration.
Figure 18. DIP8 Package
Table 18. DIP8 Package Diagram Dimensions
Dimension Min Max
A — 4.19
A1 0.55 0.75
A2 3.17 3.43
b 0.35 0.55
b2 1.14 1.78
b3 0.76 1.14
c 0.20 0.33
D 9.40 9.90
E 7.37 7.87
E1 6.10 6.60
E2 9.40 9.90
e 2.54 BSC.
L 0.38 0.89
aaa — 0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si87xx
28 Rev. 1.3
13. Land Pattern: DIP8
Figure 19 illustrates the recommended land pattern details for the Si87xx in a DIP8 package. Table 19 lists the
values for the dimensions shown in the illustration.
Figure 19. DIP8 Land Pattern
Table 19. DIP8 Land Pattern Dimensions*
Dimension Min Max
C8.858.90
E2.54 BSC
X0.600.65
Y1.651.70
*Note: This Land Pattern Design is based on the IPC-7351 specification.
Si87xx
Rev. 1.3 29
14. Package Outline: SDIP6
Figure 20 illustrates the package details for the Si87xx in an SDIP6 package. Table 20 lists the values for the
dimensions shown in the illustration.
Figure 20. SDIP6 Package
Table 20. SDIP6 Package Diagram Dimensions
Dimension Min Max
A—2.65
A1 0.10 0.30
A2 2.05 —
b0.310.51
c0.200.33
D 4.58 BSC
E 11.50 BSC
E1 7.50 BSC
e 1.27 BSC
L0.401.27
h0.250.75
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si87xx
30 Rev. 1.3
θ0° 8°
aaa — 0.10
bbb — 0.33
ccc — 0.10
ddd — 0.25
eee — 0.10
fff — 0.20
Table 20. SDIP6 Package Diagram Dimensions (Continued)
Dimension Min Max
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si87xx
Rev. 1.3 31
15. Land Pattern: SDIP6
Figure 21 illustrates the recommended land pattern details for the Si87xx in an SDIP6 package. Table 21 lists the
values for the dimensions shown in the illustration.
Figure 21. SDIP6 Land Pattern
Table 21. SDIP6 Land Pattern Dimensions*
Dimension Min Max
C 10.45 10.50
E1.27 BSC
X0.550.60
Y2.002.05
*Note: This Land Pattern Design is based on the IPC-7351 specification.
Si87xx
32 Rev. 1.3
16. Top Markings
16.1. Top Marking (8-Pin Narrow Body SOIC)
16.2. Top Marking Explanation (8-Pin Narrow Body SOIC)
Line 1 Marking: Customer Part Number Si871 = Isolator product series
X = Output configuration
0 = open collector output only
1 = open collector output w/ internal pull-up
2 = open collector output w/ output enable
S = Performance Grade:
A = 15 Mbps, 20 kV/s minimum CMTI
B = 15 Mbps, 35 kV/s minimum CMTI
C = 1 Mbps, 20 kV/s minimum CMTI
V = Insulation rating
C = 3.75 kV
Line 2 Marking: RTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase
Order form.
“R” indicates revision.
Line 3 Marking: Circle = 43 mils Diameter
Left-Justified
“e4” Pb-Free Symbol
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to
the year and work week of the mold date.
Si87xx
Rev. 1.3 33
16.3. Top Marking (DIP8)
16.4. Top Marking Explanation (DIP8)
Line 1 Marking: Customer Part Number Si871 = Isolator product series
X = Output configuration
0 = open collector output only
1 = open collector output w/ internal pull-up
2 = open collector output w/ output enable
S = Performance Grade:
A = 15 Mbps, 20 kV/s minimum CMTI
B = 15 Mbps, 35 kV/s minimum CMTI
C = 1 Mbps, 20 kV/s minimum CMTI
V = Insulation rating
C = 3.75 kV
Line 2 Marking: YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to
the year and work week of the mold date.
RTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase
Order form.
“R” indicates revision.
Line 3 Marking: Circle = 51 mils Diameter
Center-Justified
“e4” Pb-Free Symbol
Country of Origin
(Iso-Code Abbreviation)
CC
Si87xx
34 Rev. 1.3
16.5. Top Marking (SDIP6)
16.6. Top Marking Explanation (SDIP6)
Line 1 Marking: Device 871 = Isolator product series
X = Output configuration
0 = open collector output only
1 = open collector output w/ internal pull-up
2 = open collector output w/ output enable
S = Performance Grade:
A = 15 Mbps, 20 kV/s minimum CMTI
B = 15 Mbps, 35 kV/s minimum CMTI
C = 1 Mbps, 20 kV/s minimum CMTI
V = Insulation rating
C = 3.75 kV; D = 5.0 kV
Line 2 Marking: RTTTTT = Mfg Code Manufacturing Code from the Assembly Purchase
Order form.
“R” indicates revision.
Line 3 Marking: YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the
year and work week of the mold date.
Line 4 Marking: Country of Origin
(Iso-Code Abbreviation)
CC
Si87xx
35 Rev. 1.3
DOCUMENT CHANGE LIST
Revision 0.5 to Revision 1.0
Updated various specs in Table 2 on page 4.
Added Figure 1 on page 6.
Added Figure 2 on page 7.
Added Figure 7 on page 15.
Updated various specs in Table 9 on page 16.
Removed “pending” throughout.
Added references to “CQC” throughout.
Added references to “AEC-Q100 qualified” throughout.
Updated all Top Marking figures and descriptions.
Revision 1.0 to Revision 1.1
Updated Figure 1 on page 6.
Updated Ordering Guide Table 15 on page 22.
Removed references to moisture sensitivity levels from
table note.
Revision 1.1 to Revision 1.2
Removed references to LGA8 throughout.
Deleted all IEC 60747-5 and IEC 61010 references
throughout and added VDE 0884-10 references
throughout.
Updated all certification body’s certificate and file
reference numbers throughout.
Revision 1.2 to Revision 1.3
Updated "9.Ordering Guide" on page 22.
Updated Table 15.
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Si8712BC-B-IP Si8712BC-B-IS Si8712BD-B-IM Si8712CC-B-IP Si8712CC-B-IS Si8712CD-B-IM Si87xxDIP8-KIT
Si87xxSAMP-KIT Si87xxSOIC8-KIT Si8710CD-B-ISR Si8710BD-B-ISR Si8711CC-B-IPR Si8712BC-B-ISR
Si8712CC-B-IPR Si8710AD-B-ISR Si8711BC-B-IPR Si8710BC-B-ISR Si8711BD-B-IMR Si87xxLGA8-KIT
Si8710AC-B-ISR Si8711AD-B-IMR Si8710BC-B-IPR Si8712AD-B-IMR Si8711CD-B-IMR Si8711CC-B-ISR
Si8712CD-B-IMR Si8712CC-B-ISR Si8711BC-B-ISR Si8711AC-B-IPR Si8712AC-B-ISR Si87xxSDIP6-KIT
Si8712AC-B-IPR Si8712BC-B-IPR Si8712BD-B-IMR Si8710AC-B-IPR Si8711AC-B-ISR Si8710CC-B-ISR
Si8710CC-B-IPR SI8710AD-B-IS SI8710BD-B-IS SI8710CC-B-IPR SI8710CD-B-IS SI8711BC-B-IP SI8711BD-B-
IMR SI8712AC-B-IS SI8711AC-B-IS SI8711CD-B-IM SI8711CD-B-IMR SI87xxDIP8-KIT SI87xxLGA8-KIT
SI8710AC-B-IP SI8710BD-B-ISR SI8711CC-B-ISR SI8712CC-B-ISR SI8711CC-B-IP SI8710AC-B-IS SI87xxSAMP-
KIT SI8712AC-B-IPR SI8712BC-B-IS SI8712CC-B-IPR SI8712CD-B-IM SI8710BC-B-IP SI8710CC-B-ISR
SI8711BC-B-IPR SI8712AC-B-ISR SI8710BC-B-IS SI8710CD-B-ISR SI8712CC-B-IS SI87xxSOIC8-KIT SI8712BC-
B-ISR SI8711BC-B-IS SI8711CC-B-IPR SI8711AC-B-IP SI8712CC-B-IP SI8710CC-B-IP SI8711BC-B-ISR
SI8710CC-B-IS SI8712BC-B-IPR SI8712BD-B-IMR
