Publication Number 85 Revision BAmendment 5Issue Date March 17, 2009
Am29PDL128G
Am29PDL128G Cover Sheet
Data Sheet (Retired Product)
This product has been retired and is not recommended for designs. For new and current designs please contact your
Spansion representative for alternates. Availability of this document is retained for reference and historical purposes only.
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
2 Am29PDL128G 85_B5 March 17, 2009
Data Sheet (Retired Product)
This page left intentionally blank.
This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may
be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 25685 Rev: BAmendment/5
Issue Date: March 17, 2009
Am29PDL128G
128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous
Read/ Write Flash Memory with VersatileIOTM Control
This product has been retired and is not recommended for designs. For new and current designs please contact your Spansion
representative for alternates. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
128Mbit Page Mode device
— Word (16-bit) or double word (32-bit) mode selectable via
WORD# input
— Page size of 8 words/4 double words: Fast page read access
from random locations within the page
Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and program
operations for battery-powered applications
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
FlexBank Architecture
— 4 separate banks, with up to two simultaneous operations
per device
— Organized as two 16 Mbit banks (Bank 1 & 4) and two 48
Mbit banks (Bank 2 & 3)
VersatileI/OTM (VIO) Control
— Output voltage generated and input voltages tolerated on the
device is determined by the voltage on the VIO pin
SecSi (Secured Silicon) Sector region
— 128 words (64 double words) accessible through a
command sequence
Both top and bottom boot blocks in one device
Manufactured on 0.17 µm process technology
20-year data retention at 125°C
Minimum 1 million erase cycle guarantee per sector
PERFORMANCE CHARACTERISTICS
High Performance
— Page access times as fast as 25 ns
— Random access times as fast as 70 ns
Power consumption (typical values at 10 MHz)
— 38 mA active read current
— 17 mA program/erase current
— 1.5 µA typical standby mode current
SOFTWARE FEATURES
Software command-set compatible with JEDEC 42.4
standard
— Backward compatible with Am29F and Am29LV families
CFI (Common Flash Interface) complaint
— Provides device-specific information to the system, allowing
host software to easily reconfigure for different Flash devices
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
operations in other sectors of same bank
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or erase
cycle completion
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array data
WP# (Write Protect) input
—At V
IL, protects the two top and two bottom sectors,
regardless of sector protect/unprotect status
—At V
IH, allows removal of sector protection
— An internal pull up to Vcc is provided
Persistent Sector Protection
— A command sector protection method to lock combinations
of individual sectors and sector groups to prevent program or
erase operations within that sector
— Sectors can be locked and unlocked in-system at VCC level
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using
a user-defined 64-bit password
ACC (Acceleration) input provides faster programming
times in a factory setting
Package options
— 80-ball Fortified BGA
Refer to AMD’s Website (www.amd.com) for the latest information.
March 17, 2009 Am29PDL128G 3
PRELIMINARY
GENERAL DESCRIPTION
The Am29PDL128G is a 128 Mbit, 3.0 volt-only Page Mode
and Simultaneous Read/Write Flash memory device orga-
nized as 8 Mwords or 4 M double words (One word is equal
to two bytes). The device is offered in an 80-ball Fortified
BGA package. The word-wide data (x16) appears on
DQ15-DQ0; the double word mode data (x32) appears on
DQ31-DQ0. This device can be programmed in-system or in
standard EPROM programmers. A 12.0 V VPP is not required
for write or erase operations.
The device offers fast page access times of 25 and 30 ns,
with corresponding random access times of 70 and 80 ns,
respectively, allowing high speed microprocessors to oper-
ate without wait states. To eliminate bus contention the de-
vice has separate chip enable (CE#), write enable (WE#)
and output enable (OE#) controls.
Simultaneous Read/Write Operation with
Zero Latency
The Simultaneous Read/Write architecture provides simul-
taneous operation by dividing the memory space into 4
banks, which can be considered to be four separate memory
arrays as far as certain operations are concerned. The de-
vice can improve overall system performance by allowing a
host system to program or erase in one bank, then immedi-
ately and simultaneously read from another bank with zero
latency (with 2 simultaneous operations operating at any one
time). This releases the system from waiting for the comple-
tion of a program or erase operation, greatly improving sys-
tem performance.
The device can be organized in both top and bottom sector
configurations (see Ta ble 1).
Page Mode Features
The device is AC timing, input/output, and package compat-
ible with 8 Mbit x16 page mode mask ROM. The page size
is 8 words or 4 double words.
After initial page access is accomplished, the page mode op-
eration provides fast read access speed of random locations
within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V
to 3.6 V) for both read and write functions. Internally gener-
ated and regulated voltages are provided for the program
and erase operations.
The device is entirely command set compatible with the
JEDEC 42.4 single-power-supply Flash standard. Com-
mands are written to the command register using standard
microprocessor write timing. Register contents serve as in-
puts to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch ad-
dresses and data needed for the programming and erase
operations. Reading data out of the device is similar to read-
ing from other Flash or EPROM devices.
Device programming occurs by executing the program com-
mand sequence. The Unlock Bypass mode facilitates faster
programming times by requiring only two write cycles to pro-
gram data instead of four. Device erasure occurs by execut-
ing the erase command sequence.
The host system can detect whether a program or erase op-
eration is complete by reading the DQ7 (Data# Polling) and
DQ6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or ac-
cept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data con-
tents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low VCC de-
tector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any combina-
tion of sectors of memory. This can be achieved in-system or
via programming equipment.
The Erase Suspend/Erase Resume feature enables the
user to put erase on hold for any period of time to read data
from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved. If a
read is needed from the SecSi Sector area (One Time Pro-
gram area) after an erase suspend, then the user must use
the proper command sequence to enter and exit this region.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of time, the
device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power con-
sumption is greatly reduced in both these modes.
AMD’s Flash technology combined years of Flash memory
manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electri-
cally erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using
hot electron injection.
Bank/Sector Sizes
Bank
Number of
Sectors
Sector Size
(Word/Dbl.
Word) Bank Size
184/2
16 Mbit
31 32/16
2 96 32/16 48 Mbit
3 96 32/16 48 Mbit
484/2
16 Mbit
31 32/16
4 Am29PDL128G March 17, 2009
PRELIMINARY
TABLE OF CONTENTS
Continuity of Specifications ...................................................... 1
Continuity of Ordering Part Numbers ....................................... 1
For More Information ................................................................ 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Simultaneous Read/Write Block Diagram . . . . . . 7
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 8
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10
Device Bus Operations . . . . . . . . . . . . . . . . . . . . 11
Table 1. Am29PDL128G Device Bus Operations ...........................11
Word/Double Word Configuration........................................... 11
Requirements for Reading Array Data ................................... 11
Random Read (Non-Page Read) ........................................... 11
Page Mode Read .................................................................... 12
Table 2. Page Select, Double Word Mode ......................................12
Table 3. Page Select, Word Mode ..................................................12
Simultaneous Operation ......................................................... 12
Table 4. Bank Select .......................................................................12
Writing Commands/Command Sequences ............................ 12
Accelerated Program Operation ............................................. 13
Autoselect Functions .............................................................. 13
Standby Mode ........................................................................ 13
Automatic Sleep Mode ........................................................... 13
RESET#: Hardware Reset Pin ............................................... 13
Output Disable Mode .............................................................. 13
Table 5. Sector Address Table ........................................................14
Table 6. SecSi™ Sector Addresses ................................................21
Autoselect Mode..................................................................... 21
Table 7. Autoselect Codes (High Voltage Method) ........................21
Table 8. Sector Block Addresses for Protection/Unprotection ........22
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 24
Persistent Sector Protection ................................................... 25
Persistent Protection Bit (PPB) ............................................... 25
Persistent Protection Bit Lock (PPB Lock) ............................. 25
Dynamic Protection Bit (DYB) ................................................ 25
Table 9. Sector Protection Schemes ...............................................26
Persistent Sector Protection Mode Locking Bit ...................... 26
Password Protection Mode ..................................................... 26
Password and Password Mode Locking Bit ........................... 26
64-bit Password ...................................................................... 27
Write Protect (WP#) ................................................................ 27
Persistent Protection Bit Lock ................................................. 27
High Voltage Sector Protection .............................................. 27
Figure 1. In-System Sector Protection/Sector Unprotection Algorithms
28
Temporary Sector Unprotect .................................................. 29
Figure 2. Temporary Sector Unprotect Operation........................... 29
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 29
SecSi Sector Protection Bit .................................................... 30
Utilizing Password and SecSi Sector Concurrently ................ 30
Figure 3. SecSi Sector Protect Verify.............................................. 30
Hardware Data Protection ...................................................... 30
Low VCC Write Inhibit ............................................................ 31
Write Pulse “Glitch” Protection ............................................... 31
Logical Inhibit .......................................................................... 31
Power-Up Write Inhibit ............................................................ 31
Common Flash Memory Interface (CFI) . . . . . . . 31
Table 10. CFI Query Identification String ............................ 31
Table 11. System Interface String................................................... 32
Table 12. Device Geometry Definition................................. 33
Table 13. Primary Vendor-Specific Extended Query........... 34
Command Definitions. . . . . . . . . . . . . . . . . . . . . . 35
Reading Array Data ................................................................ 35
Reset Command ..................................................................... 35
Autoselect Command Sequence ............................................ 35
Enter SecSi Sector/Exit SecSi Sector
Command Sequence .............................................................. 35
Double Word/Word Program Command Sequence ................ 36
Unlock Bypass Command Sequence ..................................... 36
Figure 4. Program Operation ......................................................... 37
Chip Erase Command Sequence ........................................... 37
Sector Erase Command Sequence ........................................ 37
Figure 5. Erase Operation.............................................................. 38
Erase Suspend/Erase Resume Commands ........................... 38
Password Program Command ................................................ 38
Password Verify Command .................................................... 39
Password Protection Mode Locking Bit Program Command .. 39
Persistent Sector Protection Mode Locking Bit Program
Command ............................................................................... 39
SecSi Sector Protection Bit Program Command .................... 39
PPB Lock Bit Set Command ................................................... 39
DYB Write Command ............................................................. 40
Password Unlock Command .................................................. 40
PPB Program Command ........................................................ 40
All PPB Erase Command ........................................................ 40
DYB Write Command ............................................................. 40
PPB Lock Bit Set Command ................................................... 41
PPB Lock Bit Status Command .............................................. 41
Sector Protection Status Command ....................................... 41
Command Definitions Tables.................................................. 42
Table 14. Memory Array Command Definitions (x32 Mode) .......... 42
Table 15. Sector Protection Command Definitions (x32 Mode) ..... 43
Table 16. Memory Array Command Definitions (x16 Mode) .......... 44
Table 17. Sector Protection Command Definitions (x16 Mode) ..... 45
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 46
DQ7: Data# Polling ................................................................. 46
Figure 6. Data# Polling Algorithm .................................................. 46
RY/BY#: Ready/Busy#............................................................ 47
DQ6: Toggle Bit I .................................................................... 47
Figure 7. Toggle Bit Algorithm........................................................ 47
DQ2: Toggle Bit II ................................................................... 48
Reading Toggle Bits DQ6/DQ2 ............................................... 48
DQ5: Exceeded Timing Limits ................................................ 48
DQ3: Sector Erase Timer ....................................................... 48
Table 18. Write Operation Status ................................................... 49
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 50
Figure 8. Maximum Negative Overshoot Waveform ...................... 50
Figure 9. Maximum Positive Overshoot Waveform........................ 50
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 51
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 10. Test Setup.................................................................... 52
March 17, 2009 Am29PDL128G 5
PRELIMINARY
Figure 11. Input Waveforms and Measurement Levels .................. 52
AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 53
Read-Only Operations ........................................................... 53
Figure 12. Read Operation Timings ................................................ 53
Figure 13. Page Read Operation Timings....................................... 54
Hardware Reset (RESET#) .................................................... 55
Figure 14. Reset Timings ................................................................ 55
Word/Double Word Configuration (WORD#) .......................... 56
Figure 15. WORD# Timings for Read Operations........................... 56
Figure 16. WORD# Timings for Write Operations........................... 56
Erase and Program Operations .............................................. 57
Figure 17. Program Operation Timings........................................... 58
Figure 18. Accelerated Program Timing Diagram........................... 58
Figure 19. Chip/Sector Erase Operation Timings ........................... 59
Figure 20. Back-to-back Read/Write Cycle Timings ....................... 60
Figure 21. Data# Polling Timings (During Embedded Algorithms).. 60
Figure 22. Toggle Bit Timings (During Embedded Algorithms)....... 61
Figure 23. DQ2 vs. DQ6.................................................................. 61
Temporary Sector Unprotect .................................................. 62
Figure 24. Temporary Sector Unprotect Timing Diagram .............. 62
Figure 25. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 63
Alternate CE# Controlled Erase and Program Operations ..... 64
Figure 26. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 65
Erase And Programming Performance. . . . . . . . 66
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 66
BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 66
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 67
LAB080—80-Ball Fortified Ball Grid Array
15 x 10 mm package ..............................................................67
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 68
6 Am29PDL128G March 17, 2009
PRELIMINARY
PRODUCT SELECTOR GUIDE
Note: See “AC Characteristics” on page 53 for full specifications.
BLOCK DIAGRAM
Notes:
1. In double word mode, input/outputs are DQ31-DQ0, address range is A21-A0. In word mode, input/outputs are DQ15-DQ0, address range is
A21-A-1.
2. RY/BY# is an open drain output.
Part Number Am29PDL128G
Speed Option
Voltage Range: VCC = 3.0–3.6 V 70R
Voltage Range: VCC = 2.7–3.6 V 70 80 90
Max Access Time, ns (tACC) 708090
Max CE# Access, ns (tCE) 708090
Max Page Access, ns (tPAC C ) 253035
Max OE# Access, ns (tOE) 253040
V
CC
V
SS
State
Control
Command
Register PGM Voltage
Generator
V
CC
Detector Timer
Erase Voltage
Generator
Input/Output
Buffers
Sector
Switches
Chip Enable
Output Enable
Logic
Y-Gating
Cell Matrix
Address Latch
Y-Decoder
X-Decoder
Data Latch
RESET#
RY/BY# (Note 2)
STB
STB
A21–A2
A1–A0
(A-1)
A3, A4
CE#
OE#
WE#
DQ31–DQ0
V
IO
March 17, 2009 Am29PDL128G 7
PRELIMINARY
SIMULTANEOUS READ/WRITE BLOCK DIAGRAM
V
CC
V
SS
Bank 1 Address
Bank 2 Address
A21–A0
RESET#
WE#
CE#
DQ0–DQ15
DW/W#
WP#
ACC
STATE
CONTROL
&
COMMAND
REGISTER
RY/BY#
Bank 1
X-Decoder
OE# DW/W#
DQ31–DQ0
Status
Control
A21–A0
A21–A0
A21–A0A21–A0
DQ31–DQ0
DQ31–DQ0
DQ31–DQ0
DQ31–DQ0
Mux
Mux
Mux
Bank 2
X-Decoder
Y-gate
Bank 3
X-Decoder
Bank 4
X-Decoder
Y-gate
Bank 3 Address
Bank 4 Address
8 Am29PDL128G March 17, 2009
PRELIMINARY
CONNECTION DIAGRAMS
Special Handling Instructions for BGA
Packages
Special handling is required for Flash Memory products
in molded packages (BGA). The package and/or data
integrity may be compromised if the package body is
exposed to temperatures above 150°C for prolonged
periods of time.
B2 D2 E2 F2 G2 H2 J2
B3 D3 E3 F3 G3 H3 J3
B4 D4 E4 F4 G4 H4 J4
B5 D5 E5 F5 G5 H5 J5
B6 D6 E6 F6 G6 H6 J6
B7 D7 E7 F7 G7 H7 J7
DQ24 A19VIO
DQ26DQ13VSS
DQ15CE#
DQ8 A16DQ25DQ27DQ12DQ14DQ31/A-1A20
A14 A13DQ10RFUACCDQ29WE#WP#
A12 RFUVSS
RFURESET#DQ18A1A0
VSS A10DQ22DQ20DQ4VSS
DQ16A3
DQ23 A7
K2
K3
K4
K5
K6
K7
A17
A15
RFU
RFU
A11
A9DQ6DQ21DQ3VIO
DQ1VCC
B1 D1 E1 F1 G1 H1 J1
DQ7 A6VIO
DQ5DQ19DQ2DQ17DQ0
A1
A5
B8 D8
C2
C3
C4
C5
C6
C7
A2
A3
A4
A5
A6
A7
WORD#
A21
RFU
RY/BY#
A2
A4
C1
C8 E8 F8 G8 H8 J8
DQ9 VCC
K1
A8
K8
A18VSS
DQ11DQ28VIO
DQ30VSS
A8
OE#
80-Ball Fortified BGA
Top View, Balls Facing Down
March 17, 2009 Am29PDL128G 9
PRELIMINARY
PIN DESCRIPTION
A21–A0 = 22 Addresses
DQ30–DQ0 = 31 Data Inputs/Outputs
DQ31/A-1 = DQ31 (Data Input/Output, double
word mode), A-1 (LSB Address In-
put, word mode)
CE# = Chip Enable
OE# = Output Enable
WE# = Write Enable
WP# = Hardware Write Protect Input
ACC = Acceleration Input
RESET# = Hardware Reset Pin, Active Low
WORD# = Word Enable Input
At VIL, selects 16-bit mode,
At VIH, selects 32-bit mode
RY/BY# = Ready/Busy Output
VCC = 3.0 Volt-only Single Power Supply
(see Product Selector Guide for
speed options and voltage supply
tolerances)
VIO = Output Buffer Power Supply
VSS = Device Ground
NC = Pin Not Connected Internally
RFU = Reserved for Future Use
LOGIC SYMBOL
22
32 or 16
DQ31–DQ0
(A-1)
A21–A0
CE#
OE#
WE#
RESET#
WORD#
RY/BY#
ACC
WP#
VIO
10 Am29PDL128G March 17, 2009
PRELIMINARY
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be supported in
volume for this device. Consult the local AMD sales office to con-
firm availability of specific valid combinations and to check on
newly released combinations.
Am29PDL128G 70 PE I
OPTIONAL PROCESSING
Blank = Standard Processing
N = 16-byte ESN devices
(Contact an AMD representative for more information)
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
F = Industrial (–40°C to +85°C) for Pb-free Package
K = Extended (-55C to +125C) for Pb-free Package
PACKAGE TYPE
PE = 80-Ball Fortified Ball Grid Array (fBGA)
1 mm pitch, 15 x 10 mm package (LAB080)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29PDL128G
128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
Valid Combinations for BGA Packages
Order Number Package Marking
Am29PDL128G70R PEF
PEI
PD128G70R I,F
Am29PDL128G70 PD128G70V
Am29PDL128G80 PEI,
PEE,
PEF,
PEK
PD128G80V
I, E
F, K
Am29PDL128G90 PD128G90V
March 17, 2009 Am29PDL128G 11
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Ta b l e 1 lists the device bus operations, the in-
puts and control levels required, and the resulting out-
put. The following subsections describe each of these
operations in further detail.
Table 1. Am29PDL128G Device Bus Operations
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, V HH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A21–A0 in double word mode (WORD# = VIH), A21–A-1 in word mode (WORD# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector Protection”
on page 24.
Word/Double Word Configuration
The WORD# pin controls whether the device data I/O
pins operate in the word or double word configuration.
If the WORD# pin is set at VIH, the device is in double
word configuration, DQ31–DQ0 are active and con-
trolled by CE# and OE#.
If the WORD# pin is set at VIL, the device is in word
configuration, and only data I/O pins DQ15–DQ0 are
active and controlled by CE# and OE#. The data I/O
pins DQ30–DQ16 are tri-stated, and the DQ31 pin is
used as an input for the least significant address bit
(LSB) function, which is named A-1.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH. The WORD# pin determines
whether the device outputs array data in words or dou-
ble words.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the AC Read-Only Operations table on
page 53 for timing specifications and to Ta b l e 1 2 for
the timing diagram. ICC1 in the DC Characteristics table
represents the active current specification for reading
array data.
Random Read (Non-Page Read)
Address access time (tACC) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (tCE) is the delay from the stable ad-
dresses and stable CE# to valid data at the output in-
puts. The output enable access time is the delay from
the falling edge of the OE# to valid data at the output
Operation CE# OE# WE# RESET# WP#
Addresses
(Note 1)
DQ31–DQ16
DQ15–
DQ0
WORD#
= VIH
WORD#
= VIL
Read L L H H X AIN DOUT DQ30–DQ16 =
High-Z, DQ31 = A-1
DOUT
Write L H L H X AIN DIN DIN
Standby VCC ±
0.3 V XX
VCC ±
0.3 V X X High-Z High-Z High-Z
Output Disable L H H H X X High-Z High-Z High-Z
Reset X X X L X X High-Z High-Z High-Z
Temporary Sector
Unprotect (High Voltage) XXX V
ID XA
IN DIN XD
IN
12 Am29PDL128G March 17, 2009
PRELIMINARY
inputs (assuming the addresses have been stable for
at least tACC–tOE time).
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 8 words, or 4 double words, with the ap-
propriate page being selected by the higher address
bits A21–A2 and the LSB bits A1–A0 (in the double
word mode) and A1 to A-1 (in the word mode) deter-
mining the specific word/double word within that page.
This is an asynchronous operation with the micropro-
cessor supplying the specific word or double word lo-
cation.
The random or initial page access is equal to tACC or
tCE and subsequent page read accesses (as long as
the locations specified by the microprocessor falls
within that page) is equivalent to tPACC. When CE# is
deasserted and reasserted for a subsequent access,
the access time is tACC or tCE. Here again, CE# selects
the device and OE# is the output control and should
be used to gate data to the output inputs if the device
is selected. Fast page mode accesses are obtained by
keeping A21–A2 constant and changing A1 to A0 to
select the specific double word, or changing A1 to A-1
to select the specific word, within that page.
Table 2. Page Select, Double Word Mode
Table 3. Page Select, Word Mode
Simultaneous Operation
The device is capable of reading data from one bank
of memory while a program or erase operation is in
progress in another bank of memory (simultaneous
operation), in addition to the conventional features
(read, program, erase-suspend read, and erase-sus-
pend program). The bank selected can be selected by
bank addresses (A21–A19) with zero latency.
The simultaneous operation can execute multi-func-
tion mode in the same bank.
Table 4. Bank Select
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the WORD# pin determines
whether the device accepts program data in double
words or words. Refer to “Word/Double Word Configu-
ration” for more information.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once a bank enters the Un-
lock Bypass mode, only two write cycles are required
to program a double word or word, instead of four. See
“Double Word/Word Program Command Sequence”
on page 36 for details on programming data to the de-
vice using both standard and Unlock Bypass com-
mand sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Ta bl e 5 indicates the address
space that each sector occupies. A “bank address” is
the address bits required to uniquely select a bank.
Similarly, a “sector address” refers to the address bits
required to uniquely select a sector. The “Command
Definitions” section has details on erasing a sector or
the entire chip, or suspending/resuming the erase op-
eration.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. See “AC
Characteristics” on page 53 for timing specification ta-
bles and timing diagrams for write operations.
Word A1 A0
Double Word 0 0 0
Double Word 1 0 1
Double Word 2 1 0
Double Word 3 1 1
Word A1 A0 A-1
Word 0000
Word 1001
Word 2010
Word 3011
Word 4100
Word 5101
Word 6110
Word 7111
Bank A21–A19
Bank 1 000
Bank 2 001, 010, 011
Bank 3 100, 101, 110
Bank 4 111
March 17, 2009 Am29PDL128G 13
PRELIMINARY
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput at the
factory.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the ACC pin returns the device to normal op-
eration. Note that VHH must not be asserted on ACC
for operations other than accelerated programming, or
device damage may result.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ15–DQ0. Standard read cycle timings apply in
this mode. See “Autoselect Mode” on page 21 and
“Autoselect Command Sequence” on page 35 for
more information.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note: This is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device is in the standby mode, but the
standby current is greater. The device requires stan-
dard access time (tCE) for read access when the de-
vice is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
CMOS standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for tACC +
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Note that during automatic sleep mode, OE# must be
at VIH before the device reduces current to the stated
sleep mode specification. ICC5 in the DC Characteris-
tics table represents the automatic sleep mode current
specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is
held at VIL but not within VSS±0.3 V, the standby cur-
rent is greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The sys-
tem can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
Refer to tables in AC Characteristics for RESET# pa-
rameters and to Figure 13 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins (except for RY/BY#) are
placed in the high impedance state.
14 Am29PDL128G March 17, 2009
PRELIMINARY
Table 5. Sector Address Table (Sheet 1 of 7)
Bank Sector
Sector Address
(A21-A11)
Sector Size
(Kwords/
Kdoublewords)
Address Range
(x16)
Address Range
(x32)
Bank 1
SA0 00000000000 4/2 00000h–00FFFh 000000h–0007FFh
SA1 00000000001 4/2 01000h–01FFFh 000800h–000FFFh
SA2 00000000010 4/2 02000h–02FFFh 001000h–0017FFh
SA3 00000000011 4/2 03000h–03FFFh 001800h–001FFFh
SA4 00000000100 4/2 04000h–04FFFh 002000h–0027FFh
SA5 00000000101 4/2 05000h–05FFFh 002800h–002FFFh
SA6 00000000110 4/2 06000h–06FFFh 003000h–0037FFh
SA7 00000000111 4/2 07000h–07FFFh 003800h–003FFFh
SA8 00000001XXX 32/16 08000h–0FFFFh 004000h–007FFFh
SA9 00000010XXX 32/16 10000h–17FFFh 008000h–00BFFFh
SA10 00000011XXX 32/16 18000h–1FFFFh 00C000h–00FFFFh
SA11 00000100XXX 32/16 20000h–27FFFh 010000h–013FFFh
SA12 00000101XXX 32/16 28000h–2FFFFh 014000h–017FFFh
SA13 00000110XXX 32/16 30000h–37FFFh 018000h–01BFFFh
SA14 00000111XXX 32/16 38000h–3FFFFh 01C000h–01FFFFh
SA15 00001000XXX 32/16 40000h–47FFFh 020000h–023FFFh
SA16 00001001XXX 32/16 48000h–4FFFFh 024000h–027FFFh
SA17 00001010XXX 32/16 50000h–57FFFh 028000h–02BFFFh
SA18 00001011XXX 32/16 58000h–5FFFFh 02C000h–02FFFFh
SA19 00001100XXX 32/16 60000h–67FFFh 030000h–033FFFh
SA20 00001101XXX 32/16 68000h–6FFFFh 034000h–037FFFh
SA21 00001110XXX 32/16 70000h–77FFFh 038000h–03BFFFh
SA22 00001111XXX 32/16 78000h–7FFFFh 03C000h–03FFFFh
SA23 00010000XXX 32/16 80000h–87FFFh 040000h–043FFFh
SA24 00010001XXX 32/16 88000h–8FFFFh 044000h–047FFFh
SA25 00010010XXX 32/16 90000h–97FFFh 048000h–04BFFFh
SA26 00010011XXX 32/16 98000h–9FFFFh 04C000h–04FFFFh
SA27 00010100XXX 32/16 A0000h–A7FFFh 050000h–053FFFh
SA28 00010101XXX 32/16 A8000h–AFFFFh 054000h–057FFFh
SA29 00010110XXX 32/16 B0000h–B7FFFh 058000h–05BFFFh
SA30 00010111XXX 32/16 B8000h–BFFFFh 05C000h–05FFFFh
SA31 00011000XXX 32/16 C0000h–C7FFFh 060000h–063FFFh
SA32 00011001XXX 32/16 C8000h–CFFFFh 064000h–067FFFh
SA33 00011010XXX 32/16 D0000h–D7FFFh 068000h–06BFFFh
SA34 00011011XXX 32/16 D8000h–DFFFFh 06C000h–06FFFFh
SA35 00011100XXX 32/16 E0000h–E7FFFh 070000h–073FFFh
SA36 00011101XXX 32/16 E8000h–EFFFFh 074000h–077FFFh
SA37 00011110XXX 32/16 F0000h–F7FFFh 078000h–07BFFFh
SA38 00011111XXX 32/16 F8000h–FFFFFh 07C000–07FFFFh
March 17, 2009 Am29PDL128G 15
PRELIMINARY
Bank 2
SA39 00100000XXX 32/16 100000h–107FFFh 080000h–083FFFh
SA40 00100001XXX 32/16 108000h–10FFFFh 084000h–087FFFh
SA41 00100010XXX 32/16 110000h–117FFFh 088000h–08BFFFh
SA42 00100011XXX 32/16 118000h–11FFFFh 08C000h–08FFFFh
SA43 00100100XXX 32/16 120000h–127FFFh 090000h–093FFFh
SA44 00100101XXX 32/16 128000h–12FFFFh 094000h–097FFFh
SA45 00100110XXX 32/16 130000h–137FFFh 098000h–09BFFFh
SA46 00100111XXX 32/16 138000h–13FFFFh 09C000h–09FFFFh
SA47 00101000XXX 32/16 140000h–147FFFh 0A0000h–0A3FFFh
SA48 00101001XXX 32/16 148000h–14FFFFh 0A4000h–0A7FFFh
SA49 00101010XXX 32/16 150000h–157FFFh 0A8000h–0ABFFFh
SA50 00101011XXX 32/16 158000h–15FFFFh 0AC000h–0AFFFFh
SA51 00101100XXX 32/16 160000h–167FFFh 0B0000h–0B3FFFh
SA52 00101101XXX 32/16 168000h–16FFFFh 0B4000h–0B7FFFh
SA53 00101110XXX 32/16 170000h–177FFFh 0B8000h–0BBFFFh
SA54 00101111XXX 32/16 178000h–17FFFFh 0BC000h–0BFFFFh
SA55 00110000XXX 32/16 180000h–187FFFh 0C0000h–0C3FFFh
SA56 00110001XXX 32/16 188000h–18FFFFh 0C4000h–0C7FFFh
SA57 00110010XXX 32/16 190000h–197FFFh 0C8000h–0CBFFFh
SA58 00110011XXX 32/16 198000h–19FFFFh 0CC000h–0CFFFFh
SA59 00110100XXX 32/16 1A0000h–1A7FFFh 0D0000h–0D3FFFh
SA60 00110101XXX 32/16 1A8000h–1AFFFFh 0D4000h–0D7FFFh
SA61 00110110XXX 32/16 1B0000h–1B7FFFh 0D8000h–0DBFFFh
SA62 00110111XXX 32/16 1B8000h–1BFFFFh 0DC000h–0DFFFFh
SA63 00111000XXX 32/16 1C0000h–1C7FFFh 0E0000h–0E3FFFh
SA64 00111001XXX 32/16 1C8000h–1CFFFFh 0E4000h–0E7FFFh
SA65 00111010XXX 32/16 1D0000h–1D7FFFh 0E8000h–0EBFFFh
SA66 00111011XXX 32/16 1D8000h–1DFFFFh 0EC000h–0EFFFFh
SA67 00111100XXX 32/16 1E0000h–1E7FFFh 0F0000h–0F3FFFh
SA68 00111101XXX 32/16 1E8000h–1EFFFFh 0F4000h–0F7FFFh
SA69 00111110XXX 32/16 1F0000h–1F7FFFh 0F8000h–0FBFFFh
SA70 00111111XXX 32/16 1F8000h–1FFFFFh 0FC000h–0FFFFFh
SA71 01000000XXX 32/16 200000h–207FFFh 100000h–103FFFh
SA72 01000001XXX 32/16 208000h–20FFFFh 104000h–107FFFh
SA73 01000010XXX 32/16 210000h–217FFFh 108000h–10BFFFh
SA74 01000011XXX 32/16 218000h–21FFFFh 10C000h–10FFFFh
SA75 01000100XXX 32/16 220000h–227FFFh 110000h–113FFFh
SA76 01000101XXX 32/16 228000h–22FFFFh 114000h–117FFFh
SA77 01000110XXX 32/16 230000h–237FFFh 118000h–11BFFFh
SA78 01000111XXX 32/16 238000h–23FFFFh 11C000h–11FFFFh
SA79 01001000XXX 32/16 240000h–247FFFh 120000h–123FFFh
SA80 01001001XXX 32/16 248000h–24FFFFh 124000h–127FFFh
Table 5. Sector Address Table (Sheet 2 of 7)
Bank Sector
Sector Address
(A21-A11)
Sector Size
(Kwords/
Kdoublewords)
Address Range
(x16)
Address Range
(x32)
16 Am29PDL128G March 17, 2009
PRELIMINARY
Bank 2 (continued)
SA81 01001010XXX 32/16 250000h–257FFFh 128000h–12BFFFh
SA82 01001011XXX 32/16 258000h–25FFFFh 12C000h–12FFFFh
SA83 01001100XXX 32/16 260000h–267FFFh 130000h–133FFFh
SA84 01001101XXX 32/16 268000h–26FFFFh 134000h–137FFFh
SA85 01001110XXX 32/16 270000h–277FFFh 138000h–13BFFFh
SA86 01001111XXX 32/16 278000h–27FFFFh 13C000h–13FFFFh
SA87 01010000XXX 32/16 280000h–287FFFh 140000h–143FFFh
SA88 01010001XXX 32/16 288000h–28FFFFh 144000h–147FFFh
SA89 01010010XXX 32/16 290000h–297FFFh 148000h–14BFFFh
SA90 01010011XXX 32/16 298000h–29FFFFh 14C000h–14FFFFh
SA91 01010100XXX 32/16 2A0000h–2A7FFFh 150000h–153FFFh
SA92 01010101XXX 32/16 2A8000h–2AFFFFh 154000h–157FFFh
SA93 01010110XXX 32/16 2B0000h–2B7FFFh 158000h–15BFFFh
SA94 01010111XXX 32/16 2B8000h–2BFFFFh 15C000h–15FFFFh
SA95 01011000XXX 32/16 2C0000h–2C7FFFh 160000h–163FFFh
SA96 01011001XXX 32/16 2C8000h–2CFFFFh 164000h–167FFFh
SA97 01011010XXX 32/16 2D0000h–2D7FFFh 168000h–16BFFFh
SA98 01011011XXX 32/16 2D8000h–2DFFFFh 16C000h–16FFFFh
SA99 01011100XXX 32/16 2E0000h–2E7FFFh 170000h–173FFFh
SA100 01011101XXX 32/16 2E8000h–2EFFFFh 174000h–177FFFh
SA101 01011110XXX 32/16 2F0000h–2F7FFFh 178000h–17BFFFh
SA102 01011111XXX 32/16 2F8000h–2FFFFFh 17C000h–17FFFFh
SA103 01100000XXX 32/16 300000h–307FFFh 180000h–183FFFh
SA104 01100001XXX 32/16 308000h–30FFFFh 184000h–187FFFh
SA105 01100010XXX 32/16 310000h–317FFFh 188000h–18BFFFh
SA106 01100011XXX 32/16 318000h–31FFFFh 18C000h–18FFFFh
SA107 01100100XXX 32/16 320000h–327FFFh 190000h–193FFFh
SA108 01100101XXX 32/16 328000h–32FFFFh 194000h–197FFFh
SA109 01100110XXX 32/16 330000h–337FFFh 198000h–19BFFFh
SA110 01100111XXX 32/16 338000h–33FFFFh 19C000h–19FFFFh
SA111 01101000XXX 32/16 340000h–347FFFh 1A0000h–1A3FFFh
SA112 01101001XXX 32/16 348000h–34FFFFh 1A4000h–1A7FFFh
SA113 01101010XXX 32/16 350000h–357FFFh 1A8000h–1ABFFFh
SA114 01101011XXX 32/16 358000h–35FFFFh 1AC000h–1AFFFFh
SA115 01101100XXX 32/16 360000h–367FFFh 1B0000h–1B3FFFh
SA116 01101101XXX 32/16 368000h–36FFFFh 1B4000h–1B7FFFh
SA117 01101110XXX 32/16 370000h–377FFFh 1B8000h–1BBFFFh
SA118 01101111XXX 32/16 378000h–37FFFFh 1BC000h–1BFFFFh
SA119 01110000XXX 32/16 380000h–387FFFh 1C0000h–1C3FFFh
Table 5. Sector Address Table (Sheet 3 of 7)
Bank Sector
Sector Address
(A21-A11)
Sector Size
(Kwords/
Kdoublewords)
Address Range
(x16)
Address Range
(x32)
March 17, 2009 Am29PDL128G 17
PRELIMINARY
Bank 2 (continued)
SA120 01110001XXX 32/16 388000h–38FFFFh 1C4000h–1C7FFFh
SA121 01110010XXX 32/16 390000h–397FFFh 1C8000h–1CBFFFh
SA122 01110011XXX 32/16 398000h–39FFFFh 1CC000h–1CFFFFh
SA123 01110100XXX 32/16 3A0000h–3A7FFFh 1D0000h–1D3FFFh
SA124 01110101XXX 32/16 3A8000h–3AFFFFh 1D4000h–1D7FFFh
SA125 01110110XXX 32/16 3B0000h–3B7FFFh 1D8000h–1DBFFFh
SA126 01110111XXX 32/16 3B8000h–3BFFFFh 1DC000h–1DFFFFh
SA127 01111000XXX 32/16 3C0000h–3C7FFFh 1E0000h–1E3FFFh
SA128 01111001XXX 32/16 3C8000h–3CFFFFh 1E4000h–1E7FFFh
SA129 01111010XXX 32/16 3D0000h–3D7FFFh 1E8000h–1EBFFFh
SA130 01111011XXX 32/16 3D8000h–3DFFFFh 1EC000h–1EFFFFh
SA131 01111100XXX 32/16 3E0000h–3E7FFFh 1F0000h–1F3FFFh
SA132 01111101XXX 32/16 3E8000h–3EFFFFh 1F4000h–1F7FFFh
SA133 01111110XXX 32/16 3F0000h–3F7FFFh 1F8000h–1FBFFFh
SA134 01111111XXX 32/16 3F8000h–3FFFFFh 1FC000h–1FFFFFh
Bank 3
SA135 10000000XXX 32/16 400000h–407FFFh 200000h–203FFFh
SA136 10000001XXX 32/16 408000h–40FFFFh 204000h–207FFFh
SA137 10000010XXX 32/16 410000h–417FFFh 208000h–20BFFFh
SA138 10000011XXX 32/16 418000h–41FFFFh 20C000h–20FFFFh
SA139 10000100XXX 32/16 420000h–427FFFh 210000h–213FFFh
SA140 10000101XXX 32/16 428000h–42FFFFh 214000h–217FFFh
SA141 10000110XXX 32/16 430000h–437FFFh 218000h–21BFFFh
SA142 10000111XXX 32/16 438000h–43FFFFh 21C000h–21FFFFh
SA143 10001000XXX 32/16 440000h–447FFFh 220000h–223FFFh
SA144 10001001XXX 32/16 448000h–44FFFFh 224000h–227FFFh
SA145 10001010XXX 32/16 450000h–457FFFh 228000h–22BFFFh
SA146 10001011XXX 32/16 458000h–45FFFFh 22C000h–22FFFFh
SA147 10001100XXX 32/16 460000h–467FFFh 230000h–233FFFh
SA148 10001101XXX 32/16 468000h–46FFFFh 234000h–237FFFh
SA149 10001110XXX 32/16 470000h–477FFFh 238000h–23BFFFh
SA150 10001111XXX 32/16 478000h–47FFFFh 23C000h–23FFFFh
SA151 10010000XXX 32/16 480000h–487FFFh 240000h–243FFFh
SA152 10010001XXX 32/16 488000h–48FFFFh 244000h–247FFFh
SA153 10010010XXX 32/16 490000h–497FFFh 248000h–24BFFFh
SA154 10010011XXX 32/16 498000h–49FFFFh 24C000h–24FFFFh
SA155 10010100XXX 32/16 4A0000h–4A7FFFh 250000h–253FFFh
SA156 10010101XXX 32/16 4A8000h–4AFFFFh 254000h–257FFFh
SA157 10010110XXX 32/16 4B0000h–4B7FFFh 258000h–25BFFFh
SA158 10010111XXX 32/16 A48000h–4BFFFFh 25C000h–25FFFFh
Table 5. Sector Address Table (Sheet 4 of 7)
Bank Sector
Sector Address
(A21-A11)
Sector Size
(Kwords/
Kdoublewords)
Address Range
(x16)
Address Range
(x32)
18 Am29PDL128G March 17, 2009
PRELIMINARY
Bank 3 (continued)
SA159 10011000XXX 32/16 4C0000h–4C7FFFh 260000h–263FFFh
SA160 10011001XXX 32/16 4C8000h–4CFFFFh 264000h–267FFFh
SA161 10011010XXX 32/16 4D0000h–4D7FFFh 268000h–26BFFFh
SA162 10011011XXX 32/16 4D8000h–4DFFFFh 26C000h–26FFFFh
SA163 10011100XXX 32/16 4E0000h–4E7FFFh 270000h–273FFFh
SA164 10011101XXX 32/16 4E8000h–4EFFFFh 274000h–277FFFh
SA165 10011110XXX 32/16 4F0000h–4F7FFFh 278000h–27BFFFh
SA166 10011111XXX 32/16 4F8000h–4FFFFFh 27C000h–27FFFFh
SA167 10100000XXX 32/16 500000h–507FFFh 280000h–283FFFh
SA168 10100001XXX 32/16 508000h–50FFFFh 284000h–287FFFh
SA169 10100010XXX 32/16 510000h–517FFFh 288000h–28BFFFh
SA170 10100011XXX 32/16 518000h–51FFFFh 28C000h–28FFFFh
SA171 10100100XXX 32/16 520000h–527FFFh 290000h–293FFFh
SA172 10100101XXX 32/16 528000h–52FFFFh 294000h–297FFFh
SA173 10100110XXX 32/16 530000h–537FFFh 298000h–29BFFFh
SA174 10100111XXX 32/16 538000h–53FFFFh 29C000h–29FFFFh
SA175 10101000XXX 32/16 540000h–547FFFh 2A0000h–2A3FFFh
SA176 10101001XXX 32/16 548000h–54FFFFh 2A4000h–2A7FFFh
SA177 10101010XXX 32/16 550000h–557FFFh 2A8000h–2ABFFFh
SA178 10101011XXX 32/16 558000h–55FFFFh 2AC000h–2AFFFFh
SA179 10101100XXX 32/16 560000h–567FFFh 2B0000h–2B3FFFh
SA180 10101101XXX 32/16 568000h–56FFFFh 2B4000h–2B7FFFh
SA181 10101110XXX 32/16 570000h–577FFFh 2B8000h–2BBFFFh
SA182 10101111XXX 32/16 578000h–57FFFFh 2BC000h–2BFFFFh
SA183 10110000XXX 32/16 580000h–587FFFh 2C0000h–2C3FFFh
SA184 10110001XXX 32/16 588000h–58FFFFh 2C4000h–2C7FFFh
SA185 10110010XXX 32/16 590000h–597FFFh 2C8000h–2CBFFFh
SA186 10110011XXX 32/16 598000h–59FFFFh 2CC000h–2CFFFFh
SA187 10110100XXX 32/16 5A0000h–5A7FFFh 2D0000h–2D3FFFh
SA188 10110101XXX 32/16 5A8000h–5AFFFFh 2D4000h–2D7FFFh
SA189 10110110XXX 32/16 5B0000h–5B7FFFh 2D8000h–2DBFFFh
SA190 10110111XXX 32/16 5B8000h–5BFFFFh 2DC000h–2DFFFFh
SA191 10111000XXX 32/16 5C0000h–5C7FFFh 2E0000h–2E3FFFh
SA192 10111001XXX 32/16 5C8000h–5CFFFFh 2E4000h–2E7FFFh
SA193 10111010XXX 32/16 5D0000h–5D7FFFh 2E8000h–2EBFFFh
SA194 10111011XXX 32/16 5D8000h–5DFFFFh 2EC000h–2EFFFFh
SA195 10111100XXX 32/16 5E0000h–5E7FFFh 2F0000h–2F3FFFh
SA196 10111101XXX 32/16 5E8000h–5EFFFFh 2F4000h–2F7FFFh
SA197 10111110XXX 32/16 5F0000h–5F7FFFh 2F8000h–2FBFFFh
Table 5. Sector Address Table (Sheet 5 of 7)
Bank Sector
Sector Address
(A21-A11)
Sector Size
(Kwords/
Kdoublewords)
Address Range
(x16)
Address Range
(x32)
March 17, 2009 Am29PDL128G 19
PRELIMINARY
Bank 3 (continued)
SA198 10111111XXX 32/16 5F8000h–5FFFFFh 2FC000h–2FFFFFh
SA199 11000000XXX 32/16 600000h–607FFFh 300000h–303FFFh
SA200 11000001XXX 32/16 608000h–60FFFFh 304000h–307FFFh
SA201 11000010XXX 32/16 610000h–617FFFh 308000h–30BFFFh
SA202 11000011XXX 32/16 618000h–61FFFFh 30C000h–30FFFFh
SA203 11000100XXX 32/16 620000h–627FFFh 310000h–313FFFh
SA204 11000101XXX 32/16 628000h–62FFFFh 314000h–317FFFh
SA205 11000110XXX 32/16 630000h–637FFFh 318000h–31BFFFh
SA206 11000111XXX 32/16 638000h–63FFFFh 31C000h–31FFFFh
SA207 11001000XXX 32/16 640000h–647FFFh 320000h–323FFFh
SA208 11001001XXX 32/16 648000h–64FFFFh 324000h–327FFFh
SA209 11001010XXX 32/16 650000h–657FFFh 328000h–32BFFFh
SA210 11001011XXX 32/16 658000h–65FFFFh 32C000h–32FFFFh
SA211 11001100XXX 32/16 660000h–667FFFh 330000h–333FFFh
SA212 11001101XXX 32/16 668000h–66FFFFh 334000h–337FFFh
SA213 11001110XXX 32/16 670000h–677FFFh 338000h–33BFFFh
SA214 11001111XXX 32/16 678000h–67FFFFh 33C000h–33FFFFh
SA215 11010000XXX 32/16 680000h–687FFFh 340000h–343FFFh
SA216 11010001XXX 32/16 688000h–68FFFFh 344000h–347FFFh
SA217 11010010XXX 32/16 690000h–697FFFh 348000h–34BFFFh
SA218 11010011XXX 32/16 698000h–69FFFFh 34C000h–34FFFFh
SA219 11010100XXX 32/16 6A0000h–6A7FFFh 350000h–353FFFh
SA220 11010101XXX 32/16 6A8000h–6AFFFFh 354000h–357FFFh
SA221 11010110XXX 32/16 6B0000h–6B7FFFh 358000h–35BFFFh
SA222 11010111XXX 32/16 6B8000h–6BFFFFh 35C000h–35FFFFh
SA223 11011000XXX 32/16 6C0000h–6C7FFFh 360000h–363FFFh
SA224 11011001XXX 32/16 6C8000h–6CFFFFh 364000h–367FFFh
SA225 11011010XXX 32/16 6D0000h–6D7FFFh 368000h–36BFFFh
SA226 11011011XXX 32/16 6D8000h–6DFFFFh 36C000h–36FFFFh
SA227 11011100XXX 32/16 6E0000h–6E7FFFh 370000h–373FFFh
SA228 11011101XXX 32/16 6E8000h–6EFFFFh 374000h–377FFFh
SA229 11011110XXX 32/16 6F0000h–6F7FFFh 378000h–37BFFFh
SA230 11011111XXX 32/16 6F8000h–6FFFFFh 37C000h–37FFFFh
Table 5. Sector Address Table (Sheet 6 of 7)
Bank Sector
Sector Address
(A21-A11)
Sector Size
(Kwords/
Kdoublewords)
Address Range
(x16)
Address Range
(x32)