1.5 On Resistance, 15 V/12 V/5 V, iCMOS, Dual SPDT Switch ADG1436 FEATURES FUNCTIONAL BLOCK DIAGRAMS 1.5 on resistance 0.3 on-resistance flatness 0.1 on-resistance match between channels Continuous current per channel LFCSP package: up to 400 mA TSSOP package: up to 260 mA Fully specified at +12 V, 15 V, and 5 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 16-lead TSSOP and 4 mm x 4 mm, 16-lead LFCSP packages ADG1436 S1A D1 S1B IN1 IN2 S2A D2 APPLICATIONS SWITCHES SHOWN FOR A ONE-INPUT LOGIC. Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Communication systems Relay replacement 06817-001 S2B Figure 1. TSSOP Package ADG1436 S1A S2A D2 D1 S2B S1B IN1 IN2 EN SWITCHES SHOWN FOR A ONE-INPUT LOGIC. 06817-002 LOGIC Figure 2. LFCSP Package GENERAL DESCRIPTION The ADG1436 is a monolithic CMOS device containing two independently selectable SPDT switches. An EN input on the LFCSP package is used to enable or disable the device. When disabled, all channels are switched off. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. Both switches exhibit break-before-make switching action for use in multiplexer applications. The ADG1436 is designed on an iCMOS(R) process. iCMOS (industrial-CMOS) is a modular manufacturing process combining high voltage CMOS (complementary metal-oxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. iCMOS construction ensures ultralow power dissipation, making the part ideally suited for portable and battery-powered instruments. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 2.6 maximum on resistance over temperature. Minimum distortion. Ultralow power dissipation: <0.03 W. 16-lead TSSOP and 16-lead 4 mm x 4 mm LFCSP packages. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008-2009 Analog Devices, Inc. All rights reserved. ADG1436 TABLE OF CONTENTS Features .............................................................................................. 1 Continuous Current per Channel ...............................................6 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................7 Functional Block Diagrams ............................................................. 1 ESD Caution...................................................................................7 General Description ......................................................................... 1 Pin Configurations and Function Descriptions ............................8 Product Highlights ........................................................................... 1 Truth Table For Switches ..............................................................8 Revision History ............................................................................... 2 Typical Performance Characteristics ..............................................9 Specifications..................................................................................... 3 Terminology .................................................................................... 12 15 V Dual Supply .......................................................................... 3 Test Circuits ..................................................................................... 13 12 V Single Supply ........................................................................ 4 Outline Dimensions ....................................................................... 16 5 V Dual Supply ............................................................................ 5 Ordering Guide .......................................................................... 16 REVISION HISTORY 3/09--Rev. 0 to Rev. A Change to IDD Parameter, Table 1 ................................................... 3 Change to IDD Parameter, Table 2 ................................................... 4 7/08--Revision 0: Initial Version Rev. A | Page 2 of 16 ADG1436 SPECIFICATIONS 15 V DUAL SUPPLY VDD = 15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25C 1.5 1.8 0.1 0.18 0.28 0.36 0.04 0.55 0.04 0.55 0.1 2 -40C to +85C -40C to +125C Unit Test Conditions/Comments VDD to VSS V typ max typ VS = 10 V, IS = -10 mA; see Figure 23 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -10 mA 2.3 2.6 0.19 0.21 0.4 0.45 2 12.5 2 12.5 4 35 2.0 0.8 0.005 0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 3.5 nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ Break-Before-Make Time Delay, tBBM 125 170 95 120 105 130 20 Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -20 -80 -80 0.011 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ 110 -0.18 23 50 120 MHz typ dB typ pF typ pF typ pF typ tON (EN) tOFF (EN) 215 245 140 155 150 170 10 -3 dB Bandwidth Insertion Loss CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD 0.001 1 IDD 170 285 ISS 0.001 VDD/VSS 1 max typ max 1.0 4.5/16.5 Guaranteed by design, not subject to production test. Rev. A | Page 3 of 16 A typ A max A typ A max A typ A max V min/max VS = 10 V, IS = -10 mA VDD = +16.5 V, VSS = -16.5 V VS = 10 V, VS = 10 V; see Figure 24 VS = 10 V, VS = 10 V; see Figure 24 VS = VD = 10 V; see Figure 25 VIN = VGND or VDD RL = 300 , CL = 35 pF VS = +10 V; see Figure 30 RL = 300 , CL = 35 pF VS = 10 V; see Figure 30 RL = 300 , CL = 35 pF VS = 10 V; see Figure 30 RL = 300 , CL = 35 pF VS1 = VS2 = +10 V; see Figure 31 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 33 RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 26 RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 27 RL = 110 , 15 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 , CL = 5 pF; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28 f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V f = 1 MHz, VS = 0 V VDD = +16.5 V, VSS = -16.5 V Digital Inputs = 0 V or VDD Digital Input = 5 V Digital Inputs = 0 V, 5 V, or VDD GND = 0 V ADG1436 12 V SINGLE SUPPLY VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25C 2.8 3.5 0.13 0.21 0.6 1.1 0.04 0.55 0.04 0.55 0.1 1 -40C to +85C -40C to +125C Unit Test Conditions/Comments 0 V to VDD V typ max typ VS = 0 V to 10 V, IS = -10 mA; see Figure 23 VDD = +10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -10 mA 4.3 4.8 0.23 0.25 1.2 1.3 2 12.5 2 12.5 4 35 2.0 0.8 0.001 0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 3.5 nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ Break-Before-Make Time Delay, tBBM 200 270 175 235 105 145 70 Charge Injection Off Isolation 30 -80 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ Channel-to-Channel Crosstalk -80 dB typ 78 -0.3 40 80 140 MHz typ dB typ pF typ pF typ pF typ tON (EN) tOFF (EN) 320 350 280 310 175 195 10 -3 dB Bandwidth Insertion Loss CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD 0.001 1.0 IDD 170 VDD 1 max typ max 285 5/16.5 Guaranteed by design, not subject to production test. Rev. A | Page 4 of 16 A typ A max A typ A max V min/max VS = 0 V to 10 V, IS = -10 mA VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24 VS = VD = 1 V or 10 V; see Figure 25 VIN = VGND or VDD RL = 300 , CL = 35 pF VS = 8 V; see Figure 30 RL = 300 , CL = 35 pF VS = 8 V; see Figure 30 RL = 300 , CL = 35 pF VS = 8 V; see Figure 30 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; see Figure 31 VS = 6 V, RS = 0 , CL = 1 nF; see Figure 33 RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 26; RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 27 RL = 50 , CL = 5 pF; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28 f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V f = 1 MHz, VS = 6 V VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V GND = 0 V, VSS = 0 V ADG1436 5 V DUAL SUPPLY VDD = 5 V 10%, VSS = -5 V 10%, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25C 3.3 4 0.13 0.22 0.9 1.1 -40C to +85C -40C to +125C Unit Test Conditions/Comments VDD to VSS V typ max typ VS = 4.5 V, IS = -10 mA; see Figure 23 VDD = +4.5 V, VSS = -4.5 V VS = 4.5 V, IS = -10 mA 4.9 5.4 0.23 0.25 1.24 1.31 nA typ 1 12.5 nA max nA typ 0.2 0.05 0.25 1 12.5 VS = VD = 4.5V; see Figure 25 1.5 35 nA max nA typ nA max V min V max A typ A max pF typ VIN = VGND or VDD 2.0 0.8 0.001 3.5 Break-Before-Make Time Delay, tBBM Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise 30 -80 -80 0.03 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ -3 dB Bandwidth 85 -0.28 33 65 145 MHz typ dB typ pF typ pF typ pF typ tOFF (EN) 510 565 415 460 355 400 10 Insertion Loss CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD 0.001 1.0 ISS 0.001 VDD/VSS 1 VS = 4.5 V, VD = 4.5 V; see Figure 24 0.2 0.03 310 445 255 355 215 305 80 tON (EN) VS = 4.5 V, IS = -10 mA VDD = +5.5 V, VSS = -5.5 V 0.03 0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION max typ max 1.0 4.5/16.5 Guaranteed by design, not subject to production test. Rev. A | Page 5 of 16 A typ A max A typ A max V min/max VS = 4.5 V, VD = 4.5 V; see Figure 24 RL = 300 , CL = 35 pF VS = 3 V; see Figure 30 RL = 300 , CL = 35 pF VS = 3 V; see Figure 30 RL = 300 , CL = 35 pF VS = 3 V; see Figure 30 RL = 300 , CL = 35 pF VS1 = VS2 = 3 V; see Figure 31 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 33 RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 26 RL = 50 , CL = 5 pF, f = 100 kHz; see Figure 27 RL = 110 , 2.5 V pp, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 , CL = 5 pF; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 28 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +5.5 V, VSS = -5.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V ADG1436 CONTINUOUS CURRENT PER CHANNEL Table 4. Parameter CONTINUOUS CURRENT PER CHANNEL 1 15 V Dual Supply ADG1436 TSSOP ADG1436 LFCSP 12 V Single Supply ADG1436 TSSOP ADG1436 LFCSP 5 V Dual Supply ADG1436 TSSOP ADG1436 LFCSP 1 25C 85C 125C Unit 260 400 170 250 100 120 mA max mA max 240 350 160 240 100 120 mA max mA max 240 300 160 240 100 120 mA max mA max Test Conditions/Comments VDD = +13.5 V, VSS = -13.5 V VDD = 10.8 V, VSS = 0 V VDD = +4.5 V, VSS = -4.5 V Guaranteed by design, not subject to production test. Rev. A | Page 6 of 16 ADG1436 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 5. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs 1 Digital Inputs1 Peak Current, S or D Continuous Current per Channel, S or D 2 Operating Temperature Range Automotive (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP, JA Thermal Impedance (4-Layer Board) 16-Lead LFCSP, JA Thermal Impedance Reflow Soldering Peak Temperature, Pb Free Ratings 35 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 600 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION -40C to +125C -65C to +150C 150C 112C/W 30.4C/W 260(+0/-5)C 1 Over voltages at IN, S, and D are clamped by internal diodes. Current should be limited to the maximum ratings given. 2 See data given in Table 4. Rev. A | Page 7 of 16 ADG1436 14 NC S1B 2 ADG1436 13 VDD TOP VIEW VSS 5 (Not to Scale) 12 S2B VSS 3 S1B 4 D2 NC 7 10 S2A NC 8 9 IN2 NC = NO CONNECT 14 NC 13 NC 12 EN ADG1436 11 VDD TOP VIEW (Not to Scale) 9 D2 NC 5 11 GND 4 10 S2B NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. 2. NC = NO CONNECT. 06817-003 GND 6 PIN 1 INDICATOR D1 1 06817-004 NC D1 3 S2A 8 NC 15 NC 7 16 IN2 6 IN1 1 S1A 2 15 IN1 16 S1A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. LFCSP Pin Configuration Figure 3.TSSOP Pin Configuration Table 6. Pin Function Descriptions Pin No. TSSOP LFCSP 1 15 2 16 3 1 4 2 5 3 6 4 7, 8, 14 to 16 5, 7, 13, 14 9 6 10 8 11 9 12 10 13 11 N/A 12 Mnemonic IN1 S1A D1 S1B VSS GND NC IN2 S2A D2 S2B VDD EN Function Logic Control Input. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. Most Negative Power Supply Potential. Ground (0 V) Reference. No Connect. Logic Control Input. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. Most Positive Power Supply Potential. Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When this pin is high, INx logic inputs determine the on switches. TRUTH TABLE FOR SWITCHES Table 7. ADG1436 TSSOP Truth Table INx 0 1 SxA Off On SxB On Off Table 8. ADG1436 LFCSP Truth Table EN 0 1 1 INx X 0 1 SxA Off Off On Rev. A | Page 8 of 16 SxB Off On Off ADG1436 TYPICAL PERFORMANCE CHARACTERISTICS 2.5 3.0 VDD = +10V, VSS = -10V 2.5 1.5 VDD = +13.5V, VSS = -13.5V 1.0 VDD = +16.5V, VSS = -16.5V VDD = +15V, VSS = -15V 0.5 TA = +85C 1.5 TA = +25C TA = -40C 1.0 0.5 TA = 25C IS = -10mA -12.5 -8.5 -4.5 -0.5 3.5 11.5 7.5 15.5 VS OR VD (V) Figure 5. On Resistance vs. VD or VS, Dual Supply 4.0 5 10 15 4.5 ON RESISTANCE () 4.0 VDD = +7V, VSS = -7V VDD = +5.5V, VSS = -5.5V 1.5 0 5.0 2.5 2.0 -5 Figure 8. On Resistance vs. VD or VS for Different Temperatures, 15 V Dual Supply VDD = +5V, VSS = -5V 3.0 -10 VS OR VD (V) VDD = +4.5V, VSS = -4.5V 3.5 VDD = +15V VSS = -15V IS = -10mA 0 -15 06815-104 0 -16.5 ON RESISTANCE () TA = +125C 2.0 06815-107 VDD = +12V, VSS = -12V ON RESISTANCE () ON RESISTANCE () 2.0 TA = +125C 3.5 TA = +85C 3.0 TA = +25C 2.5 2.0 TA = -40C 1.5 1.0 1.0 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 VS OR VD (V) 7 0 -5 Figure 6. On Resistance vs. VD or VS, Dual Supply -4 -3 -2 -1 0 1 2 3 4 5 VS OR VD (V) Figure 9. On Resistance vs. VD or VS for Different Temperatures, 5 V Dual Supply 7 4.5 VDD = 5V, VSS = 0V 4.0 VDD = 10.8V, VSS = 0V VDD = 8V, VSS = 0V 4 ON RESISTANCE () 5 VDD = 12V, VSS = 0V 3 2 VDD = 13.2V, VSS = 0V TA = 25C IS = -10mA 0 0 2 4 6 8 10 12 VS OR VD (V) Figure 7. On Resistance vs. VD or VS, Single Supply 14 TA = +125C 3.0 TA = +85C 2.5 TA = +25C 2.0 TA = -40C 1.5 1.0 VDD = 15V, VSS = 0V VDD = 12V VSS = 0V IS = -10mA 0.5 0 06815-106 1 3.5 0 2 4 6 VS OR VD (V) 8 10 12 06815-109 6 ON RESISTANCE () VDD = +5V VSS = -5V IS = -10mA 06815-108 0 -7 0.5 TA = 25C IS = -10mA 06815-105 0.5 Figure 10. On Resistance vs. VD or VS for Different Temperatures, Single Supply Rev. A | Page 9 of 16 ADG1436 2 80 1 70 60 -1 IS (OFF) + - ID (OFF) + - IS (OFF) - + ID (OFF) - + ID, IS (ON) + + ID, IS (ON) - - -2 -3 -4 50 IDD (A) 40 VDD = +15V VSS = -15V VDD = +12V VSS = 0V 30 20 -5 VDD = +15V VSS = -15V VBIAS = +10V/-10V -7 0 20 40 10 60 80 100 120 TEMPERATURE (C) VDD = +5V VSS = -5V 0 06817-111 -6 0 2 4 6 8 10 12 06817-008 LEAKAGE (nA) 0 TA = 25C IDD PER LOGIC INPUT 14 LOGIC, Ax (V) Figure 11. Leakage Currents vs. Temperature, 15 V Dual Supply Figure 14. IDD vs. Logic Level 1.5 600 TA = 25C 1.0 400 CHARGE INJECTION (pC) 0 IS (OFF) + - ID (OFF) + - IS (OFF) - + ID (OFF) - + ID, IS (ON) + + ID, IS (ON) - - -1.5 -2.5 0 20 40 VDD = +5V, VSS = -5V 0 VDD = +12V, VSS = 0V -200 -400 VDD = +5V VSS = -5V VBIAS = +4.5V/-4.5V -2.0 200 60 80 100 120 TEMPERATURE (C) -600 -15 450 7 400 6 5 TIME (ns) 200 VDD = +15V VSS = -15V 100 0 VDD = 12V VSS = 0V VBIAS = 1V/10V 0 20 50 40 60 80 100 120 TEMPERATURE (C) 06817-112 -2 15 VDD = +12V VSS = 0V 250 150 1 -1 10 300 IS (OFF) + - ID (OFF) + - IS (OFF) - + ID (OFF) - + ID, IS (ON) + + ID, IS (ON) - - 2 5 VDD = +5V VSS = -5V 350 3 0 Figure 15. Charge Injection vs. Source Voltage 8 4 -5 VS (V) Figure 12. Leakage Currents vs. Temperature, 5 V Dual Supply LEAKAGE (nA) -10 06817-012 -1.0 VDD = +15V, VSS = -15V Figure 13. Leakage Currents vs. Temperature, 12 V Single Supply 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 16. tTRANSITION Time vs. Temperature Rev. A | Page 10 of 16 120 06817-217 -0.5 06817-113 LEAKAGE (nA) 0.5 ADG1436 0 0 VDD = +15V VSS = -15V TA = 25C -10 -20 VDD = +15V VSS = -15V V p-p = 0.63V TA = 25C -30 -40 -50 -60 -40 -60 -70 -70 -80 -80 -90 -90 -100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) NO DECOUPLING CAPACITORS -50 DECOUPLING CAPACITORS ON SUPPLIES -100 1k 10k Figure 17. Off Isolation vs. Frequency 0 -20 100k 1M 10M FREQUENCY (Hz) 06817-017 ACPSRR (dB) -30 06817-014 OFF ISOLATION (dB) -20 -10 Figure 20. ACPSRR vs. Frequency 0.024 VDD = +15V VSS = -15V TA = 25C 0.022 0.020 VS = 20V p-p VDD = +15V VSS = -15V TA = 25C CHANNEL-TO-CHANNEL (SxA TO SxB) THD + N (%) CROSSTALK (dB) 0.018 -40 -60 -80 0.014 VS = 15V p-p 0.012 0.010 0.008 MUX-TO-MUX (S1x TO S2x) -100 0.016 VS = 10V p-p 0.006 100k 1M 10M 100M FREQUENCY (Hz) 0.002 10 06817-019 10k 0 10k 100k Figure 21. THD + N vs. Frequency, 15 V Dual Supply 1 VDD = +15V VSS = -15V TA = 25C VDD = +5V VSS = -5V TA = 25C -1.0 VS = 10V p-p -1.5 0.1 THD + N (%) -2.0 -2.5 -3.0 VS = 5V p-p 0.01 -3.5 VS = 2.5V p-p -4.0 -5.0 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 1G Figure 19. On Response vs. Frequency 0.001 10 100 1k 10k FREQUENCY (Hz) Figure 22. THD + N vs. Frequency, 5 V Dual Supply Rev. A | Page 11 of 16 100k 06817-118 -4.5 06817-020 INSERTION LOSS (dB) 1k FREQUENCY (Hz) Figure 18. Crosstalk vs. Frequency -0.5 100 06817-117 0.004 -120 1k ADG1436 TERMINOLOGY CD (Off) The off-switch drain capacitance, which is measured with reference to ground. IDD The positive supply current. ISS The negative supply current. VD, VS The analog voltage on Terminal D and Terminal S. CD, CS (On) The on-switch capacitance, which is measured with reference to ground. RON The ohmic resistance between Terminal D and Terminal S. CIN The digital input capacitance. RFLAT(ON) Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. tTRANSITION The delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another. IS (Off) The source leakage current with the switch off. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. VINH The minimum input voltage for Logic 1. IINL, IINH The input current of the digital input. CS (Off) The off-switch source capacitance, which is measured with reference to ground. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. Rev. A | Page 12 of 16 ADG1436 TEST CIRCUITS VDD VSS 0.1F 0.1F VDD SxA INx NETWORK ANALYZER VSS NC SxB 50 50 VS Dx V VIN SxA/SxB Dx RL 50 GND VOUT 06817-023 OFF ISOLATION = 20 log 06817-030 IDS VS VOUT VS Figure 26. Off Isolation Figure 23. On Resistance VDD VSS 0.1F 0.1F VDD SxA INx NETWORK ANALYZER VSS NC SxB 50 50 VS Dx Dx GND A VD VS RL 50 INSERTION LOSS = 20 log VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 27. Channel-to-Channel Crosstalk Figure 24. Off Leakage VDD VSS 0.1F 0.1F NETWORK ANALYZER VOUT VDD SxA VSS RL 50 SxB VS Dx NC = NO CONNECT R 50 GND A VD 06817-025 SxA/SxB Dx INx ID (ON) NC VOUT 06817-031 SxA/SxB 06817-024 A VIN ID (OFF) CHANNEL-TO-CHANNEL CROSSTALK = 20 log Figure 25. On Leakage VOUT VS Figure 28. Bandwidth Rev. A | Page 13 of 16 06817-032 IS (OFF) ADG1436 VDD VSS 0.1F 0.1F AUDIO PRECISION VDD VSS RS SxA/SxB INx VS V p-p Dx VIN RL 110 06817-033 GND VOUT Figure 29. THD + Noise VDD VSS VIN 50% 50% VIN 50% 50% VSS VDD SxB VS 0.1F Dx SxA VOUT RL 300 INx CL 35pF 90% VOUT GND VIN 90% tON tOFF 06817-026 0.1F Figure 30. Switching Times 0.1F VS VDD VSS VDD VSS SxB 0.1F VIN Dx VOUT SxA RL 300 INx VOUT 80% tBBM GND tBBM 06817-027 VIN CL 35pF Figure 31. Break-Before-Make Time Delay Rev. A | Page 14 of 16 ADG1436 3V ENABLE DRIVE (VIN) 50% 50% VDD VSS VDD VSS INx SxA VS SxB 0V tON (EN) tOFF (EN) 0.9VOUT OUTPUT 0.9VOUT Dx EN OUTPUT VIN 50 300 35pF 06817-028 GND Figure 32. Enable Delay, tON (EN), tOFF (EN) VS VDD VSS VDD VSS VIN (NORMALLY CLOSED SWITCH) SxB Dx SxA INx VIN 0.1F GND ON OFF NC VOUT CL 1nF VIN (NORMALLY OPEN SWITCH) VOUT VOUT Figure 33. Charge Injection Rev. A | Page 15 of 16 QINJ = CL x VOUT 06817-029 0.1F ADG1436 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8 0 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 4.00 BSC SQ 0.60 MAX 12 13 3.75 BSC SQ TOP VIEW 12 MAX 1.00 0.85 0.80 SEATING 0.30 PLANE 0.23 0.18 1 16 EXPOSED PAD 0.65 BSC 4 8 9 PIN 1 INDICATOR 2.65 2.50 SQ 2.35 5 0.25 MIN 1.95 BCS 0.80 MAX 0.65 TYP BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.20 REF 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGC. 031006-A PIN 1 INDICATOR 0.50 0.40 0.30 Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-16-13) Dimensions shown in millimeters ORDERING GUIDE Model ADG1436YRUZ 1 ADG1436YRUZ-REEL71 ADG1436YCPZ-REEL1 ADG1436YCPZ-REEL71 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Thin Shrink Small Outline Package (TSSOP) 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Z = RoHS Compliant Part. (c)2008-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06817-0-3/09(A) Rev. A | Page 16 of 16 Package Option RU-16 RU-16 CP-16-13 CP-16-13