1.5 Ω On Resistance,
±15 V/12 V/±5 V, iCMOS, Dual SPDT Switch
ADG1436
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.
FEATURES
1.5 Ω on resistance
0.3 Ω on-resistance flatness
0.1 Ω on-resistance match between channels
Continuous current per channel
LFCSP package: up to 400 mA
TSSOP package: up to 260 mA
Fully specified at +12 V, ±15 V, and ±5 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 4 mm × 4 mm, 16-lead LFCSP packages
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Communication systems
Relay replacement
FUNCTIONAL BLOCK DIAGRAMS
ADG1436
S1A
S1B
IN1
S2A
S2B
IN2
D1
D2
SWITCHES SHOWN FOR A ONE-INPUT LOGIC.
06817-001
Figure 1. TSSOP Package
ADG1436
S2A
D2
S2B
S1A
D1
S1B
IN2 ENIN1
LOGIC
SWITCHES SHOWN FOR A ONE-INPUT LOGIC.
06817-002
Figure 2. LFCSP Package
GENERAL DESCRIPTION
The ADG1436 is a monolithic CMOS device containing two
independently selectable SPDT switches. An EN input on the
LFCSP package is used to enable or disable the device. When
disabled, all channels are switched off. Each switch conducts
equally well in both directions when on and has an input signal
range that extends to the supplies. In the off condition, signal
levels up to the supplies are blocked. Both switches exhibit
break-before-make switching action for use in multiplexer
applications.
The ADG1436 is designed on an iCMOS® process. iCMOS
(industrial-CMOS) is a modular manufacturing process combining
high voltage CMOS (complementary metal-oxide semiconductor)
and bipolar technologies. It enables the development of a wide
range of high performance analog ICs capable of 33 V operation
in a footprint that no previous generation of high voltage parts
has been able to achieve. Unlike analog ICs using conventional
CMOS processes, iCMOS components can tolerate high supply
voltages while providing increased performance, dramatically
lower power consumption, and reduced package size.
The on-resistance profile is very flat over the full analog input
range, ensuring excellent linearity and low distortion when
switching audio signals. iCMOS construction ensures ultralow
power dissipation, making the part ideally suited for portable
and battery-powered instruments.
PRODUCT HIGHLIGHTS
1. 2.6 Ω maximum on resistance over temperature.
2. Minimum distortion.
3. Ultralow power dissipation: <0.03 μW.
4. 16-lead TSSOP and 16-lead 4 mm × 4 mm LFCSP packages.
ADG1436
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
15 V Dual Supply .......................................................................... 3
12 V Single Supply ........................................................................ 4
5 V Dual Supply ............................................................................ 5
Continuous Current per Channel ...............................................6
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions ............................8
Truth Table For Switches ..............................................................8
Typical Performance Characteristics ..............................................9
Terminology .................................................................................... 12
Test Circuits ..................................................................................... 13
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
3/09—Rev. 0 to Rev. A
Change to IDD Parameter, Table 1 ................................................... 3
Change to IDD Parameter, Table 2 ................................................... 4
7/08—Revision 0: Initial Version
ADG1436
Rev. A | Page 3 of 16
SPECIFICATIONS
15 V DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance (RON) 1.5 Ω typ VS = ±10 V, IS = −10 mA; see Figure 23
1.8 2.3 2.6 Ω max VDD = +13.5 V, VSS = −13.5 V
On-Resistance Match
Between Channels (∆RON)
0.1 Ω typ VS = ±10 V, IS = −10 mA
0.18 0.19 0.21 Ω max
On-Resistance Flatness (RFLAT(ON)) 0.28 Ω typ VS = ±10 V, IS = −10 mA
0.36 0.4 0.45 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off) ±0.04 nA typ VS = ±10 V, VS = ±10 V; see Figure 24
±0.55 ±2 ±12.5 nA max
Drain Off Leakage, ID (Off) ±0.04 nA typ VS = ±10 V, VS = ±10 V; see Figure 24
±0.55 ±2 ±12.5 nA max
Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = ±10 V; see Figure 25
±2 ±4 ±35 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.005 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 3.5 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 125 ns typ RL = 300 Ω, CL = 35 pF
170 215 245 ns max VS = +10 V; see Figure 30
tON (EN) 95 ns typ RL = 300 Ω, CL = 35 pF
120 140 155 ns max VS = 10 V; see Figure 30
tOFF (EN) 105 ns typ RL = 300 Ω, CL = 35 pF
130 150 170 ns max VS = 10 V; see Figure 30
Break-Before-Make Time Delay, tBBM 20 ns typ RL = 300 Ω, CL = 35 pF
10 ns min VS1 = VS2 = +10 V; see Figure 31
Charge Injection −20 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33
Off Isolation −80 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 26
Channel-to-Channel Crosstalk −80 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27
Total Harmonic Distortion + Noise 0.011 % typ RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz; see
Figure 29
−3 dB Bandwidth 110 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 28
Insertion Loss −0.18 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
CS (Off) 23 pF typ f = 1 MHz, VS = 0 V
CD (Off) 50 pF typ f = 1 MHz, VS = 0 V
CD, CS (On) 120 pF typ f = 1 MHz, VS = 0 V
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
IDD 0.001 μA typ Digital Inputs = 0 V or VDD
1 μA max
IDD 170 μA typ Digital Input = 5 V
285 μA max
ISS 0.001 μA typ Digital Inputs = 0 V, 5 V, or VDD
1.0 μA max
VDD/VSS ±4.5/±16.5 V min/max GND = 0 V
1 Guaranteed by design, not subject to production test.
ADG1436
Rev. A | Page 4 of 16
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance (RON) 2.8 Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 23
3.5 4.3 4.8 Ω max VDD = +10.8 V, VSS = 0 V
On-Resistance Match
Between Channels (∆RON)
0.13 Ω typ VS = 0 V to 10 V, IS = −10 mA
0.21 0.23 0.25 Ω max
On-Resistance Flatness (RFLAT(ON)) 0.6 Ω typ VS = 0 V to 10 V, IS = −10 mA
1.1 1.2 1.3 Ω max
LEAKAGE CURRENTS
VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.04 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
±0.55 ±2 ±12.5
nA max
Drain Off Leakage, ID (Off) ±0.04 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
±0.55 ±2 ±12.5
nA max
Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = 1 V or 10 V; see Figure 25
±1 ±4 ±35 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.001
μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 3.5
pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 200 ns typ RL = 300 Ω, CL = 35 pF
270 320 350 ns max VS = 8 V; see Figure 30
tON (EN) 175 ns typ RL = 300 Ω, CL = 35 pF
235 280 310 ns max VS = 8 V; see Figure 30
tOFF (EN) 105 ns typ RL = 300 Ω, CL = 35 pF
145 175 195 ns max VS = 8 V; see Figure 30
Break-Before-Make Time Delay, tBBM 70 ns typ RL = 300 Ω, CL = 35 pF
10 ns min VS1 = VS2 = 8 V; see Figure 31
Charge Injection 30 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 33
Off Isolation −80 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see
Figure 26;
Channel-to-Channel Crosstalk −80 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see
Figure 27
−3 dB Bandwidth 78 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 28
Insertion Loss −0.3 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
CS (Off) 40 pF typ f = 1 MHz, VS = 6 V
CD (Off) 80 pF typ f = 1 MHz, VS = 6 V
CD, CS (On) 140 pF typ f = 1 MHz, VS = 6 V
POWER REQUIREMENTS VDD = 13.2 V
IDD 0.001
μA typ Digital inputs = 0 V or VDD
1.0 μA max
IDD 170
μA typ Digital inputs = 5 V
285 μA max
VDD 5/16.5 V min/max GND = 0 V, VSS = 0 V
1 Guaranteed by design, not subject to production test.
ADG1436
Rev. A | Page 5 of 16
5 V DUAL SUPPLY
VDD = 5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 3.
Parameter 25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance (RON) 3.3 Ω typ VS = ±4.5 V, IS = −10 mA; see Figure 23
4 4.9 5.4 Ω max VDD = +4.5 V, VSS = −4.5 V
On-Resistance Match
Between Channels (∆RON)
0.13 Ω typ VS = ±4.5 V, IS = −10 mA
0.22 0.23 0.25 Ω max
On-Resistance Flatness (RFLAT(ON)) 0.9 Ω typ VS = ±4.5 V, IS = −10 mA
1.1 1.24 1.31 Ω max
LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V
Source Off Leakage, IS (Off) ±0.03 nA typ VS = ±4.5 V, VD = ∓4.5 V; see Figure 24
±0.2
±1 ±12.5
nA max
Drain Off Leakage, ID (Off) ±0.03 nA typ VS = ±4.5 V, VD = ∓4.5 V; see Figure 24
±0.2
±1 ±12.5
nA max
Channel On Leakage, ID, IS (On) ±0.05 nA typ VS = VD = ±4.5V; see Figure 25
±0.25
±1.5 ±35 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.001 μA typ VIN = VGND or VDD
±0.1 μA max
Digital Input Capacitance, CIN 3.5 pF typ
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 310 ns typ RL = 300 Ω, CL = 35 pF
445 510 565 ns max VS = 3 V; see Figure 30
tON (EN) 255 ns typ RL = 300 Ω, CL = 35 pF
355 415 460 ns max VS = 3 V; see Figure 30
tOFF (EN) 215 ns typ RL = 300 Ω, CL = 35 pF
305 355 400 ns max VS = 3 V; see Figure 30
Break-Before-Make Time Delay, tBBM 80 ns typ RL = 300 Ω, CL = 35 pF
10 ns min VS1 = VS2 = 3 V; see Figure 31
Charge Injection 30 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33
Off Isolation −80 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 26
Channel-to-Channel Crosstalk −80 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 27
Total Harmonic Distortion + Noise 0.03 % typ RL = 110 Ω, 2.5 V pp, f = 20 Hz to 20 kHz; see
Figure 29
−3 dB Bandwidth 85 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 28
Insertion Loss −0.28 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
CS (Off) 33 pF typ VS = 0 V, f = 1 MHz
CD (Off) 65 pF typ VS = 0 V, f = 1 MHz
CD, CS (On) 145 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V
IDD 0.001 μA typ Digital inputs = 0 V or VDD
1.0 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD
1.0 μA max
VDD/VSS ±4.5/±16.5 V min/max GND = 0 V
1 Guaranteed by design, not subject to production test.
ADG1436
Rev. A | Page 6 of 16
CONTINUOUS CURRENT PER CHANNEL
Table 4.
Parameter 25°C 85°C 125°C Unit Test Conditions/Comments
CONTINUOUS CURRENT PER CHANNEL1
15 V Dual Supply VDD = +13.5 V, VSS = −13.5 V
ADG1436 TSSOP 260 170 100 mA max
ADG1436 LFCSP 400 250 120 mA max
12 V Single Supply VDD = 10.8 V, VSS = 0 V
ADG1436 TSSOP 240 160 100 mA max
ADG1436 LFCSP 350 240 120 mA max
5 V Dual Supply V
DD = +4.5 V, VSS = −4.5 V
ADG1436 TSSOP 240 160 100 mA max
ADG1436 LFCSP 300 240 120 mA max
1 Guaranteed by design, not subject to production test.
ADG1436
Rev. A | Page 7 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Ratings
VDD to VSS 35 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Analog Inputs1VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Digital Inputs1
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Peak Current, S or D 600 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Continuous Current per
Channel, S or D2
Data + 15%
Operating Temperature Range
Automotive (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
16-Lead TSSOP, θJA Thermal
Impedance (4-Layer Board)
112°C/W
16-Lead LFCSP, θJA Thermal
Impedance
30.4°C/W
Reflow Soldering Peak
Temperature, Pb Free
260(+0/−5)°C
1 Over voltages at IN, S, and D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
2 See data given in Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADG1436
Rev. A | Page 8 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN1 1
S1A 2
D1 3
S1B 4
NC16
NC
15
NC14
VDD
13
VSS 5S2B
12
GND 6D211
NC 7S2A10
NC 8IN2
9
NC = NO CONNECT
ADG1436
TOP VIEW
(Not to Scale)
06817-003
Figure 3.TSSOP Pin Configuration
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, V
SS
.
2. NC = NO CONNECT.
PIN 1
INDICATOR
1D1
2S1B
3V
SS
4GND
11 V
DD
12 EN
10 S2B
9D2
5
NC
6
IN2
7
NC
8
S2A
15 IN1
16 S1A
14 NC
13 NC
TOP VIEW
(Not to Scale)
ADG1436
06817-004
Figure 4. LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Function
1 15 IN1 Logic Control Input.
2 16 S1A Source Terminal. Can be an input or output.
3 1 D1 Drain Terminal. Can be an input or output.
4 2 S1B Source Terminal. Can be an input or output.
5 3 VSS Most Negative Power Supply Potential.
6 4 GND Ground (0 V) Reference.
7, 8, 14 to 16 5, 7, 13, 14 NC No Connect.
9 6 IN2 Logic Control Input.
10 8 S2A Source Terminal. Can be an input or output.
11 9 D2 Drain Terminal. Can be an input or output.
12 10 S2B Source Terminal. Can be an input or output.
13 11 VDD Most Positive Power Supply Potential.
N/A 12 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are
off. When this pin is high, INx logic inputs determine the on switches.
TRUTH TABLE FOR SWITCHES
Table 7. ADG1436 TSSOP Truth Table
INx SxA SxB
0 Off On
1 On Off
Table 8. ADG1436 LFCSP Truth Table
EN INx SxA SxB
0 X Off Off
1 0 Off On
1 1 On Off
ADG1436
Rev. A | Page 9 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
2.5
2.0
1.5
1.0
0.5
0
–16.5 –12.5 –8.5 –4.5 –0.5 3.5 7.5 15.5
ON RESISTANCE ()
VS OR VD (V)
11.5
VDD = +16.5V,
VSS = –16.5V
TA = 25°C
IS = –10mA
VDD = +15V,
VSS = –15V
VDD = +13.5V,
VSS = –13.5V
VDD = +12V,
VSS = –12V
VDD = +10V,
VSS = –10V
06815-104
Figure 5. On Resistance vs. VD or VS, Dual Supply
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–7 –6 –5 –3 –1–4 –2 0 1 6
ON RESISTANCE ()
VS OR VD (V)
34 752
TA = 25°C
IS = –10mA
VDD = +7V,
VSS = –7V
VDD = +5.5V,
VSS = –5.5V
VDD = +5V,
VSS = –5V
VDD = +4.5V,
VSS = –4.5V
06815-105
Figure 6. On Resistance vs. VD or VS, Dual Supply
7
6
5
4
3
2
1
0
01412108642
ON RESISTANCE ()
VS OR VD (V)
TA = 25°C
IS = –10mA
VDD = 15V,
VSS = 0V
VDD = 13.2V,
VSS = 0V
VDD = 12V,
VSS = 0V
VDD = 10.8V,
VSS = 0V
VDD = 8V,
VSS = 0V
VDD = 5V,
VSS = 0V
06815-106
Figure 7. On Resistance vs. VD or VS, Single Supply
3.0
2.5
2.0
1.5
1.0
0.5
0
–15 151050–5–10
ON RESISTANCE ()
VS OR VD (V)
VDD = +15V
VSS = –15V
IS = –10mA
TA = +25°C
TA = +85°C
TA = +125°C
TA = –40°C
06815-107
Figure 8. On Resistance vs. VD or VS for Different Temperatures, 15 V Dual Supply
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–5 –4 –3 –2 –1 0 1 2 3 4 5
ON RESISTANCE ()
V
S
OR V
D
(V)
V
DD
= +5V
V
SS
= –5V
I
S
= –10mA
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
T
A
= –40°C
06815-108
Figure 9. On Resistance vs. VD or VS for Different Temperatures, 5 V Dual Supply
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
01108642
ON RESISTANCE ()
V
S
OR V
D
(V)
2
V
DD
= 12V
V
SS
= 0V
I
S
= –10mA
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
T
A
= –40°C
06815-109
Figure 10. On Resistance vs. VD or VS for Different Temperatures, Single Supply
ADG1436
Rev. A | Page 10 of 16
2
1
0
–1
–2
–3
–4
–5
–6
–7
0 20406080100120
LEAKAGE (nA)
TEMPERATURE (°C)
06817-111
V
DD
= +15V
V
SS
= –15V
V
BIAS
= +10V/–10V
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
D
, I
S
(ON) + +
I
D
, I
S
(ON) – –
Figure 11. Leakage Currents vs. Temperature, 15 V Dual Supply
1.5
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
0 20406080100120
LEAKAGE (nA)
TEMPERATURE (°C)
06817-113
V
DD
= +5V
V
SS
= –5V
V
BIAS
= +4.5V/–4.5V
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
D
, I
S
(ON) + +
I
D
, I
S
(ON) – –
Figure 12. Leakage Currents vs. Temperature, 5 V Dual Supply
8
7
6
5
4
3
2
1
0
–1
–2
0 20406080100120
LEAKAGE (nA)
TEMPERATURE (°C)
06817-112
V
DD
= 12V
V
SS
= 0V
V
BIAS
= 1V/10V
I
S
(OFF) + –
I
D
(OFF) + –
I
S
(OFF) – +
I
D
(OFF) – +
I
D
, I
S
(ON) + +
I
D
, I
S
(ON) – –
Figure 13. Leakage Currents vs. Temperature, 12 V Single Supply
80
70
60
50
40
30
20
10
0
0112108642
I
DD
(µA)
LOGIC, Ax (V)
4
T
A
= 25°C
I
DD
PER LOGIC INPUT
V
DD
= +15V
V
SS
= –15V
V
DD
= +12V
V
SS
= 0V
V
DD
= +5V
V
SS
= –5V
06817-008
Figure 14. IDD vs. Logic Level
600
400
200
0
–200
–400
–600
–15 –10 –5 0 5 10 15
CHARGE INJECTION (pC)
V
S
(V)
V
DD
= +15V, V
SS
= –15V
V
DD
= +12V, V
SS
= 0V
V
DD
= +5V, V
SS
= –5V
T
A
= 25°C
06817-012
Figure 15. Charge Injection vs. Source Voltage
450
0
50
100
150
200
250
300
350
400
–40 120100806040200–20
TIME (ns)
TEMPERATURE (°C)
06817-217
V
DD
= +5V
V
SS
= –5V
V
DD
= +12V
V
SS
= 0V
V
DD
= +15V
V
SS
= –15V
Figure 16. tTRANSITION Time vs. Temperature
ADG1436
Rev. A | Page 11 of 16
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
1k 10k 100k 1M 10M 1G100M
OFF ISOLATION (dB)
FREQUENCY (Hz)
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
06817-014
Figure 17. Off Isolation vs. Frequency
0
–20
–40
–60
–80
–100
–120
1k 100M10M1M100k10k
CROSSTALK (dB)
FREQUENCY (Hz)
06817-019
CHANNEL-TO-CHANNEL
(SxA TO SxB)
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
MUX-TO-MUX
(S1x TO S2x)
Figure 18. Crosstalk vs. Frequency
0
–5.0
–4.5
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
1k 1G100M10M1M100k10k
INSERTION LOSS (dB)
FREQUENCY (Hz)
06817-020
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
Figure 19. On Response vs. Frequency
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
1k 10k 100k 1M 10M
ACPSRR (dB)
FREQUENCY (Hz)
V
DD
= +15V
V
SS
= –15V
V p-p = 0.63V
T
A
= 25°C
NO DECOUPLING
CAPACITORS
DECOUPLING
CAPACITORS
ON SUPPLIES
06817-017
Figure 20. ACPSRR vs. Frequency
0.024
0.022
0.020
0.018
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.002
10 100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
VDD = +15V
VSS = –15V
TA = 25°C
VS = 20V p-p
VS = 15V p-p
VS = 10V p-p
06817-117
Figure 21. THD + N vs. Frequency, 15 V Dual Supply
1
0.1
0.01
0.001
10 100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
VDD = +5V
VSS = –5V
TA = 25°C
VS = 10V p-p
VS = 5V p-p
VS = 2.5V p-p
06817-118
Figure 22. THD + N vs. Frequency, 5 V Dual Supply
ADG1436
Rev. A | Page 12 of 16
TERMINOLOGY
IDD
The positive supply current.
ISS
The negative supply current.
VD, VS
The analog voltage on Terminal D and Terminal S.
RON
The ohmic resistance between Terminal D and Terminal S.
RFLAT(ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the
specified analog signal range.
IS (Off)
The source leakage current with the switch off.
ID (Off)
The drain leakage current with the switch off.
ID, IS (On)
The channel leakage current with the switch on.
VINL
The maximum input voltage for Logic 0.
VINH
The minimum input voltage for Logic 1.
IINL, IINH
The input current of the digital input.
CS (Off)
The off-switch source capacitance, which is measured with
reference to ground.
CD (Off)
The off-switch drain capacitance, which is measured with
reference to ground.
CD, CS (On)
The on-switch capacitance, which is measured with reference
to ground.
CIN
The digital input capacitance.
tTRANSITION
The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one
address state to another.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
ADG1436
Rev. A | Page 13 of 16
TEST CIRCUITS
I
DS
SxA/SxB Dx
V
S
V
06817-023
Figure 23. On Resistance
SxA/SxB Dx
V
S
A A
V
D
I
S
(OFF) I
D
(OFF)
06817-024
Figure 24. Off Leakage
SxA/SxB Dx A
VD
ID (ON)
NC
NC = NO CONNECT
06817-025
Figure 25. On Leakage
V
OUT
50
NETWORK
ANALYZER
R
L
50
INx
V
IN
SxA
Dx
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
50
NC
SxB
OFF ISOLATION = 20 log
V
OUT
V
S
06817-030
Figure 26. Off Isolation
V
OUT
50
NETWORK
ANALYZER
R
L
50
INx
V
IN
SxA
Dx
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
50
NC
SxB
INSERTION LOSS = 20 log
V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
06817-031
Figure 27. Channel-to-Channel Crosstalk
CHANNEL-TO-CHANNEL CROSSTALK = 20 log V
OUT
GND
SxA
Dx
SxB
V
OUT
NETWORK
ANALYZER
R
L
50
R
50
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
INx
06817-032
Figure 28. Bandwidth
ADG1436
Rev. A | Page 14 of 16
VOUT
RS
AUDIO PRECISION
RL
110
INx
VIN
SxA/SxB
Dx
VS
V p-p
VDD VSS
0.1µF
VDD
0.1µF
VSS
GND
06817-033
Figure 29. THD + Noise
INx
V
OUT
Dx
SxA
V
DD
V
SS
V
DD
V
SS
GND
C
L
35pF
SxB
V
IN
V
S
0.1µF0.1µF
R
L
300
50%
50%
90%
50%
50%
90%
t
ON
t
OFF
V
IN
V
OUT
V
IN
06817-026
Figure 30. Switching Times
INx
V
OUT
Dx
SxA
V
DD
V
SS
V
DD
V
SS
GND
C
L
35pF
SxB
V
IN
V
S
0.1µF0.1µF
R
L
300
80%
t
BBM
t
BBM
V
OUT
V
IN
06817-027
Figure 31. Break-Before-Make Time Delay
ADG1436
Rev. A | Page 15 of 16
OUTPUT
INx
50300
GND
SxA
SxB
Dx
35pF
VIN
EN
VDD VSS
VDD VSS
VS
3V
0V
OUTPUT
50% 50%
tOFF (EN)tON (EN)
0.9VOUT 0.9VOUT
ENABLE
DRIVE (VIN)
06817-028
Figure 32. Enable Delay, tON (EN), tOFF (EN)
V
IN
(NORMALLY
CLOSED SWITCH)
V
OUT
V
IN
(NORMALLY
OPEN SWITCH)
OFF
V
OUT
ON
Q
INJ
= C
L
× V
OUT
INx
V
OUT
Dx
SxA
V
DD
V
SS
V
DD
V
SS
GND
C
L
1nF
NC
SxB
V
IN
V
S
0.1µF0.1µF
06817-029
Figure 33. Charge Injection
ADG1436
Rev. A | Page 16 of 16
OUTLINE DIMENSIONS
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
COMPLIANT
TO
JEDEC STANDARDS MO-220-VGGC.
1
0.65
BSC
0.60 MAX
PIN 1
INDICATOR
1.95 BCS
0.50
0.40
0.30
0.25 MIN
3.75
BSC SQ
TOP VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDI
C
ATOR
COPLANARITY
0.08
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
4.00
BSC SQ
2.65
2.50 SQ
2.35
16
5
13
8
9
12
4
EXPOSED
PAD
BOTTOM VIEW
031006-A
Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG1436YRUZ1−40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
ADG1436YRUZ-REEL71
−40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
ADG1436YCPZ-REEL1
−40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-13
ADG1436YCPZ-REEL71
−40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-13
1 Z = RoHS Compliant Part.
©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06817-0-3/09(A)
