FemtoClock®®
®®
® Multi-Rate 3.3V, 2.5V
LVPECL Frequency Synthesizer ICS843034
DATA SHEET
ICS843034CY REVISION A MARCH 7, 2012 1©2012 Integrated Device T echnology, Inc.
GENERAL DESCRIPTION
The ICS843034 is a general purpose, low phase noise
LVPECL synthesizer which can generate frequencies for a wide
variety of applications. The ICS843034 has a 4:1 input
Multiplexer from which the following inputs can be selected:
one differential input, one single-ended input, or two crystal
oscillators, thus making the device ideal for frequency
translation or frequency generation. Each differential LVPECL
output pair has an output divider which can be independently
set so that two different frequencies can be generated.
Additionally, each LVPECL output pair has a dedicated power
supply pin so the outputs can run at 3.3V or 2.5V. The ICS843034
also supplies a buffered copy of the reference clock or crystal
frequency on the single-ended REF_CLK output pin which
can be enabled or disabled (disabled by default). The output
frequency can be programmed using either a serial or parallel
programming interface.
The phase jitter of the ICS843034 is less than 1ps rms, making
it suitable for use in Fibre Channel, SONET, and Ethernet
applications.
Example applications include systems which must support both
FEC and non FEC rates. In 10Gb Fibre Channel, for example,
you can use a 25.5MHz crystal to generate a 159.375MHz
reference clock, and then switch to a 20.544MHz crystal to
generate 164.355MHz for 66/64 FEC. Other applications could
include supporting both Ethernet frequencies and SONET
frequencies in an application. When Ethernet frequencies are
needed, a 25MHz crystal can be used and when SONET
frequencies are needed, the input MUX can be switched to
select a 38.88MHz crystal.
FEATURES
•Dual differential 3.3V LVPECL outputs which can be set
independently for either 3.3V or 2.5V
•4:1 Input Mux:
One differential input
One single-ended input
Two crystal oscillator interfaces
•CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
•TEST_CLK accepts LVCMOS or LVTTL input levels
•Output frequency range: 35MHz to 625MHz
•Crystal input frequency range: 12MHz to 40MHz
•VCO range: 560MHz to 625MHz
•Parallel or serial interface for programming feedback divider
and output dividers
•RMS phase jitter at 333.33MHz, using a 22.222MHz crystal
(12kHz to 20MHz): 0.91ps (typical)
•Supply voltage modes:
LVPECL outputs (core/outputs):
3.3V/3.3V
3.3V/2.5V
REF_CLK output (core/outputs):
3.3V/3.3V
•0°C to 70°C ambient operating temperature
•Industrial temperature available upon request with E-pad
option.
•Available in lead-free (RoHS 6) packages
PIN ASSIGNMENT
13
16
17
20
21
24
1
2
4
5
6
8
9
11
12
36
35
34
33
32
31
30
29
28
27
26
25
M8
NB0
NB1
NB2
OE_REF
OE_A
V
CC
NA0
NA1
NA2
V
EE
XTAL_OUT1
XTAL_IN1
XTAL_OUT0
XTAL_IN0
TEST_CLK
SEL1
SEL0
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
TEST
V
CC
nFOUTA0
V
CCO_A
n
V
CCO_B
REF_OUT
V
nc
V
EE
M6
M5
M4
M3
M2
M1
M0
VCO_SEL
nP_LOAD
nCLK
CLK
M7
48
47
46
45
44
43
42
41
40
39
38
37
IC
S8
4303
4
48-PIN L
Q
F
P
7mm x 7mm x 1.4mm
packa
g
e bod
y
Y Packa
ge
Top Vie
w
ICS843034CY REVISION A MARCH 7, 2012 2©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
BLOCK DIAGRAM
OSC
CONFIGURATION
INTERFAC E
LOGIC
¸M
0
1000 ¸ 1
001 ¸ 2
010 ¸ 3
011 ¸ 4
100 ¸ 5
101 ¸ 6
110 ¸ 8
111 ¸16
000 ¸ 1
001 ¸ 2
010 ¸ 3
011 ¸ 4
100 ¸ 5
101 ¸ 6
110 ¸ 8
111 ¸16
OSC
PHASE
DETECTOR VCO
00
01
10
11
FOUTA0
nFOUTA
0
FOUTB0
nFOUTB
0
REF_CL
K
TEST
VCCO_REF
VCCO_B
VCCO_A
OE_A
OE_B
MR
VCO_SEL
CLK
nCLK
SEL1
SEL0
TEST_CLK
OE_REF
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M8:M0
NA2, NA0, NA1
NB2, NA0, NB1
XTAL_IN0
XTAL_OUT0
XTAL_IN1
XTAL_OUT1
Pullup
Pulldown
Pulldown, Pullup, Pullup
Pulldown
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown, Pullup, Pullup
Pulldown
Pulldown
Pulldown/Pullup
Pullup
Pulldown
ICS843034CY REVISION A MARCH 7, 2012 3©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
specific default state that will automatically occur during power-
up. The TEST output is LOW when operating in the parallel input
mode. The relationship between the VCO frequency, the crystal
frequency and the M divider is defined as follows:
The M value and the required values of M0 through M8 are
shown in Table 3B to program the VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 23 ≤ M ≤ 30. The frequency
out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and Nx output divider
when S_LOAD transitions from LOW-to-HIGH. The M divide
and Nx output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the
S_DATA input is passed directly to the M divider and Nx output
divider on each rising edge of S_CLOCK. The serial mode can
be used to program the M and Nx bits and test bits T1 and T0.
The internal registers T0 and T1 determine the state of the
TEST output as follows:
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes opera-
tion using a 25MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
The ICS843034 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
A fundamental crystal is used as the input to the on-chip oscil-
lator. The output of the oscillator is fed into the phase detector.
A 25MHz crystal provides a 25MHz phase detector reference
frequency. The VCO of the PLL operates over a range of 560MHz
to 625MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output of
the VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers. The divider provides a 50% output duty
cycle.
The ICS843034 supports either serial or parallel programming
modes to program the M feedback divider and N output divider.
Figure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on the M,
NA, and NB inputs are passed directly to the M divider and
both N output dividers. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M and N dividers
remain loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and Nx bits can
be hardwired to set the M divider and Nx output divider to a
T1 T0 TEST Output
0 0 LOW
0 1 S_Data, Shift Register Output
1 0 Output of M divider
1 1 Same frequencey as FOUTA0
fVCO = fxtal x M
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
T 1 T0 NB2 NB1 NB0 NA2 NA1 NA0 M8 M7 M6 M5 M4 M3 M2 M1 M 0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, NA0:NA2, NB0:NB2
nP_LOAD
S_LOAD
SERIAL LOADING
PARALLEL LOADING
M, N
t
S
t
S
t
H
t
S
t
H
Time
FOUT = fVCO = fxtal x M
N N
ICS843034CY REVISION A MARCH 7, 2012 4©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
,24,14,1
,44,34
84,74,54
,1M,0M,8M
,3M,2M
7M,6M,4M
tupnInwodlluP fonoitisnartHGIH-ot-WO
LnodehctalataD.tupniredividM
.slevelecafretniLTTVL/SOMCVL.tupniDAOL_Pn
3,21BN,0BNtupnIpulluP ,C3elbaTnideni
fedsaeulavredividtuptuosenimreteD
.slevelecafretniLTTVL/SOMCVL.elbaTnoitcnuF
42BNtupnInwodlluP
5FER_EOtupnInwo
dlluP
.tuptuoKLC_FERfognilbasiddnagnilbaneslortnoC.elbanetuptuO
FER_EOnehwelbanesiKLC_FER.slevelecafret
niLTTVL/SOMCVL
stluafedFER_EO.WOLsiFER_EOnehwZ-iHsiKLC_FER.HGIHsi
.WOLot
6A_EOtupnIpulluP ,0ATUOFfognilbasid
dnagnilbaneslortnoC.elbanetuptuO
.slevelecafretniLTTVL/SOMCVL.stuptuo0ATUOFn
7B_EOtupnIpulluP ,0BTUOFfognil
basiddnagnilbaneslortnoC.elbanetuptuO
.slevelecafretniLTTVL/SOMCVL.stuptuo0BTUOFn
41,8V
CC
rewoP.snipylppuseroC
01,91AN,0ANtupnIpulluP ,C3elbaTnidenifedsaeulavredividtuptuosenimreteD
.slevelecafretni
LTTVL/SOMCVL.elbaTnoitcnuF
112ANtupnInwodlluP
42,21V
EE
rewoP.snipylppusevitageN
31TSETtuptuO
.noitarepofoedomlairesehtniEVITCAsihcihwtuptuotseT
.edomlellarapniWOL
nevirdtuptuO
.slevelecafretniLTTVL/SOMCVL
61,51 ,0ATUOF
0ATUOFn tuptuO .slevelecafretniLCEPVL.rezisehtnyseh
troftuptuolaitnereffiD
71V
A_OCC
rewoP.0ATUOFn,0ATUOFrofnipylppustuptuO
91,81 ,0BTUOF
0BTUOFn tuptuO .slevelecafretniLCEPVL.rezisehtnysehtro
ftuptuolaitnereffiD
02V
B_OCC
rewoP.0BTUOFn,0BTUOFrofnipylppustuptuO
12KLC_FERtuptuO .slevelecafretniLTTVL/SOMCVL.tuptuokcolcecnerefeR
22V
FER_OCC
rewoP.KLC_FERrofnipylppustuptuO
32cndesunU.tcennocoN
52RMtupnInwodlluP
lanretniehtsecrof,HGIHcigolnehW.teseRret
saMhgiHevitcA
ehtdnawologotxTUOFstuptuoeurtehtgnisuactesererasredivid
lanretnieht,WOLcigolnehW.hgihogotxTUOFnstuptuodetrevni
tonseodRMfonoitressA.delbaneerastuptuoehtdnasredivid
.slevelecafretniLTTVL/SOMCVL
.seulavTdna,N,Mdedaoltceffa
62KCOLC_StupnInwodlluP retsigertfihsehtotnitupniATAD_Statneserpatadlairesniskc
olC
.slevelecafretniLTTVL/SOMCVL.KCOLC_Sfoegdegnisirehtno
72ATAD_StupnInwodlluP egdegnisirehtnodelpmasataD.
tupnilairesretsigertfihS
.slevelecafretniLTTVL/SOMCVL.KCOLC_Sfo
82DAOL_StupnInwodlluP .sredividehtotniretsi
gertfihsmorfatadfonoitisnartslortnoC
.slevelecafretniLTTVL/SOMCVL
92V
ACC
rewoP.nipylppusgolanA
13,031LES,0LEStupnInwodlluP.slevelecafretniLTTVL/SOMCVL.stupnitceleskcolC
23KLC_TSETtupn
InwodlluP.slevelecafretniLTTVL/SOMCVL.tupnikcolctseT
43,33 ,0NI_LATX
0TUO_LATX tupnI ,tupniehtsi0NI_LATX.eca
fretnirotallicsolatsyrC
.tuptuoehtsi0TUO_LATX
63,53 ,1NI_LATX
1TUO_LATX tupnI ,tupniehtsi1NI_LATX.ecafretni
rotallicsolatsyrC
.tuptuoehtsi1TUO_LATX
...egaptxennodeunitnoC
ICS843034CY REVISION A MARCH 7, 2012 5©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TABLE 2. PIN CHARACTERISTICS
TABLE 1. PIN DESCRIPTIONS, CONTINUED
rebmuNemaNepyTnoitpircseD
73KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN
83KLCntupnI /pulluP
nwodlluP V.tup
nikcolclaitnereffidgnitrevnI
CC
.gnitaolftfelnehwtluafed2/
93DAOL_PntupnInwodlluP
si0M:8MtatneserpatadnehwsenimreteD.tupnidaollellaraP
dna0
AN:2ANtatneserpatadnehwdna,redividMotnidedaol
.sredividtuptuoNehtotnidedaolsi0BN:2BN
.slevelecafretniLT
TVL/SOMCVL
04LES_OCVtupnIpulluP .edomssapybroLLPnisirezisehtnysrehtehwsenimreteD
.slevelecafretniLTTVL/SOMC
VL
645MtupnIpulluP noitisnartHGIH-ot-WOLnodehctalataD.stupniredividM
.slevelecafretniLTTVL/SOMCVL.tupniDAOL
_Pnfo
:ETON pulluP dna nwodlluP .seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotref
er
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
ecnaticapaCtupnI 4Fp
R
PULLUP
rotsiseRpulluPtupnI 15kΩ
R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
R
TUO
ecnadepmItuptuOKLC_FERV
FER_OCC
V3.3=5721Ω
ICS843034CY REVISION A MARCH 7, 2012 6©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. P ARALLEL AND SERIAL MODE FUNCTION TABLE
stupnI snoitidnoC
RMDAOL_PnMNDAOL_SKCOLC_SATAD_S
HX XXX X X .WOLstuptuosecroF.teseR
LL ataDataDX X X MehtotyltceriddessapstupniNdnaM
noataD
.WOLdecroftuptuoTSET.redividtuptuoNdnaredivid
L↑ataDataDL X X dedaolsniamerdnasretsigertupniotnidehctal
siataD
.sruccotnevelairesalitnuronoitisnartWOLtxenlitnu
LH XXL ↑ataD noatadhtiwdedaolsiretsigertfihS.edomtupni
laireS
.KCOLC_SfoegdegnisirhcaenoATAD_S
LH XX↑LataD ehtotdessaperaretsigertfihsehtfostnetnoC
.redividtuptuoNdn
aredividM
LH XX↓LataD.dehctaleraseulavredividtuptuoNdnaredividM
LH XXL X X .sretsigertfihstceffatonodtupnilairesrolellar
aP
LH XXH ↑ataD.dekcolcsitisaredividMotyltceriddessapATAD_S
WOL=L:ETON
HGIH=H
eract'noD=X
↑noitisnartegdegnisiR=
↓noitisnartegdegnillaF=
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
ycneuqerFOCV )zHM( ediviDM 652821462361 8421
8M7M6M5M4M3M2M1M0M
57532 000010111
• • •••••••••
00782 000011100
• • •••••••••
05703 000011110
.zHM52foycneuqerftupniKLC_TSETrolatsyrcotdnop
serrocseicneuqerfgnitluserehtdnaseulavedividMesehT:1ETON
stupnI eulaVrediviDN )zHM(ycneuqerFtuptuO
2XN*1XN*0XN*muminiMmumixaM
000 1 065526
00 1 2 082573
010 3 66.681052
011 )tluafed(40415.781
10 0 5 211051
10 1 6 3
3.39521
110 8 0757.39
111 6153578.64
BknaBroAknaBsetonedX:ETON*
ICS843034CY REVISION A MARCH 7, 2012 7©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO_A = VCCO_B = 3.3V±5% OR 2.5V±5%, VEE = 0V, TA = 0°C TO 70°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC 4.6V
Inputs, VI-0.5V to VCC + 0.5V
Outputs, VO (LVCMOS) -0.5V to VCCO + 0.5V
Outputs, IO (LVPECL)
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θJA 65.7°C/W (0 mps)
Storage Temperature, T
STG -65°C to 150°C
TABLE 3D. OE_REF TABLE 3E. OE_A, OE_B
FER_EOKLC_FER
0)tluafed(ZiH
1delbanE
A_EO B_EO 0ATUOFn,0ATUOF 0BTUOFn,0BTUOF
0)ZiH(delbasiD
1)tluafed(delbanE
TABLE 3F. SEL0, SEL1
0LES1LESTUPNI
00 )tluafed(0TUO_LATX,0NI_LATX
01 KLCn,KLC
10 1TUO_LATX,1NI_LATX
11 KLC_TSET
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
egatloVylppuSeroC 531.33.3564.3V
V
ACC
egatloVylppuSgolanAV
CC
81.0–3.3V
CC
V
V
,A_OCC
V
B_OCC
egatloVylppuStuptuO 531.33.3564.3V
573.25.2526.2V
V
FER_OCC
ylppuStuptuOKLC_FER531.33.3564.3V
I
EE
tnerruCylppuSrewoP 881Am
I
ACC
tnerruCylppuSgolanA 81Am
ICS843034CY REVISION A MARCH 7, 2012 8©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TABLE 4B. L VCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO_A = VCCO_B = VCCO_REF = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
tnerruChgiHtupnI KLCnV
NI
V=
CC
V564.3=051Aμ
KLCV
NI
V=
CC
V564.3=051Aμ
I
LI
tnerruCwoLtupnI KLCnV
NI
V,V0=
CC
V564.3=051-Aμ
KLCV
NI
V,V0=
CC
V564.3=5-Aμ
V
PP
1ETON;egatloVtupnIkaeP-ot-kaeP 51.03.1V
V
RMC
2,1ETON;egatloVtupnIedoMnommoCV
EE
5.0+V
CC
58.0-V
V:1ETON
LI
.V3.0-nahtsselebtondluohs
siegatlovedomnommoC:2ETONVsadenifed
HI
.
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO_A = VCCO_B = 3.3V±5% OR 2.5V±5%, VEE = 0V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI2V
CC
3.0+V
V
LI
egatloVwoLtupnI 3.0-8.0V
I
HI
tupnI
tnerruChgiH
,RM,KLC_TSET
,FER_EO,]0:1[LES
,ATAD_S,KCOLC_S
,DAOL_Pn,DAOL_S
8M:6M,4M:1M,2xN
V
CC
V=
NI
V564.3=051Aμ
,A_EO,5M,1xN,0xN
LES_OCV,B_EO V
CC
V=
NI
V564.3=5Aμ
I
LI
tupnI
tnerruCwoL
,RM,KLC_TSET
,FER_EO,]0:1[LES
,ATAD_S,KCOLC_S
,DAOL_Pn,DAOL_S
8M:6M,4M:1M,2xN
V
CC
,V564.3=
V
NI
V0= 5-Aμ
,A_EO,5M,1xN,0xN
LES_OCV,B_EO
V
CC
,V564.3=
V
NI
V0= 051-Aμ
V
HO
tuptuO
egatloVhgiH
1ETON;TSET V
FER_OCC
%5±V3.3= 6.2V
KLC_FERV
FER_OCC
V3.0-V
V
LO
tuptuO
egatloVwoL
1ETON;TSET V
FER_OCC
%5±V3.3= 5.0V
KLC_FER 4.0V
ICS843034CY REVISION A MARCH 7, 2012 9©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TABLE 4D. L VPECL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO_A = VCCO_B = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C
TABLE 4E. L VPECL DC CHARACTERISTICS, VCC = 3.3V±5%, VCCO_A = VCCO_B = 2.5V±5%, VEE = 0V, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuOV
OCC
4.1-V
OCC
9.0-V
V
LO
1ETON;egatloVwoLtuptuOV
OCC
0.2-V
OCC
6.1-V
V
GNIWS
gniwSegatloVtuptuOkaeP-ot-kaeP 4.01.1V
05htiwdetanimretstuptuO:1ETON ΩVot
,A_OCC
V
B_OCC
.V2-
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
1ETON;egatloVhgiHtuptuOV
OCC
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V
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TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = 3.3V±5%, VCCO_A = VCCO_B = 3.3V±5% OR 2.5V±5%, VEE = 0V, TA = 0°C TO 70°C
TABLE 6. CRYSTAL CHARACTERISTICS
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ICS843034CY REVISION A MARCH 7, 2012 10 ©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TABLE 7A. AC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C
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ICS843034CY REVISION A MARCH 7, 2012 11 ©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TABLE 7B. AC CHARACTERISTICS, VCC = 3.3V±5%, VCCO_A = VCCO_B = 2.5V±5%, TA = 0°C TO 70°C
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ICS843034CY REVISION A MARCH 7, 2012 12 ©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 333.33MHZ
OFFSET FREQUENCY (HZ)
NOISE POWER dBc
Hz
333.33MHz
22.222MHz XT AL
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.91ps (typical)
ICS843034CY REVISION A MARCH 7, 2012 13 ©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
SCOPE
Qx
V
EE
SCOPE
Qx
nQx
VEE
SCOPE
Qx
nQx
V
EE
OUTPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
FOUTA0
nFOUTA0
PARAMETER MEASUREMENT INFORMATION
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
FOUTA0/nFOUTA0, FOUTB0/nFOUTB0
2V
-1.3V ± 0.165V
V
CC,
V
CCO_A,
V
CCO__B
3.3VCORE/3.3V REF_CLK OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
FOUTA0/nFOUTA0, FOUTB0/nFOUTB0
2.8V±0.04V
-0.5V ± 0.125V
V
CC
V
CCO_A,
V
CCO__B
2V
1.65V±5%
-1.65V ± 5%
V
CC,
V
CCO_REF
LVPECL OUTPUT RISE/FALL TIME
LVCMOS OUTPUT RISE/FALL TIME
2V 2.8V±0.04V
1.65V±5%
tsk(o)
nFOUTx
FOUTx
nFOUTy
FOUTy
OUTPUT SKEW
20%
80% 80%
20%
t
R
t
F
V
SWIN
G
20%
80% 80%
20%
t
R
t
F
nFOUTx
FOUTx
REF_CLK
V
CCA V
CCA
V
CCA
ICS843034CY REVISION A MARCH 7, 2012 14 ©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
Figure 1 shows how a differential input can be wired to accept
single ended levels. The reference voltage VREF = VCC/2 is
generated by the bias resistors R1 and R2. The bypass capacitor
(C1) is used to help filter noise on the DC bias. This bias circuit
should be located as close to the input pin as possible. The
ratio of R1 and R2 might need to be adjusted to position the
VREF in the center of the input voltage swing. For example, if the
input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value
should be adjusted to set VREF at 1.25V. The values below are
for when both the single ended swing and VCC are at the same
voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs)
equals the transmission line impedance. In addition, matched
termination at the input will attenuate the signal in half. This can
be done in one of two ways. First, R3 and R4 in parallel should
WIRING THE DIFFERENTIAL INPUT LEVEL APPLICATION
equal the transmission line impedance. For most 50W
applications, R3 and R4 can be 100W. The values of the resistors
can be increased to reduce the loading for slower and weaker
LVCMOS driver. When using single-ended signaling, the noise
rejection benefits of differential signaling are reduced. Even
though the differential input can handle full rail LVCMOS signaling,
it is recommended that the amplitude be reduced. The datasheet
specifies a lower differential amplitude, however this only applies
to differential signals. For single-ended applications, the swing
can be larger, however VIL cannot be less than -0.3V and VIH
cannot be more than VCC + 0.3V. Though some of the
recommended components might not be used, the pads should
be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
FIGURE 1. RECOMMENDED SCHEMATIC FOR WIRING A DIFFERENTIAL INPUT TO ACCEPT SINGLE-ENDED LEVELS
ICS843034CY REVISION A MARCH 7, 2012 15 ©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
FIGURE 2C. CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 2B. CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 2D . CLK/nCLK INPUT
DRIVEN BY A 3.3V L VDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and
other differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 2A to 2E show interface
examples for the CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples
FIGURE 2A. CLK/nCLK I NPUT
DRIVEN BY AN IDT OPEN EMITTER
L VHSTL DRIVER
only. Please consult with the vendor of the driver component to
confirm the driver termination requirements. For example in Figure
2A, the input termination applies for IDT open emitter LVHSTL
drivers. If you are using an LVHSTL driver from another vendor,
use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 2E. CLK/nCLK INPUT
DRIVEN BY A 3.3V HCSL DRIVER
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
HCSL
*R3 33
*R4 33
CLK
nCLK
2.5V
3.3V
Zo = 50Ω
Zo = 50Ω
HiPerClock
S
Input
R1
50 R2
50
*Optional – R3 and R4 can be 0Ω
ICS843034CY REVISION A MARCH 7, 2012 16 ©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
OVERDRIVING THE XTAL INTERFACE
The XTAL_IN input can be overdriven by an LVCMOS driver or by
one side of a differential driver through an AC coupling capacitor.
The XTAL_OUT pin can be left floating. The amplitude of the input
signal should be between 500mV and 1.8V and the slew rate
should not be less than 0.2V/nS. For 3.3V LVCMOS inputs, the
amplitude must be reduced from full swing to at least half the
swing in order to prevent signal interference with the power rail
and to reduce internal noise. Figure 3A shows an example of the
interface diagram for a high speed 3.3V LVCMOS driver. This
configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the
transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
FIGURE 3A. GENERAL DIAGRAM FOR L VCMOS DRIVER TO XT AL INPUT INTERFACE
done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50W
applications, R1 and R2 can be 100W. This can also be
accomplished by removing R1 and changing R2 to 50W. The
values of the resistors can be increased to reduce the loading
for a slower and weaker LVCMOS driver. Figure 3B shows an
example of the interface diagram for an LVPECL driver. This is a
standard LVPECL termination with one side of the driver feeding
the XTAL_IN input. It is recommended that all components in the
schematics be placed in the layout. Though some components
might not be used, they can be utilized for debugging purposes.
The datasheet specifications are characterized and guaranteed
by using a quartz crystal as the input.
VCC XTA L _O U T
XTAL _ I N
R1
100
R2
100
Zo = 50 ohmsRs
Ro
Zo = Ro + Rs
C1
.1uf
LVCMOS Driver
XTAL _ OU T
XTAL _ I N
Zo = 50 ohms C2
.1uf
LVPECL Driver
Zo = 50 ohms
R1
50
R2
50
R3
50
FIGURE 3B. GENERAL DIAGRAM FOR L VPECL DRIVER TO XTAL INPUT INTERFACE
ICS843034CY REVISION A MARCH 7, 2012 17 ©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
3.3V
V
CC
- 2V
R1
50ΩR2
50Ω
RTT
Z
o
= 50Ω
Z
o
= 50Ω
+
_
R
TT = * Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
LVPECL Inpu
t
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
FIGURE 4B. L VPECL OUTPUT TERMINATIONFIGURE 4A. L VPECL OUTPUT TERMINATION
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
R1
84ΩR2
84Ω
3.3V
R3
125ΩR4
125Ω
Zo = 50Ω
Zo = 50Ω
LVPECL Inp
ut
3.3V
3
.3V
+
_
INPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator
input, both XTAL_INx and XTAL_OUTx can be left floating. Though
not required, but for additional protection, a 1kΩ resistor can be
tied from XTAL_IN to ground.
TEST_CLK INPUT
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the TEST_CLK to ground.
L VCMOS CONTROL PINS
All select pins have internal pullups and pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
L VCMOS OUTPUTS
The unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
ICS843034CY REVISION A MARCH 7, 2012 18 ©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCCO - 2V . For VCCO = 2.5V, the VCCO - 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination
is shown in Figure 5C.
FIGURE 5C. 2.5V L VPECL TERMINATION EXAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPEC L
Driver
FIGURE 5B. 2.5V L VPECL DRIVER TERMINATION EXAMPLE
VCCO=2.5V
R1
50 R2
50
Zo = 50 O hm
R3
18
2, 5V LVPECL
Driver
Zo = 50 O hm
+
-
2.5V
FIGURE 5A. 2.5V L VPECL DRIVER TERMINATION EXAMPLE
R2
62.5
2.5V
2, 5V LVPECL
Driver
R3
250
Z o = 50 Oh m
Z o = 50 Oh m
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
ICS843034CY REVISION A MARCH 7, 2012 19 ©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
APPLICATION SCHEMATIC EXAMPLE
Figure 6 shows an example of ICS843034 application schematic.
In this example, the device is operated VCC = VCCO_A = VCCO_B =
VCCO_REF = 3.3V. The 18pF parallel resonant 25MHz crystal is used.
The load capacitance C1 = 18pF and C2 = 22pF are
recommended for frequency accuracy. Depending on the
parasitic of the printed circuit board layout, these values might
require a slight adjustment to optimize the frequency accuracy.
Crystals with other load capacitance specifications can be used.
This will require adjusting C1 and C2. For this device, the crystal
load capacitors are required for proper operation.
As with any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The ICS843034
provides separate power supplies to isolate any high switching
noise from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended
that the placement of the filter components be on the device side
of the PCB as close to the power pins as possible. If space is
FIGURE 6. ICS843034 APPLICATION SCHEMATIC EXAMPLE
limited, the 0.1uF capacitor in each power pin filter should be
placed on the device side. The other components can be on the
opposite side of the PCB. Power supply filter recommendations
are a general guideline to be used for reducing external noise
from coupling into the devices. The filter performance is designed
for wide range of noise frequency. This low-pass filter starts to
attenuate noise at approximately 10kHz. If a specific frequency
noise component with high amplitude interference is known,
such as switching power supplies frequencies, it is
recommended that component values be adjusted and if
required, additional filtering be added. Additionally general
design practice for power plane voltage stability suggests adding
bulk capacitances in the general area of all devices. The
schematic example focuses on functional connections and is
not configuration specific. Refer to the pin description and
functional tables in the datasheet to ensure the logic control
inputs are properly set.
U1
M8
1
NB0
2
NB1
3
NB2
4
OE_REF
5
OE_A
6
OE_B
7
VCC
8
NA0
9
NA1
10
NA2
11
VEE
12
TEST
13
VCC
14
FOUT A0
15
nFOU TA0
16
VCCO _A
17
FOUTB0
18
nFOUTB0
19
VC CO_ B
20
REF_CLK
21
VC CO_ REF
22
nc
23
VEE
24
XTA L_O U T1 36
XT A L _ I N 1 35
XTA L_O U T0 34
XT A L _ I N 0 33
TE ST _ C L K 32
SE L1 31
SE L0 30
VC CA 29
S_LOAD 28
S_DATA 27
S_C LOCK 26
MR 25
M7 48
M6 47
M5 46
M4 45
M3 44
M2 43
M1 42
M0 41
VCO_SEL 40
nP_LOAD 39
nCLK 38
CLK 37
3.3V
Zo = 50 Ohm
R11
50
R12
50
REF_CLK
Zo = 50 Ohm
Zo = 50 Ohm
+
-
R10
50
M7
M5
M6
M4
M2
M3
M1
M0
VCO_SEL
OE_R EF
OE_A
OE_B
nFOU TA 0
FOUTA0
XTA L_O U T1
VCC
VC C
C10
0.1u
Zo = 50 Ohm
R2
133
R6
82.5
Zo = 50 Ohm
R1
133
R5
82 .5
LV PE C L
C9
0.1u
3.3V
R9
10
R4
133
R8
82. 5
+
-
RU2
Not Install
Optional
Y -Termi nation
RU1
1K
C2
22pF
R3
133
RD2
1K
RD1
Not Install
X125MHz
Zo = 50 Ohm
Zo = 50 Ohm
C1
18 p F
R7
82 . 5
VC CVCC
18pF
Dr iv er _ LV PECL
C4
10u
M8
VC CO
C6
0.1uF
C7
10uF
3.3V BLM18BB221SN1
Ferrite Bead
1 2
C8
0. 1u F
VCC
C12
10uF
C13
0. 1u F
BLM18BB221SN1
Ferrite Bead
1 2
3.3V
C11
0.1uF
VCCO
VCCO
Logic Control In put Examples
S et Logic
Input to
'1'
To L ogi c
In pu t
pi ns
To Lo gi c
In pu t
pins
Set Logic
Input to
'0'
VC C A
FOUTA0
nFOUT A0
C5
0. 1u
nFOUTB0
FOU TB 0
FOUTB0
nFOUTB0
NB1
NB0
NB2
NA0
NA2
NA1
SE L1
MR
SE L0
C3
0.1u
VC C
XTA L_I N 1
R13
33
LVCMOS
ICS843034CY REVISION A MARCH 7, 2012 20 ©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843034.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843034 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
·Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 188mA = 651.42mW
·Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 32.6mW = 65.2mW
·Power (ROUT) = ROUT* lOUT
2 = 12Ω* (49.2 mA)2 = 29.05mW
Total Power Dissipation
·Total Power
= Power (core) +Power (outputs) +Power (ROUT)
= 651.42mW + 65.2mW + 29.05mW
= 745.67mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 65.7°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.746W * 65.7°C/W = 119.0°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (multi-layer).
TABLE 8. THERMAL RESISTANCE θθ
θθ
θJA FOR 48-PIN LQFP, FORCED CONVECTION
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 65.7°C/W 55.9°C/W 52.4°C/W
ICS843034CY REVISION A MARCH 7, 2012 21 ©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 10.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination voltage of V
CCO
– 2V.
• For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX - VOH_MAX
) = 0.9V
• For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.6V
(VCCO_MAX - VOL_MAX
) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX
– (VCCO_MAX
– 2V))/R
L
] * (VCCO_MAX
– VOH_MAX) = [(2V
– (VCCO_MAX
– VOH_MAX
))/R
L
] * (VCCO_MAX
– VOH_MAX) =
[(2V
– 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX
– (VCCO_MAX
– 2V))/R
L
] * (VCCO_MAX
– VOL_MAX) = [(2V
– (VCCO_MAX
– VOL_MAX
))/R
L
] * (VCCO_MAX
– VOL_MAX) =
[(2V
– 1.6V)/50Ω] * 1.6V = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.6mW
FIGURE 7. LVPECL D RIVER CIRCUIT AND TERMINATION
Q1
VOUT
VCCO
RL
50
VCCO - 2V
ICS843034CY REVISION A MARCH 7, 2012 22 ©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS843034 is: 11,748
TABLE 9. θ
JAVS. AIR FLOW TABLE FOR 48 LEAD LQFP
θθ
θθ
θJA by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 65.7°C/W 55.9°C/W 52.4°C/W
ICS843034CY REVISION A MARCH 7, 2012 23 ©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
TABLE 10. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MS-026
NOITAIRAVCEDEJ SRETEMILLIMNISNOISNEMIDLLA
LOBMYS CBB
MUMINIMLANIMONMUMIXAM
N84
A----06.1
1A 50.0--51.0
2A 53.104.154.1
b71.022.072.0
c90.0--02.0
DCISAB00.9
1D CISAB00.7
2D .feR05.5
ECISAB00.9
1E CISAB00.7
2E .feR05.5
eCISAB05.0
L54.006.057.0
θθ
θ
θθ 0
°
-- 7
°
ccc ----80.0
ICS843034CY REVISION A MARCH 7, 2012 24 ©2012 Integrated Device T echnology , Inc.
ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TABLE 11. ORDERING INFORMATION
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ICS843034 Data Sheet FEMTOCLOCK® MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
