LM3481QMMX - National Semiconductor

LM3481/LM3481Q

April 3, 2012

High Efficiency Low-Side N-Channel Controller for

Switching Regulators

General Description

The LM3481 is a versatile Low-Side N-FET high performance

controller for switching regulators. It is suitable for use in

topologies requiring a low-side FET, such as boost, flyback,

SEPIC, etc. The LM3481 can be operated at extremely high

switching frequencies in order to reduce the overall solution

size. The switching frequency of the LM3481 can be adjusted

to any value between 100 kHz and 1 MHz by using a single

external resistor or by synchronizing it to an external clock.

Current mode control provides superior bandwidth and tran-

sient response in addition to cycle-by-cycle current limiting.

Current limit can be programmed with a single external resis-

tor.

The LM3481 has built in protection features such as thermal

shutdown, short-circuit protection and over voltage protec-

tion. Power saving shutdown mode reduces the total supply

current to 5µA and allows power supply sequencing. Internal

soft-start limits the inrush current at start-up.

Key Specifications

■Wide supply voltage range of 2.97V to 48V

■100 kHz to 1 MHz Adjustable and Synchronizable clock

frequency

■±1.5% (over temperature) internal reference

■10 µA shutdown current (over temperature)

Features

■LM3481QMM in the MSOP-10 package are Automotive

Grade products that are AEC-Q100 grade 1 qualified (-40°

C to +125°C operating junction temperature)

■10-lead MSOP package

■Internal push-pull driver with 1A peak current capability

■Current limit and thermal shutdown

■Frequency compensation optimized with a capacitor and

a resistor

■Internal softstart

■Current Mode Operation

■Adjustable Undervoltage Lockout with Hysteresis

■Pulse Skipping at Light Loads

Applications

■Distributed Power Systems

■Notebook, PDA, Digital Camera, and other Portable

Applications

■Offline Power Supplies

■Set-Top Boxes

Typical Application Circuit

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Typical SEPIC Converter

LM3481/LM3481Q High Efficiency Low-Side N-Channel Controller for Switching Regulators

Connection Diagram

20136502

10-Lead Mini SOIC Package (MSOP-10 Package)

Package Marking and Ordering Information

Order Number** Package Type Package

Marking

Supplied As: Feature

LM3481MM/NOPB MSOP-10 SJPB 1000 units on Tape and Reel

LM3481MMX/NOPB MSOP-10 SJPB 3500 units on Tape and Reel

LM3481QMM/NOPB MSOP-10 SUAB 1000 units on Tape and Reel AEC-Q100 Grade 1

qualified. Automotive

Grade Production Flow*

LM3481QMMX/NOPB MSOP-10 SUAB 3500 units on Tape and Reel

*Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies.

Reliability qualification is compliant with the requirements and temperature grades defined in the AEC-Q100 standard. Automotive grade products are identified

with the letter Q. For more information go to http://www.national.com/automotive.

**Full order number to include /NOPB eg. LM3481MMX/NOPB.

Pin Descriptions

Pin Name Pin Number Description

ISEN 1Current sense input pin. Voltage generated across an external sense

resistor is fed into this pin.

UVLO 2 Under voltage lockout pin. A resistor divider from VIN to ground is

connected to the UVLO pin. The ratio of these resistances determine

the input voltage which allows switching and the hysteresis to disable

switching.

COMP 3 Compensation pin. A resistor and capacitor combination connected to

this pin provides compensation for the control loop.

FB 4 Feedback pin. Inverting input of the error amplifier.

AGND 5 Analog ground pin. Internal bias circuitry reference. Should be

connected to PGND at a single point.

FA/SYNC/SD 6 Frequency adjust, synchronization, and shutdown pin. A resistor

connected from this pin to ground sets the oscillator frequency. An

external clock signal at this pin will synchronize the controller to the

frequency of the clock. A high level on this pin for ≥ 30 µs will turn the

device off and the device will then draw 5 µA from the supply typically.

PGND 7 Power ground pin. External power circuitry reference. Should be

connected to AGND at a single point.

DR 8 Drive pin of the IC. The gate of the external MOSFET should be

connected to this pin.

VCC 9Driver supply voltage pin. A bypass capacitor must be connected from

this pin to PGND. See DRIVER SUPPLY CAPACITOR SELECTION

section.

VIN 10 Power supply input pin.

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LM3481/LM3481Q

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the Texas Instruments Sales Office/

Distributors for availability and specifications.

VIN pin Voltage -0.4V to 50V

FB Pin Voltage -0.4V to 6V

FA/SYNC/SD Pin Voltage -0.4V to 6V

COMP Pin Voltage -0.4V to 6V

UVLO Pin Voltage -0.4V to 6V

VCC Pin Voltage -0.4V to 6V

DR Pin Voltage -0.4V to 6V

ISEN Pin Voltage –0.4V to 600 mV

Peak Driver Output Current 1.0A

Power Dissipation Internally Limited

Storage Temperature Range −65°C to +150°C

Junction Temperature +150°C

ESD Susceptibilty

Human Body Model (Note 2) 2 kV

Lead Temperature

MM Package

Vapor Phase (60 sec.)

Infared (15 sec.)

215°C

220°C

Operating Ratings (Note 1)

Supply Voltage 2.97V to 48V

Junction Temperature Range −40°C to +125°C

Switching Frequency

Range 100 kHz to 1 MHz

Electrical Characteristics

VIN=12V, RFA=40 kΩ unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply

for TJ = 25°C. Limits appearing in boldface type apply over the full Operating Temperature Range (-40°C to 125°C). Datasheet

min/max specification limits are guaranteed by design, test, or statistical analysis. (Note 3, Note 4)

Symbol Parameter Conditions Min Typical Max Units

VFB Feedback Voltage VCOMP = 1.4V,

2.97 ≤ VIN ≤ 48V 1.256 1.275 1.294 V

ΔVLINE

Feedback Voltage Line

Regulation 2.97 ≤ VIN ≤ 48V 0.003 %/V

ΔVLOAD

Output Voltage Load

Regulation IEAO Source/Sink ±0.5 %/A

VUVLOSEN

Undervoltage Lockout

Reference Voltage VUVLO Ramping Down 1.345 1.430 1.517 V

IUVLO UVLO Source Current Enabled 356µA

VUVLOSD UVLO Shutdown Voltage 0.7 V

ICOMP COMP pin Current Sink VFB = 0V 640 µA

VCOMP VFB = 1.275V 1 V

fnom

Nominal Switching

Frequency RFA = 40 kΩ406 475 550 kHz

Vsync-HI

Threshold for

Synchronization on

FA/SYNC/SD pin

Synchronization Voltage

Rising 1.4 V

Vsync-LOW

Threshold for

Synchronization on

FA/SYNC/SD pin

Synchronization Voltage

Falling 0.7 V

RDS1 (ON)

Driver Switch On

Resistance (top) IDR = 0.2A, VIN= 5V 4 Ω

RDS2 (ON)

Driver Switch On

Resistance (bottom) IDR = 0.2A 2 Ω

VDR (max)

Maximum Drive Voltage

Swing(Note 6)

VIN < 6V VIN V

VIN ≥ 6V 6

Dmax Maximum Duty Cycle 85 %

tmin (on) Minimum On Time 250 ns

ISUPPLY Supply Current (switching) (Note 8) 3.7 5.0 mA

Quiescent Current in

Shutdown Mode

VFA/SYNC/SD = 3V(Note 9),

VIN = 12V 9 15

µA

VFA/SYNC/SD = 3V(Note 9),

VIN = 5V 5 10

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LM3481/LM3481Q

Symbol Parameter Conditions Min Typical Max Units

VSENSE

Current Sense Threshold

Voltage 100 160 190 mV

VSC

Over Load Current Limit

Sense Voltage 157 220 275 mV

VSL

Internal Compensation

Ramp Voltage 90 mV

VOVP

Output Over-voltage

Protection (with respect to

feedback voltage) (Note 7)

VCOMP = 1.4V 26 85 135 mV

VOVP(HYS)

Output Over-Voltage

Protection Hysteresis VCOMP = 1.4V 28 70 106 mV

Gm Error Amplifier

Transconductance VCOMP = 1.4V 216 450 690 µmho

AVOL

Error Amplifier Voltage

Gain

VCOMP = 1.4V

IEAO = 100 µA (Source/Sink) 35 60 66 V/V

IEAO

Error Amplifier Output

Current (Source/ Sink)

Source, VCOMP = 1.4V, VFB =

1.1V 475 640 837 µA

Sink, VCOMP = 1.4V, VFB = 1.4V 31 65 100 µA

VEAO

Error Amplifier Output

Voltage Swing

Upper Limit

VFB = 0V

COMP Pin Floating

2.45 2.70 2.93 V

Lower Limit

VFB = 1.4V 0.32 0.60 0.90 V

tSS Internal Soft-Start Delay VFB = 1.2V, COMP Pin Floating 15 ms

trDrive Pin Rise Time Cgs = 3000 pf, VDR = 0V to 3V 25 ns

tfDrive Pin Fall Time Cgs = 3000 pf, VDR = 3V to 0V 25 ns

VSD

Shutdown signal threshold

(Note 5) FA/SYNC/SD pin

Output = High (Shutdown) 1.31 1.40 V

Output = Low (Enable) 0.40 0.68 V

ISD

Shutdown Pin Current

FA/SYNC/SD pin

VSD = 5V −1 µA

VSD = 0V 20

TSD Thermal Shutdown 165 °C

Tsh

Thermal Shutdown

Hysteresis 10 °C

θJA Thermal Resistance MM Package 200 °C/W

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LM3481/LM3481Q

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings indicates conditions for which the device is

intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.

The guaranteed specifications apply only for the test conditions.

Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.

Note 3: All limits are guaranteed at room temperature (standard type face) and at temperature extremes (bold type face). All room temperature limits are 100%

tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate

Average Outgoing Quality Level (AOQL).

Note 4: Typical numbers are at 25°C and represent the most likely norm.

Note 5: The FA/SYNC/SD pin should be pulled to VIN through a resistor to turn the regulator off. The voltage on the FA/SYNC/SD pin must be above the max

limit for the Output = High longer than 30 µs to keep the regulator off and must be below the minimum limit for Output = Low to keep the regulator on.

Note 6: The drive pin voltage, VDR, is equal to the input voltage when input voltage is less than 6V. VDR is equal to 6V when the input voltage is greater than or

equal to 6V.

Note 7: The over-voltage protection is specified with respect to the feedback voltage. This is because the over-voltage protection tracks the feedback voltage.

The over-voltage threshold can be calculated by adding the feedback voltage (VFB) to the over-voltage protection specification.

Note 8: For this test, the FA/SYNC/SD Pin is pulled to ground using a 40 kΩ resistor .

Note 9: For this test, the FA/SYNC/SD Pin is pulled to 3V using a 40 kΩ resistor.

Typical Performance Characteristics Unless otherwise specified, VIN = 12V, TJ = 25°C.

Comp Pin Voltage vs. Load Current

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Switching Frequency vs. RFA

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Efficiency vs. Load Current (3.3VIN and 12VOUT)

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Efficiency vs. Load Current (5VIN and 12VOUT)

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LM3481/LM3481Q

Efficiency vs. Load Current (9VIN and 12VOUT)

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Frequency vs. Temperature

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COMP Pin Source Current vs. Temperature

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ISupply vs. Input Voltage (Non-Switching)

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ISupply vs. Input Voltage (Switching)

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Shutdown Threshold Hysteresis vs. Temperature

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LM3481/LM3481Q

Drive Voltage vs. Input Voltage

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Short Circuit Protection vs. VIN

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Current Sense Threshold vs. Input Voltage

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Compensation Ramp Amplitude vs. Input Voltage

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Minimum On-Time vs. Temperature

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LM3481/LM3481Q

Functional Block Diagram

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Functional Description

The LM3481 uses a fixed frequency, Pulse Width Modulated

(PWM), current mode control architecture. In a typical appli-

cation circuit, the peak current through the external MOSFET

is sensed through an external sense resistor. The voltage

across this resistor is fed into the ISEN pin. This voltage is then

level shifted and fed into the positive input of the PWM com-

parator. The output voltage is also sensed through an external

feedback resistor divider network and fed into the error am-

plifier (EA) negative input (feedback pin, FB). The output of

the error amplifier (COMP pin) is added to the slope compen-

sation ramp and fed into the negative input of the PWM

comparator.

At the start of any switching cycle, the oscillator sets the RS

latch using the SET/Blank-out and switch logic blocks. This

forces a high signal on the DR pin (gate of the external MOS-

FET) and the external MOSFET turns on. When the voltage

on the positive input of the PWM comparator exceeds the

negative input, the RS latch is reset and the external MOSFET

turns off.

The voltage sensed across the sense resistor generally con-

tains spurious noise spikes, as shown in Figure 1. These

spikes can force the PWM comparator to reset the RS latch

prematurely. To prevent these spikes from resetting the latch,

a blank-out circuit inside the IC prevents the PWM comparator

from resetting the latch for a short duration after the latch is

set. This duration, called the blank-out time, is typically 250

ns and is specified as tmin (on) in the electrical characteristics

section.

Under extremely light load or no-load conditions, the energy

delivered to the output capacitor when the external MOSFET

is on during the blank-out time is more than what is delivered

to the load. An over-voltage comparator inside the LM3481

prevents the output voltage from rising under these conditions

by sensing the feedback (FB pin) voltage and resetting the

RS latch. The latch remains in a reset state until the output

decays to the nominal value. Thus the operating frequency

decreases at light loads, resulting in excellent efficiency.

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LM3481/LM3481Q

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FIGURE 1. Basic Operation of the PWM comparator

OVER VOLTAGE PROTECTION

The LM3481 has over voltage protection (OVP) for the output

voltage. OVP is sensed at the feedback pin (FB). If at anytime

the voltage at the feedback pin rises to VFB + VOVP, OVP is

triggered. See the electrical characteristics section for limits

on VFB and VOVP.

OVP will cause the drive pin (DR) to go low, forcing the power

MOSFET off. With the MOSFET off, the output voltage will

drop. The LM3481 will begin switching again when the feed-

back voltage reaches VFB + (VOVP - VOVP(HYS)). See the elec-

trical characteristics section for limits on VOVP(HYS).

The internal bias of the LM3481 comes from either the internal

bias voltage generator as shown in the block diagram or di-

rectly from the voltage at the VIN pin. At input voltages lower

than 6V the internal IC bias is the input voltage and at voltages

above 6V the internal bias voltage generator of the LM3481

provides the bias.

SLOPE COMPENSATION RAMP

The LM3481 uses a current mode control scheme. The main

advantages of current mode control are inherent cycle-by-cy-

cle current limit for the switch and simpler control loop char-

acteristics. It is easy to parallel power stages using current

mode control since current sharing is automatic. However

there is a natural instability that will occur for duty cycles, D,

greater than 50% if additional slope compensation is not ad-

dressed as described below.

The current mode control scheme samples the inductor cur-

rent, IL, and compares the sampled signal, Vsamp, to a inter-

nally generated control signal, Vc. The current sense resistor,

RSEN, as shown in Figure 5, converts the sampled inductor

current, IL, to the voltage signal, Vsamp, that is proportional to

IL such that:

Vsamp = IL x RSEN

The rising and falling slopes, M1 and −M2 respectively, of

Vsamp are also proportional to the inductor current rising and

falling slopes, Mon and −Moff respectively. Where Mon is the

inductor slope during the switch on-time and −Moff is the in-

ductor slope during the switch off-time and are related to M1

and −M2 by:

M1 = Mon x RSEN

−M2 = −Moff x RSEN

For the boost topology:

Mon = VIN / L

−Moff = (VIN − VOUT) / L

M1 = [VIN / L] x RSEN

−M2 = [(VIN − VOUT) / L] x RSEN

M2 = [(VOUT − VIN) / L] x RSEN

Current mode control has an inherent instability for duty cy-

cles greater than 50%, as shown in Figure 2, where the control

signal slope, MC, equals zero. In Figure 2, a small increase in

the load current causes the sampled signal to increase by

ΔVsamp0. The effect of this load change, ΔVsamp1, at the end

of the first switching cycle is :

From the above equation, when D > 0.5, ΔVsamp1 will be

greater than ΔVsamp0. In other words, the disturbance is di-

vergent. So a very small perturbation in the load will cause

the disturbance to increase. To ensure that the perturbed sig-

nal converges we must maintain:

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LM3481/LM3481Q

20136509

FIGURE 2. Sub-Harmonic Oscillation for D>0.5

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FIGURE 3. Compensation Ramp Avoids Sub-Harmonic Oscillation

To prevent the sub-harmonic oscillations, a compensation

ramp is added to the control signal, as shown in Figure 3.

With the compensation ramp, ΔVsamp1 and the convergence

criteria are expressed by,

The compensation ramp has been added internally in the

LM3481. The slope of this compensation ramp has been se-

lected to satisfy most applications, and it's value depends on

the switching frequency. This slope can be calculated using

the formula:

MC = VSL x fS

In the above equation, VSL is the amplitude of the internal

compensation ramp and fS is the controller's switching fre-

quency. Limits for VSL have been specified in the electrical

characteristics section.

In order to provide the user additional flexibility, a patented

scheme has been implemented inside the IC to increase the

slope of the compensation ramp externally, if the need arises.

Adding a single external resistor, RSL(as shown in Figure 5)

increases the amplitude of the compensation ramp as shown

in Figure 4.

201365a1

FIGURE 4. Additional Slope Compensation Added Using

External Resistor RSL

Where,

ΔVSL = K x RSL

K = 40 µA typically and changes slightly as the switching fre-

quency changes. Figure 6 shows the effect the current K has

on ΔVSLand different values of RSL as the switching frequency

changes.

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LM3481/LM3481Q

A more general equation for the slope compensation ramp,

MC, is shown below to include ΔVSL caused by the resistor

RSL.

MC = (VSL + ΔVSL) x fS

It is good design practice to only add as much slope com-

pensation as needed to avoid subharmonic oscillation. Addi-

tional slope compensation minimizes the influence of the

sensed current in the control loop. With very large slope com-

pensation the control loop characteristics are similar to a

voltage mode regulator which compares the error voltage to

a saw tooth waveform rather than the inductor current.

20136513

FIGURE 5. Increasing the Slope of the Compensation

Ramp

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FIGURE 6. ΔVSL vs RSL

FREQUENCY ADJUST/SYNCHRONIZATION/SHUTDOWN

The switching frequency of the LM3481 can be adjusted be-

tween 100 kHz and 1 MHz using a single external resistor.

This resistor must be connected between the FA/SYNC/SD

pin and ground, as shown in Figure 7. Please refer to the typ-

ical performance characteristics to determine the value of the

resistor required for a desired switching frequency.

The following equation can also be used to estimate the fre-

quency adjust resistor.

Where fS is in kHz and RFA in kΩ.

The LM3481 can be synchronized to an external clock. The

external clock must be connected between the FA/SYNC/SD

pin and ground, as shown in Figure 8. The frequency adjust

resistor may remain connected while synchronizing a signal,

therefore if there is a loss of signal, the switching frequency

will be set by the frequency adjust resistor.

It is also necessary to have the width of the synchronization

pulse narrower than the duty cycle of the converter and to

have the synchronization pulse width ≥ 300 ns.

The FA/SYNC/SD pin also functions as a shutdown pin. If a

high signal (refer to the electrical characteristics section for

definition of high signal) appears on the FA/SYNC/SD pin, the

LM3481 stops switching and goes into a low current mode.

The total supply current of the IC reduces to 5 µA, typically,

under these conditions.

Figure 9 and Figure 10 shows an implementation of a shut-

down function when operating in frequency adjust mode and

synchronization mode respectively. In frequency adjust

mode, connecting the FA/SYNC/SD pin to ground forces the

clock to run at a certain frequency. Pulling this pin high shuts

down the IC. In frequency adjust or synchronization mode, a

high signal for more than 30 µs shuts down the IC.

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LM3481/LM3481Q

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FIGURE 7. Frequency Adjust

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FIGURE 8. Frequency Synchronization

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FIGURE 9. Shutdown Operation in Frequency Adjust Mode

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FIGURE 10. Shutdown Operation in Synchronization Mode

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LM3481/LM3481Q

Under Voltage Lockout (UVLO) Pin

The UVLO pin provides user programmable enable and shut-

down thresholds. The UVLO pin is compared to an internal

reference of 1.43V (typical), and a resistor divider programs

the enable threshold, VEN. When the IC is enabled, a 5 μA

current is sourced out of the UVLO pin, which effectively

causes a hysteresis, and the UVLO shutdown threshold,

VSH, is now lower than the enable threshold. Setting these

thresholds requires two resistors connected from the VIN pin

to the UVLO pin and from the UVLO pin to GND (see Figure

11). Select the desired enable, VEN, and UVLO shutdown,

VSH, threshold voltages and use the following equations to

determine the resistance values:

20136596

FIGURE 11. UVLO Pin Resistor Divider

If the UVLO pin function is not desired, select R8 and R7 of

equal magnitude greater than 100 kΩ. This will allow VIN to

be in control of the UVLO thresholds. The UVLO pin may also

be used to implement the enable/disable function. If a signal

pulls the UVLO pin below the 1.43V (typical) threshold, the

converter will be disabled.

Short Circuit Protection

When the voltage across the sense resistor (measured on the

ISEN Pin) exceeds 220 mV, short-circuit current limit gets ac-

tivated. A comparator inside the LM3481 reduces the switch-

ing frequency by a factor of 8 and maintains this condition until

the short is removed.

Typical Applications

The LM3481 may be operated in either continuous or discon-

tinuous conduction mode. The following applications are de-

signed for continuous conduction operation. This mode of

operation has higher efficiency and lower EMI characteristics

than the discontinuous mode.

BOOST CONVERTER

The most common topology for the LM3481 is the boost or

step-up topology. The boost converter converts a low input

voltage into a higher output voltage. The basic configuration

for a boost regulator is shown in Figure 12. In continuous

conduction mode (when the inductor current never reaches

zero at steady state), the boost regulator operates in two cy-

cles. In the first cycle of operation, MOSFET Q is turned on

and energy is stored in the inductor. During this cycle, diode

D1 is reverse biased and load current is supplied by the output

capacitor, COUT.

In the second cycle, MOSFET Q is off and the diode is forward

biased. The energy stored in the inductor is transferred to the

load and output capacitor. The ratio of these two cycles de-

termines the output voltage. The output voltage is defined as:

(ignoring the voltage drop across the MOSFET and the

diode), or

where D is the duty cycle of the switch, VD1 is the forward

voltage drop of the diode, and VQ is the drop across the MOS-

FET when it is on. The following sections describe selection

of components for a boost converter.

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FIGURE 12. Simplified Boost Converter Diagram (a) First cycle of operation. (b) Second cycle of operation

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LM3481/LM3481Q

POWER INDUCTOR SELECTION

The inductor is one of the two energy storage elements in a

boost converter. Figure 13 shows how the inductor current

varies during a switching cycle. The current through an in-

ductor is quantified as:

20136524

FIGURE 13. a. Inductor current b. Diode current c. Switch

current

If VL(t) is constant, diL(t)/dt must be constant. Hence, for a

given input voltage and output voltage, the current in the in-

ductor changes at a constant rate.

The important quantities in determining a proper inductance

value are IL (the average inductor current) and ΔiL (the induc-

tor current ripple difference between the peak inductor current

and the average inductor current). If ΔiL is larger than IL, the

inductor current will drop to zero for a portion of the cycle and

the converter will operate in discontinuous conduction mode.

If ΔiL is smaller than IL, the inductor current will stay above

zero and the converter will operate in continuous conduction

mode. All the analysis in this datasheet assumes operation in

continuous conduction mode. To operate in continuous con-

duction mode, the following conditions must be met:

IL > ΔiL

Choose the minimum IOUT to determine the minimum L. A

common choice is to set (2 x ΔiL) to 30% of IL. Choosing an

appropriate core size for the inductor involves calculating the

average and peak currents expected through the inductor. In

a boost converter,

IL_peak = IL(max) + ΔiL(max)

A core size with ratings higher than these values should be

chosen. If the core is not properly rated, saturation will dra-

matically reduce overall efficiency.

The LM3481 can be set to switch at very high frequencies.

When the switching frequency is high, the converter can op-

erate with very small inductor values. With a small inductor

value, the peak inductor current can be extremely higher than

the output currents, especially under light load conditions.

The LM3481 senses the peak current through the switch. The

peak current through the switch is the same as the peak cur-

rent calculated above.

PROGRAMMING THE OUTPUT VOLTAGE AND OUTPUT

CURRENT

The output voltage can be programmed using a resistor di-

vider between the output and the feedback pins, as shown in

Figure 14. The resistors are selected such that the voltage at

the feedback pin is 1.275V. RF1 and RF2 can be selected using

the equation,

A 100 pF capacitor may be connected between the feedback

and ground pins to reduce noise.

The maximum amount of current that can be delivered at the

output can be controlled by the sense resistor, RSEN. Current

limit occurs when the voltage that is generated across the

sense resistor equals the current sense threshold voltage,

VSENSE. Limits for VSENSE have been specified in the electrical

characteristics section. This can be expressed as:

Isw(peak) x RSEN = VSENSE- D x VSL

The peak current through the switch is equal to the peak in-

ductor current.

Isw(peak) = IL(max) + ΔiL

Therefore for a boost converter

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LM3481/LM3481Q

Combining the two equations yields an expression for RSEN

Evaluate RSEN at the maximum and minimum VIN values and

choose the smallest RSEN calculated.

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FIGURE 14. Adjusting the Output Voltage

CURRENT LIMIT WITH ADDITIONAL SLOPE

COMPENSATION

If an external slope compensation resistor is used (see Figure

5) the internal control signal will be modified and this will have

an effect on the current limit.

If RSL is used, then this will add to the existing slope compen-

sation. The command voltage, VCS, will then be given by:

VCS = VSENSE − D x (VSL + ΔVSL)

Where VSENSE is a defined parameter in the electrical char-

acteristics section and ΔVSL is the additional slope compen-

sation generated as discussed in the Slope Compensation

Ramp section. This changes the equation for RSEN to:

Note that since ΔVSL = RSL x K as defined earlier, RSLcan be

used to provide an additional method for setting the current

limit. In some designs RSL can also be used to help filter noise

to keep the ISEN pin quiet.

POWER DIODE SELECTION

Observation of the boost converter circuit shows that the av-

erage current through the diode is the average load current,

and the peak current through the diode is the peak current

through the inductor. The diode should be rated to handle

more than the inductor peak current. The peak diode current

can be calculated using the formula:

ID(Peak) = [IOUT/ (1−D)] + ΔiL

In the above equation, IOUT is the output current and ΔiL has

been defined in Figure 13.

The peak reverse voltage for a boost converter is equal to the

regulator output voltage. The diode must be capable of han-

dling this peak reverse voltage. To improve efficiency, a low

forward drop Schottky diode is recommended.

POWER MOSFET SELECTION

The drive pin, DR, of the LM3481 must be connected to the

gate of an external MOSFET. In a boost topology, the drain

of the external N-Channel MOSFET is connected to the in-

ductor and the source is connected to the ground. The drive

pin voltage, VDR, depends on the input voltage (see typical

performance characteristics). In most applications, a logic

level MOSFET can be used. For very low input voltages, a

sub-logic level MOSFET should be used.

The selected MOSFET directly controls the efficiency. The

critical parameters for selection of a MOSFET are:

1. Minimum threshold voltage, VTH(MIN)

2. On-resistance, RDS(ON)

3. Total gate charge, Qg

15 www.ti.com

LM3481/LM3481Q

4. Reverse transfer capacitance, CRSS

5. Maximum drain to source voltage, VDS(MAX)

The off-state voltage of the MOSFET is approximately equal

to the output voltage. VDS(MAX) of the MOSFET must be

greater than the output voltage. The power losses in the

MOSFET can be categorized into conduction losses and ac

switching or transition losses. RDS(ON) is needed to estimate

the conduction losses. The conduction loss, PCOND, is the

I2R loss across the MOSFET. The maximum conduction loss

is given by:

where DMAX is the maximum duty cycle.

At high switching frequencies the switching losses may be the

largest portion of the total losses.

The switching losses are very difficult to calculate due to

changing parasitics of a given MOSFET in operation. Often,

the individual MOSFET datasheet does not give enough in-

formation to yield a useful result. The following formulas give

a rough idea how the switching losses are calculated:

INPUT CAPACITOR SELECTION

Due to the presence of an inductor at the input of a boost

converter, the input current waveform is continuous and tri-

angular, as shown in Figure 13. The inductor ensures that the

input capacitor sees fairly low ripple currents. However, as the

input capacitor gets smaller, the input ripple goes up. The rms

current in the input capacitor is given by:

The input capacitor should be capable of handling the rms

current. Although the input capacitor is not as critical in a

boost application, low values can cause impedance interac-

tions. Therefore a good quality capacitor should be chosen in

the range of 100 µF to 200 µF. If a value lower than 100 µF is

used, then problems with impedance interactions or switching

noise can affect the LM3481. To improve performance, es-

pecially with VIN below 8V, it is recommended to use a 20Ω

resistor at the input to provide a RC filter. This resistor is

placed in series with the VIN pin with only a bypass capacitor

attached to the VIN pin directly (see Figure 15). A 0.1 µF or 1

µF ceramic capacitor is necessary in this configuration. The

bulk input capacitor and inductor will connect on the other side

of the resistor with the input power supply.

20136593

FIGURE 15. Reducing IC Input Noise

OUTPUT CAPACITOR SELECTION

The output capacitor in a boost converter provides all the out-

put current when the inductor is charging. As a result it sees

very large ripple currents. The output capacitor should be ca-

pable of handling the maximum rms current. The rms current

in the output capacitor is:

Where

and D, the duty cycle is equal to (VOUT − VIN)/VOUT.

The ESR and ESL of the output capacitor directly control the

output ripple. Use capacitors with low ESR and ESL at the

output for high efficiency and low ripple voltage. Surface

mount tantalums, surface mount polymer electrolytic and

polymer tantalum, Sanyo- OSCON, or multi-layer ceramic ca-

pacitors are recommended at the output.

DRIVER SUPPLY CAPACITOR SELECTION

A good quality ceramic bypass capacitor must be connected

from the VCC pin to the PGND pin for proper operation. This

capacitor supplies the transient current required by the inter-

nal MOSFET driver, as well as filtering the internal supply

voltage for the controller. A value of between 0.47µF and

4.7µF is recommended.

LAYOUT GUIDELINES

Good board layout is critical for switching controllers such as

the LM3481. First the ground plane area must be sufficient for

thermal dissipation purposes and second, appropriate guide-

lines must be followed to reduce the effects of switching noise.

Switch mode converters are very fast switching devices. In

such devices, the rapid increase of input current combined

with the parasitic trace inductance generates unwanted Ldi/

dt noise spikes. The magnitude of this noise tends to increase

as the output current increases. This parasitic spike noise

may turn into electromagnetic interference (EMI), and can al-

so cause problems in device performance. Therefore, care

must be taken in layout to minimize the effect of this switching

noise. The current sensing circuit in current mode devices can

be easily effected by switching noise. This noise can cause

duty cycle jitter which leads to increased spectral noise. Al-

though the LM3481 has 250 ns blanking time at the beginning

of every cycle to ignore this noise, some noise may remain

after the blanking time.

The most important layout rule is to keep the AC current loops

as small as possible. Figure 16 shows the current flow of a

boost converter. The top schematic shows a dotted line which

represents the current flow during on-state and the middle

www.ti.com 16

LM3481/LM3481Q

schematic shows the current flow during off-state. The bottom

schematic shows the currents we refer to as AC currents.

They are the most critical ones since current is changing in

very short time periods. The dotted lined traces of the bottom

schematic are the once to make as short as possible.

20136597

FIGURE 16. Current Flow In A Boost Application

The PGND and AGND pins have to be connected to the same

ground very close to the IC. To avoid ground loop currents

attach all the grounds of the system only at one point.

A ceramic input capacitor should be connected as close as

possible to the Vin pin and grounded close to the GND pin.

For a layout example please see Application Note 1204. For

more information about layout in switch mode power supplies

please refer to Application Note 1229.

COMPENSATION

For detailed explanation on how to select the right compen-

sation components to attach to the compensation pin for a

boost topology please see Application Note 1286. When cal-

culating the Error Amplifier DC gain, AEA, ROUT = 152 kΩ for

the LM3481.

17 www.ti.com

LM3481/LM3481Q

Designing SEPIC Using LM3481

Since the LM3481 controls a low-side N-Channel MOSFET,

it can also be used in SEPIC (Single Ended Primary Induc-

tance Converter) applications. An example of SEPIC using

the LM3481 is shown in Figure 17. As shown in Figure 17, the

output voltage can be higher or lower than the input voltage.

The SEPIC uses two inductors to step-up or step-down the

input voltage. The inductors L1 and L2 can be two discrete

inductors or two windings of a coupled transformer since

equal voltages are applied across the inductor throughout the

switching cycle. Using two discrete inductors allows use of

catalog magnetics, as opposed to a custom transformer. The

input ripple can be reduced along with size by using the cou-

pled windings of transformer for L1 and L2.

Due to the presence of the inductor L1 at the input, the SEPIC

inherits all the benefits of a boost converter. One main ad-

vantage of SEPIC over a boost converter is the inherent input

to output isolation. The capacitor CS isolates the input from

the output and provides protection against shorted or mal-

functioning load. Hence, the SEPIC is useful for replacing

boost circuits when true shutdown is required. This means

that the output voltage falls to 0V when the switch is turned

off. In a boost converter, the output can only fall to the input

voltage minus a diode drop.

The duty cycle of a SEPIC is given by:

In the above equation, VQ is the on-state voltage of the MOS-

FET, Q1, and VDIODE is the forward voltage drop of the diode.

POWER MOSFET SELECTION

As in a boost converter, the parameters governing the selec-

tion of the MOSFET are the minimum threshold voltage, VTH

(MIN), the on-resistance, RDS(ON), the total gate charge, Qg, the

reverse transfer capacitance, CRSS, and the maximum drain

to source voltage, VDS(MAX). The peak switch voltage in a

SEPIC is given by:

VSW(PEAK) = VIN + VOUT + VDIODE

The selected MOSFET should satisfy the condition:

VDS(MAX) > VSW(PEAK)

The peak switch current is given by:

Where ΔIL1 and ΔIL2 are the peak-to-peak inductor ripple cur-

rents of inductors L1 and L2 respectively.

The rms current through the switch is given by:

POWER DIODE SELECTION

The Power diode must be selected to handle the peak current

and the peak reverse voltage. In a SEPIC, the diode peak

current is the same as the switch peak current. The off-state

voltage or peak reverse voltage of the diode is VIN + VOUT.

Similar to the boost converter, the average diode current is

equal to the output current. Schottky diodes are recommend-

ed.

20136544

FIGURE 17. Typical SEPIC Converter

www.ti.com 18

LM3481/LM3481Q

SELECTION OF INDUCTORS L1 AND L2

Proper selection of the inductors L1 and L2 to maintain con-

stant current mode requires calculations of the following pa-

rameters.

Average current in the inductors:

IL2AVE = IOUT

Peak to peak ripple current, to calculate core loss if neces-

sary:

Maintaining the condition IL > ΔIL/2 to ensure continuous con-

duction mode yields the following minimum values for L1 and

L2:

Peak current in the inductor, to ensure the inductor does not

saturate:

IL1PK must be lower than the maximum current rating set by

the current sense resistor.

The value of L1 can be increased above the minimum rec-

ommended value to reduce input ripple and output ripple.

However, once ΔIL1 is less than 20% of IL1AVE, the benefit to

output ripple is minimal.

By increasing the value of L2 above the minimum recommen-

dation, ΔIL2 can be reduced, which in turn will reduce the

output ripple voltage:

where ESR is the effective series resistance of the output ca-

pacitor.

If L1 and L2 are wound on the same core, then L1 = L2 = L.

All the equations above will hold true if the inductance is re-

placed by 2L. A good choice for transformer with equal turns

is Coiltronics CTX series Octopack.

SENSE RESISTOR SELECTION

The peak current through the switch, ISWPEAK, can be adjusted

using the current sense resistor, RSEN, to provide a certain

output current. Resistor RSEN can be selected using the for-

mula:

Sepic Capacitor Selection

The selection of SEPIC capacitor, CS, depends on the rms

current. The rms current of the SEPIC capacitor is given by:

The SEPIC capacitor must be rated for a large ACrms current

relative to the output power. This property makes the SEPIC

much better suited to lower power applications where the rms

current through the capacitor is small (relative to capacitor

technology). The voltage rating of the SEPIC capacitor must

be greater than the maximum input voltage. Tantalum capac-

itors are the best choice for SMT, having high rms current

ratings relative to size. Ceramic capacitors could be used, but

the low C values will tend to cause larger changes in voltage

across the capacitor due to the large currents, and high C

value ceramics are expensive. Electrolytics work well for

through hole applications where the size required to meet the

rms current rating can be accommodated. There is an energy

balance between CS and L1, which can be used to determine

the value of the capacitor. The basic energy balance equation

is:

Where

is the ripple voltage across the SEPIC capacitor, and

is the ripple current through the inductor L1. The energy bal-

ance equation can be solved to provide a minimum value for

CS:

19 www.ti.com

LM3481/LM3481Q

Input Capacitor Selection

Similar to a boost converter, the SEPIC has an inductor at the

input. Hence, the input current waveform is continuous and

triangular. The inductor ensures that the input capacitor sees

fairly low ripple currents. However, as the input capacitor gets

smaller, the input ripple goes up. The rms current in the input

capacitor is given by:

The input capacitor should be capable of handling the rms

current. Although the input capacitor is not as critical in a

SEPIC application, low values can cause impedance interac-

tions. Therefore a good quality capacitor should be chosen in

the range of 100 µF to 200 µF. If a value lower than 100 µF is

used, then problems with impedance interactions or switching

noise can affect the LM3481. To improve performance, es-

pecially with VIN below 8V, it is recommended to use a 20Ω

resistor at the input to provide a RC filter. This resistor is

placed in series with the VIN pin with only a bypass capacitor

attached to the VIN pin directly (see Figure 15). A 0.1 µF or 1

µF ceramic capacitor is necessary in this configuration. The

bulk input capacitor and inductor will connect on the other side

of the resistor with the input power supply.

Output Capacitor Selection

The output capacitor of the SEPIC sees very large ripple cur-

rents similar to the output capacitor of a boost converter. The

rms current through the output capacitor is given by:

The ESR and ESL of the output capacitor directly control the

output ripple. Use capacitors with low ESR and ESL at the

output for high efficiency and low ripple voltage. Surface

mount tantalums, surface mount polymer electrolytic and

polymer tantalum, Sanyo- OSCON, or multi-layer ceramic ca-

pacitors are recommended at the output for low ripple.

Other Application Circuits

20136543

FIGURE 18. Typical High Efficiency Step-Up (Boost) Converter

www.ti.com 20

LM3481/LM3481Q

Physical Dimensions inches (millimeters) unless otherwise noted

10-Lead MSOP Package

NS Package Number MUB10A

21 www.ti.com

LM3481/LM3481Q

Notes

LM3481/LM3481Q High Efficiency Low-Side N-Channel Controller for Switching Regulators

www.ti.com

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