SENSOR +-+
-
ADC
PRESSURE
EMI HARDENED EMI HARDENED
+
-
V+R1
R2
INTERFERING
RF SOURCES
NO RF RELATED
DISTURBANCES
LMV861, LMV862
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SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
LMV861/LMV862 30 MHz Low Power CMOS, EMI Hardened Operational Amplifiers
Check for Samples: LMV861,LMV862
1FEATURES DESCRIPTION
TI’s LMV861 and LMV862 are CMOS input, low
2Unless Otherwise Noted, Typical Values at TApower op amp IC's, providing a low input bias current,
= 25°C, V+= 3.3V a wide temperature range of −40°C to +125°C and
• Supply Voltage 2.7V to 5.5V exceptional performance making them robust general
• Supply Current (per Channel) 2.25 mA purpose parts. Additionally, the LMV861 and LMV862
are EMI hardened to minimize any interference so
• Input Offset Voltage 1 mV Max they are ideal for EMI sensitive applications.
• Input Bias Current 0.1 pA The unity gain stable LMV861 and LMV862 feature
• GBW 30 MHz 30 MHz of bandwidth while consuming only 2.25 mA
• EMIRR at 1.8 GHz 105 dB of current per channel. These parts also maintain
• Input Noise Voltage at 1 kHz 8 nV/√Hz stability for capacitive loads as large as 200 pF. The
LMV861 and LMV862 provide superior performance
• Slew Rate 18 V/µs and economy in terms of power and space usage.
• Output Voltage Swing Rail-to-Rail This family of parts has a maximum input offset
• Output Current Drive 67 mA voltage of 1 mV, a rail-to-rail output stage and an
• Operating Ambient Temperature Range −40°C input common-mode voltage range that includes
to 125°C ground. Over an operating range from 2.7V to 5.5V
the LMV861 and LMV862 provide a PSRR of 93 dB,
APPLICATIONS and a CMRR of 93 dB. The LMV861 is offered in the
space saving 5-Pin SC70 package, and the LMV862
• Photodiode Preamp in the 8-Pin VSSOP.
• Weight Scale Systems
• Filters/Buffers
• Medical Diagnosis Equipment
Typical Application
Figure 1. EMI Hardened Sensor Application
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMV861, LMV862
SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Human Body Model 2 kV
ESD Tolerance(3) Charge-Device Model 1 kV
Machine Model 200V
VIN Differential ± Supply Voltage
Supply Voltage (VS= V+– V−) 6V
Voltage at Input/Output Pins V++0.4V
V−−0.4V
Storage Temperature Range −65°C to +150°C
Junction Temperature(4) +150°C
Soldering Information Infrared or Convection (20 sec) 260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(4) The maximum power dissipation is a function of TJ(MAX),θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
Operating Ratings(1)
Temperature Range(2) −40°C to +125°C
Supply Voltage (VS= V+– V−) 2.7V to 5.5V
Package Thermal Resistance (θJA(2)) 5-Pin SC70 302°C/W
8-Pin VSSOP 217°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
(2) The maximum power dissipation is a function of TJ(MAX),θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
3.3V Electrical Characteristics(1)
Unless otherwise specified, all limits are guaranteed for TA= 25°C, V+= 3.3V, V−= 0V, VCM = V+/2, and RL=10 kΩto V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
VOS Input Offset Voltage(4) ±273 ±1000 μV
1260
TCVOS Input Offset Voltage Temperature ±0.7 ±2.6 μV/°C
Drift(4)(5)
IBInput Bias Current(5) 0.1 10 pA
500
IOS Input Offset Current 1 pA
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No assurance of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ> TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting
distribution
(5) This parameter is specified by design and/or characterization and is not tested in production.
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SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
3.3V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are guaranteed for TA= 25°C, V+= 3.3V, V−= 0V, VCM = V+/2, and RL=10 kΩto V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
CMRR Common-Mode Rejection Ratio(4) 0.2V ≤VCM ≤V+- 1.2V 77 93 dB
75
PSRR Power Supply Rejection Ratio(4) 2.7V ≤V+≤5.5V, 77 93 dB
VOUT = 1V 76
EMIRR EMI Rejection Ratio, IN+ and IN−(6) VRF_PEAK = 100 mVP(−20 dBVP), 70
f = 400 MHz
VRF_PEAK = 100 mVP(−20 dBVP), 80
f = 900 MHz dB
VRF_PEAK = 100 mVP(−20 dBVP), 105
f = 1800 MHz
VRF_PEAK = 100 mVP(−20 dBVP), 110
f = 2400 MHz
CMVR Input Common-Mode Voltage Range CMRR ≥65 dB −0.1 2.1 V
AVOL Large Signal Voltage Gain(7) RL= 2 kΩ100 110
VOUT = 0.15V to 1.65V, 97
VOUT = 3.15V to 1.65V dB
RL= 10 kΩ100 113
VOUT = 0.1V to 1.65V, 98
VOUT = 3.2V to 1.65V
VOUT Output Voltage Swing High LMV861, 12 14
RL= 2 kΩto V+/2 18
LMV862, 12 16
RL= 2 kΩto V+/2 19
LMV861, 3 4
RL= 10 kΩto V+/2 5
LMV862, 3 6
RL= 10 kΩto V+/2 7mV from
either rail
Output Voltage Swing Low LMV861, 8 12
RL= 2 kΩto V+/2 16
LMV862, 10 14
RL= 2 kΩto V+/2 17
LMV861, 2 4
RL= 10 kΩto V+/2 5
LMV862, 3 7
RL= 10 kΩto V+/2 8
IOUT Output Short Circuit Current Sourcing, VOUT = VCM, 61 70
VIN = 100 mV 52 mA
Sinking, VOUT = VCM, 72 86
VIN =−100 mV 58
ISSupply Current LMV861 2.25 2.59
3.00 mA
LMV862 4.42 5.02
5.77
SR Slew Rate(8) AV= +1, VOUT = 1 VPP, 18 V/μs
10% to 90%
GBW Gain Bandwidth Product 30 MHz
ΦmPhase Margin 70 deg
enInput Referred Voltage Noise Density f = 1 kHz 8 nV/√Hz
f = 100 kHz 5
inInput Referred Current Noise Density f = 1 kHz 0.015 pA/√Hz
(6) The EMI Rejection Ratio is defined as EMIRR = 20log ( VRF_PEAK/ΔVOS).
(7) The specified limits represent the lower of the measured values for each output range condition.
(8) Number specified is the slower of positive and negative slew rates.
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3.3V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are guaranteed for TA= 25°C, V+= 3.3V, V−= 0V, VCM = V+/2, and RL=10 kΩto V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
ROUT Closed Loop Output Impedance f = 20 MHz 80 Ω
CIN Common-Mode Input Capacitance 21 pF
Differential-Mode Input Capacitance 15
THD+N Total Harmonic Distortion + Noise f = 1 kHz, AV= 1, BW ≥500 kHz 0.02 %
5V Electrical Characteristics(1)
Unless otherwise specified, all limits are ensured for T = 25°C, V+= 5V, V−= 0V, VCM = V+/2, and RL=10 kΩto V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
VOS Input Offset Voltage(4) ±273 ±1000 μV
1260
TCVOS Input Offset Voltage Temperature ±0.7 ±2.6 μV/°C
Drift(4)(5)
IBInput Bias Current(5) 0.1 10 pA
500
IOS Input Offset Current 1 pA
CMRR Common-Mode Rejection Ratio(4) 0V ≤VCM ≤V+–1.2V 78 94 dB
77
PSRR Power Supply Rejection Ratio(4) 2.7V ≤V+≤5.5V, 77 93 dB
VOUT = 1V 76
EMIRR EMI Rejection Ratio, IN+ and IN−(6) VRF_PEAK = 100 mVP(−20 dBVP), 70
f = 400 MHz
VRF_PEAK = 100 mVP(−20 dBVP), 80
f = 900 MHz dB
VRF_PEAK = 100 mVP(−20 dBVP), 105
f = 1800 MHz
VRF_PEAK = 100 mVP(−20 dBVP), 110
f = 2400 MHz
CMVR Input Common-Mode Voltage Range CMRR ≥65 dB −0.1 3.9 V
AVOL Large Signal Voltage Gain(7) RL= 2 kΩ103 111
VOUT = 0.15V to 2.5V, 100
VOUT = 4.85V to 2.5V dB
RL= 10 kΩ103 113
VOUT = 0.1V to 2.5V, 100
VOUT = 4.9V to 2.5V
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No assurance of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ> TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting
distribution
(5) This parameter is specified by design and/or characterization and is not tested in production.
(6) The EMI Rejection Ratio is defined as EMIRR = 20log ( VRF_PEAK/ΔVOS).
(7) The specified limits represent the lower of the measured values for each output range condition.
4Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
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SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for T = 25°C, V+= 5V, V−= 0V, VCM = V+/2, and RL=10 kΩto V+/2.
Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
VOUT Output Voltage Swing High, LMV861, 13 15
RL= 2 kΩto V+/2 19
LMV862, 13 17
RL= 2 kΩto V+/2 20
LMV861, 3 4
RL= 10 kΩto V+/2 5
LMV862, 3 6
RL= 10 kΩto V+/2 7mV from
either rail
Output Voltage Swing Low, LMV861, 10 14
RL= 2 kΩto V+/2 18
LMV862, 12 17
RL= 2 kΩto V+/2 20
LMV861, 3 4
RL= 10 kΩto V+/2 5
LMV862, 3 7
RL= 10 kΩto V+/2 8
IOUT Output Short Circuit Current Sourcing, VOUT = VCM, 90 150
VIN = 100 mV 86 mA
Sinking, VOUT = VCM, 90 150
VIN =−100 mV 86
ISSupply Current LMV861 2.47 2.84
3.27 mA
LMV862 4.85 5.63
6.35
SR Slew Rate(8) AV= +1, VOUT = 2VPP, 20 V/μs
10% to 90%
GBW Gain Bandwidth Product 31 MHz
ΦmPhase Margin 71 deg
enInput Referred Voltage Noise Density f = 1 kHz 8 nV/√Hz
f = 100 kHz 5
inInput Referred Current Noise Density f = 1 kHz 0.015 pA/√Hz
ROUT Closed Loop Output Impedance f = 20 MHz 60 Ω
CIN Common-Mode Input Capacitance 20 pF
Differential-Input Capacitance 15
THD+N Total Harmonic Distortion + Noise f = 1 kHz, AV= 1, BW ≥500 kHz 0.02 %
(8) Number specified is the slower of positive and negative slew rates.
Connection Diagram
Figure 2. 5-Pin SC70 Figure 3. 8-Pin VSSOP
(Top View) (Top View)
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Product Folder Links: LMV861 LMV862
VOUT (V)
VOS (µV)
12
9
6
3
0
-3
-6
-9
-12
012345
V+ = 5.0V, RL = 2k
VCM (V)
IB (pA)
5
4
3
2
1
0
-1
-2
-3
-4
-5
-1 0 1 2 3 4 5 6
3.3V
5V
TA = 25°C
VSUPPLY (V)
VOS (mV)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-40°C
25°C 85°C 125°C
TEMPERATURE (°C)
VOS (PV)
200
150
100
50
0
-50
-100
-150
-200
-50 -25 0 25 50 75 100 125
3.3V
5.0V
VCM (V)
VOS (mV)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
125°C 85°C
25°C
-40°C
V+ = 3.3V
VCM (V)
VOS (mV)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.5 0.5 1.5 2.5 3.5 4.5 5.5
125°C 85°C
25°C
-40°C
V+ = 5.0V
LMV861, LMV862
SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics
At TA= 25°C. RL= 10 kΩ, V+= 3.3V, V−= 0V, unless otherwise specified.
VOS vs. VCM at V+= 3.3V VOS vs. VCM at V+= 5.0V
Figure 4. Figure 5.
VOS vs. Supply Voltage VOS vs. Temperature
Figure 6. Figure 7.
VOS vs. VOUT Input Bias Current vs. VCM at 25°C
Figure 8. Figure 9.
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TEMPERATURE (°C)
SUPPLY CURRENT (mA)
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
-50 -25 0 25 50 75 100 125
3.3V
5.0V
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
-50 -25 0 25 50 75 100 125
3.3V
5.0V
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-40°C
25°C
85°C
125°C
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-40°C
25°C
85°C
125°C
VCM (V)
IBIAS (pA)
50
40
30
20
10
0
-10
-20
-30
-40
-50
-1 0 1 2 3 4 5 6
3.3V
5.0V
TA = 85°C
VCM (V)
IBIAS (pA)
500
400
300
200
100
0
-100
-200
-300
-400
-500
-1 0 1 2 3 4 5 6
3.3V
5.0V
TA = 125°C
LMV861, LMV862
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SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
Typical Performance Characteristics (continued)
At TA= 25°C. RL= 10 kΩ, V+= 3.3V, V−= 0V, unless otherwise specified.
Input Bias Current vs. VCM at 85°C Input Bias Current vs. VCM at 125°C
Figure 10. Figure 11.
Supply Current vs. Supply Voltage Single LMV861 Supply Current vs. Supply Voltage Dual LMV862
Figure 12. Figure 13.
Supply Current vs. Temperature Single LMV861 Supply Current vs. Temperature Dual LMV862
Figure 14. Figure 15.
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SUPPLY VOLTAGE (V)
VOUT FROM RAIL LOW (mV)
20
15
10
5
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-40°C
25°C
85°C 125°C
RL = 2k
SUPPLY VOLTAGE (V)
VOUT FROM RAIL LOW (mV)
5
4
3
2
1
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-40°C
25°C
85°C
125°C
RL = 10k
SUPPLY VOLTAGE (V)
VOUT FROM RAIL HIGH (mV)
20
15
10
5
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-40°C
25°C
85°C
125°C
RL = 2k
SUPPLY VOLTAGE (V)
VOUT FROM RAIL HIGH (mV)
5
4
3
2
1
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-40°C 25°C
85°C
125°C
RL = 10k
SUPPLY VOLTAGE (V)
ISINK (mA)
250
200
150
100
50
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-40°C 25°C
85°C 125°C
SUPPLY VOLTAGE (V)
ISOURCE (mA)
250
200
150
100
50
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
-40°C 25°C
85°C 125°C
LMV861, LMV862
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www.ti.com
Typical Performance Characteristics (continued)
At TA= 25°C. RL= 10 kΩ, V+= 3.3V, V−= 0V, unless otherwise specified.
Sinking Current vs. Supply Voltage Sourcing Current vs. Supply Voltage
Figure 16. Figure 17.
Output Swing High vs. Supply Voltage RL= 2 kΩOutput Swing High vs. Supply Voltage RL= 10 kΩ
Figure 18. Figure 19.
Output Swing Low vs. Supply Voltage RL= 2 kΩOutput Swing Low vs. Supply Voltage RL= 10 kΩ
Figure 20. Figure 21.
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Product Folder Links: LMV861 LMV862
CLOAD (pF)
PHASE(°)
80
70
60
50
40
30
20
10
0
1 10 100 1000
V+ = 3.3V, 5.0V
FREQUENCY (Hz)
PSRR (dB)
120
100
80
60
40
20
0
100 1k 10k 100k 1M 10M
3.3V
5.0V
5.0V
3.3V
+PSRR
-PSRR
PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
80
70
60
50
40
30
20
10
0
-40°C
GAIN
PHASE
CL = 5 pF
120
105
90
75
60
45
30
15
0
-40°C
25°C
85°C
125°C
25°C
85°C
125°C
100M10M1M100k10k
PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
80
70
60
50
40
30
20
10
0
10k 100k 1M 10M 100M
PHASE
GAIN
5 pF
100 pF
5 pF
100 pF
120
105
90
75
60
45
30
15
0
20 pF
50 pF
CL = 5 pF
= 20 pF
= 50 pF
= 100 pF
ILOAD (mA)
VOUT FROM RAIL (V)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 10 20 30 40 50 60 70 80
-40°C
SOURCE
125°C
SOURCE
-40°C
125°C
SINK
V+ = 3.3V
ILOAD (mA)
VOUT FROM RAIL (V)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 10 20 30 40 50 60 70 80
-40°C
125°C
V+ = 5.0V
SOURCE
-40°C
125°C
SINK
LMV861, LMV862
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SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
Typical Performance Characteristics (continued)
At TA= 25°C. RL= 10 kΩ, V+= 3.3V, V−= 0V, unless otherwise specified.
Output Voltage Swing vs. Load Current at V+= 3.3V Output Voltage Swing vs. Load Current at V+= 5.0V
Figure 22. Figure 23.
Open Loop Frequency Response vs. Temperature Open Loop Frequency Response vs. Load Conditions
Figure 24. Figure 25.
Phase Margin vs. Capacitive Load PSRR vs. Frequency
Figure 26. Figure 27.
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100 ns/DIV
20 mV/DIV
f = 1 MHz
AV = +1
VIN = 100 mVPP
100 ns/DIV
20 mV/DIV
f = 1 MHz
AV = +10
VIN = 10 mVPP
100 ns/DIV
100 mV/DIV
f = 1 MHz
AV = +1
VIN = 500 mVPP
100 ns/DIV
200 mV/DIV
f = 1 MHz
AV = +10
VIN = 100 mVPP
FREQUENCY (Hz)
CMRR (dB)
100
80
60
40
20
100 1k 10k 100k 1M 10M
V+ = 3.3V, 5.0V
AC CMRR
DC CMRR
FREQUENCY (Hz)
CHANNEL SEPARATION (dB)
160
140
120
100
80
60
1k 10k 100k 1M 10M
V+ = 3.3V, 5.0V
LMV861, LMV862
SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
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Typical Performance Characteristics (continued)
At TA= 25°C. RL= 10 kΩ, V+= 3.3V, V−= 0V, unless otherwise specified.
CMRR vs. Frequency Channel Separation vs. Frequency
Figure 28. Figure 29.
Large Signal Step Response with Gain = 1 Large Signal Step Response with Gain = 10
Figure 30. Figure 31.
Small Signal Step Response with Gain = 1 Small Signal Step Response with Gain = 10
Figure 32. Figure 33.
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FREQUENCY (Hz)
ROUT (Ö)
100
10
1
0.1
0.01
0.001
100
80
60
40
20
0
100 1k 10k 100k 1M 10M
AV = 10x
AV = 100x
AV = 1x
RF INPUT PEAK VOLTAGE (dBVp)
EMIRR V_PEAK (dB)
120
110
100
90
80
70
60
50
40
30
20
-40 -30 -20 -10 0 10
-40°C
25°C
125°C
85°C
fRF = 400 MHz
FREQUENCY (Hz)
THD + N (%)
0.1
0.01
0.001
0.0001
10 100 1k 10k 100k
BW = >500 kHz
V+=3.3V, VIN=320 mVPP
V+=5.0V, VIN=480 mVPP
V+=3.3V, VIN=2.3 VPP
V+=5.0V, VIN=3.8 VPP
AV = 1x
AV = 10x
VOUT (VPP)
THD + N (%)
10
1
0.1
0.01
0.001
1m 10m 100m 1 10
f = 1 kHz
BW = >500 kHz
V+ = 3.3V
AV = 10x
AV = 1x
V+ = 5.0V
SUPPLY VOLTAGE (V)
SLEWRATE (V/µs)
30
28
26
24
22
20
18
16
14
12
10
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
FALLING EDGE
RISING EDGE
AV = +1
CL = 5 pF
FREQUENCY (Hz)
NOISE (nV/ Hz)
100
10
1
10 100 1k 10k 100k 1M
V+ = 3.3V, 5.0V
LMV861, LMV862
www.ti.com
SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
Typical Performance Characteristics (continued)
At TA= 25°C. RL= 10 kΩ, V+= 3.3V, V−= 0V, unless otherwise specified.
Slew Rate vs. Supply Voltage Input Voltage Noise vs. Frequency
Figure 34. Figure 35.
THD+N vs. Frequency THD+N vs. Amplitude
Figure 36. Figure 37.
ROUT vs. Frequency EMIRR IN+ vs. Power at 400 MHz
Figure 38. Figure 39.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LMV861 LMV862
RF INPUT PEAK VOLTAGE (dBVp)
EMIRR V_PEAK (dB)
120
110
100
90
80
70
60
50
40
30
20
-40 -30 -20 -10 0 10
-40°C
25°C
125°C
85°C
fRF = 2400 MHz
FREQUENCY (MHz)
EMIRRV_PEAK (dB)
120
110
100
90
80
70
60
50
40
30
20
10 100 1000 10000
125°C
85°C
25°C
VPEAK = -20dBVp
V+ = 3.3V, 5.0V
VRF PEAK = -20 dBVp
-40°C
RF INPUT PEAK VOLTAGE (dBVp)
EMIRR V_PEAK (dB)
120
110
100
90
80
70
60
50
40
30
20
-40 -30 -20 -10 0 10
-40°C
25°C
125°C
85°C
fRF = 900 MHz
RF INPUT PEAK VOLTAGE (dBVp)
EMIRR V_PEAK (dB)
120
110
100
90
80
70
60
50
40
30
20
-40 -30 -20 -10 0 10
-40°C
25°C
125°C
85°C
fRF = 1800 MHz
LMV861, LMV862
SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
At TA= 25°C. RL= 10 kΩ, V+= 3.3V, V−= 0V, unless otherwise specified.
EMIRR IN+ vs. Power at 900 MHz EMIRR IN+ vs. Power at 1800 MHz
Figure 40. Figure 41.
EMIRR IN+ vs. Power at 2400 MHz EMIRR IN+ vs. Frequency
Figure 42. Figure 43.
12 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMV861 LMV862
VIN
+
-+
-
R1
1 k:
LMV86x Buffer VOUT
R11
1 k:
R2
1 k:
R12
995:V-
V+
P1
10:
V+BUFFER
V-BUFFER
LMV861, LMV862
www.ti.com
SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
APPLICATION INFORMATION
INTRODUCTION
The LMV861 and LMV862 are operational amplifiers with excellent specifications, such as low offset, low noise
and a rail-to-rail output. These specifications make the LMV861 and LMV862 great choices for medical and
instrumentation applications such as diagnosis equipment and power line monitors. The low supply current is
perfect for battery powered equipment. The small packages, SC70 package for the LMV861, and the VSSOP
package for the dual LMV862, make these parts a perfect choice for portable electronics. Additionally, the EMI
hardening makes the LMV861 and LMV862 a must for almost all op amp applications. Most applications are
exposed to Radio Frequency (RF) signals such as the signals transmitted by mobile phones or wireless
computer peripherals. The LMV861 and LMV862 will effectively reduce disturbances caused by RF signals to a
level that will be hardly noticeable. This again reduces the need for additional filtering and shielding. Using this
EMI resistant series of op amps will thus reduce the number of components and space needed for applications
that are affected by EMI, and will help applications, not yet identified as possible EMI sensitive, to be more robust
for EMI.
INPUT CHARACTERISTICS
The input common mode voltage range of the LMV861 and LMV862 includes ground, and can even sense well
below ground. The CMRR level does not degrade for input levels up to 1.2V below the supply voltage. For a
supply voltage of 5V, the maximum voltage that should be applied to the input for best CMRR performance is
thus 3.8V.
When not configured as unity gain, this input limitation will usually not degrade the effective signal range. The
output is rail-to-rail and therefore will introduce no limitations to the signal range.
The typical offset is only 0.273 mV, and the TCVOS is 0.7 μV/°C, specifications close to precision op amps.
CMRR MEASUREMENT
The CMRR measurement results may need some clarification. This is because different setups are used to
measure the AC CMRR and the DC CMRR.
The DC CMRR is derived from ΔVOS versus ΔVCM. This value is stated in the tables, and is tested during
production testing. The AC CMRR is measured with the test circuit shown in Figure 44.
Figure 44. AC CMRR Measurement Setup
The configuration is largely the usually applied balanced configuration. With potentiometer P1, the balance can
be tuned to compensate for the DC offset in the DUT. The main difference is the addition of the buffer. This
buffer prevents the open-loop output impedance of the DUT from affecting the balance of the feedback network.
Now the closed-loop output impedance of the buffer is a part of the balance. But as the closed-loop output
impedance is much lower, and by careful selection of the buffer also has a larger bandwidth, the total effect is
that the CMRR of the DUT can be measured much more accurately. The differences are apparent in the larger
measured bandwidth of the AC CMRR.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMV861 LMV862
+
-VOUT
VIN
RISO
CL
FREQUENCY (Hz)
CMRR (dB)
100
80
60
40
20
100 1k 10k 100k 1M 10M
V+ = 3.3V, 5.0V
AC CMRR
DC CMRR
LMV861, LMV862
SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
www.ti.com
One artifact from this test circuit is that the low frequency CMRR results appear higher than expected. This is
because in the AC CMRR test circuit the potentiometer is used to compensate for the DC mismatches. So,
mainly AC mismatch is all that remains. Therefore, the obtained DC CMRR from this AC CMRR test circuit tends
to be higher than the actual DC CMRR based on DC measurements.
The CMRR curve in Figure 45 shows a combination of the AC CMRR and the DC CMRR.
Figure 45. CMRR Curve
OUTPUT CHARACTERISTICS
As already mentioned the output is rail-to-rail. When loading the output with a 10 kΩresistor the maximum swing
of the output is typically 3 mV from the positive and negative rail.
The output of the LMV861 and LMV862 can drive currents up to 70 mA at 3.3V, and even up to 150 mA at 5V.
The LMV861 and LMV862 can be connected as non-inverting unity gain amplifiers. This configuration is the most
sensitive to capacitive loading. The combination of a capacitive load placed at the output of an amplifier along
with the amplifier’s output impedance creates a phase lag, which reduces the phase margin of the amplifier. If
the phase margin is significantly reduced, the response will be under damped which causes peaking in the
transfer and, when there is too much peaking, the op amp might start oscillating. The LMV861 and LMV862 can
directly drive capacitive loads up to 200 pF without any stability issues. In order to drive heavier capacitive loads,
an isolation resistor, RISO, should be used, as shown in Figure 46. By using this isolation resistor, the capacitive
load is isolated from the amplifier’s output, and hence, the pole caused by CLis no longer in the feedback loop.
The larger the value of RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the
feedback loop will be stable, independent of the value of CL. However, larger values of RISO result in reduced
output swing and reduced output current drive.
Figure 46. Isolating Capacitive Load
A resistor value of around 50Ωwould be sufficient. As an example some values are given in the following table,
for 5V and an open loop gain of 111 dB.
CLOAD RISO
300 pF 62Ω
400 pF 55Ω
500 pF 50Ω
14 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LMV861 LMV862
'VOS
VRF_PEAK
EMIRRVRF_PEAK= 20 log ¸
¸
¹
·
¨
¨
©
§
RF SIGNAL
VOUT OPAMP
(AV = 1)
NO RF RF
VOS + VDETECTED
VOS
LMV861, LMV862
www.ti.com
SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
When increasing the closed-loop gain the capacitive load can be increased even further. With a closed loop gain
of 2 and a 27Ωisolation resistor, the load can be 1 nF
EMIRR
With the increase of RF transmitting devices in the world, the electromagnetic interference (EMI) between those
devices and other equipment becomes a bigger challenge. The LMV861 and LMV862 are EMI hardened op
amps which are specifically designed to overcome electromagnetic interference. Along with EMI hardened op
amps, the EMIRR parameter is introduced to unambiguously specify the EMI performance of an op amp. This
section presents an overview of EMIRR. A detailed description on this specification for EMI hardened op amps
can be found in Application Note AN-1698.
The dimensions of an op amp IC are relatively small compared to the wavelength of the disturbing RF signals. As
a result the op amp itself will hardly receive any disturbances. The RF signals interfering with the op amp are
dominantly received by the PCB and wiring connected to the op amp. As a result the RF signals on the pins of
the op amp can be represented by voltages and currents. This representation significantly simplifies the
unambiguous measurement and specification of the EMI performance of an op amp.
RF signals interfere with op amps via the non-linearity of the op amp circuitry. This non-linearity results in the
detection of the so called out-of-band signals. The obtained effect is that the amplitude modulation of the out-of-
band signal is downconverted into the base band. This base band can easily overlap with the band of the op
amp circuit. As an example Figure 47 depicts a typical output signal of a unity-gain connected op amp in the
presence of an interfering RF signal. Clearly the output voltage varies in the rhythm of the on-off keying of the RF
carrier.
Figure 47. Offset voltage variation due to an interfering RF signal
EMIRR Definition
To identify EMI hardened op amps, a parameter is needed that quantitatively describes the EMI performance of
op amps. A quantitative measure enables the comparison and the ranking of op amps on their EMI robustness.
Therefore the EMI Rejection Ratio (EMIRR) is introduced. This parameter describes the resulting input-referred
offset voltage shift of an op amp as a result of an applied RF carrier (interference) with a certain frequency and
level. The definition of EMIRR is given by:
where
• VRF_PEAK is the amplitude of the applied un-modulated RF signal (V)
•ΔVOS is the resulting input-referred offset voltage shift (V) (1)
The offset voltage depends quadratically on the applied RF level, and therefore, the RF level at which the EMIRR
is determined should be specified. The standard level for the RF signal is 100 mVP. Application Note AN-1698
addresses the conversion of an EMIRR measured for an other signal level than 100 mVP. The interpretation of
the EMIRR parameter is straightforward. When two op amps have EMIRRs which differ by 20 dB, the resulting
error signals when used in identical configurations, differs by 20 dB as well. So, the higher the EMIRR, the more
robust the op amp.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMV861 LMV862
+
-
R1
50:
RFin
C1
22 pF
C2
10 µF
100 pF
VDD
VSS
Out
+
C3
100 pF
10 µF
+
C4
C5
LMV861, LMV862
SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
www.ti.com
Coupling an RF Signal to the IN+ Pin
Each of the op amp pins can be tested separately on EMIRR. In this section the measurements on the IN+ pin
(which, based on symmetry considerations, also apply to the IN- pin) are discussed. In Application Note AN-1698
the other pins of the op amp are treated as well. For testing the IN+ pin the op amp is connected in the unity gain
configuration. Applying the RF signal is straightforward as it can be connected directly to the IN+ pin. As a result
the RF signal path has a minimum of components that might affect the RF signal level at the pin. The circuit
diagram is shown in Figure 48. The PCB trace from RFIN to the IN+ pin should be a 50Ωstripline in order to
match the RF impedance of the cabling and the RF generator. On the PCB a 50Ωtermination is used. This 50Ω
resistor is also used to set the bias level of the IN+ pin to ground level. For determining the EMIRR, two
measurements are needed: one is measuring the DC output level when the RF signal is off; and the other is
measuring the DC output level when the RF signal is switched on. The difference of the two DC levels is the
output voltage shift as a result of the RF signal. As the op amp is in the unity gain configuration, the input
referred offset voltage shift corresponds one-to-one to the measured output voltage shift.
Figure 48. Circuit for coupling the RF signal to IN+
Cell Phone Call
The effect of electromagnetic interference is demonstrated in a setup where a cell phone interferes with a
pressure sensor application. The application is show in Figure 50.
This application needs two op amps and therefore a dual op amp is used. The op amp configured as a buffer
and connected at the negative output of the pressure sensor prevents the loading of the bridge by resistor R2.
The buffer also prevents the resistors of the sensor from affecting the gain of the following gain stage. The op
amps are placed in a single supply configuration.
The experiment is performed on two different op amps: a typical standard op amp and the LMV862, EMI
hardened dual op amp. A cell phone is placed on a fixed position a couple of centimeters from the op amps in
the sensor circuit.
When the cell phone is called, the PCB and wiring connected to the op amps receive the RF signal.
Subsequently, the op amps detect the RF voltages and currents that end up at their pins. The resulting effect on
the output of the second op amp is shown in Figure 49.
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Product Folder Links: LMV861 LMV862
TIME (0.5s/DIV)
VOUT (0.5V/DIV)
Typical Opamp
LMV862
LMV861, LMV862
www.ti.com
SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
Figure 49. Comparing EMI Robustness
The difference between the two types of op amps is clearly visible. The typical standard dual op amp has an
output shift (disturbed signal) larger than 1V as a result of the RF signal transmitted by the cell phone. The
LMV862, EMI hardened op amp does not show any significant disturbances. This means that the RF signal will
not disturb the signal entering the ADC when using the LMV862.
Figure 50. Pressure Sensor Application
DECOUPLING AND LAYOUT
Care must be given when creating a board layout for the op amp. For decoupling the supply lines it is suggested
that 10 nF capacitors be placed as close as possible to the op amp. For single supply, place a capacitor between
V+and V−. For dual supplies, place one capacitor between V+and the board ground, and a second capacitor
between ground and V−.
Even with the LMV861 and LMV862 inherent hardening against EMI, it is still recommended to keep the input
traces short and as far as possible from RF sources. Then the RF signals entering the chip are as low as
possible, and the remaining EMI can be, almost, completely eliminated in the chip by the EMI reducing features
of the LMV861 and LMV862.
LOAD CELL SENSOR APPLICATION
The LMV861 and LMV862 can be used for weight measuring system applications which use a load cell sensor.
Examples of such systems are: bathroom weight scales, industrial weight scales and weight measurement
devices on moving equipment such as forklift trucks.
The following example describes a typical load cell sensor application that can be used as a starting point for
many different types of sensors and applications. Applications in environments where EMI may appear would
especially benefit from the EMIRR performance of the LMV861 and LMV862.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LMV861 LMV862
R1
R3 x VSENSE +R5
R3
©
§x VDD
©
§
-
=+1x VREF R5
R3
VOUT
LMV861, LMV862
SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
www.ti.com
Load Cell Characteristics
The load cell used in this example is a Wheatstone bridge. The value of the resistors in the bridge changes when
pressure is applied to the sensor. This change of the resistor values will result in a differential output voltage
depending on the sensitivity of the sensor, the used supply voltage and the applied pressure. The difference
between the output at full scale pressure and the output at zero pressure is defined as the span of the load cell.
A typical value for the span is 10 mV/V.
The circuit configuration should be chosen such that loading of the sensor is prevented. Loading of the resistor
bridge due to the circuit following the sensor, could result in incorrect output voltages of the sensor.
Load Cell Example
Figure 51 shows a typical schematic for a load cell application. It uses a single supply and has an adjustment for
both positive and negative offset of the load cell. An ADC converts the amplified signal to a digital signal.
The op amps A1 and A2 are configured as buffers, and are connected at both the positive and the negative
output of the load cell. This is to prevent the loading of the resistor bridge in the sensor by the resistors
configuring the differential op amp circuit (op amp A4). The buffers also prevent the resistors of the sensor from
affecting the gain of the following gain stage. The third buffer (A3) is used to create a reference voltage, to
correct for the offset in the system.
Given the differential output voltage VSof the load cell, the output signal of this op amp configuration, VOUT,
equals:
(2)
To align the pressure range with the full range of an ADC the correct gain needs to be set. To calculate the
correct gain, the power supply voltage and the span of the load cell are needed. For this example a power supply
of 5V is used and the span of the sensor, in this case a 125 kg sensor, is 100 mV. With the configuration as
shown in Figure 51, this signal is covering almost the full input range of the ADC. With no weight on the load cell,
the output of the sensor and the op amp A4 will be close to 0V. With the full weight on the load cell, the output of
the sensor is 100 mV, and will be amplified with the gain from the configuration. In the case of the configuration
of Figure 51 the gain is R3/R1 = 51 kΩ/100Ω= 50. This will result in a maximum output of 100 mV x 50 = 5V,
which covers the full range of the ADC.
For further processing the digital signal can be processed by a microprocessor following the ADC, this can be
used to display or log the weight on the load cell. To get a resolution of 0.5 kg, the LSB of the ADC should be
smaller then 0.5 kg/125 kg = 1/1000. A 12-bit ADC would be sufficient as this gives 4096 steps. A 12-bit ADC
such as the two channel 12-bit ADC122S021 can be used for this application.
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Product Folder Links: LMV861 LMV862
CELL +-+
-
ADC
LOAD
+
-
R3
R1
100:
5 k:
VDD
VDD
LMV861
LMV861 VOUT
+
-
LMV861
R2
100:
R4
5 k:
+
-
LMV861
VDD
VDD
R5
5 k:
R6
80 k:
P1
20 k:
A1
A2
A3
A4
R6
80 k:
VREF
VSENSE
LMV861, LMV862
www.ti.com
SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
Figure 51. Load Cell Application
IR PHOTODIODE APPLICATION
The LMV861 and LMV862 are also very good choices to be used in photodiode applications, such as IR
communication, monitoring, etc. The large bandwidth of the LMV861 and LM862 makes it possible to create high
speed detection. This, together with the low noise, makes the LMV861 and LMV862 ideal for medical
applications such as fetal monitors and bed side monitors. Another application where the LMV861 and LMV862
would fit perfectly is a bill validator, an instrument to detect counterfeit bank notes. The following example
describes an application that can be used for different types of photodiode sensors and applications.
IR Photodiode Example
The circuit shown in Figure 53 is a typical configuration for the readout of a photodiode. The response of a
photodiode to incoming light is a variation in the diode current. In many applications a voltage is required, i.e.
when connecting to an ADC. Therefore the first step is to convert the diode signal current into a voltage by an I-V
converter. In Figure 53 the left op amp is configured as an I-V converter, with a gain set by R1.
Some types of photodiodes can have a large capacitance. This could potentially lead to oscillation. The addition
of resistor R2 isolates the photodiode capacitance from the feedback loop, thereby preventing the loop from
oscillating.
The capacitor in between the two op amp configurations, blocks the DC component, thus removing the DC offset
of the first op amp circuit, and the offset created by the ambient light entering the photodiode. The second op
amp amplifies the signal to levels that can be converted to a digital signal by an ADC. To prevent floating of the
input of the second op amp, resistor R5 is added. By allowing the input bias current of a few pA to flow through
this resistor a stable input is ensured.
In Figure 52 a sensed and amplified signal is shown from an IR source, in this case an IR remote control.
The data from the ADC can then be used by a DSP or microprocessor for further processing.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LMV861 LMV862
+
-
ADC
IR
Photodiode
+
-
R2
R1
100 k:
330:VDD
LMV861 LMV861 VOUT
R4
100:
VDD
VEE VEE
VEE
R3
100 k:
C1
1 nF
1 M:
R5
20 µs/DIV
1 V/DIV
LMV861, LMV862
SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
www.ti.com
Figure 52. IR Photodiode Signal
Figure 53. IR Photodiode Application
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LMV861, LMV862
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SNOSAZ5C –FEBRUARY 2008–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision B (March 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 19
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LMV861 LMV862
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMV861MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 AEA
LMV861MGE/NOPB ACTIVE SC70 DCK 5 250 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 AEA
LMV861MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 AEA
LMV862MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 AJ5A
LMV862MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 AJ5A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMV861MG/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV861MGE/NOPB SC70 DCK 5 250 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV861MGX/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV862MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMV862MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV861MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0
LMV861MGE/NOPB SC70 DCK 5 250 210.0 185.0 35.0
LMV861MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0
LMV862MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LMV862MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2013
Pack Materials-Page 2
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