SUMMIT SMT4004 MICROELECTRONICS, Inc. Quad Power Supply Controller FEATURES DESCRIPTION l Programmable Voltage and Current Monitoring The SMT4004 is a fully integrated programmable voltage manager IC, providing supervisory functions and tracking control for up to four independent power supplies. The four internal managers perform the following functions: Monitor source (bus-side) voltages for under- and overvoltage conditions, monitor each supply for over-current conditions, monitor back end (card-side) voltages for two staged levels of under-voltage conditions, insure power to the card-side logic tracks within the specified parametric limits, and provide supply status information to a host processor. w Monitors 4 independent supplies w Programmable Host-side Under- and OverVoltage Thresholds w Programmable Card-side Under-Voltage Monitors w Programmable Card-side Circuit Breaker Delay and QuickTripTM Threshold Levels l Programmable Card-side Trakker Function w Programmable Slew Rate Control w Guarantees and Enforces Supply Differential Tracking l Programmable Watchdog and Longdog Timers (0 to 6.4 seconds) l Operates From Any One of Four Supply Voltages l Nonvolatile Fault Register w Records Source of Any Interrupt The SMT4004 incorporates nonvolatile programmable circuits for setting all of the monitored thresholds for each manager. Individual functions are also programmable allowing interrupts or reset conditions to be generated by any combination of events. Because of a proprietary EEPROM technology that it employs it is also able to store fault conditions as they occur. In the case of a catastrophic failure the fault is recorded in the registers and then can be read for analysis. Programming of configuration, control and calibration values by the user can be simplified with the interface adapter and Windows GUI software obtainable from Summit Microelectronics. w Readable in "Dead Board" Environment l All Communications to Configuration Registers and Memory Array are via I2C Interface SIMPLIFIED APPLICATION DIAGRAM 5V 3.3V 2.5V GND1 GND2 GND3 GND4 VDD_CAP VO1 VO2 VO3 VO4 VG4 VG3 VG2 VG1 CB1 CB2 CB3 CB4 SMT4004 SDA SCL A0 A1 A2 VI1 VI2 VI3 VI4 1.8V OPTIONAL CROWBAR CROWBAR 100 GND I2C (c)SUMMIT MICROELECTRONICS, Inc., 2001 * 300 Orchard City Dr., Suite 131 * Campbell, CA 95008 * Phone 408-378-6461 * FAX 408-378-6586 * www.summitmicro.com Characteristics subject to change without notice 2049 3.1 3/19/01 1 SMT4004 FUNCTIONAL BLOCK DIAGRAM PWR_ON FORCE_SD SEATED1# SEATED2# MR# IRQ_CLR# 33 27 11 10 6 5 UV_OVERRIDE 12 7 IRQ# 13 RST1# VO1 20 CB1 37 VI1 41 VO2 21 CB2 36 VI2 40 14 RST2# SUPPLY MANAGER #1 RESET & STATUS OUTPUT CONTROL LOGIC 16 RST4# 3 CROWBAR 25 CBFAULT SEQUENCE ENABLE LOGIC SUPPLY MANAGER #2 15 RST3# 26 HEALTHY# 32 VGATE1 31 VGATE2 VO3 22 CB3 35 VI3 39 VO4 23 CB4 34 VI4 38 CHARGE PUMP & VGATE CONTROL SUPPLY MANAGER #3 30 VGATE3 29 VGATE4 28 VGG_CAP 24 ENABLE SUPPLY MANAGER #4 TRAKKER LOGIC 9 TRKR_IRQ# All Resistors are 100k 48 WLDI TIMER LOGIC 1.25VREF 1 LDO# 2 WDO# 4 43 A0 POWER SUPPLY ARBITRATION MEMORY & 2-WIRE BUS INTERFACE 44 A1 45 A2 46 SDA 47 SCL 42 2 18 8 VDD_CAP PGND 19 DGND AGND 2049 3.1 3/19/01 17 PGND 2049 BD 2.2 SUMMIT MICROELECTRONICS, Inc. SMT4004 PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 WLDI SCL SDA A2 A1 A0 VDD_CAP VI1 VI2 VI3 VI4 CB1 48-Pin TQFP 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 CB2 CB3 CB4 PWR_ON VGATE1 VGATE2 VGATE3 VGATE4 VGG_CAP FORCE_SD HEALTHY# CBFAULT RST1# RST2# RST3# RST4# PGND DGND AGND VO1 VO2 VO3 VO4 ENABLE 13 14 15 16 17 18 19 20 21 22 23 24 LDO# WDO# CROWBAR 1.25VREF MR# IRQ_CLR# IRQ# PGND TRKR_IRQ# SEATED1# SEATED2# UV_OVERRIDE 2049 PCon 2.1 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ....................... -55C to 125C Storage Temperature ............................ -65C to 150C Lead Solder Temperature (10 secs) ................... 300 C Terminal Voltage with Respect to GND: V0, V1, V2, and V3 ........... -0.3V to 6.0V All Others ........................ -0.3V to 6.0V *COMMENT Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RECOMMENDED OPERATING CONDITIONS Temperature -40C to 85C. Voltage 2.7V to 5.5V SUMMIT MICROELECTRONICS, Inc. 2049 3.1 3/19/01 3 SMT4004 DC OPERATING CHARACTERISTICS (Over Recommended Operating Conditions; Voltages are relative to GND) Symbol Parameter Notes Min. VI Supply voltages VI1 through VI4 Highest VI (2.7V) powers the SMT4004 2.7 IDD On IDD Off Power supply current PWR_ON and ENABLE active Programmable VI input threshold 8-bit resolution, 20mV/bit range VIHYS OV/UV trip hysteresis 15 Programmable. Set by Register R1B, data bits D1 & D0, respectively VQCB Quick-trip voltage VREF 1.25VREF output voltage RLOAD = 2k VVG Off IVG SRVG VGATE drive output voltage POVT OVHYS Input low voltage VOL Open drain outputs Crowbar output pulse width tCROW mA mA 6.0 V 25 mV 40 mV 0 0 25 s 0 1 50 s 1 0 100 s 1 1 200 s 0 0 Off 0 1 75 mV 1 0 100 mV 1 1 150 1.23 1.25 mV 1.27 V VGSINK = 1mA 0 0.4 V 80 A 0 0 40 100 140 V/s 0 1 100 250 350 V/s 1 0 200 500 700 V/s 1 1 400 1000 1400 V/s VO pins, delta differential allowed 8-bit resolution, 20mV/bit 100 0.9 OV input hysteresis VIL 3 0.1 V VGATE output voltage slew rate Input high voltage V 16 Programmable. Set by Register R10, data bits D3 & D2 or D1 & D0, respectively VIH 5.5 14 MOSFET switches On Programmable card-side voltage threshold range Units MOSFET switches On VGATE drive output current SRDELTA TRAKKER slew differential Max. 10 Programmable. Set by Register R1A, data bits D7 & D6 (e.g.), respectively VVG On 0.9 Circuit breaker trip voltage CBDELAY Over-current filter 1 ENABLE inactive PVIT VCB Typ. mV 6.0 10 V mV VI = 2.7V 0.9 x VI VI V VI = 5V 0.7 x VI VI V VI = 2.7V -0.1 0.1 x VI V VI = 5V -0.1 0.3 x VI V ISINK = 2mA 0 0.4 V 2.5V min. into 1k 16 28 s 2049 Elect Table 1.1 4 2049 3.1 3/19/01 SUMMIT MICROELECTRONICS, Inc. SMT4004 PIN DESCRIPTIONS AND DEVICE OPERATION THE TRAKKER SUPPLY VOLTAGES SUPPLY MANAGERS The VI inputs of all four supply managers are diode ORed and tied to the device's internal VDD node. The TRAKKER will use the highest VI input for its supply voltage. At least one VI input must be at or above 2.7V for proper device operation. The electrical placement of the SMT4004 on a printed circuit card is such that it separates the host power supply and any on-board DC-to-DC converters (or LDOs) from the backend circuitry such as multiple DSPs, microprocessors and associated glue logic. The host supplies, and any other regulated voltages that will be "switched" by the device, are referred to as bus-side voltages. The voltages that are on the backend circuitry side of the switches are referred to as card-side voltages. VDD_CAP -- Charge storage connection for the chip's internal power supply. For most applications a 10F capacitor should be connected to his pin. VGG_CAP -- This pin should be tied to a capacitor to be charged by the charge pump. The capacitor should be of sufficient size so as to provide current to the VGATE outputs under varying load conditions. PGND -- Power ground The four supply manager blocks are identical. Each contains three primary functional blocks: the first monitors the bus-side voltages, the second monitors the card-side voltages, and the third monitors over-current conditions for that particular supply. DGND -- Digital Ground BUS-SIDE MANAGEMENT AGND -- Analog Ground Figure 1 illustrates the functional blocks of the four supply managers. Each manager block can be independently enabled or electrically removed from the device. TIMERS LDO# -- The longdog timer output is an active-low opendrain output that can be wire-ORed with other open-drain signals. The longdog timer is generally programmed to generate an output at a time interval longer than the watchdog timer. The time interval is programmed in Register R1C. WDO# -- The watchdog timer output is an active-low open-drain output that can be wire-ORed with other opendrain signals. The watchdog timer is generally programmed to generate an output at a time interval shorter than the longdog timer. The time interval is programmed in Register R1C. WLDI -- Watchdog and longdog timer reset input. A lowto-high transition on this pin will reset both the watchdog timer and the longdog timer. The watchdog and longdog work in tandem: resetting one resets the other. Generally, the longdog will be programmed to time out sometime after the watchdog. As an example, the WDO# output could be used to generate a warning interrupt and the LDO# output could be tied to a system reset line. Both timers can be turned off, facilitating system debug and also allowing operating systems to `boot up' and configure themselves without interrupts or resets. SUMMIT MICROELECTRONICS, Inc. The VI input monitors the bus-side voltage for both undervoltage and over-voltage conditions. The thresholds for the under-voltage detection for VI inputs are programmed in Registers R00 through R03. The VI input is effectively the VREF of a nonvolatile DAC. The DAC has been designed so that the threshold can be determined by multiplying the binary value of the Register times 20mV and adding that to 0.9V in the formula PVIT = 0.9V + (0.2mV x n), where n is the register value (0 - 255 decimal). This allows very precise monitoring of voltages in the range of 0.9V to 6V without the use of external resistor divider networks. The over-voltage level is determined by the value in registers R04 through R07, and is selected by the SMT4004 GUI. All enabled manager blocks must ensure their respective VI inputs are within the programmed limits before the VGATE outputs can be turned on and the TRAKKER logic enabled. The VI comparator outputs can also be used to generate a general interrupt. It should be noted that either one or both of the bus-side monitors could be disabled via Registers R04 through R07. 2049 3.1 3/19/01 5 SMT4004 VIX - + OV Comparator VGATE Enable + VREF CBX Programmable Delay UV - Comparator + 25mV VGATE and TRAKKER Logic Circuit Breaker Comparator ( = Programmable) - OC To IRQ + - Quick Trip Comparator Programmable Quick Trip Threshold VOX Quick Trip To Crowbar - + To RST UV1 Comparator + VREF - UV2 Comparator 2049 Fig01 1.0 Figure 1. Supply Manager Circuit CARD-SIDE MANAGEMENT On the card-side the TRAKKER monitors two programmable under-voltage thresholds on the VO inputs: UV1 and UV2. UV1 can be used to generate a warning interrupt that the supply is decaying, and UV2 can be used to generate a reset condition or a crowbar output. The cardside under-voltage (UV1) threshold value is programmed in Registers R08 through R0B. Like the bus-side thresholds the levels can be programmed in 20mV increments (on top of 0.9V). The second level (UV2) is determined by 6 the value in Registers R0C through R0F, and is selected by the SMT4004 GUI. It should be noted that either one or both of the card-side monitors can be disabled via Registers R0C through R0F. OVER-CURRENT PROTECTION The CB inputs are the circuit breaker inputs for the supply voltages. With a series resistor placed in the supply path between VI and CB the circuit breaker will trip whenever the voltage across the resistor exceeds 25mV. 2049 3.1 3/19/01 SUMMIT MICROELECTRONICS, Inc. SMT4004 The on-board electronic circuit breaker can be programmed to application specific levels. The circuit breaker delay defines the period of time the voltage drop across RS is greater than 25mV but less than VQCB before the VGATE output will be shut down. This is effectively a filter to prevent spurious shutdowns of VGATE. The delays that can be programmed are 25s, 50s, 100s and 200s. The programmable delay bits are located in Register R1B. The Quick-Trip circuit breaker threshold (VQCB) can be set to 150mV, 100mV, 75mV or off (Register R1A). This is the threshold voltage drop across RS that is placed between VSS and CBSENSE. If the voltage drop exceeds the programmed threshold, the electronic circuit breaker will immediately trigger with no delay. The outputs of these comparators can be used to generate interrupts and reset conditions and toggle the crowbar output. POWER-ON SEQUENCING In order to begin sequencing of the card-side supplies (ramping the VGATE outputs) a number of conditions must be met. All enabled bus-side voltages must be above their respective under-voltage thresholds, the card-side voltages (e.g., residual capacitor stored potentials) must be near zero volts, and the following inputs must be properly set. ENABLE -- When active the ENABLE input brings the IC out of a standby mode where the charge pump supplying the VGATE outputs is turned on (and begins charging the VGG_CAP) and the bandgap reference is turned on. The ENABLE input can be programmed to be either active low (default from the factory) or active high (Register R1B). SEATED1# and SEATED2# -- the SEATED inputs are effectively two additional enable inputs that must be low to enable the sequencing of the card-side voltages. In a staggered pin environment these inputs can be tied to the "short" pins, insuring the card is fully seated before any power is applied to the cardside logic. These inputs can also be tied to card insertion switches to indicate proper seating. PWR_ON -- the PWR_ON input is the last input that will typically be driven to enable power sequencing to the card-side. The PWR_ON input can be programmed to be either active low (default from the factory) or active high (Register R1B). SUMMIT MICROELECTRONICS, Inc. TRAKKING AND SOFTSTART CONTROL VGATE -- The VGATE outputs are used to control the "turning-on" of the card-side voltages. The ramp rate (for both turn-on and turn-off) of the outputs is programmable from 100V/s to 1000V/s (Register R10). The four outputs ramp at the same slew-rate, so normally there will be no differential voltage between any of the supplies until each reaches its maximum level. The ramp rates are inherently adaptive. That is, if the difference between any VO input is greater than 100mV in the linear region, the slew rate will be increased or decreased to minimize the differential. The comparisons are made between VO1 and VO2, VO2 and VO3, VO3 and VO4, and VO4 and VO1. If at any time a differential of greater than 300mV is detected a pre-programmed (Register R10) action can be taken. The TRAKKER can shut down the offending supply, generate an interrupt output, or ignore the situation. If SoftStart is enabled (Registers R0C through R0F) the supply or supplies designated will be ramped as soon as the input conditions are met and no Trakking will be performed. Any supply not designated as a softstart supply will not be ramped until the designated supply has reached its VO threshold. This type of operation would commonly be used where a bus voltage (e.g., 5V) is first switched to a DC-to-DC converter or group of LDOs; and then their outputs would be switched in a Trakking mode to the card-side logic. Supply managers designated for Trakking will not begin start-up until the soft start channels are fully turned on. The delay is approximated by the formula tD =16,000 / SR, where tD is the time delay in milliseconds between the PWR_ON signal going high and the start of the tracking ramp-up, and SR is the programmed start-up slew rate in V/s. For example, the time delay for a programmed slew rate of 500V/s is: tD = 16,000 / 500 = 32ms. POWER MANAGEMENT STATUS OUTPUTS The TRAKKER has two types of status outputs that it provides to the host system or host processor resident on its board. One type of output is "hardwired" internally and the other is programmable. HEALTHY# -- The HEALTHY output is an active-low open-drain output that can be wire-ORed with other opendrain signals. It is driven low when all of the enabled managers' card-side voltages are valid and there are no over-current conditions. The signal is used to indicate the power supplies are within their programmed operating limits. 2049 3.1 3/19/01 7 SMT4004 CBFAULT -- CBFAULT is driven active whenever an over-current condition is detected. It is a programmable output that can be either an active high or active low (factory default) output. RESETS RST1# to RST4# -- Associated with each manager is a reset output. They are active-low open-drain outputs that can be wire-ORed with other open-drain signals. The user can select UV1, UV2 and/or an over-current condition as the trigger for the reset pulse by programming Registers R11 and R12 (the default condition from the factory is all conditions generate a reset). The reset pulse width is adjustable by writing to Register R1C (default condition from the factory is pulse of 200ms). MR# -- When driven low the manual reset input will automatically drive all four reset outputs low. During programming the MR# input must be pulled low. INTERRUPTS Whenever an interrupt is generated the cause of the fault will be recorded in the nonvolatile status Register. In order to avoid false recordings during power-down situations, no faults will be recorded if the PWR_ON input has been deactivated. The fault Registers are located at R1D through R1F. The fault source is indicated by a "1" in the assigned bit location. Overwriting the fault Register with "0's" is the only way to clear a recorded fault condition. CROWBAR -- The CROWBAR output is another form of status output. The conditions to generate a crowbar output are programmable in Register R19. Whenever one of the conditions occurs the CROWBAR output will strobe. Rapid shutdown of the card-side supplies may be required to prevent damage to the DSP's or microprocessors. The VGATE outputs will be shut down when CROWBAR occurs. SCRs with a fast turn-on time make excellent crowbar devices and only need a pulse of gate current to `trigger.' MEMORY AND REGISTER ACCESS IRQ# -- the IRQ# output is an active low open-drain output that is driven low whenever one or more of its programmed triggers is active. There are twenty programmable sources for generating the interrupt: bus-side over- and under-voltage, card-side under-voltage 1 and 2, and an over-current condition. Each source is individually enabled by writing to Registers R13, R14 and R15. The default from the factory is to enable all sources. The IRQ# output can only be cleared by bringing IRQ_CLR# low, or after a power-down/power-up sequence. TRKR_IRQ# -- the TRAKKER interrupt indicates there was a skew of greater than 300mV during the power on cycle. The source of the TRKR_IRQ# is programmable and can be initiated by any one of the managers. The configuration Registers R11 and R12 select the source of interrupt. Configuration Register R10 enables the TRKR_IRQ# output (or one of three other options). The default from the factory is to enable all sources. The TRKR_IRQ# output can only be cleared by bringing IRQ_CLR# low or after a power-down/power-up sequence. In order to avoid false interrupts during a power-on sequence there is a programmable "power-on interrupt holdoff" register. The delay can be programmed from 200ms to 1600ms. The interrupt hold-off is in Register R15 and its default value from the factory will be 1600ms. 8 FAULT REGISTER A0, A1 & A2 -- The address pins are biased either to the highest VI pin or GND, and provide a mechanism for assigning a unique address to the SMT4004. SDA -- SDA is a bidirectional serial data pin. It is configured as an open drain output and will require a pullup to the highest VI pin. SCL -- SCL is the serial clock input. MISCELLANEOUS MANAGER SIGNALS 1.25VREF -- This pin is a 1.25V Reference output that can be used in conjunction with external circuitry. UV_OVERRIDE -- The Under-Voltage Override input will disable the under-voltage comparators. This can be used for board test and also during system margining. FORCE_SD -- When asserted the Force Shut Down input will immediately clamp the VGATE outputs to ground. This can be used in conjunction with the CROWBAR. The active level for FORCE_SD is programmable and accessible in Register R1B. 2049 3.1 3/19/01 SUMMIT MICROELECTRONICS, Inc. SMT4004 REGISTER FORMATS AND FUNCTIONS There are four basic register types. The first are those that set a monitoring threshold where the binary value written to the register is multiplied times the base incremental voltage. The second type enables or disables a specific function: unless otherwise indicated a "1" will always enable the function and a "0" will disable or deselect that function. Note: only the enabled condition will be depicted in the following tables. The third Register type allows selection of various timer values. These are not incremen- tal, like the thresholds, but specific bit patterns select specific timer values. The fourth register type is the nonvolatile fault register that records fault conditions. A "0" in any bit location indicates its corresponding monitor function was within specified limits when the fault occurred. A "1" in any bit location indicates its corresponding monitor function was outside its specified limits when the fault occurred. Bus-side Under-voltage Threshold Registers 00, 01, 02 and 03 are identical. Their contents select the under-voltage threshold for the VI1, VI2, VI3 and VI4 inputs, respectively. Register R00, R01, R02, R03 D7 D6 D5 D4 D3 D2 D1 D0 Action 1 1 1 1 1 1 1 1 Highest threshold adjustment = 6.0V 0 0 0 0 0 0 0 0 Lowest threshold adjustment = 0.9V 0 0 0 0 0 0 1 0 Threshold = 0.9V + (2 x .02V) = 0.94V, e.g. 2049 Table01 1.0 Bus-side Under-voltage Threshold Enable and Over-voltage Offset * Note: In Register 4 (only) Bit 7 can be set to allow tracking to begin even when the card side voltages haven't bled down to zero. Registers 04*, 05, 06 and 07 are identical. Their contents determine whetheror not the under- or over-voltage capabilities are enabled, and establish the over-voltage offset value for the VI1, VI2, VI3 and VI4 inputs, respectively. Register R04, R05, R06, R07 D7 D6 D5 D4 D3 D2 D1 D0 Action x* 1 x x x x x x Enables under voltage detection x x 1 x x x x x Enables over voltage detection x x x 0 0 0 1 0 Threshold configuration selected by SMT4004 GUI 2049 Table02 1.1 Card-side Under-voltage Threshold Registers 08, 09, 0A and 0B are identical. Their contents select the under-voltage threshold for the VO1, VO2, VO3 and VO4 inputs, respectively. Register R08, R09, R0A, R0B D7 D6 D5 D4 D3 D2 D1 D0 Action 1 1 1 1 1 1 1 1 Highest threshold adjustment = 6.0V 0 0 0 0 0 0 0 0 Lowest threshold adjustment = 0.9V 0 0 0 0 0 0 1 0 Threshold = 0.9V + (2 x .02V) = 0.94V, e.g. 2049 Table03 1.0 SUMMIT MICROELECTRONICS, Inc. 2049 3.1 3/19/01 9 SMT4004 agement functions and soft start capability. Their contents also determine whether the under- or over-voltage capabilities are enabled and the contents establish the overvoltage offset value for the VO1, VO2, VO3 and VO4 inputs, respectively. Card- side Under-voltage Threshold Enable and Over-voltage Offset Registers 0C, 0D, 0E and 0F are identical These registers will either enable or disable their associated power man- Register R0C, R0D, R0E, R0F D7 D6 D5 D4 D3 D2 D1 D0 Action 1 x x x x x x x Power management channel enabled x 1 x x x x x x 1 = Enable soft start; 0 = Enable Trakking x x 1 x x x x x Enables under voltage 2 x x x 0 0 0 1 0 Threshold configuration selected by SMT4004 GUI 2049 Table04 1.1 any bus request addressing its device type identifier, or whether it will be selective and only respond if the A2, A1 and A0 bits match the biasing of the external pins. Bit 6 selects the device type identifier to be used for the memory array. Addressing and Slew Rate Control Configuration Register 10 is used to configure the addressing protocol for the TRAKKER. Bit 7 determines whether the device will respond with an acknowledge to Register R10 D7 D6 0 x 1 x x 0 x 1 D5 D4 D3 D2 D1 D0 Action Responds only to Pin biased bus addresses Responds to all bus addresses x Memory device-type identifier 1010 Memory device-type identifier 1011 TRAKKER over/under 300mV differential action 0 0 Ignore 0 1 Shut down the faulty supply and TRKR_IRQ# 1 0 Shut down all supplies and TRKR_IRQ# 1 1 Generate TRKR_IRQ# x x TRAKKER slew rate low to high (off to on) x 0 0 0 1 1 0 1 1 100V/s 250V/s x 500V/s 1000V/s TRAKKER slew rate high to low (on to off) 0 100V/s 0 1 250V/s 1 0 500V/s 1 1 1000V/s 0 x 2049 Table05 1.0 10 2049 3.1 3/19/01 SUMMIT MICROELECTRONICS, Inc. SMT4004 Reset Source Select and TRAKKER IRQ Select (for Supply Managers 1 and 2) Register R11 D7 D6 D5 D4 D3 D2 D1 D0 VO1-1 VO1-2 VI1O TRKR1 VO2-1 VO2-2 VI2O TRKR2 1 x x x x x x x Selects card-side1 UV1 as RST#1 trigger x 1 x x x x x x Selects card-side1 UV2 as RST#1 trigger x x 1 x x x x x Selects CBI1 as RST#1 trigger x x x 1 x x x x Selects TRK1 error as an interrupt source x x x x 1 x x x Selects card-side2 UV1 as RST#2 trigger x x x x x 1 x x Selects card-side2 UV2 as RST#2 trigger x x x x x x 1 x Selects CBI2 as RST#2 trigger x x x x x x x 1 Selects TRK2 error as an interrupt source Action 2049 Table06 1.0 Reset Source Select and TRAKKER IRQ Select (for Supply Managers 3 and 4) Register R12 D7 D6 D5 D4 D3 D2 D1 D0 VO3-1 VO3-2 VI3O TRKR3 VO4-1 VO4-2 VI4O TRKR4 1 x x x x x x x Selects card-side3 UV1 as RST#3 trigger x 1 x x x x x x Selects card-side3 UV2 as RST#3 trigger x x 1 x x x x x Selects CBI3 as RST#3 trigger x x x 1 x x x x Selects TRK3 error as an interrupt source x x x x 1 x x x Selects card-side4 UV1 as RST#4 trigger x x x x x 1 x x Selects card-side4 UV2 as RST#4 trigger x x x x x x 1 x Selects CBI4 as RST#4 trigger 1 Selects TRK4 error as an interrupt source x x x x x x x Action 2049 Table07 1.0 SUMMIT MICROELECTRONICS, Inc. 2049 3.1 3/19/01 11 SMT4004 IRQ Source Select (for Supply Managers 1 and 2) Register R13 D7 D6 D5 D4 D3 D2 D1 D0 VI1-OV VI1-UV VO1-1 VO1-2 VI2-OV VI2-UV VO2-1 VO2-2 1 x x x x x x x Selects bus-side1 OV as an IRQ# trigger x 1 x x x x x x Selects bus-side1 UV as an IRQ# trigger x x 1 x x x x x Selects card-side1 UV1 as an IRQ# trigger x x x 1 x x x x Selects card-side1 UV2 as an IRQ# trigger x x x x 1 x x x Selects bus-side2 OV as an IRQ# trigger x x x x x 1 x x Selects bus-side2 UV as an IRQ# trigger x x x x x x 1 x Selects card-side2 UV1 as an IRQ# trigger x x x x x x x 1 Selects card-side2 UV2 as an IRQ# trigger Action 2049 Table08 1.0 IRQ Source Select (for Supply Managers 3 and 4) Register R14 D7 D6 D5 D4 D3 D2 D1 D0 VI3-OV VI3-UV VO3-1 VO3-2 VI4-OV VI4-UV VO4-1 VO4-2 1 x x x x x x x Selects bus-side3 OV as an IRQ# trigger x 1 x x x x x x Selects bus-side3 UV as an IRQ# trigger x x 1 x x x x x Selects card-side3 UV1 as an IRQ# trigger x x x 1 x x x x Selects card-side3 UV2 as an IRQ# trigger x x x x 1 x x x Selects bus-side4 OV as an IRQ# trigger x x x x x 1 x x Selects bus-side4 UV as an IRQ# trigger x x x x x x 1 x Selects card-side4 UV1 as an IRQ# trigger x x x x x x x 1 Selects card-side4 UV2 as an IRQ# trigger Action 2049 Table09 1.0 12 2049 3.1 3/19/01 SUMMIT MICROELECTRONICS, Inc. SMT4004 IRQ Power-on Delay and Source Select (for All Supply Managers) Register R15 D7 D6 D5 D4 D3 D2 D1 D0 Action x 0 0 0 x x x x IRQ# power on delay off (0ms) x 1 0 0 x x x x IRQ# power on delay 200ms x 1 0 1 x x x x IRQ# power on delay 400ms x 1 1 0 x x x x IRQ# power on delay 800ms x 1 1 1 x x x x IRQ# power on delay 1600ms x x x x 1 x x x Supply 1 over-current triggers IRQ# x x x x x 1 x x Supply 2 over-current triggers IRQ# x x x x x x 1 x Supply 3 over-current triggers IRQ# x x x x x x x 1 Supply 4 over-current triggers IRQ# 2049 Table10 1.0 CROWBAR Source Enables Register R19 D7 D6 D5 D4 D3 D2 D1 D0 FORCE _SD IRQ# TRK_ IRQ# RST1 RST2 RST3 RST4 QUICK TRIP Action 1 x x x x x x x Enable FORCE_SD x 1 x x x x x x General interrupt x x 1 x x x x x TRAKKER interrupt x x x 1 x x x x Supply 1 reset x x x x 1 x x x Supply 2 reset x x x x x 1 x x Supply 3 reset x x x x x x 1 x Supply 4 reset x x x x x x x 1 Quick Trip condition 2049 Table11 1.0 SUMMIT MICROELECTRONICS, Inc. 2049 3.1 3/19/01 13 SMT4004 Quick-trip Voltage Thresholds Register R1A D7 D6 D5 MANAGER 1 0 0 0 1 1 0 1 1 D4 MANAGER 2 D3 D2 D1 MANAGER 3 D0 Action MANAGER 4 Off 75mV x 100mV 150mV 0 x Off 0 0 1 1 0 1 1 x 75mV x 100mV 150mV 0 0 0 1 1 0 1 1 Off 100mV 150mV 0 Off 0 1 75mV 1 0 100mV 1 1 150mV 0 x 75mV x 2049 Table12 1.0 Over-current Delay and Active Pin Level Select Register R1B D7 D6 D5 D4 D3 D2 na na CB EN PO F-SD 1 x x x x x D1 D0 Action OC - DLY x x CBFAULT output (1 = active high) x 1 x x x x ENABLE input (1 = active high) x x 1 x x x PWR_ON input (1 = active high) x x x 1 x x FORCE_SD input (1 = active high) Over-current delay x x x x x x 0 0 25s x x x x 0 1 50s x x x x 1 0 100s x x x x 1 1 200s 2049 Table13 1.0 14 2049 3.1 3/19/01 SUMMIT MICROELECTRONICS, Inc. SMT4004 Timer Configuration Register Register R1C D7 D6 D5 RESET PERIOD 0 0 0 1 1 0 1 1 x x D4 D3 LONGDOGTIMER D2 D1 D0 Action WATCHDOG TIMER 25ms x 50ms x 100ms 200ms 0 x x Off 1 0 0 800ms 1 0 1 1 1 0 3200ms 1 1 1 6400ms x x 1600ms 0 x x Off 1 0 0 400ms 1 0 1 800ms 1 1 0 1600ms 1 1 1 3200ms 2049 Table14 1.0 SUMMIT MICROELECTRONICS, Inc. 2049 3.1 3/19/01 15 SMT4004 Status Registers SR1D D7 D6 D5 D4 D3 D2 D1 D0 VI1-UV VI2-UV VI3-UV VI4-UV VI1-OV VI2-OV VI3-OV VI4-OV 1 x x x x x x x Bus-side1 UV x 1 x x x x x x Bus-side2 UV x x 1 x x x x x Bus-side3 UV x x x 1 x x x x Bus-side4 UV x x x x 1 x x x Bus-side1 OV x x x x x 1 x x Bus-side2 OV Action x x x x x x 1 x Bus-side3 OV x x x x x x x 1 Bus-side4 OV 2049 Table15 1.0 SR1E D7 D6 D5 D4 D3 D2 D1 D0 VO1UV1 VO2UV1 VO3UV1 VO4UV1 VO1UV2 VO2UV2 VO3UV2 VO4UV2 Action 1 x x x x x x x Card-side1 UV1 x 1 x x x x x x Card-side2 UV1 x x 1 x x x x x Card-side3 UV1 x x x 1 x x x x Card-side4 UV1 x x x x 1 x x x Card-side1 UV2 x x x x x 1 x x Card-side2 UV2 x x x x x x 1 x Card-side3 UV2 x x x x x x x 1 Card-side4 UV2 2049 Table16 1.0 SR1F D7 D6 D5 D4 D3 D2 D1 D0 TRK1 TRK2 TRK3 TRK4 OC1 OC2 OC3 OC4 1 x x x x x x x TRAKKER error supply 1 x 1 x x x x x x TRAKKER error supply 2 x x 1 x x x x x TRAKKER error supply 3 x x x 1 x x x x TRAKKER error supply 4 x x x x 1 x x x Over-current supply 1 x x x x x 1 x x Over-current supply 2 x x x x x x 1 x Over-current supply 3 x x x x x x x 1 Over-current supply 4 Action 2049 Table17 1.0 16 2049 3.1 3/19/01 SUMMIT MICROELECTRONICS, Inc. SMT4004 AC OPERATING CHARACTERISTICS Over recommended operating conditions Symbol Parameter Conditions Min. Max. Units 0 100 kHz fSCL SCL clock frequency tLOW Clock low period 4.7 s tHIGH Clock high period 4.0 s tBUF Bus free time 4.7 s tSU:STA Start condition setup time 4.7 s tHD:STA Start condition hold time 4.0 s tSU:STO Stop condition setup time 4.7 s tAA Clock edge to valid output SCL low to valid SDA (cycle n) 0.3 tDH Data Out hold time SCL low (cycle n+1) to SDA change 0.3 tR SCL and SDA rise time 1000 ns tF SCL and SDA fall time 300 ns Before new transmission 3.5 s s tSU:DAT Data In setup time 250 ns tHD:DAT Data In hold time 0 ns TI Noise filter SCL and SDA tWR Write cycle time Noise suppression 100 ns 5 ms 2049 Table18 2.0 tR tF tHIGH tLOW SCL tSU:SDA tHD:SDA tHD:DAT tSU:DAT tSU:STO tBUF SDA In tAA tDH SDA Out 2049 Fig02 1.0 Figure 2. Memory Operating Characteristics SUMMIT MICROELECTRONICS, Inc. 2049 3.1 3/19/01 17 SMT4004 Master S T A R Device Type Bus T Address Address 1 0 1 0 SDA B B B R A A A / 2 1 0 W S T A R T SDA B B B R A A A / 2 1 0 W S T A R T SDA SDA Slave A A A A A A A A 7 6 5 4 3 2 1 0 Up to 15 additional bytes can be written before issuing the stop. S T O P A C K A C K D D D D D D D D 7 6 5 4 3 2 1 0 The host may continue clocking out data so long as it provides an ACK response after each byte. 1 00 1 R B B A A X / W 2 1 A C K A C K Reading the Configuration Register 1 00 1 D D D D D D D D 7 6 5 4 3 2 1 0 C C C C C C C C 7 6 5 4 3 2 1 0 A C K S T A R T S T O P Writing Configuration Registers Slave Master A C K A C K Slave Master A C K Current Address Read (Alternate memory device type) 10 10 S T O P D D D D D D D D 7 6 5 4 3 2 1 0 A A A A A A A A 7 6 5 4 3 2 1 0 A C K Slave Master Typical Write Operation (Standard memory device type) B B R A A X / 2 1 W C C C C C C C C 7 6 5 4 3 2 1 0 A C K S T A R T A S C T K O P 1 00 1 B B R A A X / 2 1 W D D D D D D D D 7 6 5 4 3 2 1 0 A C K A C K 2049 Fig03 2.1 Figure 3. Read and Write Operations 18 2049 3.1 3/19/01 SUMMIT MICROELECTRONICS, Inc. SMT4004 MEMORY AND REGISTER OPERATION The TRAKKER has a nonvolatile memory that is configured as a 256 x 8 array. Configuration Registers reside in another `device type' address space. All read and write operations to both `device type' spaces are handled via an industry standard two-wire interface. The bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus. Note: The MR# input must be pulled low during programming. The TRAKKER will respond with an Acknowledge after recognition of a START condition and its slave address byte. If both the device and a write operation are selected the TRAKKER will respond with an Acknowledge after the receipt of each subsequent 8-Bit word. In the READ mode the TRAKKER transmits eight bits of data, releases the SDA line, and then monitors the line for an Acknowledge signal. If an Acknowledge is detected, and no STOP condition is generated by the master, the TRAKKER will continue to transmit data. If an Acknowledge is not detected the TRAKKER will terminate further data transmissions and await a STOP condition before returning to the standby power mode. Device Addressing Data Protocol The protocol defines any device that sends data onto the bus as a "transmitter" and any device that receives data as a "receiver." The device controlling data transmission is called the "master" and the controlled device is called the "slave." The TRAKKER will always be a "slave" device since it never initiates a data transfer. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock high time, because changes on the data line while SCL is high will be interpreted as start or stop condition. Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see the following Table). The next three bits are the physical device address. Read/Write Bit The last bit of the data stream defines the operation to be performed. When set to "1," a read operation is selected; when set to "0," a write operation. MEMORY WRITE OPERATIONS START and STOP Conditions When both the data and clock lines are high, the bus is said to be not busy. A high-to-low transition on the data line, while the clock is high, is defined as the "START" condition. A low-to- high transition on the data line while the clock is high is defined as the "STOP" condition. The TRAKKER allows two types of write operations: bytewrite and page write. A byte-write operation writes a single byte during the nonvolatile write period (tWR). The page write operation allows up to 16 bytes in the same page to be written during tWR. Byte Write Acknowledge (ACK) Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either the master or the slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line low to Acknowledge that it received the eight bits of data. After the slave address is sent (to identify both the slave device and a read or write operation), a second byte is transmitted which contains the 8-Bit address of any one of the 256 words in the array. Upon receipt of the word address the TRAKKER responds with an Acknowledge. Table 10. Register 84 VCC0/CH4 OV Threshold Device Type Bus Address D7 D6 D5 D4 1 0 1 0 1 0 1 1 1 0 0 1 D3 D2 R/W D1 D0 Action Memory device-type address A2 A1 A0 1/0 Alternate memory device-type address Configuration registers device-type address 2049 Table19 1.0 SUMMIT MICROELECTRONICS, Inc. 2049 3.1 3/19/01 19 SMT4004 After receiving the next byte of data it again responds with an Acknowledge. The master then terminates the transfer by generating a STOP condition, at which time the TRAKKER begins the internal write cycle. While the internal write cycle is in progress the TRAKKER inputs are disabled, and the device will not respond to any requests from the master. Write Cycle In Progress Issue Start Issue Stop Page Write Issue Slave Address and R/W = 0 The TRAKKER is capable of a 16-byte page-write operation. It is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word the master can transmit up to 15 more bytes of data. After the receipt of each byte the TRAKKER will respond with an Acknowledge. Yes The TRAKKER automatically increments the address for subsequent data words. After the receipt of each word, the low order address bits are internally incremented by one. The high order bits of the address byte remain constant. Should the master transmit more than 16 bytes, prior to generating the STOP condition, the address counter will "roll over" and the previously written data will be overwritten. As with the byte-write operation, all inputs are disabled during the internal write cycle. Refer to Figure 3 for the address, Acknowledge and data transfer sequence. Next Operation a Write? READ OPERATIONS Read operations are initiated with the R/W bit of the identification field set to "1." There are two different read options: 1. Current Address Byte Read No Yes Issue Stop Issue Address Proceed With Write Acknowledge Polling When the TRAKKER is performing an internal WRITE operation it will ignore any new START conditions. Since the device will only return an acknowledge after it accepts the START, the part can be continuously queried until an acknowledge is issued, indicating that the internal WRITE cycle is complete. See the flow diagram for the proper sequence of operations for polling. No ACK Returned Await Next Command 2049 Flow01 1.0 Flow Chart a read or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. When the TRAKKER receives the slave address field with the R/W bit set to "1" it issues an acknowledge and transmits the 8Bit word stored at address location n+1. The current address byte read operation only accesses a single byte of data. The master does not acknowledge the transfer, but does generate a stop condition. At this point the TRAKKER discontinues data transmission. 2. Random Address Byte Read Random Address Read Current Address Read The TRAKKER contains an internal address counter which maintains the address of the last word accessed, incremented by one. If the last address accessed (either 20 Random address read operations allow the master to access any memory location in a random fashion. This operation involves a two-step process. First, the master issues a write command which includes the start condition 2049 3.1 3/19/01 SUMMIT MICROELECTRONICS, Inc. SMT4004 and the slave address field (with the R/W bit set to WRITE), followed by the address of the word it is to read. This procedure sets the internal address counter of the TRAKKER to the desired address. After the word address acknowledge is received by the it the master immediately reissues a start condition followed by another slave address field with the R/W bit set to READ. The TRAKKER will respond with an acknowledge and then transmit the 8 data bits stored at the addressed location. At this point, the master does not acknowledge the transmission but does generate the stop condition. The TRAKKER discontinues data transmission and reverts to its standby power mode. Sequential READ Sequential reads can be initiated as either a current address READ or random access READ. The first word is transmitted as with the other byte read modes (current address byte READ or random address byte READ). However, the master now responds with an Acknowledge, indicating that it requires additional data from the TRAKKER. The TRAKKER continues to output data for each Acknowledge received. The master terminates the sequential READ operation by not responding with an Acknowledge, and issues a STOP condition. During a sequential read operation the internal address counter is automatically incremented with each Acknowledge signal. For read operations all address bits are incremented, allowing the entire array to be read using a single read command. After a count of the last memory address the address counter will `roll-over' and the memory will continue to output data. SUMMIT MICROELECTRONICS, Inc. 2049 3.1 3/19/01 21 SMT4004 APPLICATION CIRCUIT 10 VO4 VO3 VO2 VO1 SMT4004 CBFAULT IRQ# HEALTHY# A2 A1 A0 SCL SDA AGND DGND PGND PGND GND 10k 10k 4.7F RAW3.3V 4.7F To Pullup RS RAW5V VGG_CAP 10k 2m 1.8V @10A 2.5V @4A VI4 VI3 VI2 VI1 ENABLE UV_OVERRIDE SEATED1# PWR_ON FORCE_SD SEATED2# CB4 CB3 CB2 CB1 5m 2m 2.5m 10 10 10 VGATE4 VGATE3 VGATE2 VGATE1 WLDI WDO# LDO# MR# IRQ_CLR# 1.25VREF TRKR_IRQ# 100nF RST1# RST2# RST3# RST4# CROWBAR VDD_CAP 10F 1nF GND 1nF 1nF 4 x 330F 1.8V 2 x 330F 1nF 500F 5 x 220F 5V 3.3V 2.5V A typical circuit soft starting the 5V supply and TRAKKING the 3.3V, 2.5V and 1.8V supplies 2049 Fig04 2.1 Figure 4. Application Circuit 22 2049 3.1 3/19/01 SUMMIT MICROELECTRONICS, Inc. SMT4004 ORDERING INFORMATION SMT4004 F Package F = 48 Pin TQFP Base Part Number Register Hex Contents Configured as: R0 B4 VO Threshold of 4.5V R1 69 V1 Threshold of 3.OV R2 41 V2 threshold of 2.2V R3 28 V3 Threshold of 1.7V R4 60 V0 UV and OV enabled OV set to 5.5V R5 60 V1 UV and OV enabled OV set at 3.6V R6 62 V2 UV and OV enabled OV set at 2.8V R7 67 V3 UV and OV enabled OV set at 2.5V R8 B9 Card Side VO Threshold of 4.6V R9 6E Card Side V 1 Threshold of 3.1 V RA 46 Card Side V2 threshold of 2.3V RB 2D Card Side V3 Threshold of 1.8V RC A2 Card Side VO Threshold 2 of 4.5V RD A3 Card Side V 1 Threshold 2 of 3.OV RE A4 Card Side V2 threshold 2 of 2.2V RF A6 Card Side V3 Threshold 2 of 1.7V R10 05 Responds to pin biased addresses, 1010BIN, 250V/s slew rate on and off R11 FF Enable all RESET sources R12 FF Enable all RESET and IRQ sources R13 FF Enable all IRQ sources R14 FF Enable all IRQ sources R15 EF 800 ms POR to IRQ delay, enable all sources R19 81 Enable Crowbar on manual input and Quicktrip only R1A AA Enable 100mV Quicktrip all manager circuits RIB 02 All outputs active low, over current delay 100s RIC F6 Reset 200ms, Longdog 3200ms, Watchdog 1600ms 2049 Reg Table 1.0 SUMMIT MICROELECTRONICS, Inc. 2049 3.1 3/19/01 23 SMT4004 PACKAGE 48 PIN TQFP PACKAGE [A] 0.354 BSC (9.00) Ref. JEDEC MS-026 [B] 0.276 BSC (7.00) 0.02 BSC (0.5) Inches (Millimeters) 0.007 - 0.011 (0.17 - 0.27) DETAIL "A" [A] [B] 0.037 - 0.041 (0.95 - 1.05) 0.039 (1.00) 0.047 MAX (1.2) Pin 1 0.018 - 0.030 (0.45 - 0.75) 0.004 - 0.008 (0.09 - 0.20) A DETAIL "B" B 48 Pin TQFP NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. (c) Copyright 2001 SUMMIT Microelectronics, Inc. This document supersedes all previous versions. I2C is a trademark of Philips Corporation. 24 2049 3.1 3/19/01 SUMMIT MICROELECTRONICS, Inc.