PS013014-0107
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©2007 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or
technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT
ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION,
DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME
LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF
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PS013014-0107 Revision History
eZ80L92 MCU
Product Specification
iii
Revision History
Each instance in Revision History reflects a change to this document from its previous
revision. For more details, refer to the corresponding pages and appropriate link in the
table below.
Date Revision Level Section\Description Page No
October
2006
14 On Page 114, Table 57, replaced “valid only if
INTBIT is 1” with "valid only if INTBIT is 0".
Removed Preliminary.
113
March
2006
13 Added the registered trademark symbol ® to
eZ80Acclaim! and eZ80.
All
October
2004
12 Formatted to current publication standards. All
Timer Control
Registers
Clarified RST_EN
descriptions.
82
External Memory Read
Timing
Correction to T6 label,
Clock Rise to CSx
De-assertion Delay
(Figure 48).
205
External I/O Read
Timing
Correction to T6 label,
Clock Rise to CSx
De-assertion Delay
(Figure 50).
208
Real Time Clock
Oscillator and Source
Selection
Clarified language
describing RTC drive
frequency.
89
February
2004
11 Revisions to BGR Divisor, UART text 108
September
2003
10 Modified to remove "zservice@zilog.com" and
other external hyperlinks.
PS013014-0107 Table of Contents
eZ80L92 MCU
Product Specification
iv
Table of Contents
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
eZ80® CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
New and Improved Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
HALT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Clock Peripheral Power-Down Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
GPIO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
GPIO Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Non-maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Chip Selects and Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Memory and I/O Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Memory Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
I/O Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
WAIT Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Chip Selects During Bus Request/Bus Acknowledge Cycles . . . . . . . . . . . . . . . . . 53
Bus Mode Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
eZ80® Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Z80® Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Intel Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Motorola Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Chip Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Watchdog Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Programmable Reload Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Programmable Reload Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PS013014-0107 Table of Contents
eZ80L92 MCU
Product Specification
v
Programmable Reload Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Real Time Clock Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Real Time Clock Oscillator and Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Real Time Clock Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Real Time Clock Recommended Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Real Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
UART Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
UART Recommended Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
BRG Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Infrared Encoder/Decoder Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Loopback Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SPI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SPI Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Data Transfer Procedure with SPI Configured as the Master . . . . . . . . . . . . . . . . 133
Data Transfer Procedure with SPI Configured as a Slave . . . . . . . . . . . . . . . . . . . 134
SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
I2C Serial I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Transferring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
ZiLOG Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
ZDI-Supported Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
ZDI Clock and Data Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
ZDI Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
ZDI Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
ZDI Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
ZDI Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Operation of the eZ80L92 During ZDI Break Points . . . . . . . . . . . . . . . . . . . . . . . 166
Bus Requests During ZDI Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
ZDI Write-Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
PS013014-0107 Table of Contents
eZ80L92 MCU
Product Specification
vi
ZDI Read-Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
ZDI Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
On-Chip Instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
OCI Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
OCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
OCI Information Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
eZ80® CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
20 MHz Primary Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
32 kHz Real Time Clock Crystal Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . 199
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
External Memory Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
External Memory Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
External I/O Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
External I/O Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Wait State Timing for Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Wait State Timing for Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
General Purpose I/O Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
External Bus Acknowledge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
External System Clock Driver (PHI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Part Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
1
Architectural Overview
ZiLOG’s eZ80L92 MCU is a high-speed single-cycle instruction-fetch microcontroller
with a maximum clock speed of 50 MHz. The eZ80L92 MCU is a member of
eZ80Acclaim!® family of Flash microcontrollers. It operates in Z80® compatible
addressing mode (64 KB) or full 24-bit addressing mode (16 MB). The rich peripheral set
of the eZ80L92 MCU makes it suitable for various applications including industrial
control, embedded communication, and point-of-sale terminals.
Features
The features of eZ80L92 MCU include:
•
Single-cycle instruction fetch, high-performance, pipelined eZ80® CPU core1
•
Low power features including SLEEP mode, HALT mode, and selective peripheral
power-down control
•
Two Universal Asynchronous Receiver/Transmitter (UARTs) with independent baud
rate generators
•
Serial Peripheral Interface (SPI) with independent clock rate generator
•
Inter-Integrated Circuit (I2C) with independent clock rate generator
•
Infrared Data Association (IrDA)-compliant infrared encoder/decoder
•
New DMA-like eZ80 instructions for efficient block data transfer
•
Glueless external peripheral interface with 4 Chip Selects, individual Wait State
generators, and an external WAIT input pin—supports Intel-style and Motorola-style
buses Fixed-priority vectored interrupts (both internal and external) and interrupt
controller
•
Real-time clock with an on-chip 32 kHz oscillator, selectable 50/60 Hz input, and
separate VDD pin for battery backup
•
Six 16-bit Counter/Timers with prescalers and direct input/output drive
•
Watchdog Timer (WDT)
•
24 bits of General-Purpose Input/Output (GPIO)
•
JTAG and ZDI debug interfaces
•
100-pin LQFP package
•
3.0 V to 3.6 V supply voltage with 5 V tolerant inputs
1. For simplicity, the term eZ80 CPU is referred as CPU for the rest of this document.
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
2
•
Operating temperature range:
–
Standard, 0 ºC to +70 ºC
–
Extended, –40 ºC to +105 ºC
All signals with an overline are active Low. For example, B/W, for which WORD is active
Low, and B/W, for which BYTE is active Low.
Power connections follow these conventional descriptions.
Connection Circuit Device
Power VCC VDD
Ground GND VSS
Note:
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
3
Block Diagram
Figure 1
illustrates the block diagram of the eZ80L92 MCU.
Figure 1. eZ80L92 Block Diagram
RTC_V
RTC_X
RTC_X
I C
Serial
Interface
Bus
Controller
eZ80
CPU
ZiLOG
Debug
Interface
(JTAG/ZDI)
Chip
Select
and
Wait State
Generator
IrDA
Encoder/
Decoder
Watch-Dog
Timer
(WDT)
Programmable
Reload
Timer/Counters
(6)
8-Bit
General
Purpose
I/O Port
(GPIO)
Crystal
Oscillator
and
System Clock
Generator
2
Serial
Peripheral
Interface
(SPI)
Interrupt
Controller
Universal
Asynchronous
Receiver/
Transmitter
(UART)
SCL
SDA
SCK
SS
MISO
MOSI
CTS0/1
D
CD0/1
DSR0/1
DTR0/1
RI0/1
RTS0/1
RxD0/1
TxD0/1
IR_TxD
IR_RxD
PB[7:0]
PC[7:0]
PD[7:0]
X
X
PHI
T0_IN
T1_IN
T2_IN
T3_IN
T4_OUT
T5_OUT
WAIT
CS0
CS1
CS2
CS3
NMI
Interrupt
Vector
[7:0]
RESET
HALT_SLP
BUSACK
INSTRD
BUSREQ
IORQ
MREQ
RD
WR
JTAG/ZDI Signals (5)
DATA[7:0]
ADDR[23:0]
IN
OUT
Real-Time
Clock and
32 KHz
Oscillator
DD
IN
OUT
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
4
Pin Description
Figure 2
illustrates the pin layout of the eZ80L92 MCU in the 100-pin LQFP package.
Table 1
lists the 100-Pin LQFP pins
and their functions.
Figure 2. 100-Pin LQFP Configuration of the eZ80L92
PD7/RI0
PD6/DCD0
PD5/DSR0
PD4/DTR0
PD3/CTS0
PD2/RTS0
PD1/RxD0/IR_RXD
PD0/TxD0/IR_TXD
VDD
TDI
TRIGOUT
TCK
TMS
VSS
RTC_VDD
RTC_XOUT
RTC_XIN
VSS
VDD
BUSACK
BUSREQ
NMI
RESET
PHI
SCL
SDA
VSS
PB7/MOSI
PB6/MISO
PB5/T5_OUT
PB4/T4_OUT
PB3/SCK
PB2/SS
PB1/T1_IN
PB0/T0_IN
VDD
XOUT
XIN
VSS
PC7/RI1
PC6/DCD1
PC5/DSR1
PC4/DTR1
PC3/CTS1
PC2//RTS1
PC1/RxD1
PC0/TxD1
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
VDD
VSS
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
VDD
VSS
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR20
ADDR21
ADDR22
ADDR23
CS0
CS1
CS2
CS3
VDD
VSS
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
VDD
VSS
IORQ
MREQ
RD
WR
INSTRD
WAIT
100-Pin LQFP
1
10
80
90
100
TDO
VDD
HALT_SLP
91
92
93
94
95
96
97
98
99
81
82
83
84
85
86
87
88
89
76
77
78
79
9
8
7
6
5
4
3
2
11
20
19
18
17
16
15
14
13
12
21
25
24
23
22
30
40
50
41
42
43
44
45
46
47
48
49
31
32
33
34
35
36
37
38
39
26
27
28
29
51
60
59
58
57
56
55
54
53
52
61
70
69
68
67
66
65
64
63
62
71
75
74
73
72
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
5
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU
Pin No Symbol Function Signal Direction Description
1 ADDR0 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
2 ADDR1 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
3 ADDR2 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
4 ADDR3 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
5 ADDR4 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
6 ADDR5 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
6
7V
DD Power Supply Power Supply.
8V
SS Ground Ground.
9 ADDR6 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
10 ADDR7 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
11 ADDR8 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
12 ADDR9 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
13 ADDR10 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol Function Signal Direction Description
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
7
14 ADDR11 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
15 ADDR12 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
16 ADDR13 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
17 ADDR14 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
18 VDD Power Supply Power Supply.
19 VSS Ground Ground.
20 ADDR15 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol Function Signal Direction Description
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
8
21 ADDR16 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
22 ADDR17 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
23 ADDR18 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
24 ADDR19 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
25 ADDR20 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol Function Signal Direction Description
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
9
26 ADDR21 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
27 ADDR22 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
28 ADDR23 Address Bus Bidirectional Configured as an output in normal
operation. The address bus selects a
location in memory or I/O space to be
read or written. Configured as an input
during bus acknowledge cycles. Drives
the Chip Select/Wait State Generator
block to generate Chip Selects.
29 CS0 Chip Select 0 Output, Active Low CS0 Low indicates that an access is
occurring in the defined CS0 memory or
I/O address space.
30 CS1 Chip Select 1 Output, Active Low CS1 Low indicates that an access is
occurring in the defined CS1 memory or
I/O address space.
31 CS2 Chip Select 2 Output, Active Low CS2 Low indicates that an access is
occurring in the defined CS2 memory or
I/O address space.
32 CS3 Chip Select 3 Output, Active Low CS3 Low indicates that an access is
occurring in the defined CS3 memory or
I/O address space.
33 VDD Power Supply Power Supply.
34 VSS Ground Ground.
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol Function Signal Direction Description
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
10
35 DATA0 Data Bus Bidirectional The data bus transfers data to and from
I/O and memory devices. The eZ80L92
MCU drives these lines only during Write
cycles when the eZ80L92 MCU is the bus
master.
36 DATA1 Data Bus Bidirectional The data bus transfers data to and from
I/O and memory devices. The eZ80L92
MCU drives these lines only during Write
cycles when the eZ80L92 MCU is the bus
master.
37 DATA2 Data Bus Bidirectional The data bus transfers data to and from
I/O and memory devices. The eZ80L92
MCU drives these lines only during Write
cycles when the eZ80L92 MCU is the bus
master.
38 DATA3 Data Bus Bidirectional The data bus transfers data to and from
I/O and memory devices. The eZ80L92
MCU drives these lines only during Write
cycles when the eZ80L92 MCU is the bus
master.
39 DATA4 Data Bus Bidirectional The data bus transfers data to and from
I/O and memory devices. The eZ80L92
MCU drives these lines only during Write
cycles when the eZ80L92 MCU is the bus
master.
40 DATA5 Data Bus Bidirectional The data bus transfers data to and from
I/O and memory devices. The eZ80L92
MCU drives these lines only during Write
cycles when the eZ80L92 MCU is the bus
master.
41 DATA6 Data Bus Bidirectional The data bus transfers data to and from
I/O and memory devices. The eZ80L92
MCU drives these lines only during Write
cycles when the eZ80L92 MCU is the bus
master.
42 DATA7 Data Bus Bidirectional The data bus transfers data to and from
I/O and memory devices. The eZ80L92
MCU drives these lines only during Write
cycles when the eZ80L92 MCU is the bus
master.
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol Function Signal Direction Description
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
11
43 VDD Power Supply Power Supply.
44 VSS Ground Ground.
45 IORQ Input/Output
Request
Bidirectional, Active
Low
IORQ indicates that the CPU is accessing
a location in I/O space. RD and WR
indicate the type of access. The eZ80L92
MCU does not drive this line during
RESET. It is an input in bus acknowledge
cycles.
46 MREQ Memory
Request
Bidirectional, Active
Low
MREQ Low indicates that the CPU is
accessing a location in memory. The RD,
WR, and INSTRD signals indicate the
type of access. The eZ80L92 MCU does
not drive this line during RESET. It is an
input in bus acknowledge cycles.
47 RD Read Output, Active Low RD Low indicates that the eZ80L92 MCU
is reading from the current address
location. This pin is tristated during bus
acknowledge cycles.
48 WR Write Output, Active Low WR indicates that the CPU is writing to the
current address location. This pin is
tristated during bus acknowledge cycles.
49 INSTRD Instruction
Read Indicator
Output, Active Low INSTRD (with MREQ and RD) indicates
the eZ80L92 MCU is fetching an
instruction from memory. This pin is
tristated during bus acknowledge cycles.
50 WAIT WAIT Request Input, Active Low Driving the WAIT pin Low forces the CPU
to wait additional clock cycles for an
external peripheral or external memory to
complete its Read or Write operation.
51 RESET Reset Schmitt Trigger Input,
Active Low
This signal is used to initialize the
eZ80L92 MCU. This input must be Low for
a minimum of 3 system clock cycles, and
must be held Low until the clock is stable.
This input includes a Schmitt trigger to
allow RC rise times.
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol Function Signal Direction Description
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
12
52 NMI Nonmaskable
Interrupt
Schmitt Trigger Input,
Active Low
The NMI input is a higher priority input
than the maskable interrupts. It is always
recognized at the end of an instruction,
regardless of the state of the interrupt
enable control bits. This input includes a
Schmitt trigger to allow RC rise times.
53 BUSREQ Bus Request Input, Active Low External devices can request the eZ80L92
MCU to release the memory interface bus
for their use, by driving this pin Low.
54 BUSACK Bus
Acknowledge
Output, Active Low The eZ80L92 MCU responds to a Low on
BUSREQ, by tristating the address, data,
and control signals, and by driving the
BUSACK line Low. During bus
acknowledge cycles ADDR[23:0], IORQ,
and MREQ are inputs.
55 HALT_SLP HALT and
SLEEP
Indicator
Output, Active Low A Low on this pin indicates that the CPU
has entered either HALT or SLEEP mode
because of execution of either a HALT or
SLP instruction.
56 VDD Power Supply Power Supply.
57 VSS Ground Ground.
58 RTC_XIN Real-Time
Clock Crystal
Input
Input This pin is the input to the low-power
32 kHz crystal oscillator for the Real-Time
Clock.
59 RTC_XOUT Real-Time
Clock Crystal
Output
Bidirectional This pin is the output from the low-power
32 kHz crystal oscillator for the Real-Time
Clock. This pin is an input when the RTC
is configured to operate from 50/60 Hz
input clock signals and the 32 kHz crystal
oscillator is disabled.
60 RTC_VDD Real-Time
Clock Power
Supply
Power supply for the Real-Time Clock and
associated 32 kHz oscillator. Isolated from
the power supply to the remainder of the
chip. A battery can be connected to this
pin to supply constant power to the
Real-Time Clock and 32 kHz oscillator.
61 VSS Ground Ground.
62 TMS JTAG Test
Mode Select
Input JTAG Mode Select Input.
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol Function Signal Direction Description
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
13
63 TCK JTAG Test
Clock
Input JTAG and ZDI clock input.
64 TRIGOUT JTAG Test
Trigger Output
Output Active High trigger event indicator.
65 TDI JTAG Test
Data In
Bidirectional JTAG data input pin. Functions as
ZDI data I/O pin when JTAG is disabled.
66 TDO JTAG Test
Data Out
Output JTAG data output pin.
67 VDD Power Supply Power Supply.
68 PD0 GPIO Port D Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port D pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port D is multiplexed with
one UART.
TxD0 UART
Transmit Data
Output This pin is used by the UART to transmit
asynchronous serial data. This signal is
multiplexed with PD0.
IR_TXD IrDA Transmit
Data
Output This pin is used by the IrDA encoder/
decoder to transmit serial data. This signal
is multiplexed with PD0.
69 PD1 GPIO Port D Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port D pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port D is multiplexed with
one UART.
RxD0 Receive Data Input This pin is used by the UART to receive
asynchronous serial data. This signal is
multiplexed with PD1.
IR_RXD IrDA Receive
Data
Input This pin is used by the IrDA encoder/
decoder to receive serial data. This signal
is multiplexed with PD1.
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol Function Signal Direction Description
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
14
70 PD2 GPIO Port D Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port D pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port D is multiplexed with
one UART.
RTS0 Request to
Send
Output, Active Low Modem control signal from UART.
This signal is multiplexed with PD2.
71 PD3 GPIO Port D Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port D pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port D is multiplexed with
one UART.
CTS0 Clear to Send Input, Active Low Modem status signal to the UART.
This signal is multiplexed with PD3.
72 PD4 GPIO Port D Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port D pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port D is multiplexed with
one UART.
DTR0 Data Terminal
Ready
Output, Active Low Modem control signal to the UART.
This signal is multiplexed with PD4.
73 PD5 GPIO Port D Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port D pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port D is multiplexed with
one UART.
DSR0 Data Set
Ready
Input, Active Low Modem status signal to the UART.
This signal is multiplexed with PD5.
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol Function Signal Direction Description
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
15
74 PD6 GPIO Port D Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port D pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port D is multiplexed with
one UART.
DCD0 Data Carrier
Detect
Input, Active Low Modem status signal to the UART.
This signal is multiplexed with PD6.
75 PD7 GPIO Port D Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port D pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port D is multiplexed with
one UART.
RI0 Ring Indicator Input, Active Low Modem status signal to the UART.
This signal is multiplexed with PD7.
76 PC0 GPIO Port C Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port C pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port C is multiplexed with
one UART.
TxD1 Transmit Data Output This pin is used by the UART to transmit
asynchronous serial data. This signal is
multiplexed with PC0.
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol Function Signal Direction Description
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
16
77 PC1 GPIO Port C Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port C pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port C is multiplexed with
one UART.
RxD1 Receive Data Input This pin is used by the UART to receive
asynchronous serial data. This signal is
multiplexed with PC1.
78 PC2 GPIO Port C Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port C pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port C is multiplexed with
one UART.
RTS1 Request to
Send
Output, Active Low Modem control signal from UART.
This signal is multiplexed with PC2.
79 PC3 GPIO Port C Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port C pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port C is multiplexed with
one UART.
CTS1 Clear to Send Input, Active Low Modem status signal to the UART.
This signal is multiplexed with PC3.
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol Function Signal Direction Description
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
17
80 PC4 GPIO Port C Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port C pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port C is multiplexed with
one UART.
DTR1 Data Terminal
Ready
Output, Active Low Modem control signal to the UART.
This signal is multiplexed with PC4.
81 PC5 GPIO Port C Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port C pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port C is multiplexed with
one UART.
DSR1 Data Set
Ready
Input, Active Low Modem status signal to the UART.
This signal is multiplexed with PC5.
82 PC6 GPIO Port C Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port C pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port C is multiplexed with
one UART.
DCD1 Data Carrier
Detect
Input, Active Low Modem status signal to the UART.
This signal is multiplexed with PC6.
83 PC7 GPIO Port C Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port C pin,
when programmed as output, can be
selected to be an open-drain or open-
source output. Port C is multiplexed with
one UART.
RI1 Ring Indicator Input, Active Low Modem status signal to the UART.
This signal is multiplexed with PC7.
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol Function Signal Direction Description
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
18
84 VSS Ground Ground.
85 XIN System Clock
Oscillator Input
Input This pin is the input to the onboard crystal
oscillator for the primary system clock.
If an external oscillator is used, its clock
output should be connected to this pin.
When a crystal is used, it should be
connected between XIN and XOUT.
86 XOUT System Clock
Oscillator
Output
Output This pin is the output of the onboard
crystal oscillator. When used, a crystal
should be connected between XIN and
XOUT.
87 VDD Power Supply Power Supply.
88 PB0 GPIO Port B Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port B pin,
when programmed as output, can be
selected to be an open-drain or open-
source output.
T0_IN Timer 0 In Input Alternate clock source for Programmable
Reload Timers 0 and 2. This signal is
multiplexed with PB0.
89 PB1 GPIO Port B Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port B pin,
when programmed as output, can be
selected to be an open-drain or open-
source output.
T1_IN Timer 1 In Input Alternate clock source for Programmable
Reload Timers 1 and 3. This signal is
multiplexed with PB1.
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol Function Signal Direction Description
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
19
90 PB2 GPIO Port B Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port B pin,
when programmed as output, can be
selected to be an open-drain or
open-source output.
SS Slave Select Input, Active Low The slave select input line is used to
select a slave device in SPI mode.
This signal is multiplexed with PB2.
91 PB3 GPIO Port B Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port B pin,
when programmed as output, can be
selected to be an open-drain or open-
source output.
SCK SPI Serial
Clock
Bidirectional SPI serial clock. This signal is multiplexed
with PB3.
92 PB4 GPIO Port B Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port B pin,
when programmed as output, can be
selected to be an open-drain or open-
source output.
T4_OUT Timer 4 Out Output Programmable Reload Timer 4 timer-out
signal. This signal is multiplexed with PB4.
93 PB5 GPIO Port B Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port B pin,
when programmed as output, can be
selected to be an open-drain or
open-source output.
T5_OUT Timer 5 Out Output Programmable Reload Timer 5 timer-out
signal. This signal is multiplexed with PB5.
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol Function Signal Direction Description
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
20
94 PB6 GPIO Port B Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port B pin,
when programmed as output, can be
selected to be an open-drain or
open-source output.
MISO Master In
Slave Out
Bidirectional The MISO line is configured as an input
when the eZ80L92 MCU is an SPI master
device and as an output when eZ80L92
MCU is an SPI slave device. This signal is
multiplexed with PB6.
95 PB7 GPIO Port B Bidirectional This pin can be used for GPIO. It can be
individually programmed as input or
output and can also be used individually
as an interrupt input. Each Port B pin,
when programmed as output, can be
selected to be an open-drain or
open-source output.
MOSI Master Out
Slave In
Bidirectional The MOSI line is configured as an output
when the eZ80L92 MCU is an SPI master
device and as an input when the eZ80L92
MCU is an SPI slave device. This signal is
multiplexed with PB7.
96 VDD Power Supply Power Supply.
97 VSS Ground Ground.
98 SDA I2C Serial Data Bidirectional This pin carries the I2C data signal.
99 SCL I2C Serial
Clock
Bidirectional This pin is used to receive and transmit
the I2C clock.
100 PHI System Clock Output This pin is an output driven by the internal
system clock.
Table 1. 100-Pin LQFP Pin Identification of eZ80L92 MCU (Continued)
Pin No Symbol Function Signal Direction Description
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
21
Pin Characteristics
Table 2 describes the characteristics of each pin in the
eZ80L92 MCU
’s 100-pin LQFP
package.
Table 2. Pin Characteristics of eZ80L92 MCU
Pin
No. Symbol Direction
Reset
Direction
Active
Low/High
Tristate
Output
Pull
Up/Down
Schmitt
Trigger
Input
Open
Drain/Source
1 ADDR0 I/O O N/A Yes No No No
2 ADDR1 I/O O N/A Yes No No No
3 ADDR2 I/O O N/A Yes No No No
4 ADDR3 I/O O N/A Yes No No No
5 ADDR4 I/O O N/A Yes No No No
6 ADDR5 I/O O N/A Yes No No No
7V
DD
8V
SS
9 ADDR6 I/O O N/A Yes No No No
10 ADDR7 I/O O N/A Yes No No No
11 ADDR8 I/O O N/A Yes No No No
12 ADDR9 I/O O N/A Yes No No No
13 ADDR10 I/O O N/A Yes No No No
14 ADDR11 I/O O N/A Yes No No No
15 ADDR12 I/O O N/A Yes No No No
16 ADDR13 I/O O N/A Yes No No No
17 ADDR14 I/O O N/A Yes No No No
18 VDD
19 VSS
20 ADDR15 I/O O N/A Yes No No No
21 ADDR16 I/O O N/A Yes No No No
22 ADDR17 I/O O N/A Yes No No No
23 ADDR18 I/O O N/A Yes No No No
24 ADDR19 I/O O N/A Yes No No No
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
22
25 ADDR20 I/O O N/A Yes No No No
26 ADDR21 I/O O N/A Yes No No No
27 ADDR22 I/O O N/A Yes No No No
28 ADDR23 I/O O N/A Yes No No No
29 CS0 O O Low No No No No
30 CS1 O O Low No No No No
31 CS2 O O Low No No No No
32 CS3 O O Low No No No No
33 VDD
34 VSS
35 DATA0 I/O I N/A Yes No No No
36 DATA1 I/O I N/A Yes No No No
37 DATA2 I/O I N/A Yes No No No
38 DATA3 I/O I N/A Yes No No No
39 DATA4 I/O I N/A Yes No No No
40 DATA5 I/O I N/A Yes No No No
41 DATA6 I/O I N/A Yes No No No
42 DATA7 I/O I N/A Yes No No No
43 VDD
44 VSS
45 IORQ I/O O Low Yes No No No
46 MREQ I/O O Low Yes No No No
47 RD O O Low No No No No
48 WR O O Low No No No No
49 INSTRD O O Low No No No No
50 WAIT I I Low N/A No No N/A
51 RESET I I Low N/A Up Yes N/A
52 NMI I I Low N/A No Yes N/A
Table 2. Pin Characteristics of eZ80L92 MCU (Continued)
Pin
No. Symbol Direction
Reset
Direction
Active
Low/High
Tristate
Output
Pull
Up/Down
Schmitt
Trigger
Input
Open
Drain/Source
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
23
53 BUSREQ I I Low N/A No No N/A
54 BUSACK O O Low No No No No
55 HALT_SLP O O Low No No No No
56 VDD
57 VSS
58 RTC_XIN I I N/A N/A No No N/A
59 RTC_XOUT I/O U N/A N/A No No No
60 RTC_VDD
61 VSS
62 TMS I I N/A N/A Up No N/A
63 TCK I I Rising (In)
Falling
(Out)
N/A Up No N/A
64 TRIGOUT I/O O High Yes No No No
65 TDI I/O I N/A Yes Up No No
66 TDO O O N/A Yes No No No
67 VDD
68 PD0 I/O I N/A Yes No No OD and OS
69 PD1 I/O I N/A Yes No No OD and OS
70 PD2 I/O I N/A Yes No No OD and OS
71 PD3 I/O I N/A Yes No No OD and OS
72 PD4 I/O I N/A Yes No No OD and OS
73 PD5 I/O I N/A Yes No No OD and OS
74 PD6 I/O I N/A Yes No No OD and OS
75 PD7 I/O I N/A Yes No No OD and OS
76 PC0 I/O I N/A Yes No No OD and OS
77 PC1 I/O I N/A Yes No No OD and OS
78 PC2 I/O I N/A Yes No No OD and OS
79 PC3 I/O I N/A Yes No No OD and OS
Table 2. Pin Characteristics of eZ80L92 MCU (Continued)
Pin
No. Symbol Direction
Reset
Direction
Active
Low/High
Tristate
Output
Pull
Up/Down
Schmitt
Trigger
Input
Open
Drain/Source
PS013014-0107 Architectural Overview
eZ80L92 MCU
Product Specification
24
80 PC4 I/O I N/A Yes No No OD and OS
81 PC5 I/O I N/A Yes No No OD and OS
82 PC6 I/O I N/A Yes No No OD and OS
83 PC7 I/O I N/A Yes No No OD and OS
84 VSS
85 XIN I I N/A N/A No No N/A
86 XOUT OON/ANoNoNo No
87 VDD
88 PB0 I/O I N/A Yes No No OD and OS
89 PB1 I/O I N/A Yes No No OD and OS
90 PB2 I/O I N/A Yes No No OD and OS
91 PB3 I/O I N/A Yes No No OD and OS
92 PB4 I/O I N/A Yes No No OD and OS
93 PB5 I/O I N/A Yes No No OD and OS
94 PB6 I/O I N/A Yes No No OD and OS
95 PB7 I/O I N/A Yes No No OD and OS
96 VDD
97 VSS
98 SDA I/O I N/A Yes Up No OD
99 SCL I/O I N/A Yes Up No OD
100 PHI O O N/A Yes No No No
Table 2. Pin Characteristics of eZ80L92 MCU (Continued)
Pin
No. Symbol Direction
Reset
Direction
Active
Low/High
Tristate
Output
Pull
Up/Down
Schmitt
Trigger
Input
Open
Drain/Source
PS013014-0107 Register Map
eZ80L92 MCU
Product Specification
25
Register Map
All on-chip peripheral registers are accessed in the I/O address space. All I/O operations
employ 16-bit addresses. The upper byte of the 24-bit address bus is undefined during all
I/O operations (ADDR[23:16] = UU). All I/O operations using 16-bit addresses within the
range 0080h–00FFh are routed to the on-chip peripherals. External I/O Chip Selects are
not generated if the address space programmed for the I/O Chip Selects overlaps the
0080h–00FFh address range.
Registers at unused addresses within the 0080h–00FFh range assigned to on-chip
peripherals are not implemented. Read access to such addresses returns unpredictable
values and Write access produces no effect. Table 3 lists the register map for the eZ80L92
MCU.
Table 3. Register Map
Address
(hex) Mnemonic Name
Reset
(hex)
CPU
Access
Page
No
Programmable Reload Counter/Timers
0080 TMR0_CTL Timer 0 Control Register 00 R/W 82
0081 TMR0_DR_L Timer 0 Data Register—Low Byte 00 R 84
TMR0_RR_L Timer 0 Reload Register—Low Byte 00 W 85
0082 TMR0_DR_H Timer 0 Data Register—High Byte 00 R 84
TMR0_RR_H Timer 0 Reload Register—High Byte 00 W 86
0083 TMR1_CTL Timer 1 Control Register 00 R/W 82
0084 TMR1_DR_L Timer 1 Data Register—Low Byte 00 R 84
TMR1_RR_L Timer 1 Reload Register—Low Byte 00 W 85
0085 TMR1_DR_H Timer 1 Data Register—High Byte 00 R 84
TMR1_RR_H Timer 1 Reload Register—High Byte 00 W 86
0086 TMR2_CTL Timer 2 Control Register 00 R/W 82
Programmable Reload Counter/Timers
0087 TMR2_DR_L Timer 2 Data Register—Low Byte 00 R 84
TMR2_RR_L Timer 2 Reload Register—Low Byte 00 W 85
0088 TMR2_DR_H Timer 2 Data Register—High Byte 00 R 84
TMR2_RR_H Timer 2 Reload Register—High Byte 00 W 86
PS013014-0107 Register Map
eZ80L92 MCU
Product Specification
26
0089 TMR3_CTL Timer 3 Control Register 00 R/W 82
008A TMR3_DR_L Timer 3 Data Register—Low Byte 00 R 84
TMR3_RR_L Timer 3 Reload Register—Low Byte 00 W 85
008B TMR3_DR_H Timer 3 Data Register—High Byte 00 R 84
TMR3_RR_H Timer 3 Reload Register—High Byte 00 W 86
008C TMR4_CTL Timer 4 Control Register 00 R/W 82
008D TMR4_DR_L Timer 4 Data Register—Low Byte 00 R 84
TMR4_RR_L Timer 4 Reload Register—Low Byte 00 W 85
008E TMR4_DR_H Timer 4 Data Register—High Byte 00 R 84
TMR4_RR_H Timer 4 Reload Register—High Byte 00 W 86
008F TMR5_CTL Timer 5 Control Register 00 R/W 82
0090 TMR5_DR_L Timer 5 Data Register—Low Byte 00 R 84
TMR5_RR_L Timer 5 Reload Register—Low Byte 00 W 85
0091 TMR5_DR_H Timer 5 Data Register—High Byte 00 R 84
TMR5_RR_H Timer 5 Reload Register—High Byte 00 W 86
0092 TMR_ISS Timer Input Source Select Register 00 R/W 87
Watchdog Timer
0093 WDT_CTL Watch-Dog Timer Control Register100/20 R/W 75
0094 WDT_RR Watch-Dog Timer Reset Register XX W 76
General-Purpose Input/Output Ports
009A PB_DR Port B Data Register2XX R/W 42
009B PB_DDR Port B Data Direction Register FF R/W 43
009C PB_ALT1 Port B Alternate Register 1 00 R/W 43
009D PB_ALT2 Port B Alternate Register 2 00 R/W 43
009E PC_DR Port C Data Register XX R/W242
009F PC_DDR Port C Data Direction Register FF R/W 43
00A0 PC_ALT1 Port C Alternate Register 1 00 R/W 43
00A1 PC_ALT2 Port C Alternate Register 2 00 R/W 43
00A2 PD_DR Port D Data Register XX R/W242
Table 3. Register Map (Continued)
Address
(hex) Mnemonic Name
Reset
(hex)
CPU
Access
Page
No
PS013014-0107 Register Map
eZ80L92 MCU
Product Specification
27
00A3 PD_DDR Port D Data Direction Register FF R/W 43
00A4 PD_ALT1 Port D Alternate Register 1 00 R/W 43
00A5 PD_ALT2 Port D Alternate Register 2 00 R/W 43
Chip Select/Wait State Generator
00A8 CS0_LBR Chip Select 0 Lower Bound Register 00 R/W 68
00A9 CS0_UBR Chip Select 0 Upper Bound Register FF R/W 69
00AA CS0_CTL Chip Select 0 Control Register E8 R/W 70
00AB CS1_LBR Chip Select 1 Lower Bound Register 00 R/W 68
00AC CS1_UBR Chip Select 1 Upper Bound Register 00 R/W 69
00AD CS1_CTL Chip Select 1 Control Register 00 R/W 70
00AE CS2_LBR Chip Select 2 Lower Bound Register 00 R/W 68
00AF CS2_UBR Chip Select 2 Upper Bound Register 00 R/W 69
00B0 CS2_CTL Chip Select 2 Control Register 00 R/W 70
00B1 CS3_LBR Chip Select 3 Lower Bound Register 00 R/W 68
Chip Select/Wait State Generator
00B2 CS3_UBR Chip Select 3 Upper Bound Register 00 R/W 69
00B3 CS3_CTL Chip Select 3 Control Register 00 R/W 70
Serial Peripheral Interface (SPI) Block
00B8 SPI_BRG_L SPI Baud Rate Generator
Register—Low Byte
02 R/W 134
00B9 SPI_BRG_H SPI Baud Rate Generator
Register—High Byte
00 R/W 135
00BA SPI_CTL SPI Control Register 04 R/W 135
00BB SPI_SR SPI Status Register 00 R 136
00BC SPI_TSR SPI Transmit Shift Register XX W 137
SPI_RBR SPI Receive Buffer Register XX R 137
Infrared Encoder/Decoder Block
00BF IR_CTL Infrared Encoder/Decoder Control 00 R/W 126
Table 3. Register Map (Continued)
Address
(hex) Mnemonic Name
Reset
(hex)
CPU
Access
Page
No
PS013014-0107 Register Map
eZ80L92 MCU
Product Specification
28
Universal Asynchronous Receiver/Transmitter 0 (UART0) Block
00C0 UART0_RBR UART 0 Receive Buffer Register XX R 112
UART0_THR UART 0 Transmit Holding Register XX W 111
UART0_BRG_L UART 0 Baud Rate Generator
Register—Low Byte
02 R/W 110
00C1 UART0_IER UART 0 Interrupt Enable Register 00 R/W 112
UART0_BRG_H UART 0 Baud Rate Generator
Register—High Byte
00 R/W 110
00C2 UART0_IIR UART 0 Interrupt Identification Register 01 R 113
UART0_FCTL UART 0 FIFO Control Register 00 W 114
00C3 UART0_LCTL UART 0 Line Control Register 00 R/W 115
Universal Asynchronous Receiver/Transmitter 0 (UART0) Block
00C4 UART0_MCTL UART 0 Modem Control Register 00 R/W 117
00C5 UART0_LSR UART 0 Line Status Register 60 R 118
00C6 UART0_MSR UART 0 Modem Status Register XX R 120
00C7 UART0_SPR UART 0 Scratch Pad Register 00 R/W 122
I2C Block
00C8 I2C_SAR I2C Slave Address Register 00 R/W 152
00C9 I2C_XSAR I2C Extended Slave Address Register 00 R/W 152
00CA I2C_DR I2C Data Register 00 R/W 153
00CB I2C_CTL I2C Control Register 00 R/W 154
00CC I2C_SR I2C Status Register F8 R 155
I2C_CCR I2C Clock Control Register 00 W 157
00CD I2C_SRR I2C Software Reset Register XX W 159
Table 3. Register Map (Continued)
Address
(hex) Mnemonic Name
Reset
(hex)
CPU
Access
Page
No
PS013014-0107 Register Map
eZ80L92 MCU
Product Specification
29
Universal Asynchronous Receiver/Transmitter 1 (UART1) Block
00D0 UART1_RBR UART 1 Receive Buffer Register XX R 112
UART1_THR UART 1 Transmit Holding Register XX W 111
UART1_BRG_L UART 1 Baud Rate Generator
Register—Low Byte
02 R/W 110
00D1 UART1_IER UART 1 Interrupt Enable Register 00 R/W 112
UART1_BRG_H UART 1 Baud Rate Generator
Register—High Byte
00 R/W 110
00D2 UART1_IIR UART 1 Interrupt Identification Register 01 R 113
UART1_FCTL UART 1 FIFO Control Register 00 W 114
00D3 UART1_LCTL UART 1 Line Control Register 00 R/W 115
00D4 UART1_MCTL UART 1 Modem Control Register 00 R/W 117
Universal Asynchronous Receiver/Transmitter 1 (UART1) Block
00D5 UART1_LSR UART 1 Line Status Register 60 R/W 118
00D6 UART1_MSR UART 1 Modem Status Register XX R/W 120
00D7 UART1_SPR UART 1 Scratch Pad Register 00 R/W 122
Low-Power Control
00DB CLK_PPD1 Clock Peripheral Power-Down Register 1 00 R/W 36
00DC CLK_PPD2 Clock Peripheral Power-Down Register 2 00 R/W 37
Real-Time Clock
00E0 RTC_SEC RTC Seconds Register3XX R/W 90
00E1 RTC_MIN RTC Minutes Register XX R/W391
00E2 RTC_HRS RTC Hours Register XX R/W392
00E3 RTC_DOW RTC Day-of-the-Week Register XX R/W393
00E4 RTC_DOM RTC Day-of-the-Month Register XX R/W394
00E5 RTC_MON RTC Month Register XX R/W395
00E6 RTC_YR RTC Year Register XX R/W396
00E7 RTC_CEN RTC Century Register XX R/W397
00E8 RTC_ASEC RTC Alarm Seconds Register XX R/W 98
Table 3. Register Map (Continued)
Address
(hex) Mnemonic Name
Reset
(hex)
CPU
Access
Page
No
PS013014-0107 Register Map
eZ80L92 MCU
Product Specification
30
00E9 RTC_AMIN RTC Alarm Minutes Register XX R/W 99
00EA RTC_AHRS RTC Alarm Hours Register XX R/W 100
00EB RTC_ADOW RTC Alarm Day-of-the-Week Register 0X R/W 101
00EC RTC_ACTRL RTC Alarm Control Register 00 R/W 102
00ED RTC_CTRL RTC Control Register4x0xxxx00b/
x0xxxx10b
R/W 103
Chip Select Bus Mode Control
00F0 CS0_BMC Chip Select 0 Bus Mode Control Register 02h R/W 71
00F1 CS1_BMC Chip Select 1 Bus Mode Control Register 02h R/W 71
00F2 CS2_BMC Chip Select 2 Bus Mode Control Register 02h R/W 71
00F3 CS3_BMC Chip Select 3 Bus Mode Control Register 02h R/W 71
Notes
1. After an external pin reset, the Watchdog Timer Control register is reset to 00h. After a Watchdog Timer time-out
reset, the Watchdog Timer Control register is reset to 20h.
2. When the CPU reads this register, the current sampled value of the port is read.
3. Read-only if RTC is locked; Read/Write if RTC is unlocked.
4. After an external pin reset or a WDT reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm
Sleep-Mode Recovery reset, the RTC Control register is reset to x0xxxx10b.
Table 3. Register Map (Continued)
Address
(hex) Mnemonic Name
Reset
(hex)
CPU
Access
Page
No
PS013014-0107 eZ80® CPU Core
eZ80L92 MCU
Product Specification
31
eZ80® CPU Core
ZiLOG’s eZ80® CPU is the first 8-bit microprocessor to support 16 MB linear addressing.
Each software module or task under a real-time executive or operating system can operate
in Z80 compatible (64 KB) mode or full 24-bit (16 MB) address mode.
The eZ80 CPU instruction set is a superset of the instruction sets for the Z80 and Z180
CPUs. Z80 and Z180 programs are executable on an eZ80 CPU with little or no
modification.
Features
The features of eZ80 CPU includes:
•
Code-compatible with Z80 and Z180 products.
•
24-bit linear address space.
•
Single-cycle instruction fetch.
•
Pipelined fetch, decode, and execute.
•
Dual Stack Pointers for ADL (24-bit) and Z80 (16-bit) memory modes.
•
24-bit CPU registers and arithmetic logic unit (ALU).
•
Debug support.
•
Non-maskable Interrupt (NMI) supporting 128 maskable vectored interrupts.
New and Improved Instructions
These new instructions are:
•
Four new block transfer instructions provide DMA-like operations for memory-to-I/O
and I/O-to-memory transfers:
–
INDRX (input from I/O, decrement the memory address, leave the I/O address
unchanged, and repeat).
–
INIRX (input from I/O, increment the memory address, leave the I/O address
unchanged, and repeat).
–
OTDRX (output to I/O, decrement the memory address, leave the I/O address
unchanged, and repeat).
–
OTIRX (output to I/O, increment the memory address, leave the I/O address
unchanged, and repeat).
PS013014-0107 eZ80® CPU Core
eZ80L92 MCU
Product Specification
32
•
Four other block transfer instructions are modified to improve performance related to
the eZ80190 device. These modified instructions are:
–
IND2R (input from I/O, decrement the memory address, decrement the I/O
address, and repeat).
–
INI2R (input from I/O, increment the memory address, increment the I/O address,
and repeat).
–
OTD2R (output to I/O, decrement the memory address, decrement the I/O
address, and repeat).
–
OTI2R (output to I/O, increment the memory address, increment the I/O address,
and repeat).
For more information on the eZ80 CPU, its instruction set, and eZ80 programming, refer
to the eZ80® CPU User Manual. For more information on the eZ80190, refer to the
eZ80190 Product Specification.
PS013014-0107 Reset
eZ80L92 MCU
Product Specification
33
Reset
RESET Operation
The RESET controller within the eZ80L92 MCU provides a consistent system reset
(RESET) function for all type of resets that may affect the system. Following four events
can cause a RESET:
•
External RESET pin assertion.
•
Watchdog Timer (WDT) time-out when configured to generate a RESET.
•
Real time clock alarm with eZ80 CPU in low-power SLEEP mode.
•
Execution of a Debug RESET command.
During RESET, an internal RESET mode timer holds the system in RESET for
257 system clock (SCLK) cycles. The RESET mode timer begins incrementing on the
next rising edge of SCLK following deactivation of all RESET events (RESET pin, WDT,
real time clock, and Debugger)
You must determine if 257 SCLK cycles provides sufficient time for the primary crystal
oscillator to stabilize.
RESET, through the external RESET pin, must always be executed following application
of power (VDD ramp). Without the RESET, following power-up, proper operation of the
eZ80L92 cannot be guaranteed.
Note:
PS013014-0107 Low-Power Modes
eZ80L92 MCU
Product Specification
34
Low-Power Modes
The eZ80L92 MCU provides a range of power-saving features. The highest level of power
reduction is provided by SLEEP mode. The next level of power reduction is provided by
the HALT instruction. The lowest level of power reduction is provided by the clock
peripheral power-down registers.
SLEEP Mode
Execution of the eZ80 CPU’s SLP instruction places the eZ80L92 MCU into SLEEP
mode. In SLEEP mode, the operating characteristics are:
•
Primary crystal oscillator is disabled.
•
System clock is disabled.
•
eZ80 CPU is idle.
•
Program counter (PC) stops incrementing.
•
32 kHz crystal oscillator continues to operate and drives the Real-Time Clock and the
Watchdog Timer (if WDT is configured to operate from the 32 kHz oscillator.)
The eZ80 CPU can be brought out of SLEEP mode by any of the following operations:
•
RESET through the external RESET pin driven Low.
•
RESET through a Real-Time Clock alarm.
•
RESET through a Watchdog Timer time-out (if running off of the 32 kHz oscillator and
configured to generate a RESET upon time-out).
•
RESET through execution of a Debug RESET command.
After exiting SLEEP mode, the standard RESET delay occurs to allow the primary crystal
oscillator to stabilize. See Reset on page 33.
HALT Mode
Execution of the eZ80 CPU’s HALT instruction places the eZ80L92 MCU into HALT
mode. In HALT mode, the operating characteristics are:
•
Primary crystal oscillator is enabled and continues to operate.
•
System clock is enabled and continues to operate.
•
eZ80 CPU is idle.
•
Program counter stops incrementing.
PS013014-0107 Low-Power Modes
eZ80L92 MCU
Product Specification
35
The eZ80 CPU can be brought out of HALT mode by any of the following operations:
•
Non-maskable interrupt (NMI).
•
Maskable interrupt.
•
RESET through the external RESET pin driven Low.
•
Watchdog Timer time-out (if configured to generate either an NMI or RESET upon
time-out).
•
RESET through execution of a Debug RESET command.
To minimize current in HALT mode, the system clock must be disabled for all unused on-
chip peripherals through the Clock Peripheral Power-Down Registers.
Clock Peripheral Power-Down Registers
To reduce power, the Clock Peripheral Power-Down Registers allow the system clock to
be disabled to unused on-chip peripherals. On RESET, all peripherals are enabled. The
clock to unused peripherals can be disabled by setting the appropriate bit in the Clock
Peripheral Power-Down Registers to 1. When powered down, the peripherals are com-
pletely disabled. To re-enable, the bit in the Clock Peripheral Power-Down Registers must
be cleared to 0.
Many peripherals feature separate enable/disable control bits that must be appropriately
set for operation. These peripheral specific enable/disable bits do not provide the same
level of power reduction as the Clock Peripheral Power-Down Registers. When powered
down, the standard peripheral control registers are not accessible for Read or Write access.
See Table 4 and Table 5.
PS013014-0107 Low-Power Modes
eZ80L92 MCU
Product Specification
36
Table 4. Clock Peripheral Power-Down Register 1 (CLK_PPD1 = 00DBh)
Bit 7 6 5 4 3 2 1 0
Reset 0 0000000
CPU Access R/W R/W R/W R R/W R/W R/W R/W
Note: R/W = Read/Write; R = Read Only.
Bit Position Value Description
7
GPIO_D_OFF
1 System clock to GPIO Port D is powered down.
Port D alternate functions do not operate correctly.
0 System clock to GPIO Port D is powered up.
6
GPIO_C_OFF
1 System clock to GPIO Port C is powered down.
Port C alternate functions do not operate correctly.
0 System clock to GPIO Port C is powered up.
5
GPIO_B_OFF
1 System clock to GPIO Port B is powered down.
Port B alternate functions do not operate correctly.
0 System clock to GPIO Port B is powered up.
4 Reserved.
3
SPI_OFF
1 System clock to SPI is powered down.
0 System clock to SPI is powered up.
2
I2C_OFF
1 System clock to I2C is powered down.
0 System clock to I2C is powered up.
1
UART1_OFF
1 System clock to UART1 is powered down.
0 System clock to UART1 is powered up.
0
UART0_OFF
1 System clock to UART0 and IrDA endec is powered down.
0 System clock to UART0 and IrDA endec is powered up.
PS013014-0107 Low-Power Modes
eZ80L92 MCU
Product Specification
37
Table 5. Clock Peripheral Power-Down Register 2 (CLK_PPD2 = 00DCh)
Bit 7 6 5 4 3 2 1 0
Reset 00000000
CPU Access R/W R R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write; R = Read Only.
Bit Position Value Description
7
PHI_OFF
1 PHI Clock output is disabled (output is high-impedance).
0 PHI Clock output is enabled.
6 0 Reserved.
5
PRT5_OFF
1 System clock to PRT5 is powered down.
0 System clock to PRT5 is powered up.
4
PRT4_OFF
1 System clock to PRT4 is powered down.
0 System clock to PRT4 is powered up.
3
PRT3_OFF
1 System clock to PRT3 is powered down.
0 System clock to PRT3 is powered up.
2
PRT2_OFF
1 System clock to PRT2 is powered down.
0 System clock to PRT2 is powered up.
1
PRT1_OFF
1 System clock to PRT1 is powered down.
0 System clock to PRT1 is powered up.
0
PRT0_OFF
1 System clock to PRT0 is powered down.
0 System clock to PRT0 is powered up.
PS013014-0107 General-Purpose Input/Output
eZ80L92 MCU
Product Specification
38
General-Purpose Input/Output
The eZ80L92 MCU features 24 General-Purpose Input/Output (GPIO) pins. The GPIO
pins are assembled as three 8-bit ports — Port B, Port C, and Port D. All port signals can
be configured for use as either inputs or outputs. In addition, all the port pins can be used
as vectored interrupt sources for the eZ80 CPU.
GPIO Operation
The GPIO operation is same for all 3 GPIO ports (Ports B, C, and D). Each port features
eight GPIO port pins. The operating mode for each pin is controlled by four bits that are
divided between four 8-bit registers. These GPIO mode control registers are:
•
Port x Data Register (Px_DR)
•
Port x Data Direction Register (Px_DDR)
•
Port x Alternate Register 1 (Px_ALT1)
•
Port x Alternate Register 2 (Px_ALT2)
where x is B, C, or D representing any of the three GPIO ports B, C, or D. The mode for
each pin is controlled by setting each register bit pertinent to the pin to be configured. For
example, the operating mode for Port B Pin 7 (PB7), is set by the values contained in
PB_DR[7], PB_DDR[7], PB_ALT1[7], and PB_ALT2[7].
The combination of the GPIO control register bits allows individual configuration of each
port pin for nine modes. In all modes, reading of the Port x Data register returns the
sampled state, or level, of the signal on the corresponding pin. Table 6 lists the function of
each port signal based upon these four register bits. After a RESET event, all GPIO port
pins are configured as standard digital inputs, with interrupts disabled.
PS013014-0107 General-Purpose Input/Output
eZ80L92 MCU
Product Specification
39
GPIO Mode 1. This port pin is configured as a standard digital output pin. The value
written to the Port x Data register (Px_DR) is located on the pin.
GPIO Mode 2. The port pin is configured as a standard digital input pin. The output is
tristated (high impedance). The value stored in the Port x Data register produces no effect.
As in all modes, a Read from the Port x Data register returns the pin’s value. GPIO Mode
2 is the default operating mode following a RESET.
GPIO Mode 3. The port pin is configured as open-drain I/O. The GPIO pins do not feature
an internal pull-up to the supply voltage. To employ the GPIO pin in OPEN-DRAIN
mode, an external pull-up resistor must connect the pin to the supply voltage. Writing a 0
to the Port x Data register outputs a Low at the pin. Writing a 1 to the Port x Data register
results in high-impedance output.
GPIO Mode 4. The port pin is configured as open-source I/O. The GPIO pins do not
feature an internal pull-down to the supply ground. To employ the GPIO pin in OPEN-
SOURCE mode, an external pull-down resistor must connect the pin to the supply ground.
Table 6. GPIO Mode Selection
GPIO
Mode
Px_ALT2
Bits7:0
Px_ALT1
Bits7:0
Px_DDR
Bits7:0
Px_DR
Bits7:0 Port Mode Output
10000Output 0
0001Output 1
2 0 0 1 0 Input from pin High impedance
0 0 1 1 Input from pin High impedance
3 0 1 0 0 Open-Drain output 0
0 1 0 1 Open-Drain I/O High impedance
4 0 1 1 0 Open source I/O High impedance
0 1 1 1 Open source output 1
5 1 0 0 0 Reserved High impedance
6 1 0 0 1 Interrupt—dual edge triggered High impedance
7 1 0 1 0 Port B, C, or D—alternate function controls port I/O.
1 0 1 1 Port B, C, or D—alternate function controls port I/O.
8 1 1 0 0 Interrupt—active Low High impedance
1 1 0 1 Interrupt—active High High impedance
9 1 1 1 0 Interrupt—falling edge triggered High impedance
1 1 1 1 Interrupt—rising edge triggered High impedance
PS013014-0107 General-Purpose Input/Output
eZ80L92 MCU
Product Specification
40
Writing a 1 to the Port x Data register outputs a High at the pin. Writing a 0 to the Port x
Data register results in a high-impedance output.
GPIO Mode 5. Reserved. This pin generates high-impedance output.
GPIO Mode 6. This bit enables a dual edge-triggered interrupt mode. Both rising and fall-
ing edge on the pin cause an interrupt request to be sent to the eZ80® CPU. Writing 1 to
the Port x Data register bit position resets the corresponding interrupt request. Writing 0
produces no effect. You must set the Port x Data register prior to entering the edge-
triggered interrupt mode.
GPIO Mode 7. For Ports B, C, and D, this port pin is configured to pass control over to the
alternate (secondary) functions assigned to the pin. For example, the alternate mode
function for PC7 is RI1 and the alternate mode function for PB4 is the Timer 4 Out. When
GPIO Mode 7 is enabled, the pin output data and pin tristated control come from the
alternate function's data output and tristate control, respectively. The value in the Port x
Data register has no effect on operation.
Input signals are sampled by the system clock before being passed to the alternate
function input.
GPIO Mode 8. The port pin is configured for level-sensitive interrupt modes. An interrupt
request is generated when the level at the pin is the same as the level stored in the Port x
Data register. The port pin value is sampled by the system clock. The input pin must be
held at the selected interrupt level for a minimum of 2 clock periods to initiate an interrupt.
The interrupt request remains active as long as this condition is maintained at the external
source.
GPIO Mode 9. The port pin is configured for single edge-triggered interrupt mode. The
value in the Port x Data register determines if a positive or negative edge causes an
interrupt request. A 0 in the Port x Data register bit sets the selected pin to generate an
interrupt request for falling edges. A 1 in the Port x Data register bit sets the selected pin to
generate an interrupt request for rising edges. The interrupt request remains active until a 1
is written to the corresponding interrupt request of the Port x Data register bit. Writing a 0
produces no effect on operation. You must set the Port x Data register before entering the
edge-triggered interrupt mode.
A simplified block diagram of a GPIO port pin is illustrated in Figure 3.
Note:
PS013014-0107 General-Purpose Input/Output
eZ80L92 MCU
Product Specification
41
GPIO Interrupts
Each port pin can be used as an interrupt source. Interrupts are either level-triggered or
edge-triggered.
Level-Triggered Interrupts
When the port is configured for level-triggered interrupts, the corresponding port pin is
tristated. An interrupt request is generated when the level at the pin is the same as the level
stored in the Port x Data register. The port pin value is sampled by the system clock. The
input pin must be held at the selected interrupt level for a minimum of 2 consecutive clock
cycles to initiate an interrupt. The interrupt request remains active as long as this condition
is maintained at the external source.
For example, if PD3 is programmed for low-level interrupt and the pin is forced Low for
2 consecutive clock cycles, an interrupt request signal is generated from that port pin and
sent to the eZ80 CPU. The interrupt request signal remains active until the external device
driving PD3 forces the pin High.
Edge-Triggered Interrupts
When the port is configured for edge-triggered interrupts, the corresponding port pin is
tristated. If the pin receives the correct edge from an external device, the port pin generates
an interrupt request signal to the eZ80 CPU. Any time a port pin is configured for
Figure 3. GPIO Port Pin Block Diagram
Port
Pin
GPIO Register
Data (Input)
GPIO Register
Data (Output)
System Clock
System Clock
Data Bus
Mode 1
GND
VDD
Mode 1
Mode 3
Mode 4
DQ
DQDQ
PS013014-0107 General-Purpose Input/Output
eZ80L92 MCU
Product Specification
42
edge-triggered interrupt, writing a 1 to that pin’s Port x Data register causes a reset of the
edge-detected interrupt. You must set the bit in the Port x Data register to 1 before entering
either single or dual edge-triggered interrupt mode for that port pin.
When configured for dual edge-triggered interrupt mode (GPIO Mode 6), both a rising
and a falling edge on the pin cause an interrupt request to be sent to the eZ80 CPU.
When configured for single edge-triggered interrupt mode (GPIO Mode 9), the value in
the Port x Data register determines if a positive or negative edge causes an interrupt
request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate
an interrupt request for rising edges.
GPIO Control Registers
The 12 GPIO Control Registers operate in groups of four with a set for each Port (Ports B,
C, and D). Each GPIO port features a Port Data register, Port Data Direction register, Port
Alternate register 1, and Port Alternate register 2.
Port x Data Registers
When the port pins are configured for one of the output modes, the data written to the
Port x Data Registers (see Table 7) are driven on the corresponding pins. In all modes,
reading from the Port x Data registers always returns the current sampled value of the
corresponding pins. When the port pins are configured as edge-triggered interrupt sources,
writing 1 to the corresponding bit in the Port x Data register clears the interrupt signal that
is sent to the eZ80 CPU. When the port pins are configured for edge-selectable interrupts
or level-sensitive interrupts, the value written to the Port x Data register bit selects the
interrupt edge or interrupt level. See Table 6.
Table 7. Port x Data Registers (PB_DR = 009Ah, PC_DR = 009Eh, PD_DR =
00A2h)
Bit 7 6 5 4 3 2 1 0
Reset XXXXXXXX
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: X = Undefined; R/W = Read/Write.
PS013014-0107 General-Purpose Input/Output
eZ80L92 MCU
Product Specification
43
Port x Data Direction Registers
In addition to the other GPIO Control Registers, the Port x Data Direction Registers (see
Table 8) control the operating modes of the GPIO port pins. See Table 6.
Port x Alternate Register 1
In addition to other GPIO Control Registers, the Port x Alternate Register 1 (see Table 9)
control the operating modes of the GPIO port pins. See Table 6.
Port x Alternate Register 2
In addition to other GPIO Control Registers, the Port x Alternate Register 2 (see Table 10)
control the operating modes of the GPIO port pins. See Table 6.
Table 8. Port x Data Direction Registers (PB_DDR = 009Bh, PC_DDR =
009Fh, PD_DDR = 00A3h)
Bit 7 6 5 4 3 2 1 0
Reset 1111111 1
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.
Table 9. Port x Alternate Registers 1 (PB_ALT1 = 009Ch, PC_ALT1 = 00A0h,
PD_ALT1 = 00A4h)
Bit 76543210
Reset 00000000
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.
Table 10. Port x Alternate Registers 2 (PB_ALT2 = 009Dh, PC_ALT2 =
00A1h, PD_ALT2 = 00A5h)
Bit 76543210
Reset 00000000
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.
PS013014-0107 Interrupt Controller
eZ80L92 MCU
Product Specification
44
Interrupt Controller
The interrupt controller on the eZ80L92 MCU routes the interrupt request signals from the
internal peripherals and external devices (through the GPIO pins) to the eZ80 CPU.
Maskable Interrupts
On the eZ80L92 MCU, all maskable interrupts use the eZ80 CPU’s vectored interrupt
function. Table 11 lists the low-byte vector for each of the maskable interrupt sources.
The maskable interrupt sources are listed in order of their priority, with vector 00h being
the highest-priority interrupt. The 16-bit interrupt vector is located at starting address
{I[7:0], IVECT[7:0]}, where I[7:0] is the eZ80 CPU’s Interrupt Page Address Register.
Your program must store the interrupt service routine starting address in the two-byte
interrupt vector locations. For example, for ADL mode the two-byte address for the SPI
interrupt service routine would be stored at {00h, I[7:0], 1Eh} and {00h, I[7:0], 1Fh}. In
Z80 mode, the two-byte address for the SPI interrupt service routine would be stored at
Table 11. Interrupt Vector Sources by Priority
Vector Source Vector Source Vector Source Vector Source
00h Unused 1Ah UART 1 34h Port B 2 4Eh Port C 7
02h Unused 1Ch I2C 36h Port B 3 50h Port D 0
04h Unused 1Eh SPI 38h Port B 4 52h Port D 1
06h Unused 20h Unused 3Ah Port B 5 54h Port D 2
08h Unused 22h Unused 3Ch Port B 6 56h Port D 3
0Ah PRT 0 24h Unused 3Eh Port B 7 58h Port D 4
0Ch PRT 1 26h Unused 40h Port C 0 5Ah Port D 5
0Eh PRT 2 28h Unused 42h Port C 1 5Ch Port D 6
10h PRT 3 2Ah Unused 44h Port C 2 5Eh Port D 7
12h PRT 4 2Ch Unused 46h Port C 3 60h Unused
14h PRT 5 2Eh Unused 48h Port C 4 62h Unused
16h RTC 30h Port B 0 4Ah Port C 5 64h Unused
18h UART 0 32h Port B 1 4Ch Port C 6 66h Unused
Note: Absolute locations 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h, and 66h are reserved for hardware
reset, NMI, and RST instruction.
PS013014-0107 Interrupt Controller
eZ80L92 MCU
Product Specification
45
{MBASE[7:0], I[7:0], 1Eh} and {MBASE, I[7:0], 1Fh}. The least significant byte is
stored at the lower address.
When any one or more of the interrupt requests (IRQs) become active, an interrupt request
is generated by the interrupt controller and sent to the CPU. The corresponding 8-bit
interrupt vector for the highest priority interrupt is placed on the 8-bit interrupt vector bus,
IVECT[7:0]. The interrupt vector bus is internal to the eZ80L92 and is therefore not
visible externally. The response time of the eZ80 CPU to an interrupt request is a
function of the current instruction being executed as well as the number of WAIT states
being asserted.
The interrupt vector, {I[7:0], IVECT[7:0]}, is visible on the address bus, ADDR[15:0],
when the interrupt service routine begins. The response of the eZ80 CPU to a vectored
interrupt on the eZ80L92 is explained in Table 12. Interrupt sources are required to be
active until the Interrupt Service Routine (ISR) starts. We recommend you to change the
Interrupt Page Address Register (I) value from its default value of 00h as this address can
create conflicts between the non-maskable interrupt vector, the RST instruction addresses,
and the maskable interrupt vectors.
Table 12. Vectored Interrupt Operation
Memory
Mode
ADL
Bit
MADL
Bit Operation
Z80 Mode 0 0 Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
•
IEF1 ← 0
•
IEF2 ← 0
•
The starting Program Counter is effectively {MBASE, PC[15:0]}.
•
Push the 2-byte return address PC[15:0] on the ({MBASE,SPS}) stack.
•
The ADL mode bit remains cleared to 0.
•
The interrupt vector address is located at { MBASE, I[7:0], IVECT[7:0] }.
•
PC[15:0] ← ( { MBASE, I[7:0], IVECT[7:0] } ).
•
The ending Program Counter is effectively {MBASE, PC[15:0]}
•
The interrupt service routine must end with RETI.
PS013014-0107 Interrupt Controller
eZ80L92 MCU
Product Specification
46
ADL Mode 1 0 Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
•
IEF1 ← 0
•
IEF2 ← 0
•
The starting Program Counter is PC[23:0].
•
Push the 3-byte return address, PC[23:0], onto the SPL stack.
•
The ADL mode bit remains set to 1.
•
The interrupt vector address is located at { 00h, I[7:0], IVECT[7:0] }.
•
PC[15:0] ← ( { 00h, I[7:0], IVECT[7:0] } ).
•
The ending Program Counter is { 00h, PC[15:0] }.
•
The interrupt service routine must end with RETI.
Z80 Mode 0 1 Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT[7:0], bus by the interrupting peripheral.
•
IEF1 ← 0
•
IEF2 ← 0
•
The starting Program Counter is effectively {MBASE, PC[15:0]}.
•
Push the 2-byte return address, PC[15:0], onto the SPL stack.
•
Push a 00h byte onto the SPL stack to indicate an interrupt from Z80®
mode (because ADL = 0).
•
Set the ADL mode bit to 1.
•
The interrupt vector address is located at { 00h, I[7:0], IVECT[7:0] }.
•
PC[15:0] ← ( { 00h, I[7:0], IVECT[7:0] } ).
•
The ending Program Counter is { 00h, PC[15:0] }.
•
The interrupt service routine must end with RETI.L
Table 12. Vectored Interrupt Operation (Continued)
Memory
Mode
ADL
Bit
MADL
Bit Operation
PS013014-0107 Interrupt Controller
eZ80L92 MCU
Product Specification
47
Non-maskable Interrupts
An active Low input on the NMI pin generates an interrupt request to the eZ80 CPU. This
non-maskable interrupt is always serviced by the eZ80 CPU, regardless of the state of the
Interrupt Enable flags (IEF1 and IEF2). The non-maskable interrupt is prioritized higher
than all maskable interrupts. The response of the eZ80 CPU to a non-maskable interrupt is
described in detail in eZ80® CPU User Manual (UM0077).
ADL Mode 1 1 Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
•
IEF1 ← 0
•
IEF2 ← 0
•
The starting Program Counter is PC[23:0].
•
Push the 3-byte return address, PC[23:0], onto the SPL stack.
•
Push a 01h byte onto the SPL stack to indicate a restart from ADL mode
(because ADL = 1).
•
The ADL mode bit remains set to 1.
•
The interrupt vector address is located at {00h, I[7:0], IVECT[7:0]}.
•
PC[15:0] ← ( { 00h, I[7:0], IVECT[7:0] } ).
•
The ending Program Counter is { 00h, PC[15:0] }.
•
The interrupt service routine must end with RETI.L
Table 12. Vectored Interrupt Operation (Continued)
Memory
Mode
ADL
Bit
MADL
Bit Operation
PS013014-0107 Chip Selects and Wait States
eZ80L92 MCU
Product Specification
48
Chip Selects and Wait States
The eZ80L92 MCU generates four Chip Selects for external devices. Each Chip Select is
programmed to access either memory space or I/O space. The Memory Chip Selects can
be individually programmed on a 64 KB boundary. Each I/O Chip Select can choose a
256-byte section of I/O space. In addition, each Chip Select can be programmed for up to
7 wait states.
Memory and I/O Chip Selects
Each of the Chip Selects is enabled for either the memory address space or the I/O address
space, but not both. To select the memory address space for a particular Chip Select,
CSx_IO (CSx_CTL[4]) must be reset to 0. To select the I/O address space for a particular
Chip Select, CSx_IO must be set to 1. After RESET, the default is for all Chip Selects to
be configured for the memory address space. For either the memory address space or the
I/O address space, the individual Chip Selects must be enabled by setting CSx_EN
(CSx_CTL[3]) to 1.
Memory Chip Select Operation
Operation of each Memory Chip Selects is controlled by three control registers. To enable
a particular Memory Chip Select, following conditions must be fulfilled:
•
The Chip Select is enabled by setting CSx_EN to 1.
•
The Chip Select is configured for Memory by clearing CSx_IO to 0.
•
The address is in the associated Chip Select range:
CSx
_LBR[7:0]
≤
ADDR[23:16]
≤
CSx
_UBR[7:0]
•
No higher priority (lower number) Chip Select meets the above conditions.
•
A memory access instruction must be executing.
If all the above conditions are met to generate a Memory Chip Select, then the following
actions occur:
•
The appropriate Chip Select—CS0, CS1, CS2, or CS3—is asserted (driven Low).
•
MREQ is asserted (driven Low).
•
Depending upon the instruction, either RD or WR is asserted (driven Low).
If the upper and lower bounds are set to the same value (CSx_UBR = CSx_LBR), then a
particular Chip Select is valid for a single 64 KB page.
PS013014-0107 Chip Selects and Wait States
eZ80L92 MCU
Product Specification
49
Memory Chip Select Priority
A lower-numbered Chip Select is given priority over a higher-numbered Chip Select. For
example, if the address space of Chip Select 0 overlaps the Chip Select 1 address space,
Chip Select 0 is active.
RESET States
On RESET, Chip Select 0 is active for all addresses, as its Lower Bound register resets to
00h and its Upper Bound register resets to FFh. All of the other Chip Select Lower and
Upper Bound registers reset to 00h.
Memory Chip Select Example
The use of Memory Chip Selects is illustrated in Figure 4. The associated control register
values are listed in Table 13. In this example, all 4 Chip Selects are enabled and
configured for memory addresses. Also, CS1 overlaps with CS0. As CS0 has the higher
than CS1, CS1 is not active for much of its defined address space.
Figure 4. Memory Chip Select Example
Memory
Location
FFFFFFh
D00000h
CFFFFFh
A00000h
9FFFFFh
7FFFFFh
800000h
000000h
CS3_UBR = FFh
CS3_LBR = D0h
CS2_UBR = CFh
CS2_LBR = A0h
CS1_UBR = 9Fh
CS0_UBR = 7Fh
CS0_LBR = CS1_LBR = 00h
CS3 Active
3 MB Address Space
CS2 Active
3 MB Address Space
CS1 Active
2 MB Address Space
CS0 Active
8 MB Address Space
PS013014-0107 Chip Selects and Wait States
eZ80L92 MCU
Product Specification
50
I/O Chip Select Operation
I/O Chip Selects are active when the CPU is performing I/O instructions. As the I/O space
is separate from the memory space in the eZ80L92 device, there can never be a conflict
between I/O and memory addresses.
The eZ80L92 MCU supports a 16-bit I/O address. The I/O Chip Select logic decodes the
High byte of the I/O address, ADDR[15:8]. Because the upper byte of the address bus,
ADDR[23:16], is ignored, the I/O devices is always accessed from within any memory
mode (ADL or Z80). The MBASE offset value used for setting the Z80 MEMORY mode
page is also always ignored.
Four I/O Chip Selects are available with the eZ80L92. To generate a particular I/O Chip
Select, the following conditions must be fulfilled:
•
The Chip Select is enabled by setting CSX_EN to 1.
•
The Chip Select is configured for I/O by setting CSx_IO to 1.
•
An I/O Chip Select address match occurs—ADDR[15:8] = CSx_LBR[7:0].
•
No higher-priority (lower-number) Chip Select meets the above conditions.
•
The I/O address is not within the on-chip peripheral address range 0080h–00FFh. On-
chip peripheral registers assume priority for all addresses where:
0080h
≤
ADDR[15:0]
≤
00FFh
•
An I/O instruction must be executing.
Table 13. Register Values for Memory Chip Select Example in Figure 4
Chip
Select
CSx_CTL[3]
CSx_EN
CSx_CTL[4]
CSx_IO CSx_LBR CSx_UBR Description
CS0 1 0 00h 7Fh CS0 is enabled as a Memory Chip Select.
Valid addresses range from
000000h–7FFFFFh.
CS1 1 0 00h 9Fh CS1 is enabled as a Memory Chip Select.
Valid addresses range from
800000h–9FFFFFh.
CS2 1 0 A0h CFh CS2 is enabled as a Memory Chip Select.
Valid addresses range from
A00000h–CFFFFFh.
CS3 1 0 D0h FFh CS3 is enabled as a Memory Chip Select.
Valid addresses range from
D00000h–FFFFFFh.
PS013014-0107 Chip Selects and Wait States
eZ80L92 MCU
Product Specification
51
If all the above conditions are met to generate an I/O Chip Select, then the following
actions occur:
•
The appropriate Chip Select—CS0, CS1, CS2, or CS3—is asserted (driven Low).
•
IORQ is asserted (driven Low).
•
Depending upon the instruction, either RD or WR is asserted (driven Low).
WAIT States
For each of the Chip Selects, programmable WAIT states can be asserted to provide
external devices with additional clock cycles to complete their Read or Write operations.
The number of WAIT states for a particular Chip Select is controlled by the 3-bit field
CSx_WAIT (CSx_CTL[7:5]). The WAIT states can be independently programmed to
provide 0 to 7 WAIT states for each Chip Select. The WAIT states idle the CPU for the
specified number of system clock cycles.
WAIT Input Signal
Similar to the programmable WAIT states, an external peripheral drives the WAIT input
pin to force the CPU to provide additional clock cycles to complete its Read or Write oper-
ation. Driving the WAIT pin Low stalls the CPU. The CPU resumes operation on the first
rising edge of the internal system clock following de-assertion of the WAIT pin.
If the WAIT pin is to be driven by an external device, the corresponding Chip Select for the
device must be programmed to provide at least one WAIT state. Due to input sampling of
the WAIT input pin (see Figure 5), one programmable WAIT state is required to allow the
external peripheral sufficient time to assert the WAIT pin. It is recommended that the cor-
responding Chip Select for the external device be programmed to provide the maximum
number of WAIT states (seven).
Figure 5. Wait Input Sampling Block Diagram
Caution:
System Clock
DQ
Wait
Pin
eZ80
CPU
PS013014-0107 Chip Selects and Wait States
eZ80L92 MCU
Product Specification
52
An example of WAIT state operation is illustrated in Figure 6. In this example, the Chip
Select is configured to provide a single WAIT state. The external peripheral being
accessed drives the WAIT pin Low to request assertion of an additional WAIT state. If the
WA I T pin is asserted for additional system clock cycles, WAIT states are added until the
WA I T pin is de-asserted (High).
Figure 6. Wait State Operation Example (Read Operation)
TCLK WAIT
TCSx_WAIT
X
ADDR[23:0]
DATA[7:0]
(input)
CSx
MREQ
RD
IN
INSTRD
WAIT
T
PS013014-0107 Chip Selects and Wait States
eZ80L92 MCU
Product Specification
53
Chip Selects During Bus Request/Bus Acknowledge Cycles
When the CPU relinquishes the address bus to an external peripheral in response to an
external bus request (BUSREQ), it drives the bus acknowledge pin (BUSACK) Low. The
external peripheral then drives the address bus (and data bus). The CPU continues to gen-
erate Chip Select signals in response to the address on the bus. External devices cannot
access the internal registers of the eZ80L92 MCU.
Bus Mode Controller
The bus mode controller allows the address and data bus timing and signal formats of the
eZ80L92 to be configured to connect seamlessly with external eZ80, Z80, Intel-, or
Motorola-compatible devices. Bus modes for each of the chip selects can be configured
independently using the Chip Select Bus Mode Control Registers. The number of eZ80
system clock cycles per bus mode state is also independently programmable. For Intel bus
mode, multiplexed address and data can be selected in which the lower byte of the address
and the data byte both use the data bus, DATA[7:0]. Each of the bus modes is explained in
more detail in the following sections.
eZ80® Bus Mode
Chip selects configured for eZ80 Bus Mode do not modify the bus signals from the CPU.
The timing diagrams for external Memory and I/O Read and Write operations are shown
in the AC Characteristics on page 203. The default mode for each chip select is eZ80s
mode.
Z80® Bus Mode
Chip selects configured for Z80 mode modify the Z80 bus signals to match the Z80
microprocessor address and data bus interface signal format and timing. During Read
operations, the Z80 Bus Mode employs three states (T1, T2, and T3) as described in
Table 14.
Table 14. Z80® Bus Mode Read States
STATE T1 The Read cycle begins in State T1. The CPU drives the address onto the address bus and
the associated Chip Select signal is asserted.
STATE T2 During State T2, the RD signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one eZ80
system clock cycle prior to the end of State T2, additional WAIT states (TWAIT) are asserted
until the WAIT pin is driven High.
STATE T3 During State T3, no bus signals are altered. The data is latched by the eZ80L92 at the rising
edge of the eZ80 system clock at the end of State T3.
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During Write operations, Z80 Bus Mode employs 3 states (T1, T2, and T3) as described in
Table 15.
Z80 Bus Mode Read and Write timing is illustrated in Figure 7 and Figure 8. The Z80 Bus
Mode states can be configured for 1 to 15 eZ80 system clock cycles. In these figures, each
Z80 Bus Mode state is two eZ80 system clock cycles in duration. Figure 7 and Figure 8
also illustrate the assertion of 1 WAIT state (TWAIT) by the external peripheral during each
Z80 Bus Mode cycle.
Table 15. Z80® Bus Mode Write States
STATE T1 The Write cycle begins in State T1. The CPU drives the address onto the address bus, the
associated Chip Select signal is asserted.
STATE T2 During State T2, the WR signal is asserted. Depending upon the instruction, either the
MREQ or IORQ signal is asserted. If the external WAIT pin is driven Low at least one eZ80
system clock cycle prior to the end of State T2, additional WAIT states (TWAIT) are asserted
until the WAIT pin is driven High.
STATE T3 During State T3, no bus signals are altered.
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Figure 7. Z80® Bus Mode Read Timing Example
System Clock
ADDR[23:0]
DATA[7:0]
CSx
MREQ
or IORQ
RD
WAIT
TCLK
WR
T1 T2 T3
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Intel Bus Mode
Chip selects configured for Intel Bus Mode modify the eZ80 bus signals to duplicate a
four-state memory transfer similar to that found on Intel-style microprocessors. The bus
signals and eZ80L92 pins are mapped as illustrated in Figure 9. In Intel Bus Mode, the
user can select either multiplexed or non-multiplexed address and data buses. In non-mul-
tiplexed operation, the address and data buses are separate. In multiplexed operation, the
lower byte of the address, ADDR[7:0], also appears on the data bus, DATA[7:0], during
State T1 of the Intel Bus Mode cycle. During multiplexed operation, the lower byte of the
address bus also appears on the address bus in addition to the data bus.
Figure 8. Z80® Bus Mode Write Timing Example
System Clock
ADDR[23:0]
DATA[7:0]
CSx
MREQ
or IORQ
RD
WAIT
TCLK
WR
T1 T2 T3
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Intel Bus Mode (Separate Address and Data Buses)
During Read operations with separate address and data buses, the Intel Bus Mode employs
4 states (T1, T2, T3, and T4) as described in Table 16.
Figure 9. Intel® Bus Mode Signal and Pin Mapping
Table 16. Intel® Bus Mode Read States (Separate Address and Data Buses)
STATE T1 The Read cycle begins in State T1. The CPU drives the address onto the
address bus and the associated Chip Select signal is asserted. The CPU
drives the ALE signal High at the beginning of T1. During the middle of T1,
the CPU drives ALE Low to facilitate the latching of the address.
STATE T2 During State T2, the CPU asserts the RD signal. Depending on the
instruction, either the MREQ or IORQ signal is asserted.
eZ80 Bus Mode
Signals (Pins)
INSTRD
RD
WR
WAIT
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
Multiplexed
Bus
Controller
ADDR[7:0]
Intel Bus
Signal Equvalents
ALE
RD
WR
READY
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
Bus Mode
Controller
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During Write operations with separate address and data buses, the Intel Bus Mode
employs 4 states (T1, T2, T3, and T4) as described in Table 17.
Intel Bus Mode timing is illustrated for a Read operation in Figure 10 and for a Write
operation in Figure 11. If the ReadY signal (external WAIT pin) is driven Low prior to the
beginning of State T3, additional WAIT states (TWAIT) are asserted until the ReadY signal
is driven High. The Intel Bus Mode states can be configured for 2 to 15 eZ80 system clock
cycles. In the figures, each Intel® Bus Mode state is 2 eZ80 system clock cycles in dura-
tion. Figure 10 and Figure 11 also illustrate the assertion of one WAIT state (TWAIT) by
the selected peripheral.
STATE T3 During State T3, no bus signals are altered. If the external ReadY (WAIT)
pin is driven Low at least one eZ80 system clock cycle prior to the
beginning of State T3, additional WAIT states (TWAIT) are asserted until the
ReadY pin is driven High.
STATE T4 The CPU latches the Read data at the beginning of State T4. The CPU
deasserts the RD signal and completes the Intel Bus Mode cycle.
Table 17. Intel® Bus Mode Write States (Separate Address and Data Buses)
STATE T1 The Write cycle begins in State T1. The CPU drives the address onto the
address bus, the associated Chip Select signal is asserted, and the data is
driven onto the data bus. The CPU drives the ALE signal High at the
beginning of T1. During the middle of T1, the CPU drives ALE Low to
facilitate the latching of the address.
STATE T2 During State T2, the CPU asserts the WR signal. Depending on the
instruction, either the MREQ or IORQ signal is asserted.
STATE T3 During State T3, no bus signals are altered. If the external ReadY (WAIT)
pin is driven Low at least one eZ80 system clock cycle prior to the
beginning of State T3, additional WAIT states (TWAIT) are asserted until the
ReadY pin is driven High.
STATE T4 The CPU deasserts the WR signal at the beginning of State T4. The CPU
holds the data and address buses through the end of T4. The bus cycle is
completed at the end of T4.
Table 16. Intel® Bus Mode Read States (Separate Address and Data Buses)
(Continued)
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Figure 10. Intel® Bus Mode Read Timing Example (Separate Address and Data Buses)
System Clock
ADDR[23:0]
DATA[7:0]
CSx
MREQ
or IORQ
RD
ALE
TWAIT
WR
READY
T1 T2 T3 T4
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Figure 11. Intel® Bus Mode Write Timing Example (Separate Address and Data Buses)
e
m Clock
DR[23:0]
D
ATA[7:0]
CSx
MREQ
or IORQ
WR
ALE
T
WAIT
RD
READY
T1 T2 T3 T4
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Intel® Bus Mode (Multiplexed Address and Data Bus)
During Read operations with multiplexed address and data, the Intel® Bus Mode employs
4 states (T1, T2, T3, and T4) as described in Table 18.
During Write operations with multiplexed address and data, the Intel® Bus Mode employs
4 states (T1, T2, T3, and T4) as described in Table 19.
Table 18. Intel® Bus Mode Read States (Multiplexed Address and Data Bus)
STATE T1 The Read cycle begins in State T1. The CPU drives the address onto the
DATA bus and the associated Chip Select signal is asserted. The CPU
drives the ALE signal High at the beginning of T1. During the middle of T1,
the CPU drives ALE Low to facilitate the latching of the address.
STATE T2 During State T2, the CPU removes the address from the DATA bus and
asserts the RD signal. Depending upon the instruction, either the MREQ or
IORQ signal is asserted.
STATE T3 During State T3, no bus signals are altered. If the external ReadY (WAIT)
pin is driven Low at least one eZ80 system clock cycle prior to the
beginning of State T3, additional WAIT states (TWAIT) are asserted until the
ReadY pin is driven High.
STATE T4 The CPU latches the Read data at the beginning of State T4. The CPU de-
asserts the RD signal and completes the Intel® Bus Mode cycle.
Table 19. Intel® Bus Mode Write States (Multiplexed Address and Data Bus)
STATE T1 The Write cycle begins in State T1. The CPU drives the address onto the
DATA bus and drives the ALE signal High at the beginning of T1. During
the middle of T1, the CPU drives ALE Low to facilitate the latching of the
address.
STATE T2 During State T2, the CPU removes the address from the DATA bus and
drives the Write data onto the DATA bus. The WR signal is asserted to
indicate a Write operation.
STATE T3 During State T3, no bus signals are altered. If the external ReadY (WAIT)
pin is driven Low at least one eZ80 system clock cycle prior to the
beginning of State T3, additional WAIT states (TWAIT) are asserted until the
ReadY pin is driven High.
STATE T4 The CPU deasserts the Write signal at the beginning of T4 identifying the
end of the Write operation. The CPU holds the data and address buses
through the end of T4. The bus cycle is completed at the end of T4.
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Signal timing for Intel® Bus Mode with multiplexed address and data is illustrated for a
Read operation in Figure 12 and for a Write operation in Figure 13. In the figures, each
Intel® Bus Mode state is 2 eZ80 system clock cycles in duration. Figure 12 and Figure 13
also illustrate the assertion of one WAIT state (TWAIT) by the selected peripheral.
Figure 12. Intel® Bus Mode Read Timing Example (Multiplexed Address and Data Bus)
DATA[7:0]
System Clock
ADDR[23:0]
CSx
MREQ
or IORQ
RD
ALE
T
WAIT
WR
READY
T1 T2 T3 T4
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Motorola Bus Mode
Chip selects configured for Motorola Bus Mode modify the eZ80 bus signals to duplicate
an eight-state memory transfer similar to that found on Motorola-style microprocessors.
The bus signals (and eZ80L92 I/O pins) are mapped as illustrated in Figure 14.
Figure 13. Intel® Bus Mode Write Timing Example (Multiplexed Address and Data Bus)
System Clock
ADDR[23:0]
DATA[7:0]
CSx
MREQ
or IORQ
WR
ALE
T
WAIT
RD
READY
T1 T2 T3 T4
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During Write operations, the Motorola Bus Mode employs 8 states (S0, S1, S2, S3, S4, S5,
S6, and S7) as described in Table 20.
Figure 14. Motorola Bus Mode Signal and Pin Mapping
Table 20. Motorola Bus Mode Read States
STATE S0 The Read cycle starts in state S0. The CPU drives R/W High to identify a Read cycle.
STATE S1 Entering state S1, the CPU drives a valid address on the address bus, ADDR[23:0].
STATE S2 On the rising edge of state S2, the CPU asserts AS and DS.
STATE S3 During state S3, no bus signals are altered.
STATE S4 During state S4, the CPU waits for a cycle termination signal DTACK (WAIT), a peripheral
signal. If the termination signal is not asserted at least one full CPU clock period prior to the
rising clock edge at the end of S4, the CPU inserts WAIT (TWAIT) states until DTACK is
asserted. Each WAIT state is a full bus mode cycle.
STATE S5 During state S5, no bus signals are altered.
eZ80 Bus Mode
Signals (Pins)
INSTRD
RD
WR
WAIT
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
Motorola Bus
Signal Equvalents
AS
DS
R/W
DTACK
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
Bus Mode
Controller
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The eight states for a Write operation in Motorola Bus Mode are described in Table 21.
STATE S6 During state S6, data from the external peripheral device is driven onto the data bus.
STATE S7 On the rising edge of the clock entering state S7, the CPU latches data from the addressed
peripheral device and deasserts AS and DS. The peripheral device deasserts DTACK at
this time.
Table 21. Motorola Bus Mode Write States
STATE S0 The Write cycle starts in S0. The CPU drives R/W High (if a preceding Write cycle leaves R/
W Low).
STATE S1 Entering S1, the CPU drives a valid address on the address bus.
STATE S2 On the rising edge of S2, the CPU asserts AS and drives R/W Low.
STATE S3 During S3, the data bus is driven out of the high-impedance state as the data to be written is
placed on the bus.
STATE S4 At the rising edge of S4, the CPU asserts DS. The CPU waits for a cycle termination signal
DTACK (WAIT). If the termination signal is not asserted at least one full CPU clock period
prior to the rising clock edge at the end of S4, the CPU inserts WAIT (TWAIT) states until
DTACK is asserted. Each WAIT state is a full bus mode cycle.
STATE S5 During S5, no bus signals are altered.
STATE S6 During S6, no bus signals are altered.
STATE S7 Upon entering S7, the CPU deasserts AS and DS. As the clock rises at the end of S7, the
CPU drives R/W High. The peripheral device deasserts DTACK at this time.
Table 20. Motorola Bus Mode Read States (Continued)
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Figure 15. Motorola Bus Mode Read Timing Example
System Clock
ADDR[23:0]
DATA[7:0]
CSx
MREQ
or IORQ
DS
AS
S3
DTACK
R/W
S0 S1 S2 S4 S6
S5 S7
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Switching Between Bus Modes
Each time the bus mode controller must switch from one bus mode to another, there is a
one-cycle eZ80 system clock delay. An extra clock cycle is not required for repeated
accesses in any of the bus modes; nor is it required when the eZ80L92 switches to eZ80
Bus Mode. The extra clock cycles are not shown in the timing examples. Due to the asyn-
chronous nature of these bus protocols, the extra delay does not impact peripheral commu-
nication.
Chip Select Registers
Chip Select x Lower Bound Registers
For Memory Chip Selects, the Chip Select x Lower Bound register (see Table 22) defines
the lower bound of the address range for which the corresponding Memory Chip Select (if
Figure 16. Motorola Bus Mode Write Timing Example
System Clock
ADDR[23:0]
DATA[7:0]
CSx
MREQ
or IORQ
DS
AS
S3
DTACK
R/W
S0 S1 S2 S4 S6
S5 S7
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enabled) can be active. For I/O Chip Selects, this register defines the address to which
ADDR[15:8] is compared to generate an I/O Chip Select. All Chip Select lower bound
registers reset to 00h.
Table 22. Chip Select x Lower Bound Registers (CS0_LBR = 00A8h,
CS1_LBR = 00ABh, CS2_LBR = 00AEh, CS3_LBR = 00B1h)
Bit 76543210
CS0_LBR Reset 00000000
CS1_LBR Reset 00000000
CS2_LBR Reset 00000000
CS3_LBR Reset 00000000
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.
Bit
Position Value Description
[7:0]
CSx_LBR
00h–FFh For Memory Chip Selects (CSx_IO = 0)
This byte specifies the lower bound of the Chip Select
address range. The upper byte of the address bus,
ADDR[23:16], is compared to the values contained in these
registers for determining whether a Memory Chip Select
signal must be generated.
For I/O Chip Selects (CSx_IO = 1)
This byte specifies the Chip Select address value.
ADDR[15:8] is compared to the values contained in these
registers for determining whether an I/O Chip Select signal
must be generated.
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Chip Select x Upper Bound Registers
For Memory Chip Selects, the Chip Select x Upper Bound registers, detailed in Table 23,
defines the upper bound of the address range for which the corresponding Chip Select (if
enabled) can be active. For I/O Chip Selects, this register produces no effect. The reset
state for the Chip Select 0 Upper Bound register is FFh, while the reset state for the other
Chip Select upper bound registers is 00h.
Table 23. Chip Select x Upper Bound Registers (CS0_UBR = 00A9h,
CS1_UBR = 00ACh, CS2_UBR = 00AFh, CS3_UBR = 00B2h)
Bit 76543210
CS0_UBR Reset 11111111
CS1_UBR Reset 00000000
CS2_UBR Reset 00000000
CS3_UBR Reset 00000000
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.
Bit
Position Value Description
[7:0]
CSx_UBR
00h–FFh For Memory Chip Selects (CSx_IO = 0)
This byte specifies the upper bound of the Chip Select
address range. The upper byte of the address bus,
ADDR[23:16], is compared to the values contained in
these registers for determining whether a Chip Select
signal should be generated.
For I/O Chip Selects (CSx_IO = 1)
No effect.
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Chip Select x Control Registers
The Chip Select x Control register, detailed in Table 24, enables the Chip Selects, specifies
the type of Chip Select, and sets the number of WAIT states. The reset state for the Chip
Select 0 Control register is E8h, while the reset state for the 3 other Chip Select control
registers is 00h.
Table 24. Chip Select x Control Registers (CS0_CTL = 00AAh, CS1_CTL =
00ADh, CS2_CTL = 00B0h, CS3_CTL = 00B3h)
Bit 76543210
CS0_CTL Reset 11101000
CS1_CTL Reset 00000000
CS2_CTL Reset 00000000
CS3_CTL Reset 00000000
CPU Access R/W R/W R/W R/W R/W R R R
Note: R/W = Read/Write; R = Read Only.
Bit
Position Value Description
[7:5]
CSx_WAIT*
000 0 WAIT states are asserted when this Chip Select is active.
001 1 WAIT state is asserted when this Chip Select is active.
010 2 WAIT states are asserted when this Chip Select is active.
011 3 WAIT states are asserted when this Chip Select is active.
100 4 WAIT states are asserted when this Chip Select is active.
101 5 WAIT states are asserted when this Chip Select is active.
110 6 WAIT states are asserted when this Chip Select is active.
111 7 WAIT states are asserted when this Chip Select is active.
4
CSx_IO
0 Chip Select is configured as a Memory Chip Select.
1 Chip Select is configured as an I/O Chip Select.
3
CSx_EN
0 Chip Select is disabled.
1 Chip Select is enabled.
[2:0] 000 Reserved.
Note: *These WAIT state settings apply only to the default eZ80 bus mode. See Table 25.
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Chip Select x Bus Mode Control Registers
The Chip Select Bus Mode register, detailed in Table 25, configures the Chip Select for
eZ80, Z80, Intel®, or Motorola Bus Modes. Changing the bus mode allows the eZ80L92
to interface to peripherals based on the Z80, Intel®-, or Motorola-style asynchronous bus
interfaces. When a bus mode other than eZ80 is programmed for a particular Chip Select,
the CSx_WAIT setting in that Chip Select Control Register is ignored.
Table 25. Chip Select x Bus Mode Control Registers (CS0_BMC = 00F0h,
CS1_BMC = 00F1h, CS2_BMC = 00F2h, CS3_BMC = 00F3h)
Bit 76543210
CS0_BMC Reset 00000010
CS1_BMC Reset 00000010
CS2_BMC Reset 00000010
CS3_BMC Reset 00000010
CPU Access R/W R/W R/W R R/W R/W R/W R/W
Note: R/W = Read/Write; R = Read Only.
Bit
Position Value Description
[7:6]
BUS_MODE
00 eZ80 bus mode.
01 Z80 bus mode.
10 Intel® bus mode.
11 Motorola bus mode.
5
AD_MUX
0 Separate address and data.
1 Multiplexed address and data—appears on data bus
DATA[7:0].
4 0 Reserved.
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[3:0]
BUS_CYCLE
0000 Not valid.
0001 Each bus mode state is 1 eZ80 clock cycle in duration.1, 2, 3
0010 Each bus mode state is 2 eZ80 clock cycles in duration.
0011 Each bus mode state is 3 eZ80 clock cycles in duration.
0100 Each bus mode state is 4 eZ80 clock cycles in duration.
0101 Each bus mode state is 5 eZ80 clock cycles in duration.
0110 Each bus mode state is 6 eZ80 clock cycles in duration.
0111 Each bus mode state is 7 eZ80 clock cycles in duration.
1000 Each bus mode state is 8 eZ80 clock cycles in duration.
1001 Each bus mode state is 9 eZ80 clock cycles in duration.
1010 Each bus mode state is 10 eZ80 clock cycles in duration.
1011 Each bus mode state is 11 eZ80 clock cycles in duration.
1100 Each bus mode state is 12 eZ80 clock cycles in duration.
1101 Each bus mode state is 13 eZ80 clock cycles in duration.
1110 Each bus mode state is 14 eZ80 clock cycles in duration.
1111 Each bus mode state is 15 eZ80 clock cycles in duration.
Notes:
1. Setting the BUS_CYCLE to 1 in Intel Bus Mode causes the ALE pin to not function properly.
2. Use of the external WAIT input pin in Z80 Mode requires that BUS_CYCLE is set to a value
greater than 1.
3. These BUS_CYCLE values are not valid in eZ80 bus mode. See Table 24.
Bit
Position Value Description
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Watchdog Timer
The Watchdog Timer (WDT) helps protect against corrupt or unreliable software, power
faults, and other system-level problems which may place the eZ80 CPU into unsuitable
operating states. The eZ80L92 MCU WDT features:
•
Four programmable time-out periods: 218, 222, 225, and 227 clock cycles
•
Two selectable WDT clock sources: the system clock or the real time clock source
(on-chip 32 kHz crystal oscillator or 50/60 Hz signal)
•
A selectable time-out response: a time-out can be configured to generate either a
RESET or a non-maskable interrupt (NMI)
•
A WDT time-out RESET indicator flag
Figure 17 illustrates the block diagram for the Watchdog Timer.
Figure 17. Watchdog Timer Block Diagram
RESET
NMI to eZ80 CPU
28-Bit
Upcounter
Control Register/
Reset Register
WDT Control Logic
Data[7:0]
WDT_CLK
System Clock
RTC Clock
Time-Out Compare Logic
{WDT_PERIOD}
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Watchdog Timer Operation
Enabling and Disabling the WDT
The Watchdog Timer is disabled upon a system reset (RESET). To enable the WDT, the
application program must set the WDT_EN bit (bit 7) of the WDT_CTL register. When
enabled, the WDT cannot be disabled without a RESET.
Time-Out Period Selection
There are four choices of time-out periods for the WDT—218, 222, 225, and 227 system
clock cycles. The WDT time-out period is defined by the WDT_PERIOD field of the
WDT_CTL
register (WDT_CTL[1:0]). The approximate time-out periods for two
different WDT clock sources is listed in Table 26.
RESET Or NMI Generation
Upon a WDT time-out, the RST_FLAG in the WDT_CTL register is set to 1. In addition,
the WDT can cause a RESET or send a nonmaskable interrupt (NMI) signal to the CPU.
The default operation is for the WDT to cause a RESET. It asserts/deasserts on the rising
edge of the clock. The RST_FLAG bit can be polled by the CPU to determine the source
of the RESET event.
If the NMI_OUT bit in the WDT_CTL register is set to 1, then upon time-out, the WDT
asserts an NMI for CPU processing. The RST_FLAG bit can be polled by the CPU to
Table 26. Watchdog Timer Approximate Time-Out Delays
Clock Source Divider Value Time Out Delay
32.768 kHz Crystal Oscillator 218 8.00 s
32.768 kHz Crystal Oscillator 222 128 s
32.768 kHz Crystal Oscillator 225 1024 s
32.768 kHz Crystal Oscillator 227 4096 s
20 MHz System Clock 218 13.1 ms
20 MHz System Clock 222 209.7 ms
20 MHz System Clock 225 1.68 s
20 MHz System Clock 227 6.71 s
50 MHz System Clock 218 5.2 ms*
50 MHz System Clock 222 83.9 ms*
50 MHz System Clock 225 0.67 s
50 MHz System Clock 227 2.68 s
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determine the source of the NMI event, provided that the last RESET was not caused by
the WDT.
Watchdog Timer Registers
Watchdog Timer Control Register
The Watchdog Timer Control register, described in Table 27, is an 8-bit Read/Write regis-
ter used to enable the Watchdog Timer, set the time-out period, indicate the source of the
most recent RESET, and select the required operation upon WDT time-out.
Table 27. Watchdog Timer Control Register (WDT_CTL = 0093h)
Bit 76543210
Reset 000/100000
CPU Access R/W R/W R R/W R/W R R/W R/W
Note: R = Read only; R/W = Read/Write.
Bit
Position Value Description
7
WDT_EN
0 WDT is disabled.
1 WDT is enabled. When enabled, the WDT cannot be
disabled without a full RESET.
6
NMI_OUT
0 WDT time-out resets the CPU.
1 WDT time-out generates a nonmaskable interrupt (NMI) to
the CPU.
5
RST_FLAG*
0 RESET caused by external full-chip reset or ZDI reset.
1 RESET caused by WDT time-out. This flag is set by the WDT
time-out, even if the NMI_OUT flag is set to 1. The CPU can
poll this bit to determine the source of the RESET or NMI.
[4:3]
WDT_CLK
00 WDT clock source is system clock.
01 WDT clock source is Real-Time Clock source (32 kHz
on-chip oscillator or 50/60Hz input as set by RTC_CTRL[4]) .
10 Reserved.
11 Reserved.
2
RESERVED
0 Reserved.
Note: *RST_FLAG is only cleared by a non-WDT RESET.
PS013014-0107 Watchdog Timer
eZ80L92 MCU
Product Specification
76
Watchdog Timer Reset Register
The Watchdog Timer Reset register, described in Table 28, is an 8-bit Write-Only register.
The Watchdog Timer is reset when an A5h
value followed by 5Ah is written to this
register. Any amount of time can occur between the writing of the A5h value and the 5Ah
value, so long as the WDT time-out does not occur prior to completion.
[1:0]
WDT_PERIOD
00 WDT time-out period is 227 clock cycles.
01 WDT time-out period is 225 clock cycles.
10 WDT time-out period is 222 clock cycles.
11 WDT time-out period is 218 clock cycles.
Table 28. Watchdog Timer Reset Register (WDT_RR = 0094h)
Bit 76543210
Reset XXXXXXXX
CPU Access WWWWWWWW
Note: X = Undefined; W = Write only.
Bit
Position Value Description
[7:0]
WDT_RR
A5h The first Write value required to reset the WDT prior to a
time-out.
5Ah The second Write value required to reset the WDT prior to a
time-out. If an A5h, 5Ah sequence is written to WDT_RR, the
WDT timer is reset to its initial count value, and counting
resumes.
Bit
Position Value Description
Note: *RST_FLAG is only cleared by a non-WDT RESET.
PS013014-0107 Programmable Reload Timers
eZ80L92 MCU
Product Specification
77
Programmable Reload Timers
The eZ80L92 MCU features six Programmable Reload Timers (PRT). Each PRT contains
a 16-bit downcounter and a 16-bit reload register. In addition, each PRT features a clock
prescaler with four selectable taps for CLK ÷ 4, CLK ÷ 16, CLK ÷ 64, and CLK ÷ 256.
Each timer can be individually enabled to operate in either SINGLE PASS or
CONTINUOUS mode. The timer can be programmed to start, stop, restart from the
current value, or restart from the initial value, and generate interrupts to the CPU.
Four of the Programmable Reload Timers (timers 0–3) feature a selectable clock source
input. The input for these timers can be either the system clock or the Real-Time Clock
(RTC) source. Timers 0–3 can also be used for event counting, with their inputs received
from a GPIO port pin. Output from timers 4 and 5 can be directed to a GPIO port pin.
Each of the six PRTs available on the eZ80L92 can be controlled individually. They do not
share the same counters, reload registers, control registers, or interrupt signals.
A simplified block diagram of a programmable reload timer is illustrated in Figure 18.
Programmable Reload Timer Operation
Setting Timer Duration
There are three factors to consider when determining Programmable Reload Timer
duration—clock frequency, clock divider ratio, and initial count value. Minimum duration
Figure 18. Programmable Reload Timer Block Diagram
Reload Registers
{TMRx_RR_H, TMRx_RR_L}
Data[7:0]
Data[7:0]
Data[7:0]
TOUT_EN
(Timers 4—5 only)
16-Bit
Down Counter
Adjustable
Clock
Prescaler
TMRx_IN
(Timers 0—3
only)
TMRx_CTL[3:2]
System Clock
RTC Source
GPIO Pin
Control Register
TMRx_CTL
PRT
Control Logic
IRQ to eZ80 CPU
Timer Out
Data Registers
{TMRx_DR_H, TMRx_DR_L}
22
PS013014-0107 Programmable Reload Timers
eZ80L92 MCU
Product Specification
78
of the timer is achieved by loading 0001h. Maximum duration is achieved by loading
0000h, because the timer first rolls over to FFFFh and then continues counting down to
0000h.
The time-out period of the PRT is returned by the following equation:
To calculate the time-out period with the above equation when using an initial value of
0000h, enter a reload value of 65536 (FFFFh + 1).
Minimum time-out duration is 4 times longer than the input clock period and is generated
by setting the clock divider ratio to 1:4 and the reload value to 0001h. Maximum time-out
duration is 224 (16,777,216) times longer than the input clock period and is generated by
setting the clock divider ratio to 1:256 and the reload value to 0000h.
SINGLE PASS Mode
In SINGLE PASS mode, when the end-of-count value, 0000h, is reached, counting halts,
the timer is disabled, and the PRT_EN bit resets to 0. To restart the timer, the CPU must
reenable the timer by setting the PRT_EN bit to 1. An example of a PRT operating in
SINGLE PASS mode is illustrated in Figure 19. Timer register information is indicated
in Table 29.
PRT Time-Out Period = Clock Divider Ratio x Reload Value
System Clock Frequency
Figure 19. PRT SINGLE PASS Mode Operation Example
CLK
CLKEN
IOWRN
t 7:0]
IRQ
0
00
43 2 1
CNTH
t 7:0]
CNTL
PS013014-0107 Programmable Reload Timers
eZ80L92 MCU
Product Specification
79
CONTINUOUS Mode
In CONTINUOUS mode, when the end-of-count value, 0000h, is reached, the timer
automatically reloads the 16-bit start value from the Timer Reload registers,
TMRx_RR_H and TMRx_RR_L. Downcounting continues on the next clock edge. In
CONTINUOUS mode, the PRT continues to count until disabled. An example of a PRT
operating in CONTINUOUS mode is illustrated in Figure 20. Timer register information
is indicated in Table 30.
Table 29. PRT SINGLE PASS Mode Operation Example
Parameter Control Register(s) Value
PRT Enabled TMRx_CTL[0] 1
Reload and Restart Enabled TMRx_CTL[1] 1
PRT Clock Divider = 4 TMRx_CTL[3:2] 00b
SINGLE PASS Mode TMRx_CTL[4] 0
PRT Interrupt Enabled TMRx_CTL[6] 1
PRT Reload Value {TMRx_RR_H, TMRx_RR_L} 0004h
Figure 20. PRT CONTINUOUS Mode Operation Example
CLK
CLKEN
IOWRN
t 7:0]
IRQ
0
04
43 2 1
CNTH
t 7:0]
CNTL
PS013014-0107 Programmable Reload Timers
eZ80L92 MCU
Product Specification
80
Reading the Current Count Value
The CPU is capable of reading the current count value while the timer is running. This
Read event does not affect timer operation. The High byte of the current count value is
latched during a Read of the Low byte.
Timer Interrupts
The timer interrupt flag, PRT_IRQ, is set to 1 whenever the timer reaches its end-of-count
value, 0000h, in SINGLE PASS mode, or when the timer reloads the start value in
CONTINUOUS mode. The interrupt flag is only set when the timer reaches 0000h (or
reloads) from 0001h. The timer interrupt flag is not set to 1 when the timer is loaded with
the value 0000h, which selects the maximum time-out period.
The CPU can be programmed to poll the PRT_IRQ bit for the time-out event. Alterna-
tively, an interrupt service request signal can be sent to the CPU by setting IRQ_EN to 1.
Then, when the end-of-count value, 0000h, is reached and PRT_IRQ is set to 1, an
interrupt service request signal is passed to the CPU. PRT_IRQ is cleared to 0 and the
interrupt service request signal is inactivated whenever the CPU reads from the timer con-
trol registers, TMRx_CTL.
Timer Input Source Selection
Timers 0–3 feature programmable input source selection. By default, the input is taken
from the eZ80L92’s system clock. Alternatively, Timers 0–3 can take their input from port
input pins PB0 (Timers 0 and 2) or PB1 (Timers 1 and 3). Timers 0–3 can also use the
Real-Time Clock clock source (50, 60, or 32768 Hz) as their clock sources. When the
timer clock source is the Real-Time Clock signal, the timer decrements on the second
rising edge of the system clock following the falling edge of the RTC_XOUT pin. The
input source for these timers is set using the Timer Input Source Select register.
Table 30. PRT CONTINUOUS Mode Operation Example
Parameter Control Register(s) Value
PRT Enabled TMRx_CTL[0] 1
Reload and Restart Enabled TMRx_CTL[1] 1
PRT Clock Divider = 4 TMRx_CTL[3:2] 00b
CONTINUOUS Mode TMRx_CTL[4] 1
PRT Interrupt Enabled TMRx_CTL[6] 1
PRT Reload Value {TMRx_RR_H, TMRx_RR_L} 0004h
PS013014-0107 Programmable Reload Timers
eZ80L92 MCU
Product Specification
81
Event Counter
When Timers 0–3 are configured to take their inputs from port input pins PB0 and PB1,
they function as event counters. For event counting, the clock prescaler is bypassed.
The PRT counters decrement on every rising edge of the port pin. The port pins must
be configured as inputs. Due to the input sampling on the pins, the event input signal fre-
quency is limited to one-half the system clock frequency. Input sampling on the port pins
results in the PRT counter being updated on the fifth rising edge of the system clock after
the rising edge occurs at the port pin.
Timer Output
Two of the Programmable Reload Timers (Timers 4 and 5) can be directed to GPIO Port B
output pins (PB4 and PB5, respectively). To enable the Timer Out feature, the GPIO port
pin must be configured for alternate functions. After reset, the Timer Output feature is
disabled by default. The GPIO output pin toggles each time the PRT reaches its end-of-
count value. In CONTINUOUS mode operation, the disabling of the Timer Output feature
results in a Timer Output signal period that is twice the PRT time-out period. Examples of
the Timer Output operation are illustrated in Figure 21 and Table 31. In these examples,
the GPIO output is assumed to be Low (0) when the Timer Output function is enabled.
Figure 21. PRT Timer Output Operation Example
Table 31. PRT Timer Out Operation Example
Parameter Control Register(s) Value
PRT Enabled TMRx_CTL[0] 1
Reload and Restart Enabled TMRx_CTL[1] 1
CLK
PRT Clock
(Clock 4)
IOWRN
PRT Count
Value
Timer
Output
I/O Write to TMRx_CTL Enables PRT
X 3213
21
PS013014-0107 Programmable Reload Timers
eZ80L92 MCU
Product Specification
82
Programmable Reload Timer Registers
Each programmable reload timer is controlled using five 8-bit registers. These registers
are the Timer Control register, Timer Reload Low Byte register, Timer Reload High Byte
register, Timer Data Low Byte register, and Timer Data High Byte register.
The Timer Control register can be read or written to. The timer reload registers are Write-
Only and are located at the same I/O address as the timer data registers, which are Read-
Only.
Timer Control Registers
The Timer Control register, described in Table 32, is used to control operation of the timer,
including enabling the timer, selecting the clock divider, enabling the interrupt, selecting
between CONTINUOUS and SINGLE PASS modes, and enabling the auto-reload feature.
PRT Clock Divider = 4 TMRx_CTL[3:2] 00b
CONTINUOUS Mode TMRx_CTL[4] 1
PRT Reload Value {TMRx_RR_H,
TMRx_RR_L}
0003h
Table 32. Timer Control Registers (TMR0_CTL = 0080h, TMR1_CTL = 0083h,
TMR2_CTL = 0086h, TMR3_CTL = 0089h, TMR4_CTL = 008Ch, or TMR5_CTL
= 008Fh)
Bit 76543210
Reset 00000000
CPU Access R R/W R/W R/W R/W R/W R/W R/W
Note: R = Read only; R/W = Read/Write.
Bit
Position Value Description
7
PRT_IRQ
0 The timer does not reach its end-of-count value. This bit is reset
to 0 every time the TMRx_CTL register is read.
1 The timer reaches its end-of-count value. If IRQ_EN is set to 1,
an interrupt signal is sent to the CPU. This bit remains 1 until the
TMRx_CTL register is read.
Table 31. PRT Timer Out Operation Example (Continued)
Parameter Control Register(s) Value
PS013014-0107 Programmable Reload Timers
eZ80L92 MCU
Product Specification
83
Timer Data Registers—Low Byte
This Read-Only register returns the Low byte of the current count value of the selected
timer. The Timer Data Register—Low Byte, detailed in Table 33, can be read while the
timer is in operation. Reading the current count value does not affect timer operation. To
read the 16-bit data of the current count value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]},
first read the Timer Data Register—Low Byte and then read the Timer Data Register—
High Byte. The Timer Data Register—High Byte value is latched when a Read of the
Timer Data Register—Low Byte occurs.
The Timer Data registers and Timer Reload registers share the same address space.
6
IRQ_EN
0 Timer interrupt requests are disabled.
1 Timer interrupt requests are enabled.
5 0 Reserved.
4
PRT_MODE
0 The timer operates in SINGLE PASS mode. PRT_EN (bit 0) is
reset to 0, and counting stops when the end-of-count value is
reached.
1 The timer operates in CONTINUOUS mode. The timer reload
value is written to the counter when the end-of-count value is
reached.
[3:2]
CLK_DIV
00 Clock ÷ 4 is the timer input source.
01 Clock ÷ 16 is the timer input source.
10 Clock ÷ 64 is the timer input source.
11 Clock ÷ 256 is the timer input source.
1
RST_EN
0 The reload and restart function is disabled.
1 The reload and restart function is enabled. When a 1 is written to
RST_EN, the values in the reload registers are loaded into the
downcounter and the timer restarts.
0
PRT_EN
0 The programmable reload timer is disabled.
1 The programmable reload timer is enabled.
Note:
PS013014-0107 Programmable Reload Timers
eZ80L92 MCU
Product Specification
84
Timer Data Registers—High Byte
This Read-Only register returns the High byte of the current count value of the selected
timer. The Timer Data Register—High Byte, detailed in Table 34, can be read while the
timer is in operation. Reading the current count value does not affect timer operation. To
read the 16-bit data of the current count value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]},
first read the Timer Data Register—Low Byte and then read the Timer Data Register—
High Byte. The Timer Data Register—High Byte value is latched when a Read of the
Timer Data Register—Low Byte occurs.
The timer data registers and timer reload registers share the same address space.
Table 33. Timer Data Registers—Low Byte (TMR0_DR_L = 0081h,
TMR1_DR_L = 0084h, TMR2_DR_L = 0087h, TMR3_DR_L = 008Ah,
TMR4_DR_L = 008Dh, or TMR5_DR_L = 0090h)
Bit 76543210
Reset 00000000
CPU Access RRRRRRRR
Note: R = Read only.
Bit
Position Value Description
[7:0]
TMRx_DR_L
00h–FFh These bits represent the Low byte of the 2-byte timer data
value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}. Bit 7 is bit 7
of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the 16-bit
timer data value.
Table 34. Timer Data Registers—High Byte (TMR0_DR_H = 0082h,
TMR1_DR_H = 0085h, TMR2_DR_H = 0088h, TMR3_DR_H = 008Bh,
TMR4_DR_H = 008Eh, or TMR5_DR_H = 0091h)
Bit 76543210
Reset 00000000
CPU Access RRRRRRRR
Note: R = Read only.
Note:
PS013014-0107 Programmable Reload Timers
eZ80L92 MCU
Product Specification
85
Timer Reload Registers—Low Byte
The Timer Reload Register—Low Byte, described in Table 35, stores the least significant
byte (LSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload
value is reloaded into the timer upon end-of-count. When RST_EN (TMRx_CTL[1]) is set
to 1 to enable the automatic reload and restart function, the timer reload value is written to
the timer on the next rising edge of the clock.
The Timer Data registers and Timer Reload registers share the same address space.
Bit
Position Value Description
[7:0]
TMRx_DR_H
00h–FFh These bits represent the High byte of the 2-byte timer data
value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}. Bit 7 is bit 15
(msb) of the 16-bit timer data value. Bit 0 is bit 8 of the 16-bit
timer data value.
Table 35. Timer Reload Registers—Low Byte (TMR0_RR_L = 0081h,
TMR1_RR_L = 0084h, TMR2_RR_L = 0087h, TMR3_RR_L = 008Ah,
TMR4_RR_L = 008Dh, or TMR5_RR_L = 0090h)
Bit 76543210
Reset 00000000
CPU Access WWWWWWWW
Note: W = Write only.
Bit
Position Value Description
[7:0]
TMRx_RR_L
00h–FFh These bits represent the Low byte of the 2-byte timer
reload value, {TMRx_RR_H[7:0], TMRx_RR_L[7:0]}. Bit 7
is bit 7 of the 16-bit timer reload value. Bit 0 is bit 0 (lsb) of
the 16-bit timer reload value.
Note:
PS013014-0107 Programmable Reload Timers
eZ80L92 MCU
Product Specification
86
Timer Reload Registers—High Byte
The Timer Reload Register—High Byte, detailed in Table 36, stores the most significant
byte (MSB) of the 2-byte timer reload value. In CONTINUOUS mode, the timer reload
value is reloaded into the timer upon end-of-count. When RST_EN (TMRx_CTL[1]) is set
to 1 to enable the automatic reload and restart function, the timer reload value is written to
the timer on the next rising edge of the clock.
The Timer Data registers and Timer Reload registers share the same address space.
Timer Input Source Select Register
The Timer Input Source Select register, detailed in Table 37, sets the input source for Pro-
grammable Reload Timer 0–3 (TMR0, TMR1, TMR2, TMR3). Event frequency must be
less than one-half of the system clock frequency. When configured for event inputs
through the port pins, the Timers decrement on the fifth system clock rising edge follow-
ing the rising edge of the port pin.
Table 36. Timer Reload Registers—High Byte (TMR0_RR_H = 0082h,
TMR1_RR_H = 0085h, TMR2_RR_H = 0088h, TMR3_RR_H = 008Bh,
TMR4_RR_H = 008Eh, or TMR5_RR_H = 0091h)
Bit 76543210
Reset 00000000
CPU Access WWWWWWWW
Note: W = Write only.
Bit
Position Value Description
[7:0]
TMRx_RR_H
00h–FFh These bits represent the High byte of the 2-byte timer
reload value, {TMRx_RR_H[7:0], TMRx_RR_L[7:0]}. Bit 7
is bit 15 (msb) of the 16-bit timer reload value. Bit 0 is bit 8
of the 16-bit timer reload value.
Note:
PS013014-0107 Programmable Reload Timers
eZ80L92 MCU
Product Specification
87
Table 37. Timer Input Source Select Register (TMR_ISS = 0092h)
Bit 76543210
Reset 00000000
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.
Bit
Position Value Description
[7:6]
TMR3_IN
00 The timer counts at the system clock divided by the
prescaler.
01 The timer event input is the Real-Time Clock source
(32 kHz or 50/60 Hz—refer to the Real Time Clock section
on page 88 for details).
10 The timer event input is the GPIO Port B pin 1.
11 The timer event input is the GPIO Port B pin 1.
[5:4]
TMR2_IN
00 The timer counts at the system clock divided by the
prescaler.
01 The timer event input is the Real-Time Clock source
(32 kHz or 50/60 Hz—refer to the Real Time Clock section
on page 88 for details).
10 The timer event input is the GPIO Port B pin 0.
11 The timer event input is the GPIO Port B pin 0.
[3:2]
TMR1_IN
00 The timer counts at the system clock divided by the
prescaler.
01 The timer event input is the Real-Time Clock source
(32 kHz or 50/60 Hz—refer to the Real Time Clock section
on page 88 for details).
10 The timer event input is the GPIO Port B pin 1.
11 The timer event input is the GPIO Port B pin 1.
[1:0]
TMR0_IN
00 Timer counts at system clock divided by prescaler.
01 Timer event input is Real-Time Clock source
(32 kHz or 50/60 Hz—refer to the Real Time Clock section
on page 88 for details).
10 The timer event input is the GPIO Port B pin 0.
11 The timer event input is the GPIO Port B pin 0.
PS013014-0107 Real Time Clock
eZ80L92 MCU
Product Specification
88
Real Time Clock
The real time clock (RTC) keeps time by maintaining a count of seconds, minutes, hours,
day-of-the-week, day-of-the-month, year, and century. The current time is kept in 24-hour
format. The format for all count and alarm registers is selectable between binary and
binary-coded-decimal (BCD). The calendar operation maintains the correct day of the
month and automatically compensates for leap year. A simplified block diagram of the
RTC and the associated on-chip, low-power, 32 kHz oscillator is illustrated in Figure 22.
Connections to an external battery supply and 32 kHz crystal network are also demon-
strated in Figure 22.
Figure 22. Real Time Clock and 32 kHz Oscillator Block Diagram
RTC_V
RTC_X
DD
V
Enable
CLK_SEL
(RTC_CTRL[4])
32 KHz
Crystal
Battery
IRQ
ADDR[15:0]
DATA[7:0]
RTC Clock
System Clock
DD
VDD
IN
C
Low-Power
32 KHz Oscillator
Real-Time Clock
to eZ80 CPU
RTC_XOUT
C
R1
PS013014-0107 Real Time Clock
eZ80L92 MCU
Product Specification
89
Real Time Clock Alarm
The clock can be programmed to generate an alarm condition when the current count
matches the alarm set-point registers. Alarm registers are available for seconds, minutes,
hours, and day-of-the-week. Each alarm can be independently enabled. To generate an
alarm condition, the current time must match all enabled alarm values. For example, if the
day-of-the-week and hour alarms are both enabled, the alarm only occurs at the specified
hour on the specified day. The alarm triggers an interrupt if the interrupt enable bit,
INT_EN, is set. The alarm flag, ALARM, and corresponding interrupt to the CPU are
cleared by reading the RTC_CTRL register.
Alarm value registers and alarm control registers can be written at any time. Alarm condi-
tions are generated when the count value matches the alarm value. The comparison of
alarm and count values occurs whenever the RTC count increments (one time every sec-
ond). The RTC can also be forced to perform a comparison at any time by writing a 0 to
RTC_UNLOCK (RTC_UNLOCK is not required to be changed to a 1 first).
Real Time Clock Oscillator and Source Selection
The RTC count is driven by either an external 32 kHz on-chip oscillator or a 50/60 Hz
power-line frequency input connected to the 32 kHz RTC_XOUT pin. An internal divider
compensates for each of these options. The clock source and power-line frequencies are
selected in the RTC_CTRL register. Writing to the RTC_CTRL register resets the clock
divider.
Real Time Clock Battery Backup
The power supply pin (RTC_VDD) for the RTC and associated low-power 32 kHz
oscillator is isolated from the other power supply pins on the eZ80L92 MCU. To ensure
that the RTC continues to keep time in the event of loss of line power to the application,
a battery can be used to supply power to the RTC and the oscillator via the RTC_VDD pin.
All VSS (ground) pins must be connected together on the printed circuit assembly.
Real Time Clock Recommended Operation
Following a RESET from a powered-down condition, the counter values of the RTC are
undefined and all alarms are disabled. After a RESET from a powered-down condition,
the following procedure is recommended:
•
Write to RTC_CTRL to set RTC_UNLOCK and CLK_SEL.
•
Write values to the RTC count registers to set the current time.
•
Write values to the RTC alarm registers to set the appropriate alarm conditions.
•
Write to RTC_CTRL to clear RTC_UNLOCK; clearing the RTC_UNLOCK bit resets
and enables the clock divider.
PS013014-0107 Real Time Clock
eZ80L92 MCU
Product Specification
90
Real Time Clock Registers
The real time clock registers are accessed via the address and data bus using I/O
instructions. RTC_UNLOCK controls access to the RTC count registers. When unlocked
(RTC_UNLOCK = 1), the RTC count is disabled and the count registers are Read/Write.
When locked (RTC_UNLOCK = 0), the RTC count is enabled and the count registers are
Read-Only. The default, at RESET, is for the RTC to be locked.
Real Time Clock Seconds Register
This register contains the current seconds count. The value in the RTC_SEC register is
unchanged by a RESET. The current setting of BCD_EN determines whether the values in
this register are binary (BCD_EN = 0) or binary-coded decimal (BCD_EN = 1). Access to
this register is Read-Only if the RTC is locked and Read/Write if the RTC is unlocked.
See Table 38.
Table 38. Real Time Clock Seconds Register (RTC_SEC = 00E0h)
Bit 76543210
Reset XXXXXXXX
CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: X = Unchanged by RESET; R/W* = Read-only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1)
Bit
Position Value Description
[7:4]
TEN_SEC
0–5 The tens digit of the current seconds count.
[3:0]
SEC
0–9 The ones digit of the current seconds count.
Binary Operation (BCD_EN = 0)
Bit
Position Value Description
[7:0]
SEC
00h–3Bh The current seconds count.
PS013014-0107 Real Time Clock
eZ80L92 MCU
Product Specification
91
Real Time Clock Minutes Register
This register contains the current minutes count. See Table 39.
Table 39. Real Time Clock Minutes Register (RTC_MIN = 00E1h)
Bit 76543210
Reset XXXXXXXX
CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: X = Unchanged by RESET; R/W* = Read-only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1)
Bit
Position Value Description
[7:4]
TEN_MIN
0–5 The tens digit of the current minutes count.
[3:0]
MIN
0–9 The ones digit of the current minutes count.
Binary Operation (BCD_EN = 0)
Bit
Position Value Description
[7:0]
MIN
00h–3Bh The current minutes count.
PS013014-0107 Real Time Clock
eZ80L92 MCU
Product Specification
92
Real Time Clock Hours Register
This register contains the current hours count. See Table 40.
Table 40. Real Time Clock Hours Register (RTC_HRS = 00E2h)
Bit 76543210
Reset XXXXXXXX
CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: X = Unchanged by RESET; R/W* = Read-only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1)
Bit
Position Value Description
[7:4]
TEN_HRS
0–2 The tens digit of the current hours count.
[3:0]
HRS
0–9 The ones digit of the current hours count.
Binary Operation (BCD_EN = 0)
Bit
Position Value Description
[7:0]
HRS
00h–17h The current hours count.
PS013014-0107 Real Time Clock
eZ80L92 MCU
Product Specification
93
Real Time Clock Day-of-the-Week Register
This register contains the current day-of-the-week count. The RTC_DOW register begins
counting at 01h. See Table 41.
Table 41. Real Time Clock Day-of-the-Week Register (RTC_DOW = 00E3h)
Bit 76543210
Reset 0000XXXX
CPU Access RRRRR/W*R/W*R/W*R/W*
Note: X = Unchanged by RESET; R = Read Only; R/W* = Read-only if RTC locked, Read/Write if
RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1)
Bit
Position Value Description
[7:4] 0000 Reserved.
[3:0]
DOW
1-7 The current day-of-the-week.count.
Binary Operation (BCD_EN = 0)
Bit
Position Value Description
[7:4] 0000 Reserved.
[3:0]
DOW
01h–07h The current day-of-the-week count.
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Real Time Clock Day-of-the-Month Register
This register contains the current day-of-the-month count. The RTC_DOM register begins
counting at 01h. See Table 42.
Table 42. Real Time Clock Day-of-the-Month Register (RTC_DOM = 00E4h)
Bit 76543210
Reset XXXXXXXX
CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: X = Unchanged by RESET; R/W* = Read-only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1)
Bit
Position Value Description
[7:4]
TENS_DOM
0–3 The tens digit of the current day-of-the-month count.
[3:0]
DOM
0–9 The ones digit of the current day-of-the-month count.
Binary Operation (BCD_EN = 0)
Bit
Position Value Description
[7:0]
DOM
01h–1Fh The current day-of-the-month count.
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Real Time Clock Month Register
This register contains the current month count. See Table 43.
Table 43. Real Time Clock Month Register (RTC_MON = 00E5h)
Bit 76543210
Reset XXXXXXXX
CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: X = Unchanged by RESET; R/W* = Read-only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1)
Bit
Position Value Description
[7:4]
TENS_MON
0–1 The tens digit of the current month count.
[3:0]
MON
0–9 The ones digit of the current month count.
Binary Operation (BCD_EN = 0)
Bit
Position Value Description
[7:0]
MON
01h–0Ch The current month count.
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Real Time Clock Year Register
This register contains the current year count. See Table 44.
Table 44. Real Time Clock Year Register (RTC_YR = 00E6h)
Bit 76543210
Reset XXXXXXXX
CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: X = Unchanged by RESET; R/W* = Read-only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1)
Bit
Position Value Description
[7:4]
TENS_YR
0–9 The tens digit of the current year count.
[3:0]
YR
0–9 The ones digit of the current year count.
Binary Operation (BCD_EN = 0)
Bit
Position Value Description
[7:0]
YR
00h–63h The current year count.
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Real Time Clock Century Register
This register contains the current century count. See Table 45.
Table 45. Real Time Clock Century Register (RTC_CEN = 00E7h)
Bit 76543210
Reset XXXXXXXX
CPU Access R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: X = Unchanged by RESET; R/W* = Read-only if RTC locked, Read/Write if RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1)
Bit
Position Value Description
[7:4]
TENS_CEN
0–9 The tens digit of the current century count.
[3:0]
CEN
0–9 The ones digit of the current century count.
Binary Operation (BCD_EN = 0)
Bit
Position Value Description
[7:0]
CEN
00h–63h The current century count.
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Real Time Clock Alarm Seconds Register
This register contains the alarm seconds value. See Table 46.
Table 46. Real Time Clock Alarm Seconds Register (RTC_ASEC = 00E8h)
Bit 76543210
Reset XXXXXXXX
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: X = Unchanged by RESET; R/W = Read/Write.
Binary-Coded-Decimal Operation (BCD_EN = 1)
Bit
Position Value Description
[7:4]
ATEN_SEC
0–5 The tens digit of the alarm seconds value.
[3:0]
ASEC
0–9 The ones digit of the alarm seconds value.
Binary Operation (BCD_EN = 0)
Bit
Position Value Description
[7:0]
ASEC
00h–
3Bh
The alarm seconds value.
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Real Time Clock Alarm Minutes Register
This register contains the alarm minutes value. See Table 47.
Table 47. Real Time Clock Alarm Minutes Register (RTC_AMIN = 00E9h)
Bit 76543210
Reset XXXXXXXX
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: X = Unchanged by RESET; R/W = Read/Write.
Binary-Coded-Decimal Operation (BCD_EN = 1)
Bit
Position Value Description
[7:4]
ATEN_MIN
0–5 The tens digit of the alarm minutes value.
[3:0]
AMIN
0–9 The ones digit of the alarm minutes value.
Binary Operation (BCD_EN = 0)
Bit
Position Value Description
[7:0]
AMIN
00h–3Bh The alarm minutes value.
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Real Time Clock Alarm Hours Register
This register contains the alarm hours value. See Table 48.
Table 48. Real Time Clock Alarm Hours Register (RTC_AHRS = 00EAh)
Bit 76543210
Reset XXXXXXXX
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: X = Unchanged by RESET; R/W = Read/Write.
Binary-Coded-Decimal Operation (BCD_EN = 1)
Bit
Position Value Description
[7:4]
ATEN_HRS
0–2 The tens digit of the alarm hours value.
[3:0]
AHRS
0–9 The ones digit of the alarm hours value.
Binary Operation (BCD_EN = 0)
Bit
Position Value Description
[7:0]
AHRS
00h–17h The alarm hours value.
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Real Time Clock Alarm Day-of-the-Week Register
This register contains the alarm day-of-the-week value. See Table 49.
Table 49. Real Time Clock Alarm Day-of-the-Week Register (RTC_ADOW =
00EBh)
Bit 76543210
Reset 0000XXXX
CPU Access RRRRR/W*R/W*R/W*R/W*
Note: X = Unchanged by RESET; R = Read Only; R/W* = Read-only if RTC locked, Read/Write if
RTC unlocked.
Binary-Coded-Decimal Operation (BCD_EN = 1)
Bit
Position Value Description
[7:4] 0000 Reserved.
[3:0]
ADOW
1-7 The alarm day-of-the-week.value.
Binary Operation (BCD_EN = 0)
Bit
Position Value Description
[7:4] 0000 Reserved.
[3:0]
ADOW
01h–07h The alarm day-of-the-week value.
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Real Time Clock Alarm Control Register
This register contains alarm enable bits for the real-time clock. The RTC_ACTRL register
is cleared by a RESET. See Table 50.
Real-Time Clock Control Register
This register contains control and status bits for the real-time clock. Some bits in the
RTC_CTRL register are cleared by a RESET. The ALARM flag and associated interrupt
(if INT_EN is enabled) are cleared by reading this register. The ALARM flag is updated
by clearing (locking) RTC_UNLOCK or by an increment of the RTC count. Writing to the
RTC_CTRL register also resets the RTC count prescaler allowing the RTC to be synchro-
nized to another time source.
SLP_WAKE indicates if an RTC alarm condition initiated the CPU recovery from SLEEP
mode. This bit can be checked after RESET to determine if a sleep-mode recovery is
caused by the RTC. SLP_WAKE is cleared by a Read of the RTC_CTRL register.
Setting BCD_EN causes the RTC to use BCD counting in all registers including the alarm
set points.
Table 50. Real Time Clock Alarm Control Register (RTC_ACTRL = 00ECh)
Bit 76543210
Reset 00000000
CPU Access RRRRR/WR/WR/WR/W
Note: X = Unchanged by RESET; R = Read-only; R/W = Read/Write.
Bit
Position Value Description
[7:4] 0000 Reserved.
3
ADOW_EN
0 The day-of-the-week alarm is disabled.
1 The day-of-the-week alarm is enabled.
2
AHRS_EN
0 The hours alarm is disabled.
1 The hours alarm is enabled.
1
AMIN_EN
0 The minutes alarm is disabled.
1 The minutes alarm is enabled.
0
ASEC_EN
0 The seconds alarm is disabled.
1 The seconds alarm is enabled.
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CLK_SEL and FREQ_SEL select the RTC clock source. If the 32 kHz crystal option is
selected the oscillator is enabled and the internal prescaler is set to divide by 32768. If the
power-line frequency option is selected, the prescale value is set by FREQ_SEL, and the
32 kHz oscillator is disabled. See Table 51.
Table 51. Real Time Clock Control Register (RTC_CTRL = 00EDh)
Bit 76543210
Reset X0XXXX0/10
CPU Access R R/W R/W R/W R/W R R R/W
Note: X = Unchanged by RESET; R = Read-only; R/W = Read/Write.
Bit
Position Value Description
7
ALARM
0 Alarm interrupt is inactive.
1 Alarm interrupt is active.
6
INT_EN
0 Interrupt on alarm condition is disabled.
1 Interrupt on alarm condition is enabled.
5
BCD_EN
0 RTC count and alarm value registers are binary.
1 RTC count and alarm value registers are binary-coded
decimal (BCD).
4
CLK_SEL
0 RTC clock source is crystal oscillator output (32768 Hz).
On-chip 32768 Hz oscillator is enabled.
1 RTC clock source is power-line frequency input.
On-chip 32768 Hz oscillator is disabled.
3
FREQ_SEL
0 Power-line frequency is 60 Hz.
1 Power-line frequency is 50 Hz.
20Reserved.
1
SLP_WAKE
0 RTC does not generate a Sleep-Mode Recovery reset.
1 RTC Alarm generates a Sleep-Mode Recovery reset.
0
RTC_UNLOCK
0 RTC count registers are locked to prevent write access.
RTC counter is enabled.
1 RTC count registers are unlocked to allow write access.
RTC counter is disabled.
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eZ80L92 MCU
Product Specification
104
Universal Asynchronous Receiver/
Transmitter
The UART module implements the logic required to support various asynchronous
communications protocols. The module also implements two separate 16-byte-deep
FIFOs for both transmission and reception. A block diagram of the UART is illustrated
in Figure 23.
The UART module provides the following asynchronous communication protocol-related
features and functions:
•
5-bit, 6-bit, 7-bit, or 8-bit data transmission
•
Even parity/odd parity or no parity bit generation and detection
•
Start and stop bit generation and detection (supports up to two stop bits)
•
Line break detection and generation
•
Receiver overrun and framing errors detection
•
Logic and associated I/O to provide modem handshake capability
Figure 23. UART Block Diagram
System Clock
I/O Address
Data
Receive
Buffer
Transmit
Buffer
Modem
Control
Logic
Interrupt Signal
to eZ80 CPU
UART Control Interface and Baud Rate Generator
RxD0/RxD1
TxD0/TxD1
CTS0/CTS1
RTS0/RTS1
DSR0/DSR1
DTR0/DTR1
DCD0/DCD1
RI0/RI1
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UART Functional Description
The UART function implements the following:
•
The transmitter and associated control logic.
•
The receiver and associated control logic.
•
The modem interface and associated logic.
UART Transmitter
The transmitter block controls the data transmitted on the TxD output. It implements the
FIFO, accessed through the UARTx_THR register, the transmit shift register, the parity
generator, and control logic for the transmitter to control parameters for the asynchronous
communication protocol.
The UARTx_THR is a Write-Only register. The processor writes the data byte to be
transmitted into this register. In the FIFO mode, up to 16 data bytes can be written via the
UARTx_THR register. The data byte from the FIFO is transferred to the transmit shift
register at the appropriate time and transmitted out on TxD output. After SYNC_RESET,
the UARTx_THR register is empty. Therefore, the Transmit Holding Register Empty
(THRE) bit (bit 5 of the UARTx_LSR
register) is 1 and an interrupt is sent to the
processor (if interrupts are enabled). The processor can reset this interrupt by loading
data into the UARTx_THR register, which clears the transmitter interrupt.
The transmit shift register places the byte to be transmitted on the TxD signal serially. The
least-significant bit of the byte to be transmitted is shifted out first and the most significant
bit is shifted out last. The control logic within the block adds the asynchronous communi-
cation protocol bits to the data byte being transmitted. The transmitter block obtains the
parameters for the protocol from the bits programmed via the UARTx_LCTL register.
The TxD output is set to 1 if the transmitter is idle (it does not contain any data to be
transmitted).
The transmitter operates with the Baud Rate Generator (BRG) clock. The data bits are
placed on the TxD output one time every 16 BRG clock cycles. The transmitter block also
implements a parity generator that attaches the parity bit to the byte, if programmed.
UART Receiver
The receiver block controls the data reception from the RxD signal. The receiver block
implements a receiver shift register, receiver line error condition monitoring logic and
receiver data ready logic. It also implements the parity checker.
The UARTx_RBR is a Read-Only register of the module. The processor reads received
data from this register. The condition of the UARTx_RBR register is monitored by the
DR bit (bit 0 of the UARTx_LSR register). The DR bit is 1 when a data byte is received
and transferred to the UARTx_RBR register from the receiver shift register. The DR bit
PS013014-0107 Universal Asynchronous Receiver/Transmitter
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is reset only when the processor reads all of the received data bytes. If the number of bits
received is less than eight, the unused most significant bits of the data byte Read are 0.
The receiver uses the clock from the BRG for receiving the data. This clock must be 16
times the appropriate baud rate. The receiver synchronizes the shift clock on the falling
edge of the RxD input start bit. It then receives a complete byte according to the set
parameters. The receiver also implements logic to detect framing errors, parity errors,
overrun errors, and break signals.
UART Modem Control
The modem control logic provides two outputs and four inputs for handshaking with the
modem. Any change in the modem status inputs, except RI, is detected and an interrupt
can be generated. For RI, an interrupt is generated only when the trailing edge of the RI is
detected. The module also provides LOOP mode for self-diagnostics.
UART Interrupts
There are five different sources of interrupts from the UART are:
•
Transmitter.
•
Receiver (three different interrupts).
•
Modem status.
UART Transmitter Interrupt
The transmitter interrupt is generated if there is no data available for transmission. This
interrupt can be disabled using the individual interrupt enable bit or cleared by writing
data into the UARTx_THR register.
UART Receiver Interrupts
A receiver interrupt can be generated by three possible sources. The first source, a receiver
data ready, indicates that one or more data bytes are received and are ready to be read. This
interrupt is generated if the number of bytes in the receiver FIFO is greater than or equal to
the trigger level. If the FIFO is not enabled, the interrupt is generated if the receive buffer
contains a data byte. This interrupt is cleared by reading the UARTx_RBR.
The second interrupt source is the receiver time-out. A receiver time-out interrupt is gen-
erated when there are fewer data bytes in the receiver FIFO than the trigger level and there
are no Reads and Writes to or from the receiver FIFO for four consecutive byte times.
When the receiver time-out interrupt is generated, it is cleared only after emptying the
entire receive FIFO.
The first two interrupt sources from the receiver (data ready and time-out) share an
interrupt enable bit.
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The third source of a receiver interrupt is a line status error, indicating an error in byte
reception. This error may result from:
•
Incorrect received parity.
•
Incorrect framing; that is, the stop bit is not detected by receiver at the end of the byte.
•
Receiver over run condition.
•
A BREAK condition being detected on the receive data input.
An interrupt due to one of the above conditions is cleared when the UARTx_LSR register
is read. In FIFO mode, a line status interrupt is generated only after the received byte with
an error reaches the top of the FIFO and is ready to be read.
A line status interrupt is activated (provided this interrupt is enabled) as long as the Read
pointer of the receiver FIFO points to the location of the FIFO that contains a byte with the
error. The interrupt is immediately cleared when the UARTx_LSR register is read. The
ERR bit of the UARTx_LSR register is active as long as an erroneous byte is present in the
receiver FIFO.
UART Modem Status Interrupt
The modem status interrupt is generated if there is any change in state of the modem status
inputs to the UART. This interrupt is cleared when the processor reads the UARTx_MSR
register.
UART Recommended Usage
The following is the standard sequence of events that occur in the eZ80L92 MCU using
the UART. A description of each follows.
1. Module reset.
2. Control transfers to configure UART operation.
3. Data transfers.
Module Reset. Upon reset, all internal registers are set to their default values. All com-
mand status registers are programmed with their default values, and the FIFOs are flushed.
Control Transfers. Based on the requirements of the application, the data transfer baud
rate is determined and the BRG is configured to generate a 16X clock frequency. Inter-
rupts are disabled and the communication control parameters are programmed in the
UARTx_LCTL register. The FIFO configuration is determined and the receive trigger lev-
els are set in the UARTx_FCTL register. The status registers, UARTx_LSR and
UARTx_MSR, are read, and ensure that none of the interrupt sources are active. The inter-
PS013014-0107 Universal Asynchronous Receiver/Transmitter
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rupts are enabled (except for the transmit interrupt) and the application is ready to use the
module for transmission/reception.
Data Transfers—Transmit. To transmit data, the application enables the transmit inter-
rupt. An interrupt is immediately expected in response. The application reads the
UARTx_IIR register and determines that the interrupt occurs due to an empty
UARTx_THR register. When the application determines this occurrence, the application
writes the transmit data bytes to the UARTx_THR register. The number of bytes that the
application writes depends on whether or not the FIFO is enabled. If the FIFO is enabled,
the application can write 16 bytes at a time. If not, the application can write one byte at a
time. As a result of the first Write, the interrupt is deactivated. The processor then waits
for the next interrupt. When the interrupt is raised by the UART module, the processor
repeats the same process until it exhausts all of the data for transmission.
To control and check the modem status, the application sets up the modem by writing to
the UARTx_MCTL register and reading the UARTx_MCTL register before starting the
process mentioned above.
Data Transfers—Receive. The receiver is always enabled, and it continually checks for
the start bit on the RxD input signal. When an interrupt is raised by the UART module, the
application reads the UARTx_IIR register and determines the cause for the interrupt. If the
cause is a line status interrupt, the application reads the UARTx_LSR register, reads the
data byte and then can discard the byte or take other appropriate action. If the interrupt is
caused by a receive-data-ready condition, the application alternately reads the
UARTx_LSR and UARTx_RBR registers and removes all of the received data bytes. It
reads the UARTx_LSR register before reading the UARTx_RBR register to determine that
there is no error in the received data.
To control and check modem status, the application sets up the modem by writing to the
UARTx_MCTL register and reading the UARTx_MSR register before starting the process
mentioned above.
Poll Mode Transfers. When interrupts are disabled, all data transfers are referred to as
poll mode transfers. In poll mode transfers, the application must continually poll the
UARTx_LSR register to transmit or receive data without enabling the interrupts. The
same holds true for the UARTx_MSR register. If the interrupts are not enabled, the data in
the UARTx_IIR register cannot be used to determine the cause of interrupt.
Baud Rate Generator
The Baud Rate Generator consists of a 16-bit downcounter, two registers, and associated
decoding logic. The initial value of the Baud Rate Generator is defined by the two BRG
Divisor Latch registers, {UARTx_BRG_H, UARTx_BRG_L}. At the rising edge of each
system clock, the BRG decrements until it reaches the value 0001h. On the next system
clock rising edge, the BRG reloads the initial value from {UARTx_BRG_H,
PS013014-0107 Universal Asynchronous Receiver/Transmitter
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UARTx_BRG_L) and outputs a pulse to indicate the end-of-count. Calculate the UART
data rate with the following equation:
Upon RESET, the 16-bit BRG divisor value resets to 0002h. A minimum BRG divisor
value of 0001h is also valid, and effectively bypasses the BRG. A software Write to either
the Low- or High-byte registers for the BRG Divisor Latch causes both the Low and High
bytes to load into the BRG counter, and causes the count to restart.
The divisor registers can only be accessed if bit 7 of the UART Line Control register
(UARTx_LCTL) is set to 1. After reset, this bit is reset to 0.
Recommended Usage of the Baud Rate Generator
The following is the normal sequence of operations that should occur after the eZ80L92
MCU is powered on to configure the Baud Rate Generator:
•
Set UARTx_LCTL[7] to 1 to enable access of the BRG divisor registers
•
Program the UARTx_BRG_L and UARTx_BRG_H registers
•
Clear UARTx_LCTL[7] to 0 to disable access of the BRG divisor registers
BRG Control Registers
UART Baud Rate Generator Registers—Low and High Bytes
The registers hold the Low and High bytes of the 16-bit divisor count loaded by the pro-
cessor for UART baud rate generation. The 16-bit clock divisor value is returned by
{UARTx_BRG_H, UARTx_BRG_L}, where x is either 0 or 1 to identify the two available
UART devices. On RESET, the 16-bit BRG divisor value resets to 0002h. The initial 16-
bit divisor value must be between 0002h and FFFFh as the values 0000h and 0001h are
invalid, and proper operation is not guaranteed. As a result, the minimum BRG clock divi-
sor ratio is 2.
A Write to either the Low- or High-byte registers for the BRG Divisor Latch causes both
bytes to be loaded into the BRG counter. The count is then restarted.
Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set to 1 to
access this register. See Table 52 and Table 53. For more information, see UART Line
Control Registers (UARTx_LCTL) on page 115.
UART Data Rate (bps) = System Clock Frequency
16 x (UART Baud Rate Generator Divisor)
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The UARTx_BRG_L registers share the same address space with the UARTx_RBR and
UARTx_THR registers. The UARTx_BRG_H registers share the same address space with
the UARTx_IER registers. Bit 7 of the associated UART Line Control register
(UARTx_LCTL) must be set to 1 to enable access to the BRG registers.
UART Registers
After a RESET, all UART registers are set to their default values. Any Writes to unused
registers or register bits are ignored and Reads return a value of 0. For compatibility with
future revisions, unused bits within a register must be written with a value of 0. Read/
Table 52. UART Baud Rate Generator Registers—Low Byte (UART0_BRG_L =
00C0h, UART1_BRG_L = 00D0h)
Bit 76543210
Reset 00000010
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R = Read only; R/W = Read/Write.
Bit
Position Value Description
[7:0]
UARTx_BRG_L
00h–FFh These bits represent the Low byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value
is returned by {UARTx_BRG_H, UARTx_BRG_L}.
Table 53. UART Baud Rate Generator Registers—High Byte (UART0_BRG_H =
00C1h, UART1_BRG_H = 00D1h)
Bit 76543210
Reset 00000000
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R = Read only; R/W = Read/Write.
Bit
Position Value Description
[7:0]
UARTx_BRG_H
00h–FFh These bits represent the High byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {UARTx_BRG_H, UARTx_BRG_L}.
Note:
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Write attributes, reset conditions, and bit descriptions of all of the UART registers are pro-
vided in this section.
UART Transmit Holding Registers
If less than eight bits are programmed for transmission, the lower bits of the byte written
to this register are selected for transmission. The transmit FIFO is mapped at this address.
You can write up to 16 bytes for transmission at one time to this address if the FIFO is
enabled by the application. If the FIFO is disabled, this buffer is only one byte deep.
These registers share the same address space as the UARTx_RBR and UARTx_BRG_L
registers. See Table 54.
UART Receive Buffer Registers
The bits in this register reflect the data received. If less than eight bits are programmed for
receive, the lower bits of the byte reflect the bits received whereas upper unused bits are 0.
The receive FIFO is mapped at this address. If the FIFO is disabled, this buffer is only one
byte deep.
These registers share the same address space as the UARTx_THR and UARTx_BRG_L
registers. See Table 55.
Table 54. UART Transmit Holding Registers (UART0_THR = 00C0h, UART1_THR =
00D0h)
Bit 76543210
Reset XXXXXXXX
CPU Access WWWWWWWW
Note: W = Write only.
Bit
Position Value Description
[7:0]
TxD
00h–FFh Transmit data byte.
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UART Interrupt Enable Registers
The UARTx_IER register is used to enable and disable the UART interrupts. The
UARTx_IER registers share the same I/O addresses as the UARTx_BRG_H registers. See
Table 56.
Table 55. UART Receive Buffer Registers (UART0_RBR = 00C0h, UART1_RBR =
00 D0h)
Bit 76543210
Reset XXXXXXXX
CPU Access RRRRRRRR
Note: R = Read only.
Bit
Position Value Description
[7:0]
RxD
00h–FFh Receive data byte.
Table 56. UART Interrupt Enable Registers (UART0_IER = 00C1h, UART1_IER =
00D1h)
Bit 76543210
Reset 00000000
CPU Access RRRRR/WR/WR/WR/W
Note: R = Read only.; R/W = Read/Write.
Bit
Position Value Description
[7:4] 0000 Reserved
3
MIIE
0 Modem interrupt on edge detect of status inputs is disabled.
1 Modem interrupt on edge detect of status inputs is enabled.
2
LSIE
0 Line status interrupt is disabled.
1 Line status interrupt is enabled for receive data errors:
incorrect parity bit received, framing error, overrun error, or
break detection.
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Product Specification
113
UART Interrupt Identification Registers
The Read-Only UARTx_IIR register allows you to check whether the FIFO is enabled and
the status of interrupts. These registers share the same I/O addresses as the UARTx_FCTL
registers. See Table 57 and Table 58.
1
TIE
0 Transmit interrupt is disabled.
1 Transmit interrupt is enabled. Interrupt is generated when the
transmit FIFO/buffer is empty indicating no more bytes
available for transmission.
0
RIE
0 Receive interrupt is disabled.
1 Receive interrupt and receiver time-out interrupt are enabled.
Interrupt is generated if the FIFO/buffer contains data ready to
be read or if the receiver times out.
Table 57. UART Interrupt Identification Registers (UART0_IIR = 00C2h, UART1_IIR
= 00D2h)
Bit 76543210
Reset 00000001
CPU Access RRRRRRRR
Note: R = Read only.
Bit
Position Value Description
[7:6]
FSTS
00 FIFO is disabled.
11 FIFO is enabled.
[5:4] 00 Reserved
[3:1]
INSTS
000–110 Interrupt Status Code
The code indicated in these three bits is valid only if INTBIT
is 0. If two internal interrupt sources are active and their
respective enable bits are High, only the higher priority
interrupt is seen by the application. The lower-priority
interrupt code is indicated only after the higher-priority
interrupt is serviced. Table 58 lists the interrupt status codes.
0
INTBIT
0 There is an active interrupt source within the UART.
1 There is not an active interrupt source within the UART.
Bit
Position Value Description
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Product Specification
114
UART FIFO Control Registers
This register is used to monitor trigger levels, clear FIFO pointers, and enable or disable
the FIFO. The UARTx_FCTL registers share the same I/O addresses as the UARTx_IIR
registers. See Table 59.
Table 58. UART Interrupt Status Codes
INSTS Value Priority Interrupt Type
011 Highest Receiver Line Status
010 Second Receive Data Ready or Trigger Level
110 Third Character Time-out
001 Fourth Transmit Buffer Empty
000 Lowest Modem Status
Table 59. UART FIFO Control Registers (UART0_FCTL = 00C2h, UART1_FCTL =
00D2h)
Bit 76543210
Reset 00000000
CPU Access WWWWWWWW
Note: W = Write only.
Bit
Position Value Description
[7:6]
TRIG
00 Receive FIFO trigger level set to 1. Receive data interrupt is
generated when there is 1 byte in the FIFO. Valid only if FIFO
is enabled.
01 Receive FIFO trigger level set to 4. Receive data interrupt is
generated when there are 4 bytes in the FIFO. Valid only if
FIFO is enabled.
10 Receive FIFO trigger level set to 8. Receive data interrupt is
generated when there are 8 bytes in the FIFO. Valid only if
FIFO is enabled.
11 Receive FIFO trigger level set to 14. Receive data interrupt is
generated when there are 14 bytes in the FIFO. Valid only if
FIFO is enabled.
[5:3] 000 Reserved.
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Product Specification
115
UART Line Control Registers
This register is used to control the communication control parameters. See Table 60 and
Table 61.
2
CLRTXF
0No effect.
1 Clear the transmit FIFO and reset the transmit FIFO pointer.
Valid only if the FIFO is enabled.
1
CLRRXF
0No effect.
1 Clear the receive FIFO, clear the receive error FIFO, and reset
the receive FIFO pointer. Valid only if the FIFO is enabled.
0
FIFOEN
0 Transmit and receive FIFOs are disabled. Transmit and receive
buffers are only 1 byte deep.
1 Transmit and receive FIFOs are enabled.
Table 60. UART Line Control Registers (UART0_LCTL = 00C3h, UART1_LCTL =
00D3h)
Bit 76543210
Reset 00000000
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.
Bit
Position Value Description
7
DLAB
0 Access to the UART registers at I/O addresses UARTx_RBR,
UARTx_THR, and UARTx_IER is enabled.
1 Access to the Baud Rate Generator registers at I/O addresses
UARTx_BRG_L and UARTx_BRG_H is enabled.
Bit
Position Value Description
PS013014-0107 Universal Asynchronous Receiver/Transmitter
eZ80L92 MCU
Product Specification
116
6
SB
0 Do not send a BREAK signal.
1 Send Break
UART sends continuous zeroes on the transmit output from the
next bit boundary. The transmit data in the transmit shift
register is ignored. After forcing this bit High, the TxD output is
0 only after the bit boundary is reached. Just before forcing
TxD to 0, the transmit FIFO is cleared. Any new data written to
the transmit FIFO during a break should be written only after
the THRE bit of UARTx_LSR register goes High. This new data
is transmitted after the UART recovers from the break. After the
break is removed, the UART recovers from the break for the
next BRG edge.
5
FPE
0 Do not force a parity error.
1 Force a parity error. When this bit and the party enable bit
(PEN) are both 1, an incorrect parity bit is transmitted with the
data byte.
4
EPS
0 Use odd parity for transmission. The total number of 1 bits in
the transmit data plus parity bit is odd.
1 Use even parity for transmission. The total number of 1 bits in
the transmit data plus parity bit is even.
3
PEN
0 Parity bit transmit and receive is disabled.
1 Parity bit transmit and receive is enabled. For transmit, a parity
bit is generated and transmitted with every data character. For
receive, the parity is checked for every incoming data
character.
[2:0]
CHAR
000–111 UART Character Parameter Selection
See Table 61 for a description of the values.
Bit
Position Value Description
PS013014-0107 Universal Asynchronous Receiver/Transmitter
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Product Specification
117
UART Modem Control Registers
This register is used to control and check the modem status. See Table 62.
Table 61. UART Character Parameter Definition
CHAR[2:0]
Character Length
(Tx/Rx Data Bits)
Stop Bits
(Tx Stop Bits)
000 5 1
001 6 1
010 7 1
011 8 1
100 5 2
101 6 2
110 7 2
111 8 2
Table 62. UART Modem Control Registers (UART0_MCTL = 00C4h, UART1_MCTL =
00D4h)
Bit 76543210
Reset 00000000
CPU Access R R R R/W R/W R/W R/W R/W
Note: R = Read only.; R/W = Read/Write.
Bit
Position Value Description
[7:5] 000b Reserved.
4
LOOP
0 LOOP BACK mode is not enabled.
1 LOOP BACK mode is enabled.
The UART operates in internal LOOP BACK mode. The
transmit data output port is disconnected from the internal
transmit data output and set to 1. The receive data input port is
disconnected and internal receive data is connected to internal
transmit data. The modem status input ports are disconnected
and the four bits of the modem control register are connected
as modem status inputs. The two modem control output ports
(OUT1&2) are set to their inactive state
PS013014-0107 Universal Asynchronous Receiver/Transmitter
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Product Specification
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UART Line Status Registers
This register is used to show the status of UART interrupts and registers. See Table 63.
3
OUT2
0–1 No function in normal operation.
In LOOP BACK mode, this bit is connected to the DCD bit in
the UART Status Register.
2
OUT1
0–1 No function in normal operation.
In LOOP BACK mode, this bit is connected to the RI bit in the
UART Status Register.
1
RTS
0–1 Request to Send.
In normal operation, the RTS output port is the inverse of this
bit. In LOOP BACK mode, this bit is connected to the CTS bit in
the UART Status Register.
0
DTR
0–1 Data Terminal Ready.
In normal operation, the DTR output port is the inverse of this
bit. In LOOP BACK mode, this bit is connected to the DSR bit
in the UART Status Register.
Table 63. UART Line Status Registers (UART0_LSR = 00C5h, UART1_LSR = 00 D5h)
Bit 76543210
Reset 01100000
CPU Access RRRRRRRR
Note: R = Read only.
Bit
Position Value Description
7
ERR
0 Always 0 when operating with the FIFO disabled. With the
FIFO enabled, this bit is reset when the UARTx_LSR register is
read and there are no more bytes with error status in the FIFO.
1 Error detected in the FIFO. There is at least 1 parity, framing or
break indication error in the FIFO.
Bit
Position Value Description
PS013014-0107 Universal Asynchronous Receiver/Transmitter
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Product Specification
119
6
TEMT
0 Transmit holding register/FIFO is not empty or transmit shift
register is not empty or transmitter is not idle.
1 Transmit holding register/FIFO and transmit shift register are
empty; and the transmitter is idle. This bit cannot be set to 1
during the BREAK condition. This bit only becomes 1 after the
BREAK command is removed.
5
THRE
0 Transmit holding register/FIFO is not empty.
1 Transmit holding register/FIFO is empty. This bit cannot be set
to 1 during the BREAK condition. This bit only becomes 1 after
the BREAK command is removed.
4
BI
0 Receiver does not detect a BREAK condition. This bit is reset
to 0 when the UARTx_LSR register is read.
1 Receiver detects a BREAK condition on the receive input line.
This bit is 1 if the duration of BREAK condition on the receive
data is longer than one character transmission time, the time
depends on the programming of the
UARTx_LSR
register. In
case of FIFO only one null character is loaded into the receiver
FIFO with the framing error. The framing error is revealed to
the eZ80 whenever that particular data is read from the
receiver FIFO.
3
FE
0 No framing error detected for character at the top of the FIFO.
This bit is reset to 0 when the UARTx_LSR register is read.
1 Framing error detected for the character at the top of the FIFO.
This bit is set to 1 when the stop bit following the data/parity bit
is logic 0.
2
PE
0 The received character at the top of the FIFO does not contain
a parity error. This bit is reset to 0 when the UARTx_LSR
register is read.
1 The received character at the top of the FIFO contains a parity
error.
Bit
Position Value Description
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Product Specification
120
UART Modem Status Registers
This register is used to show the status of the UART signals. See Table 64.
1
OE
0 The received character at the top of the FIFO does not contain
an overrun error. This bit is reset to 0 when the UARTx_LSR
register is read.
1 Overrun error is detected. If the FIFO is not enabled, this
indicates that the data in the receive buffer register was not
read before the next character was transferred into the receiver
buffer register. If the FIFO is enabled, this indicates the FIFO
was already full when an additional character was received by
the receiver shift register. The character in the receiver shift
register is not put into the receiver FIFO.
0
DR
0 This bit is reset to 0 when the UARTx_RBR register is read or
all bytes are read from the receiver FIFO.
1 Data ready. If the FIFO is not enabled, this bit is set to 1 when
a complete incoming character is transferred into the receiver
buffer register from the receiver shift register. If the FIFO is
enabled, this bit is set to 1 when a character is received and
transferred to the receiver FIFO.
Table 64. UART Modem Status Registers (UART0_MSR = 00C6h, UART1_MSR =
00 D6h)
Bit 76543210
Reset XXXXXXXX
CPU Access RRRRRRRR
Note: R = Read only.
Bit
Position Value Description
PS013014-0107 Universal Asynchronous Receiver/Transmitter
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Product Specification
121
Bit
Position Value Description
7
DCD
0–1 Data Carrier Detect
In NORMAL mode, this bit reflects the inverted state of the
DCDx input pin. In LOOP BACK mode, this bit reflects the
value of the UARTx_MCTL[3] = out2.
6
RI
0–1 Ring Indicator
In NORMAL mode, this bit reflects the inverted state of the RIx
input pin. In LOOP BACK mode, this bit reflects the value of the
UARTx_MCTL[2] = out1.
5
DSR
0–1 Data Set Ready
In NORMAL mode, this bit reflects the inverted state of the
DSRx input pin. In LOOP BACK mode, this bit reflects the
value of the UARTx_MCTL[0] = DTR.
4
CTS
0–1 Clear to Send
In NORMAL mode, this bit reflects the inverted state of the
CTSx input pin. In LOOP BACK mode, this bit reflects the value
of the UARTx_MCTL[1] = RTS.
3
DDCD
0–1 Delta Status Change of DCD
This bit is set to 1 whenever the DCDx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
2
TERI
0–1 Trailing Edge Change on RI.
This bit is set to 1 whenever a falling edge is detected on the
RIx pin. This bit is reset to 0 when the UARTx_MSR register is
read.
1
DDSR
0–1 Delta Status Change of DSR
This bit is set to 1 whenever the DSRx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
0
DCTS
0–1 Delta Status Change of CTS
This bit is set to 1 whenever the CTSx pin changes state.
This bit is reset to 0 when the UARTx_MSR register is read.
PS013014-0107 Universal Asynchronous Receiver/Transmitter
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Product Specification
122
UART Scratch Pad Registers
The UARTx_SPR register can be used by the system as a general-purpose Read/Write
register. See Table 65.
Table 65. UART Scratch Pad Registers (UART0_SPR = 00C7h, UART1_SPR =
00D7h)
Bit 76543210
Reset 00000000
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.
Bit
Position Value Description
[7:0]
SPR
00h–FFh UART scratch pad register is available for use as a
general-purpose Read/Write register.
PS013014-0107 Infrared Encoder/Decoder
eZ80L92 MCU
Product Specification
123
Infrared Encoder/Decoder
The eZ80L92 MCU contains a UART to infrared encoder/decoder (endec). The infrared
encoder/decoder is integrated with the on-chip UART0 to allow easy communication
between the eZ80 CPU and IrDA Physical Layer Specification Version 1.3 compliant
infrared transceivers as illustrated in Figure 24. Infrared communication provides secure,
reliable, high-speed, low-cost, and point-to-point communication between PCs, PDAs,
mobile telephones, printers, and other infrared enabled devices.
Functional Description
When the infrared encoder/decoder is enabled, the transmit data from the on-chip UART
is encoded as digital signals in accordance with the IrDA standard and output to the
infrared transceiver. Likewise, data received from the infrared transceiver is decoded by
the infrared encoder/decoder and passed to the UART. Communication is half-duplex
meaning that simultaneous data transmission and reception is not allowed.
The baud rate is set by the UART Baud Rate Generator and supports IrDA standard baud
rates from 9600 bps to 115.2 Kbps. Higher baud rates are possible, but do not meet IrDA
specifications. The UART must be enabled to use the infrared encoder/decoder.
Figure 24. Infrared System Block Diagram
eZ80L92
To eZ80 CPU
System
Clock
UART0
RxD
TxD
RxD
TxD
IR_RxD
IR_TxD
Baud Rate
Clock
Infrared
Encoder/Decoder
Interrupt
Signal
I/O
Address
Data I/O
Address
Data
Infrared
Transceiver
PS013014-0107 Infrared Encoder/Decoder
eZ80L92 MCU
Product Specification
124
For more information on the UART and its Baud Rate Generator, see Universal Asynchro-
nous Receiver/Transmitter on page 104.
Transmit
The data to be transmitted via the IR transceiver is first sent to UART0. The UART
transmit signal (TxD) and Baud Rate Clock are used by the infrared encoder/decoder to
generate the modulation signal (IR_TXD) that drives the infrared transceiver. Each UART
bit is 16-clocks wide. If the data to be transmitted is a logical 1 (High), the IR_TXD signal
remains Low (0) for the full 16-clock period. If the data to be transmitted is a logical 0, a
3-clock High (1) pulse is output following a 7-clock Low (0) period. Following the
3-clock High pulse, a 6-clock Low pulse completes the full 16-clock data period. Data
transmission is illustrated in Figure 25. During data transmission, the IR receive function
should be disabled by clearing the IR_RXEN bit in the IR_CTL reg to 0. This prevents
transmitter to receiver cross-talk.
Receive
Data received from the IR transceiver via the IR_RXD signal is decoded by the infrared
encoder/decoder and passed to the UART. The IR_RXEN bit in the IR_CTL register must
be set to enable the receiver decoder. The SIR data format uses half duplex communica-
tion therefore the UART should not be allowed to transmit while the receiver decoder is
enabled. The UART Baud Rate Clock is used by the infrared encoder/decoder to generate
the demodulated signal (RxD) that drives the UART. Each UART bit is 16-clocks wide. If
the data to be received is a logical 1 (High), the IR_RXD signal remains High (1) for the
full 16-clock period. If the data to be received is a logical 0, a 3-clock Low (0) pulse is
Figure 25. Infrared Data Transmission
16-clock
period
3-clock
pulse
7-clock
delay
Baud Rate
Clock
UART_TxD Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
IR_TxD
PS013014-0107 Infrared Encoder/Decoder
eZ80L92 MCU
Product Specification
125
output following a 7-clock High (1) period. Following the 3-clock Low pulse, is a 6-clock
High pulse to complete the full 16-clock data period. Data transmission is illustrated in
Figure 26.
Jitter
Due to the inherent sampling of the received IR_RXD signal by the BIt Rate Clock, some
jitter can be expected on the first bit in any sequence of data. However, all subsequent bits
in the received data stream are a fixed 16-clock periods wide.
Infrared Encoder/Decoder Signal Pins
The infrared encoder/decoder signal pins (IR_TXD and IR_RXD) are multiplexed with
General-Purpose I/O (GPIO) pins. These GPIO pins must be configured for alternate func-
tion operation for the infrared encoder/decoder to operate.
The remaining six UART0 pins (CTS0, DCD0, DSR0, DTR0, RTS0 and RI0) are not
required for use with the infrared encoder/decoder. The UART0 modem status interrupt
should be disabled to prevent unwanted interrupts from these pins. The GPIO pins corre-
sponding to these six unused UART0 pins can be used for inputs, outputs, or interrupt
sources. Recommended GPIO Port D control register settings are listed in Table 66. For
additional information on setting the GPIO Port modes, see General-Purpose Input/Output
on page 38
Figure 26. Infrared Data Reception
16-clock
period
16-clock
period 16-clock
period 16-clock
period
1.6 s
min. pulse
8-clock
delay
Baud Rate
Clock
IR_RxD
Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
UART_RxD
16-clock
period
PS013014-0107 Infrared Encoder/Decoder
eZ80L92 MCU
Product Specification
126
Loopback Testing
Both internal and external loopback testing can be accomplished with the endec on the
eZ80L92 MCU. Internal loopback testing is enabled by setting the LOOP_BACK bit to 1.
During internal loopback,
IR_TXD output signal is inverted and connected on-chip to the
IR_RXD input.
External loopback testing of the off-chip IrDA transceiver may be accom-
plished by transmitting data from the UART while the receiver is enabled (IR_RXEN set
to 1).
Infrared Encoder/Decoder Register
After a RESET, the infrared encoder/decoder register is set to its default value. Any Writes
to unused register bits are ignored and Reads return a value of 0. Unused bits within a reg-
ister must always be written with a value of 0. The IR_CTL register is described in
Table 67.
Table 66. GPIO Mode Selection while using the IrDA Encoder/Decoder
GPIO Port D Bits
Allowable GPIO
Port Mode Allowable Port Mode Functions
PD0 7 Alternate Function
PD1 7 Alternate Function
PD2–PD7 Any other than GPIO Mode 7
(1, 2, 3, 4, 5, 6, 8, or 9)
Output, Input, Open-Drain, Open-Source,
Level-sensitive Interrupt Input, or Edge-
Triggered Interrupt Input
Table 67. Infrared Encoder/Decoder Control Register (IR_CTL = 00BFh)
Bit 76543210
Reset 00000000
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R = Read only; R/W = Read/Write.
Bit
Position Value Description
[7:3] 000000 Reserved.
2
LOOP_BACK
0 Internal LOOP BACK mode is disabled.
1 Internal LOOP BACK mode is enabled.
IR_TXD output is inverted and connected to IR_RXD input for
internal loop back testing.
PS013014-0107 Infrared Encoder/Decoder
eZ80L92 MCU
Product Specification
127
1
IR_RXEN
0 IR_RXD data is ignored.
1 IR_RXD data is passed to UART0 RxD.
0
IR_EN
0 Infrared Encoder/Decoder is disabled.
1 Infrared Encoder/Decoder is enabled.
Bit
Position Value Description
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eZ80L92 MCU
Product Specification
128
Serial Peripheral Interface
The Serial Peripheral Interface (SPI) is a synchronous interface allowing several SPI-type
devices to be interconnected. The SPI is a full-duplex, synchronous, and character-
oriented communication channel that employs a four-wire interface. The SPI block con-
sists of a transmitter, receiver, baud rate generator, and control unit. During an SPI trans-
fer, data is sent and received simultaneously by both the master and the slave SPI devices.
In a serial peripheral interface, separate signals are required for data and clock. The SPI
may be configured as either a master or a slave. The connection of two SPI devices (one
master and one slave) and the direction of data transfer is demonstrated in Figure 27 and
Figure 28.
Figure 27. SPI Master Device
Figure 28. SPI Slave Device
MASTER
MISO DATAOUT
CLKOUT
SS
Bit 0
8-Bit Shift Register
Baud Rate
Generator
Bit 7
SCK
DATAIN
SLAVE
MOSI MISO
SCK
DATAOUT
SS
Bit 0
8-Bit Shift Register
Bit 7
DATAIN
ENABLE
CLKIN
PS013014-0107 Serial Peripheral Interface
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Product Specification
129
SPI Signals
The four basic SPI signals are:
•
MISO (Master-In/Slave-Out)
•
MOSI (Master-Out/Slave-In)
•
SCK (SPI Serial Clock)
•
SS (Slave Select)
The following section describes the SPI signals. Each signal is described in both
MASTER and SLAVE modes.
Master-In, Slave-Out
The Master-In/Slave-Out (MISO) pin is configured as an input in a master device and as
an output in a slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. The MISO pin of a slave device is placed in a high-impedance
state if the slave is not selected. When the SPI is not enabled, this signal is in a high-
impedance state.
Master-Out, Slave-In
The Master-Out/Slave-In (MOSI) pin is configured as an output in a master device and as
an input in a slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance
state.
Slave Select
The active Low Slave Select (SS) input signal is used to select the SPI as a slave device. It
must be Low prior to all data communication and must stay Low for the duration of the
data transfer.
The SS input signal must be High for the SPI to operate as a master device. If the SS signal
goes Low, a Mode Fault error flag (MODF) is set in the SPI_SR register. See the SPI Sta-
tus Register (SPI_SR) on page 136 for more information.
When the clock phase (CPHA) is set to 0, the shift clock is the logical OR of SS with
SCK. In this clock phase mode, SS must go High between successive characters in an SPI
message. When CPHA is set to 1, SS can remain Low for several SPI characters. In cases
where there is only one SPI slave, its SS line could be tied Low as long as CPHA is set to
1. See the SPI Control Register (SPI_CTL) on page 135 for more information about
CPHA.
PS013014-0107 Serial Peripheral Interface
eZ80L92 MCU
Product Specification
130
Serial Clock
The Serial Clock (SCK) is used to synchronize data movement both in and out of the
device through its MOSI and MISO pins. The master and slave are capable of exchanging
a data byte during a sequence of eight clock cycles. As SCK is generated by the master,
the SCK pin becomes an input on a slave device. The SPI contains an internal divide-by-
two clock divider. In MASTER mode, the SPI serial clock is one-half the frequency of the
clock signal created by the SPI’s Baud Rate Generator.
As demonstrated in Figure 29 and Table 68, four possible timing relations may be chosen
by using control bits CPOL and CPHA in the SPI Control register. See the SPI Control
Register (SPI_CTL) on page 135. Both the master and slave must operate with the identi-
cal timing, Clock Polarity (CPOL), and Clock Polarity (CPHA). The master device always
places data on the MOSI line a half-cycle before the clock edge (SCK signal), in order for
the slave device to latch the data.
PS013014-0107 Serial Peripheral Interface
eZ80L92 MCU
Product Specification
131
SPI Functional Description
When a master transmits to a slave device via the MOSI signal, the slave device responds
by sending data to the master via the master's MISO signal. The resulting implication is a
full-duplex transmission, with both data out and data in synchronized with the same clock
signal. Thus the byte transmitted is replaced by the byte received and eliminates the
requirement for separate transmit-empty and receive-full status bits. A single status bit,
SPIF, is used to signify that the I/O operation is completed, see SPI Status Register
(SPI_SR) on page 136.
Figure 29. SPI Timing
Table 68. SPI Clock Phase and Clock Polarity Operation
CPHA CPOL
SCK
Transmit
Edge
SCK
Receive
Edge
SCK
Idle
State
SS High
Between
Characters?
0 0 Falling Rising Low Yes
0 1 Rising Falling High Yes
1 0 Rising Falling Low No
1 1 Falling Rising High No
SCK (CPOL bit = 0)
SCK (CPOL bit = 1)
Sample Input
(CPHA bit = 0) Data Out
Sample Input
(CPHA bit = 1) Data Out
Enable (To Slave)
Number of Cycles on the SCK Signal
1234 5678
MSB 6 5 4 3 2 1 LSB
MSB 6 5 4 3 2 1 LSB
PS013014-0107 Serial Peripheral Interface
eZ80L92 MCU
Product Specification
132
The SPI is double-buffered on Read, but not on Write. If a Write is performed during data
transfer, the transfer occurs uninterrupted, and the Write is unsuccessful. This condition
causes the WRITE COLLISION (WCOL) status bit in the SPI_SR register to be set. After
a data byte is shifted, the SPIF flag of the SPI_SR register is set.
In SPI MASTER mode, the SCK pin is an output. It idles High or Low, depending on the
CPOL bit in the SPI_CTL register, until data is written to the shift register. Data transfer is
initiated by writing to the transmit shift register, SPI_TSR. Eight clocks are then generated
to shift the eight bits of transmit data out the MOSI pin while shifting in eight bits of data
on the MISO pin. After transfer, the SCK signal idles.
In SPI SLAVE mode, the start logic receives a logic Low from the SS pin and a clock
input at the SCK pin, and the slave is synchronized to the master. Data from the master is
received serially from the slave MOSI signal and loads the 8-bit shift register. After the 8-
bit shift register is loaded, its data is parallel transferred to the Read buffer. During a Write
cycle data is written into the shift register, then the slave waits for the SPI master to initiate
a data transfer, supply a clock signal, and shift the data out on the slave's MISO signal.
If the CPHA bit in the SPI_CTL register is 0, a transfer begins when SS pin signal goes
Low and the transfer ends when SS goes High after eight clock cycles on SCK. When the
CPHA bit is set to 1, a transfer begins the first time SCK becomes active while SS is Low
and the transfer ends when the SPIF flag gets set.
SPI Flags
Mode Fault
The Mode Fault flag (MODF) indicates that there may be a multimaster conflict for sys-
tem control. The MODF bit is normally cleared to 0 and is only set to 1 when the master
device’s SS pin is pulled Low. When a mode fault is detected, the following occurs:
1. The MODF flag (SPI_SR[4]) is set to 1.
2. The SPI device is disabled by clearing the SPI_EN bit (SPI_CTL[5]) to 0.
3. The MASTER_EN bit (SPI_CTL[4]) is cleared to 0, forcing the device into SLAVE
mode.
4. If the SPI interrupt is enabled by setting IRQ_EN (SPI_CTL[7]) High, an SPI inter-
rupt is generated.
Clearing the Mode Fault flag is performed by reading the SPI Status register. The other
SPI control bits (SPI_EN and MASTER_EN) must be restored to their original states by
user software after the Mode Fault flag is cleared.
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Write Collision
The WRITE COLLISION flag, WCOL (SPI_SR[5]), is set to 1 when an attempt is made
to write to the SPI Transmit Shift register (SPI_TSR) while data transfer occurs. Clearing
the WCOL bit is performed by reading SPI_SR with the WCOL bit set.
SPI Baud Rate Generator
The SPI’s Baud Rate Generator creates a lower frequency clock from the high-frequency
system clock. The Baud Rate Generator output is used as the clock source by the SPI.
Baud Rate Generator Functional Description
The SPI’s Baud Rate Generator consists of a 16-bit downcounter, two 8-bit registers, and
associated decoding logic. The Baud Rate Generator’s initial value is defined by the two
BRG Divisor Latch registers, {SPI_BRG_H, SPI_BRG_L}. At the rising edge of each
system clock, the BRG decrements until it reaches the value 0001h. On the next system
clock rising edge, the BRG reloads the initial value from {SPI_BRG_H, SPI_BRG_L) and
outputs a pulse to indicate the end-of-count. Calculate the SPI Data Rate with the follow-
ing equation:
Upon RESET, the 16-bit BRG divisor value resets to 0002h. When the SPI is operating as
a Master, the BRG divisor value must be set to a value of 0003h or greater. When the SPI
is operating as a Slave, the BRG divisor value must be set to a value of 0004h or greater.
A software Write to either the Low- or High-byte registers for the BRG Divisor Latch
causes both the Low and High bytes to load into the BRG counter, and causes the count to
restart.
Data Transfer Procedure with SPI Configured as the Master
Follow the steps below for data transfer with SPI configured as the master:
1. Load the SPI Baud Rate Generator Registers, SPI_BRG_H and SPI_BRG_L.
2. External device must de-assert the SS pin if currently asserted.
3. Load the SPI Control Register, SPI_CTL.
4. Assert the ENABLE pin of the slave device using a GPIO pin.
5. Load the SPI Transmit Shift Register, SPI_TSR.
SPI Data Rate (bps) =
System Clock Frequency
2 X SPI Baud Rate Generator
Divisor
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6. When the SPI data transfer is complete, de-assert the ENABLE pin of the slave
device.
Data Transfer Procedure with SPI Configured as a Slave
Follow the steps below for data transfer with SPI configured as the slave:
1. Load the SPI Baud Rate Generator Registers, SPI_BRG_H and SPI_BRG_L.
2. Load the SPI Transmit Shift Register, SPI_TSR. This load cannot occur while the SPI
slave is currently receiving data.
3. Wait for the external SPI Master device to initiate the data transfer by asserting SS.
SPI Registers
There are six registers in the Serial Peripheral Interface which provide control, status, and
data storage functions. The SPI registers are described in the following section.
SPI Baud Rate Generator Registers—Low Byte and High Byte
These registers hold the Low and High bytes of the 16-bit divisor count loaded by the
processor for baud rate generation. The 16-bit clock divisor value is returned by
{SPI_BRG_H, SPI_BRG_L}. Upon RESET, the 16-bit BRG divisor value resets to
0002h. When configured as a Master, the 16-bit divisor value must be between 0003h
and FFFFh, inclusive. When configured as a Slave, the 16-bit divisor value must be
between 0004h and FFFFh, inclusive.
A Write to either the Low or High byte registers for the BRG Divisor Latch causes both
bytes to be loaded into the BRG counter and the count restarted. See Table 69 and
Table 70.
Table 69. SPI Baud Rate Generator Register—Low Byte (SPI_BRG_L = 00B8h)
Bit 76543210
Reset 00000010
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.
Bit
Position Value Description
[7:0]
SPI_BRG_L
00h–FFh These bits represent the Low byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {SPI_BRG_H, SPI_BRG_L}.
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SPI Control Register
This register is used to control and setup the serial peripheral interface. The SPI must be
disabled prior to making any changes to CPHA or CPOL. See Table 71.
Table 70. SPI Baud Rate Generator Register—High Byte (SPI_BRG_H = 00B9h)
Bit 76543210
Reset 00000000
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.
Bit
Position Value Description
[7:0]
SPI_BRG_H
00h–FFh These bits represent the High byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {SPI_BRG_H, SPI_BRG_L}.
Table 71. SPI Control Register (SPI_CTL = 00BAh)
Bit 76543210
Reset 00000100
CPU Access R/W R R/W R/W R/W R/W R R
Note: R = Read Only; R/W = Read/Write.
Bit
Position Value Description
7
IRQ_EN
0 SPI system interrupt is disabled.
1 SPI system interrupt is enabled.
6 0 Reserved.
5
SPI_EN
0 SPI is disabled.
1 SPI is enabled.
4
MASTER_EN
0 When enabled, the SPI operates as a slave.
1 When enabled, the SPI operates as a master.
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SPI Status Register
The SPI Status Read-Only register returns the status of data transmitted using the serial
peripheral interface. Reading the SPI_SR register clears Bits 7, 6, and 4 to a logical 0.
See Table 72.
3
CPOL
0 Master SCK pin idles in a Low (0) state.
1 Master SCK pin idles in a High (1) state.
2
CPHA
0 SS must go High after transfer of every byte of data.
1 SS can remain Low to transfer any number of data bytes.
[1:0] 00 Reserved.
Table 72. SPI Status Register (SPI_SR = 00BBh)
Bit 76543210
Reset 00000000
CPU Access RRRRRRRR
Note: R = Read Only
Bit
Position Value Description
7
SPIF
0 SPI data transfer is not finished.
1 SPI data transfer is finished. If enabled, an interrupt is
generated. This bit flag is cleared to 0 by a Read of the
SPI_SR register.
6
WCOL
0 An SPI write collision is not detected.
1 An SPI write collision is detected. This bit flag is cleared to
0 by a Read of the SPI_SR registers.
50Reserved.
4
MODF
0 A mode fault (multimaster conflict) is not detected.
1 A mode fault (multimaster conflict) is detected. This bit flag
is cleared to 0 by a Read of the SPI_SR register.
[3:0] 0000 Reserved.
Bit
Position Value Description
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SPI Transmit Shift Register
The SPI Transmit Shift register (SPI_TSR) is used by the SPI master to transmit data onto
the SPI serial bus to the slave device. A Write to the SPI_TSR register places data directly
into the shift register for transmission. A Write to this register within an SPI device
configured as a master initiates transmission of the byte of the data loaded into the register.
At the completion of transmitting a byte of data, the SPIF status bit (SPI_SR[7]) is set to 1
in both the master and slave devices.
The SPI Transmit Shift Write-Only register shares the same address space as the SPI
Receive Buffer Read-Only register. See Table 73.
SPI Receive Buffer Register
The SPI Receive Buffer register (SPI_RBR) is used by the SPI slave to receive data from
the serial bus. The SPIF bit must be cleared prior to a second transfer of data from the shift
register or an overrun condition exists. In cases of overrun, the byte that caused the over-
run is lost.
The SPI Receive Buffer Read-Only register shares the same address space as the SPI
Transmit Shift Write-Only register. See Table 74.
Table 73. SPI Transmit Shift Register (SPI_TSR = 00BCh)
Bit 76543210
Reset XXXXXXXX
CPU Access WWWWWWWW
Note: W= Write Only.
Bit
Position Value Description
[7:0]
TX_DATA
00h–FFh SPI transmit data.
Table 74. SPI Receive Buffer Register (SPI_RBR = 00BCh)
Bit 76543210
Reset XXXXXXXX
CPU Access RRRRRRRR
Note: R = Read Only
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Bit
Position Value Description
[7:0]
RX_DATA
00h–FFh SPI received data.
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I2C Serial I/O Interface
General Characteristics
The I2C serial I/O bus is a two-wire communication interface that can operate in four
modes:
•
MASTER TRANSMIT
•
MASTER RECEIVE
•
SLAVE TRANSMIT
•
SLAVE RECEIVE
The I2C interface consists of the Serial Clock (SCL) and the Serial Data (SDA). Both SDA
and SCL are bidirectional lines, connected to a positive supply voltage via an external
pull-up resistor. When the bus is free, both lines are High. The output stages of devices
connected to the bus must be configured as open-drain outputs. Data on the I2C bus can be
transferred at a rate of up to 100 Kbps in STANDARD mode, or up to 400 Kbps in FAST
mode. One clock pulse is generated for each data bit transferred.
Clocking Overview
If another device on the I2C bus drives the clock line when the I2C is in MASTER mode,
the I2C synchronizes its clock to the I2C bus clock. The High period of the clock is
determined by the device that generates the shortest High clock period. The Low period of
the clock is determined by the device that generates the longest Low clock period.
A slave may stretch the Low period of the clock to slow down the bus master. The Low
period may also be stretched for handshaking purposes. This can be done after each bit
transfer or each byte transfer. The I2C stretches the clock after each byte transfer until the
IFLG bit in the I2C_CTL register is cleared.
Bus Arbitration Overview
In MASTER mode, the I2C checks that each transmitted logic 1 appears on the I2C bus as
a logic 1. If another device on the bus overrules and pulls the SDA signal Low, arbitration
is lost. If arbitration is lost during the transmission of a data byte or a Not-Acknowledge
bit, the I2C returns to the idle state. If arbitration is lost during the transmission of an
address, the I2C switches to SLAVE mode so that it can recognize its own slave address or
the general call address.
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Data Validity
The data on the SDA line must be stable during the High period of the clock. The High or
Low state of the data line can only change when the clock signal on the SCL line is Low as
illustrated in Figure 30.
START and STOP Conditions
Within the I2C bus protocol, unique situations arise which are defined as START and
STOP conditions. See Figure 31. A High-to-Low transition on the SDA line while SCL is
High indicates a START condition. A Low-to-High transition on the SDA line while SCL
is High defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered to
be busy after the START condition. The bus is considered to be free a defined time after
the STOP condition.
Figure 30. I2C Clock and Data Relationship
Figure 31. START and STOP Conditions In I2C Protocol
A
Signal
L
Signal
Data Line
Stable
Data Valid
Change of
Data Allowed
SDA Signal
START Condition STOP Condition
SCL Signal
SP
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Transferring Data
Byte Format
Every character transferred on the SDA line must be a single 8-bit byte. The number of
bytes that can be transmitted per transfer is unrestricted. Each byte must be followed by an
Acknowledge (ACK)1. Data is transferred with the most significant bit (msb) first. See
Figure 32. A receiver can hold the SCL line Low to force the transmitter into a wait state.
Data transfer then continues when the receiver is ready for another byte of data and
releases SCL.
Acknowledge
Data transfer with an ACK function is obligatory. The ACK-related clock pulse is gener-
ated by the master. The transmitter releases the SDA line (High) during the ACK clock
pulse. The receiver must pull down the SDA line during the ACK clock pulse so that it
remains stable Low during the High period of this clock pulse. See Figure 33.
A receiver that is addressed is obliged to generate an ACK after each byte is received.
When a slave-receiver doesn't acknowledge the slave address (for example, unable to
receive because it's performing some real-time function), the data line must be left High
by the slave. The master then generates a STOP condition to abort the transfer.
If a slave-receiver acknowledges the slave address, but cannot receive any more data
bytes, the master must abort the transfer. The abort is indicated by the slave generating the
Not Acknowledge (NACK) on the first byte to follow. The slave leaves the data line High
and the master generates the STOP condition.
If a master-receiver is involved in a transfer, it must signal the end of data to the slave-
transmitter by not generating an ACK on the final byte that is clocked out of the slave. The
1. ACK is defined as a general Acknowledge bit. By contrast, the I2C Acknowledge bit is repre-
sented as AAK, bit 2 of the I2C Control Register, which identifies which ACK signal to transmit.
See Table 84 on page 154.
Figure 32. I2C Frame Structure
SDA Signal
SCL Signal
START Condition
Clock Line Held Low By Receiver
STOP Condition
S P
Acknowledge from
Receiver
MSB
ACK
91912 8
Acknowledge from
Receiver
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slave-transmitter must release the data line to allow the master to generate a STOP or a
repeated START condition.
Clock Synchronization
All masters generate their own clocks on the SCL line to transfer messages on the I2C bus.
Data is only valid during the High period of each clock.
Clock synchronization is performed using the wired AND connection of the I2C interfaces
to the SCL line, meaning that a High-to-Low transition on the SCL line causes the relevant
devices to start counting from their Low period. When a device clock goes Low, it holds
the SCL line in that state until the clock High state is reached. See Figure 34. The Low-to-
High transition of this clock, however, may not change the state of the SCL line if another
clock is still within its Low period. The SCL line is held Low by the device with the long-
est Low period. Devices with shorter Low periods enter a High wait-state during this time.
When all devices concerned count off their Low period, the clock line is released and goes
High. There is no difference between the device clocks and the state of the SCL line, and
all of the devices start counting their High periods. The first device to complete its High
period again pulls the SCL line Low. In this way, a synchronized SCL clock is generated
with its Low period determined by the device with the longest clock Low period, and its
High period determined by the one with the shortest clock High period.
Figure 33. I2C Acknowledge
Data Output
by Transmitter
Data Output
by Receiver
SCL Signal
from Master
START Condition
S
MSB
1
Clock Pulse for Acknowledge
912 8
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Arbitration
A master may start a transfer only if the bus is free. Two or more masters may generate a
START condition within the minimum hold time of the START condition which results in
a defined START condition to the bus. Arbitration takes place on the SDA line, while the
SCL line is at the High level, in such a way that the master which transmits a High level,
while another master is transmitting a Low level switches off its data output stage because
the level on the bus doesn't correspond to its own level.
Arbitration can continue for many bits. Its first stage is comparison of the address bits. If
the masters are each trying to address the same device, arbitration continues with compar-
ison of the data. Because address and data information about the I2C bus is used for arbi-
tration, no information is lost during this process. A master which loses the arbitration can
generate clock pulses until the end of the byte in which it loses the arbitration.
If a master also incorporates a slave function and it loses arbitration during the addressing
stage, it's possible that the winning master is trying to address it. The losing master must
switch over immediately to its slave-receiver mode. Figure 34 illustrates the arbitration
procedure for two masters. Of course, more may be involved (depending on how many
masters are connected to the bus). The moment there is a difference between the internal
data level of the master generating DATA 1 and the actual level on the SDA line, its data
output is switched off, which means that a High output level is then connected to the bus.
As a result, the data transfer initiated by the winning master is not affected. Because con-
trol of the I2C bus is decided solely on the address and data sent by competing masters,
there is no central master, nor any order of priority on the bus.
Special attention must be paid if, during a serial transfer, the arbitration procedure is still
in progress at the moment when a repeated START condition or a STOP condition is trans-
mitted to the I2C bus. If it is possible for such a situation to occur, the masters involved
must send this repeated START condition or STOP condition at the same position in the
format frame. In other words, arbitration is not allowed between:
Figure 34. Clock Synchronization In I2C Protocol
CLK1 Signal
CLK2 Signal
SCL Signal
Counter
Reset
Wait
State
Start Counting
High Period
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•
A repeated START condition and a data bit.
•
A STOP condition and a data bit.
•
A repeated START condition and a STOP condition.
Clock Synchronization for Handshake
The Clock synchronizing mechanism can function as a handshake, enabling receivers to
cope with fast data transfers, on either a byte or bit level. The byte level allows a device to
receive a byte of data at a fast rate, but allows the device more time to store the received
byte or to prepare another byte for transmission. Slaves hold the SCL line Low after recep-
tion and acknowledge the byte, forcing the master into a wait state until the slave is ready
for the next byte transfer in a handshake procedure.
Operating Modes
Master Transmit
In MASTER TRANSMIT mode, the I2C transmits a number of bytes to a slave receiver.
Enter MASTER TRANSMIT mode by setting the STA bit in the I2C_CTL register to 1.
The I2C then tests the I2C bus and transmits a START condition when the bus is free.
When a START condition is transmitted, the IFLG bit is 1 and the status code in the
I2C_SR register is 08h. Before this interrupt is serviced, the I2C_DR register must be
loaded with either a 7-bit slave address or the first part of a 10-bit slave address, with the
lsb cleared to 0 to specify TRANSMIT mode. The IFLG bit should now be cleared to 0 to
prompt the transfer to continue.
After the 7-bit slave address (or the first part of a 10-bit address) plus the Write bit are
transmitted, the IFLG is set again. A number of status codes are possible in the I2C_SR
register. See Table 75.
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If 10-bit addressing is being used, then the status code is 18h or 20h after the first part of
a 10-bit address plus the Write bit are successfully transmitted.
After this interrupt is serviced and the second part of the 10-bit address is transmitted, the
I2C_SR register contains one of the codes in Table 76.
Table 75. I2C Master Transmit Status Codes
Code I2C State MCU Response Next I2C Action
18h Addr+W transmitted1,
ACK received
For a 7-bit address: write
byte to DATA, clear IFLG
Transmit data byte,
receive ACK
Or set STA, clear IFLG Transmit repeated
START
Or set STP, clear IFLG Transmit STOP
Or set STA & STP, clear
IFLG
Transmit STOP then
START
For a 10-bit address: write
extended address byte to
DATA, clear IFLG
Transmit extended
address byte
20h Addr+W transmitted,
ACK not received
Same as code 18h Same as code 18h
38h Arbitration lost Clear IFLG Return to idle
Or set STA, clear IFLG Transmit START when
bus is free
68h Arbitration lost,
+W received,
ACK transmitted
Clear IFLG, AAK = 02Receive data byte,
transmit NACK
Or clear IFLG, AAK = 1 Receive data byte,
transmit ACK
78h Arbitration lost,
General call addr
received, ACK
transmitted
Same as code 68h Same as code 68h
B0h Arbitration lost,
SLA+R received,
ACK transmitted
Write byte to DATA, clear
IFLG, clear AAK = 0
Transmit last byte,
receive ACK
Or write byte to DATA, clear
IFLG, set AAK = 1
Transmit data byte,
receive ACK
Notes:
1. W is defined as the Write bit; i.e., the lsb is cleared to 0.
2. AAK is defined as the I2C Acknowledge bit.
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If a repeated START condition is transmitted, the status code is 10h instead of 08h.
After each data byte is transmitted, the IFLG is 1 and one of the status codes listed in
Table 77 is in the I2C_SR
register.
Table 76. I2C 10-Bit Master Transmit Status Codes
Code I2C State MCU Response Next I2C Action
38h Arbitration lost Clear IFLG Return to idle
Or set STA, clear IFLG Transmit START when
bus free
68h Arbitration lost,
SLA+W received,
ACK transmitted
Clear IFLG, clear AAK = 0 Receive data byte,
transmit NACK
Or clear IFLG, set AAK = 1 Receive data byte,
transmit ACK
B0h Arbitration lost,
SLA+R received,
ACK transmitted
Write byte to DATA,
clear IFLG, clear AAK = 0
Transmit last byte,
receive ACK
Or write byte to DATA,
clear IFLG, set AAK = 1
Transmit data byte,
receive ACK
D0h Second Address byte
+ W transmitted,
ACK received
Write byte to DATA,
clear IFLG
Transmit data byte,
receive ACK
Or set STA, clear IFLG Transmit repeated
START
Or set STP, clear IFLG Transmit STOP
Or set STA & STP,
clear IFLG
Transmit STOP then
START
D8h Second Address byte
+ W transmitted,
ACK not received
Same as code D0h Same as code D0h
Table 77. I2C Master Transmit Status Codes For Data Bytes
Code I2C State MCU Response Next I2C Action
28h Data byte transmitted,
ACK received
Write byte to DATA,
clear IFLG
Transmit data byte,
receive ACK
Or set STA, clear IFLG Transmit repeated START
Or set STP, clear IFLG Transmit STOP
Or set STA & STP,
clear IFLG
Transmit START then STOP
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When all bytes are transmitted, the processor should write a 1 to the STP bit in the
I2C_CTL register. The I2C then transmits a STOP condition, clears the STP bit and returns
to the idle state.
Master Receive
In MASTER RECEIVE mode, the I2C receives a number of bytes from a slave transmit-
ter.
After the START condition is transmitted, the IFLG bit is 1 and the status code 08h is
loaded in the I2C_SR register. The I2C_DR register should be loaded with the slave
address (or the first part of a 10-bit slave address), with the lsb set to 1 to signify a Read.
The IFLG bit should be cleared to 0 as a prompt for the transfer to continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the Read bit are
transmitted, the IFLG bit is set and one of the status codes listed in Table 78 is in the
I2C_SR register.
30h Data byte transmitted,
ACK not received
Same as code 28h Same as code 28h
38h Arbitration lost Clear IFLG Return to idle
Or set STA, clear IFLG Transmit START when bus
free
Table 78. I2C Master Receive Status Codes
Code I2C State MCU Response Next I2C Action
40h Addr + R
transmitted, ACK
received
For a 7-bit address,
clear IFLG, AAK = 0
Receive data byte,
transmit NACK
Or clear IFLG, AAK = 1 Receive data byte,
transmit ACK
For a 10-bit address
Write extended address
byte to DATA, clear IFLG
Transmit extended
address byte
Note: R = Read bit; in essence, the lsb is set to 1.
Table 77. I2C Master Transmit Status Codes For Data Bytes (Continued)
Code I2C State MCU Response Next I2C Action
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If 10-bit addressing is being used, the slave is first addressed using the full 10-bit address
plus the Write bit. The master then issues a restart followed by the first part of the 10-bit
address again, but with the Read bit. The status code then becomes 40h or 48h. It is the
responsibility of the slave to remember that it had been selected prior to the restart.
If a repeated START condition is received, the status code is 10h instead of 08h.
After each data byte is received, the IFLG is set and one of the status codes listed in
Table 79 is in the I2C_SR register.
48h Addr + R
transmitted, ACK not
received
For a 7-bit address:
Set STA, clear IFLG
Transmit repeated
START
Or set STP, clear IFLG Transmit STOP
Or set STA & STP,
clear IFLG
Transmit STOP then
START
For a 10-bit address:
Write extended address byte
to DATA, clear IFLG
Transmit extended
address byte
38h Arbitration lost Clear IFLG Return to idle
Or set STA, clear IFLG Transmit START when
bus is free
68h Arbitration lost,
SLA+W received,
ACK transmitted
Clear IFLG, clear AAK = 0 Receive data byte,
transmit NACK
Or clear IFLG, set AAK = 1 Receive data byte,
transmit ACK
78h Arbitration lost,
General call addr
received, ACK
transmitted
Same as code 68h Same as code 68h
B0h Arbitration lost,
SLA+R received,
ACK transmitted
Write byte to DATA,
clear IFLG, clear AAK = 0
Transmit last byte,
receive ACK
Or write byte to DATA,
clear IFLG, set AAK = 1
Transmit data byte,
receive ACK
Table 78. I2C Master Receive Status Codes (Continued)
Code I2C State MCU Response Next I2C Action
Note: R = Read bit; in essence, the lsb is set to 1.
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When all bytes are received, a NACK should be sent, then the processor should write a 1
to the STP bit in the
I2C_CTL register. The I2C then transmits a STOP condition, clears
the STP bit and returns to the idle state.
Slave Transmit
In SLAVE TRANSMIT mode, a number of bytes are transmitted to a master receiver.
The I2C enters SLAVE TRANSMIT mode when it receives its own slave address and a
Read bit after a START condition. The I2C then transmits an acknowledge bit (if the AAK
bit is set to 1) and sets the IFLG bit in the I2C_CTL register and the I2C_SR register con-
tains the status code A8h.
When I2C contains a 10-bit slave address (signified by F0h–F7h in the I2C_SAR regis-
ter), it transmits an acknowledge after the first address byte is received after a restart. An
interrupt is generated, IFLG is set but the status does not change. No second address byte
is sent by the master. It is up to the slave to remember it had been selected prior to the
restart.
I2C goes from MASTER mode to SLAVE TRANSMIT mode when arbitration is lost dur-
ing the transmission of an address, and the slave address and Read bit are received. This
action is represented by the status code B0h in the
I2C_SR register.
The data byte to be transmitted is loaded into the
I2C_DR register and the IFLG bit
cleared. After the I2C transmits the byte and receives an acknowledge, the IFLG bit is set
and the I2C_SR
register contains B8h. When the final byte to be transmitted is loaded into
the I2C_DR register, the AAK bit is cleared when the IFLG is cleared. After the final byte
Table 79. I2C Master Receive Status Codes For Data Bytes
Code I2C State MCU Response Next I2C Action
50h Data byte received,
ACK transmitted
Read DATA, clear IFLG,
clear AAK = 0
Receive data byte,
transmit NACK
Or read DATA, clear IFLG,
set AAK = 1
Receive data byte,
transmit ACK
58h Data byte received,
NACK transmitted
Read DATA, set STA,
clear IFLG
Transmit repeated START
Or read DATA, set STP,
clear IFLG
Transmit STOP
Or read DATA, set
STA & STP, clear IFLG
Transmit STOP then
START
38h Arbitration lost in
NACK bit
Same as master transmit Same as master transmit
Note:
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is transmitted, the IFLG is set and the I2C_SR
register contains C8h and the I2C returns to
the idle state. The AAK bit must be set to 1 before reentering SLAVE mode.
If no acknowledge is received after transmitting a byte, the IFLG is set and the I2C_SR
register contains C0h. The I2C then returns to the idle state.
If a STOP condition is detected after an acknowledge bit, the I2C returns to the idle state.
Slave Receive
In SLAVE RECEIVE mode, a number of data bytes are received from a master transmit-
ter.
The I2C enters SLAVE RECEIVE mode when it receives its own slave address and a
Write bit (lsb = 0) after a START condition. The I2C transmits an acknowledge bit and sets
the IFLG bit in the
I2C_CTL register and the I2C_SR register contains the status code
60h. The I2C also enters SLAVE RECEIVE mode when it receives the general call
address 00h (if the GCE bit in the I2C_SAR register is set). The status code is then 70h.
When the I2C contains a 10-bit slave address (signified by F0h–F7h in the
I2C_SAR
reg-
ister), it transmits an acknowledge after the first address byte is received but no interrupt is
generated. IFLG is not set and the status does not change. The I2C generates an interrupt
only after the second address byte is received. The I2C sets the IFLG bit and loads the sta-
tus code as described above.
I2C goes from MASTER mode to SLAVE RECEIVE mode when arbitration is lost during
the transmission of an address, and the slave address and Write bit (or the general call
address if the CGE bit in the
I2C_SAR register is set to 1) are received. The status code in
the
I2C_SR register is 68h if the slave address is received or 78h if the general call
address is received. The IFLG bit must be cleared to 0 to allow data transfer to continue.
If the AAK bit in the I2C_CTL
register is set to 1 then an acknowledge bit (Low level on
SDA) is transmitted and the IFLG bit is set after each byte is received. The I2C_SR regis-
ter contains the status code 80h or 90h if SLAVE RECEIVE mode is entered with the
general call address. The received data byte can be read from the I2C_DR register and the
IFLG bit must be cleared to allow the transfer to continue. If a STOP condition or a
repeated START condition is detected after the acknowledge bit, the IFLG bit is set and
the I2C_SR register contains status code A0h.
If the AAK bit is cleared to 0 during a transfer, the I2C transmits a not-acknowledge bit
(High level on SDA) after the next byte is received, and set the IFLG bit. The
I2C_SR reg-
ister contains the status code 88h or 98h if SLAVE RECEIVE mode is entered with the
general call address. The I2C returns to the idle state when the IFLG bit is cleared to 0.
Note:
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I2C Registers
Addressing
The processor interface provides access to six 8-bit registers: four Read/Write registers,
one Read-Only register and two Write-Only registers, as indicated in Table 80.
Resetting the I2C Registers
Hardware reset. When the I2C is reset by a hardware reset of the eZ80L92, the
I2C_SAR,
I2C_XSAR, I2C_DR
and
I2C_CTL registers are cleared to 00h; while the I2C_SR regis-
ter is set to F8h.
Software Reset. Perform a software reset by writing any value to the I2C Software Reset
Register (I2C_SRR). A software reset sets the I2C back to idle and the STP, STA, and
IFLG bits of the
I2C_CTL register to 0.
I2C Slave Address Register
The I2C_SAR register provides the 7-bit address of the I2C when in SLAVE mode and
allows 10-bit addressing in conjunction with the I2C_XSAR register. I2C_SAR[7:1] =
sla[6:0] is the 7-bit address of the I2C when in 7-bit SLAVE mode. When the I2C receives
this address after a START condition, it enters SLAVE mode. I2C_SAR[7] corresponds to
the first bit received from the I2C bus.
When the register receives an address starting with F7h to F0h (I2C_SAR[7:3] = 11110b),
the I2C recognizes that a 10-bit slave addressing mode is being selected. The I2C sends an
ACK after receiving the I2C_SAR byte (the device does not generate an interrupt at this
point). After the next byte of the address (I2C_XSAR) is received, the I2C generates an
interrupt and goes into SLAVE mode. Then I2C_SAR[2:1] are used as the upper 2 bits for
the 10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}. See Table 81.
Table 80. I2C Register Descriptions
Register Description
I2C_SAR Slave address register
I2C_XSAR Extended slave address register
I2C_DR Data byte register
I2C_CTL Control register
I2C_SR Status register (Read-Only)
I2C_CCR Clock Control register (Write-Only)
I2C_SRR Software reset register (Write-Only)
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I2C Extended Slave Address Register
The I2C_XSAR register is used in conjunction with the I2C_SAR register to provide 10-
bit addressing of the I2C when in SLAVE mode. The I2C_SAR value forms the lower 8
bits of the 10-bit slave address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}.
When the register receives an address starting with F7h to F0h (I2C_SAR[7:3] = 11110b),
the I2C recognizes that a 10-bit slave addressing mode is being selected. The I2C sends an
ACK after receiving the I2C_XSAR byte (the device does not generate an interrupt at this
point). After the next byte of the address (I2C_XSAR) is received, the I2C generates an
interrupt and goes into SLAVE mode. Then I2C_SAR[2:1] are used as the upper 2 bits for
the 10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}. See Table 82.
Table 81. I2C Slave Address Register (I2C_SAR = 00C8h)
Bit 76543210
Reset 00000000
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.
Bit
Position Value Description
[7:1]
SLA
00h–7Fh 7-bit slave address or upper 2 bits,I2C_SAR[2:1],
of address when operating in 10-bit mode.
0
GCE
0I
2C not enabled to recognize the General Call Address.
1I
2C enabled to recognize the General Call Address.
Table 82. I2C Extended Slave Address Register (I2C_XSAR = 00C9h)
Bit 76543210
Reset 00000000
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.
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I2C Data Register
This register contains the data byte/slave address to be transmitted or the data byte just
received. In transmit mode, the most significant bit of the byte is transmitted first. In
receive mode, the first bit received is placed in the most significant bit of the register.
After each byte is transmitted, the I2C_DR register contains the byte that is present on the
bus in case a lost arbitration event occurs. See Table 83.
I2C Control Register
The I2C_CTL register is a control register that is used to control the interrupts and the
master slave relationships on the I2C bus.
When the Interrupt Enable bit (IEN) is set to 1, the interrupt line goes High when the IFLG
is set to 1. When IEN is cleared to 0, the interrupt line always remains Low.
When the Bus Enable bit (ENAB) is set to 0, the I2C bus inputs SCLx and SDAx are
ignored and the I2C module does not respond to any address on the bus. When ENAB is
set to 1, the I2C responds to calls to its slave address and to the general call address if the
GCE bit (I2C_SAR[0]) is set to 1.
When the Master Mode Start bit (STA) is set to 1, the I2C enters MASTER mode and
sends a START condition on the bus when the bus is free. If the STA bit is set to 1 when
the I2C module is already in MASTER mode and one or more bytes are transmitted, then a
repeated START condition is sent. If the STA bit is set to 1 when the I2C block is being
Bit
Position Value Description
[7:0]
SLAX
00h–FFh Least significant 8 bits of the 10-bit extended slave address.
Table 83. I2C Data Register (I2C_DR = 00CAh)
Bit 76543210
Reset 00000000
CPU Access R/W R/W R/W R/W R/W R/W R/W R/W
Note: R/W = Read/Write.
Bit
Position Value Description
[7:0]
DATA
00h–FFh I2C data byte.
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accessed in SLAVE mode, the I2C completes the data transfer in SLAVE mode and then
enters MASTER mode when the bus is released. The STA bit is automatically cleared after
a START condition is set. Writing a 0 to this bit produces no effect.
If the Master Mode Stop bit (STP) is set to 1 in MASTER mode, a STOP condition is
transmitted on the I2C bus. If the STP bit is set to 1 in slave move, the I2C module operates
as if a STOP condition is received, but no STOP condition is transmitted. If both STA and
STP bits are set, the I2C block first transmits the STOP condition (if in MASTER mode)
and then transmit the START condition. The STP bit is cleared automatically. Writing a 0
to this bit produces no effect.
The I2C Interrupt Flag (IFLG) is set to 1 automatically when any of 30 of the possible 31
I2C states is entered. The only state that does not set the IFLG bit is state F8h. If IFLG is
set to 1 and the IEN bit is also set, an interrupt is generated. When IFLG is set by the I2C,
the Low period of the I2C bus clock line is stretched and the data transfer is suspended.
When a 0 is written to IFLG, the interrupt is cleared and the I2C clock line is released.
When the I2C Acknowledge bit (AAK) is set to 1, an Acknowledge is sent during the
acknowledge clock pulse on the I2C bus if:
•
Either the whole of a 7-bit slave address or the first or second byte of a 10-bit slave ad-
dress is received
•
The general call address is received and the General Call Enable bit in I2C_SAR is set
to 1
•
A data byte is received while in MASTER or SLAVE modes
When AAK is cleared to 0, a NACK is sent when a data byte is received in MASTER or
SLAVE mode. If AAK is cleared to 0 in the Slave Transmitter mode, the byte in the
I2C_DR register is assumed to be the final byte. After this byte is transmitted, the I2C
block enter states C8h, then returns to the idle state. The I2C module does not respond to
its slave address unless AAK is set. See Table 84.
Table 84. I2C Control Registers (I2C_CTL = 00CBh)
Bit 76543210
Reset 00000000
CPU Access R/W R/W R/W R/W R/W R/W R R
Note: R/W = Read/Write; R = Read Only.
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I2C Status Register
The I2C_SR register is a Read-Only register that contains a 5-bit status code in the five
most significant bits: the three least significant bits are always 0. The Read-Only I2C_SR
registers share the same I/O addresses as the Write-Only I2C_CCR registers. See Table 85.
Bit
Position Value Description
7
IEN
0I
2C interrupt is disabled.
1I
2C interrupt is enabled.
6
ENAB
0The I
2C bus (SCL/SDA) is disabled and all inputs are
ignored.
1The I
2C bus (SCL/SDA) is enabled.
5
STA
0 Master mode START condition is sent.
1 Master mode start-transmit START condition on the bus.
4
STP
0 Master mode STOP condition is sent.
1 Master mode stop-transmit STOP condition on the bus.
3
IFLG
0I
2C interrupt flag is not set.
1I
2C interrupt flag is set.
2
AAK
0 Not Acknowledge.
1 Acknowledge.
[1:0] 00 Reserved.
Table 85. I2C Status Registers (I2C_SR = 00CCh)
Bit 76543210
Reset 11111000
CPU Access RRRRRRRR
Note: R = Read only.
Bit
Position Value Description
[7:3]
STAT
00000–11111 5-bit I2C status code.
[2:0] 000 Reserved.
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There are 29 possible status codes, as listed in Table 86. When the I2C_SR register con-
tains the status code F8h, no relevant status information is available, no interrupt is gener-
ated and the IFLG bit in the I2C_CTL register is not set. All other status codes correspond
to a defined state of the I2C.
When each of these states is entered, the corresponding status code appears in this register
and the IFLG bit in the I2C_CTL register is set. When the IFLG bit is cleared, the status
code returns to F8h.
Table 86. I2C Status Codes
Code Status
00h Bus error
08h START condition transmitted
10h Repeated START condition transmitted
18h Address and Write bit transmitted, ACK received
20h Address and Write bit transmitted, ACK not received
28h Data byte transmitted in MASTER mode, ACK received
30h Data byte transmitted in MASTER mode, ACK not received
38h Arbitration lost in address or data byte
40h Address and Read bit transmitted, ACK received
48h Address and Read bit transmitted, ACK not received
50h Data byte received in MASTER mode, ACK transmitted
58h Data byte received in MASTER mode, NACK transmitted
60h Slave address and Write bit received, ACK transmitted
68h Arbitration lost in address as master, slave address and Write bit received,
ACK transmitted
70h General Call address received, ACK transmitted
78h Arbitration lost in address as master, General Call address received, ACK
transmitted
80h Data byte received after slave address received, ACK transmitted
88h Data byte received after slave address received, NACK transmitted
90h Data byte received after General Call received, ACK transmitted
98h Data byte received after General Call received, NACK transmitted
A0h STOP or repeated START condition received in SLAVE mode
A8h Slave address and Read bit received, ACK transmitted
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If an illegal condition occurs on the I2C bus, the bus error state is entered (status code
00h). To recover from this state, the STP bit in the I2C_CTL
register must be set and the
IFLG bit cleared. The I2C then returns to the idle state. No STOP condition is transmitted
on the I2C bus.
The STP and STA bits may be set to 1 at the same time to recover from the bus error. The
I2C then sends a START.
I2C Clock Control Register
The I2C_CCR register is a Write-Only register. The seven LSBs control the frequency at
which the I2C bus is sampled and the frequency of the I2C clock line (SCL) when the I2C
is in MASTER mode. The Write-Only I2C_CCR registers share the same I/O addresses as
the Read-Only I2C_SR registers. See Table 87.
B0h Arbitration lost in address as master, slave address and Read bit received,
ACK transmitted
B8h Data byte transmitted in SLAVE mode, ACK received
C0h Data byte transmitted in SLAVE mode, ACK not received
C8h Last byte transmitted in SLAVE mode, ACK received
D0h Second Address byte and Write bit transmitted, ACK received
D8h Second Address byte and Write bit transmitted, ACK not received
F8h No relevant status information, IFLG = 0
Table 87. I2C Clock Control Registers (I2C_CCR = 00CCh)
Bit 76543210
Reset 00000000
CPU Access WWWWWWWW
Note: W = Read only.
Bit
Position Value Description
7 0 Reserved.
Table 86. I2C Status Codes (Continued)
Code Status
Note:
PS013014-0107 I2C Serial I/O Interface
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158
The I2C clocks are derived from the eZ80L92’s system clock. The frequency of the
eZ80L92 system clock is fSCK. The I2C bus is sampled by the I2C block at the frequency
fSAMP supplied by:
In MASTER mode, the I2C clock output frequency on SCL (fSCL) is supplied by:
The use of two separately-programmable dividers allows the MASTER mode output fre-
quency to be set independently of the frequency at which the I2C bus is sampled. This fea-
ture is particularly useful in multimaster systems because the frequency at which the I2C
bus is sampled must be at least 10 times the frequency of the fastest master on the bus to
ensure that START and STOP conditions are always detected. By using two programma-
ble clock divider stages, a high sampling frequency can be ensured while allowing the
MASTER mode output to be set to a lower frequency.
Bus Clock Speed
The I2C bus is defined for bus clock speeds up to 100 Kbps (400 Kbps in FAST mode).
To ensure correct detection of START and STOP conditions on the bus, the I2C must sam-
ple the I2C bus at least ten times faster than the bus clock speed of the fastest master on the
bus. The sampling frequency should therefore be at least 1 MHz (4 MHz in FAST mode)
to guarantee correct operation with other bus masters.
The I2C sampling frequency is determined by the frequency of the eZ80L92 system clock
and the value in the I2C_CCR bits 2 to 0. The bus clock speed generated by the I2C in
MASTER mode is determined by the frequency of the input clock and the values in
I2C_CCR[2:0] and I2C_CCR[6:3].
[6:3]
M
0000–1111 I2C clock divider scalar value.
[2:0]
N
000–111 I2C clock divider exponent.
fSAMP =fSCLK
2N
fSCL =fSCLK
10 • (M + 1)(2)N
Bit
Position Value Description
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eZ80L92 MCU
Product Specification
159
I2C Software Reset Register
The I2C_SRR register is a Write-Only register. Writing any value to this register performs
a software reset of the I2C module. See Table 88.
Table 88. I2C Software Reset Register (I2C_SRR = 00CDh)
Bit 76543210
Reset XXXXXXXX
CPU Access WWWWWWWW
Note: W = Write-Only.
Bit
Position Value Description
[7:0]
SRR
00h–FFh Writing any value to this register performs a software
reset of the I2C module.
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160
ZiLOG Debug Interface
The ZiLOG Debug Interface (ZDI) provides a built-in debugging interface to the eZ80
CPU. ZDI provides basic in-circuit emulation features including:
•
Examining and modifying internal registers.
•
Examining and modifying memory.
•
Starting and stopping the user program.
•
Setting program and data break points.
•
Single-stepping the user program.
•
Executing user-supplied instructions.
•
Debugging the final product with the inclusion of one small connector.
•
Downloading code into SRAM.
•
‘C’ source-level debugging using ZiLOG Developer Studio (ZDS II)
The above features are built into the silicon. Control is provided through a two-wire inter-
face that is connected to the ZPAK II emulator. Figure 35 illustrates a typical setup using a
target board, ZPAK II, and the host PC running ZDS II. For more information on ZPAK II
and ZDS II, refer to www.zilog.com.
ZDI allows reading and writing of most internal registers without disturbing the state of
the machine. Reads and Writes to memory may occur as fast as the ZDI can download and
upload data, with a maximum frequency of one-half the eZ80L92 system clock frequency.
Figure 35. Typical ZDI Debug Setup
ZiLOG
Developer
Studio
ZPAK
Emulator
eZ80
Product
Target Board
C
O
N
N
E
C
T
O
R
PS013014-0107 ZiLOG Debug Interface
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Table 89 lists the recommended frequencies of the ZDI clock in relation to the system
clock.
ZDI-Supported Protocol
ZDI supports a bidirectional serial protocol. The protocol defines any device that sends
data as the transmitter and any receiving device as the receiver. The device controlling the
transfer is the master and the device being controlled is the slave. The master always
initiates the data transfers and provides the clock for both receive and transmit operations.
The ZDI block on the eZ80L92 MCU is considered as slave in all data transfers.
Figure 36 illustrates the schematic for building a connector on a target board. This
connector allows you to connect directly to the ZPAK emulator using a six-pin header.
Table 89. Recommended ZDI Clock versus System Clock Frequency
System Clock
Frequency
ZDI Clock
Frequency
3–10 MHz 1 MHz
8–16 MHz 2 MHz
12–24 MHz 4 MHz
20–50 MHz 8 MHz
Figure 36. Schematic For Building a Target Board ZPAK Connector
6-Pin Target Connector
1
3
5
2
4
6
eZ80L92
MCU
10 K‰ 10 K‰
TCK (ZCL)
TDI (ZDA)
TVDD
(Target V )
DD
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ZDI Clock and Data Conventions
The two pins used for communication with the ZDI block are ZDI Clock pin (ZCL) and
ZDI Data pin (ZDA). On eZ80L92 MCU, the ZCL pin is shared with the TCK pin while
the ZDA pin is shared with the TDI pin. The ZCL pin and ZDA pin functions are only
available when the on-chip instrumentation is disabled and the ZDI is therefore enabled.
For general data communication, the data value on the ZDA pin changes only when ZCL
is Low (0). The only exception is the ZDI START bit, which is indicated by a High-to-
Low transition (falling edge) on the ZDA pin while ZCL is High.
Data is shifted in and out of ZDI, with the most significant bit (bit 7) of each byte being
first in time, and the least significant bit (bit 0) last in time. The information is transferred
between the master and the slave in 8-bit (single-byte) units. Each byte is transferred with
nine clock cycles: eight to shift the data, and the ninth for internal operations.
ZDI START Condition
All the ZDI commands are preceded by a ZDI START signal, which is a High-to-Low
transition of ZDA when ZCL is High. The ZDI slave on the eZ80L92 continually monitors
the ZDA and ZCL lines for the START signal and does not respond to any command until
this condition is met. The master pulls ZDA Low, with ZCL High, to indicate the
beginning of a data transfer with the ZDI block. Figure 37 and Figure 38 illustrate a valid
ZDI START signal prior to writing and reading the data, respectively. A Low-to-High
transition of ZDA while the ZCL is High produces no effect.
Data is shifted in during a Write to the ZDI block on the rising edge of ZCL, as illustrated
in Figure 37. Data is shifted out during a Read from the ZDI block on the falling edge of
ZCL as illustrated in Figure 38. When an operation is completed, the master stops during
the ninth cycle and holds the ZCL signal High.
Figure 37. ZDI Write Timing
ZDI Data In
(Write)
ZDI Data In
(Write)
Start Signal
ZCL
ZDA
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ZDI Single-Bit Byte Separator
Following each 8-bit ZDI data transfer, a single-bit byte separator is used. To initiate a
new ZDI command, the single-bit byte separator must be High (logical 1) to allow a new
ZDI START command to be sent. For all other cases, the single-bit byte separator is either
Low (logical 0) or High (logical 1). When ZDI is configured to allow the CPU to accept
external bus requests, the single-bit byte separator must be Low (logical 0) during all ZDI
commands. This Low value indicates that ZDI is still operating and is not ready to
relinquish the Bus. The CPU does not accept the external bus requests until the single-bit
byte separator is a High (logical 1). For more information on accepting bus requests in
ZDI DEBUG mode, see Bus Requests During ZDI Debug Mode on page 167.
ZDI Register Addressing
Following a START signal, the ZDI master must output the ZDI register address. All data
transfers with the ZDI block use special ZDI registers. The ZDI control registers that
reside in the ZDI register address space should not be confused with the eZ80L92 periph-
eral registers that reside in the I/O address space.
Many locations in the ZDI control register address space are shared by two registers, one
for Read-Only access and another one for Write-Only access. For example, a Read from
ZDI register address 00h returns the eZ80 Product ID Low Byte while a Write to this same
location, 00h, stores the Low byte of one of the address match values used for generating
break points.
The format for a ZDI address is seven bits of address, followed by one bit for Read or
Write control, and completed by a single-bit byte separator. The ZDI executes a Read or
Write operation depending on the state of the R/W bit (0 = Write, 1 = Read). If no new
START command is issued at completion of the Read or Write operation, the operation
Figure 38. ZDI Read Timing
ZDI Data Out
(Read)
ZDI Data Out
(Read)
Start Signal
ZCL
ZDA
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164
can be repeated. This allows repeated Read or Write operations without having to resend
the ZDI command. A START signal must follow to initiate a new ZDI command.
Figure 39 illustrates the timing for address Writes to ZDI registers.
ZDI Write Operations
ZDI Single-Byte Write
For single-byte Write operations, the address and write control bit are first written to the
ZDI block. Following the single-bit byte separator, the data is shifted into the ZDI block
on the next 8 rising edges of ZCL. The master terminates activity after 8 clock cycles.
Figure 40 illustrates the timing for ZDI single-byte Write operations.
Figure 39. ZDI Address Write Timing
Figure 40. ZDI Single-Byte Data Write Timing
ZDI Address Byte
Single-Bit
Byte Separator
or new ZDI
START Signal
START
Signal
0 = WRITE
1 = READ
lsbmsb
ZCLS 1 23 45 67 89
A6 A5 A4 A3 A2 A1 A0 R/W 0/1ZDA
ZDI Data Byte
lsb of
ZDI Address
Single-Bit
Byte Separator
lsb
of DATA
msb
of DATA
End of Data
or New ZDI
START Signal
ZCL 789123456789
A0 Write 0/1 D7 D6 D5 D4 D3 D2 D1 D0 1
ZDA
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ZDI Block Write
The Block Write operation is initiated in the same manner as the single-byte Write opera-
tion, but instead of terminating the Write operation after the first data byte is transferred,
the ZDI master can continue to transmit additional bytes of data to the ZDI slave on the
eZ80L92. After the receipt of each byte of data the ZDI register address increments by 1.
If the ZDI register address reaches the end of the Write-Only ZDI register address space
(30h), the address stops incrementing. Figure 41 illustrates the timing for ZDI Block
Write operations.
ZDI Read Operations
ZDI Single-Byte Read
Single-byte Read operations are initiated in the same manner as single-byte Write opera-
tions, with the exception that the R/W bit of the ZDI register address is set to 1. Upon
receipt of a slave address with the R/W bit set to 1, the eZ80L92’s ZDI block loads the
selected data into the shifter at the beginning of the first cycle following the single-bit data
separator. The most significant bit (msb) is shifted out first. Figure 42 illustrates the timing
for ZDI single-byte Read operations.
Figure 41. ZDI Block Data Write Timing
ZDI Data Bytes
lsb of
ZDI Address
Single-Bit
Byte Separator
msb
of DATA
Byte 2
msb
of DATA
Byte 1
lsb
of DATA
Byte 1
Single-Bit
Byte Separator
ZCL 789123789129
A0 Write 0/1 D7 D6 D5 D1 D0 0/1 D7 D6 1
ZDA
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ZDI Block Read
A Block Read operation is initiated the same as a single-byte Read; however, the ZDI
master continues to clock in the next byte from the ZDI slave as the ZDI slave continues to
output data. The ZDI register address counter increments with each Read. If the ZDI
register address reaches the end of the Read-Only ZDI register address space (20h), the
address stops incrementing. Figure 43 illustrates the ZDI’s Block Read timing.
Operation of the eZ80L92 During ZDI Break Points
If the ZDI forces the CPU to break, only the CPU suspends operation. The system clock
continues to operate and drive other peripherals. Those peripherals that can operate auton-
omously from the CPU may continue to operate, if so enabled. For example, the Watchdog
Timer and Programmable Reload Timers continue to count during a ZDI break point.
Figure 42. ZDI Single-Byte Data Read Timing
Figure 43. ZDI Block Data Read Timing
ZDI Data Byte
lsb of
ZDI Address
Single-Bit
Byte Separator
lsb
of DATA
msb
of DATA
End of Data
or New ZDI
START Signal
ZCL 789123456789
A0 Read 0/1 D7 D6 D5 D4 D3 D2 D1 D0 1
ZDA
ZDI Data Bytes
lsb of
ZDI Address
Single-Bit
Byte Separator
msb
of DATA
Byte 2
msb
of DATA
Byte 1
lsb
of DATA
Byte 1
Single-Bit
Byte Separator
ZCL 789123789129
A0 Read 0/1 D7 D6 D5 D1 D0 0/1 D7 D6 1
ZDA
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When using the ZDI interface, any Write or Read operations of peripheral registers in the
I/O address space produces the same effect as Read or Write operations using the CPU.
Because many register Read/Write operations exhibit secondary effects, such as clearing
flags or causing operations to commence, the effects of the Read/Write operations during a
ZDI Break must be taken into consideration.
Bus Requests During ZDI Debug Mode
The ZDI block on the eZ80L92 allows an external device to take control of the address
and data bus while the eZ80L92 is in DEBUG mode. ZDI_BUSACK_EN causes ZDI to
allow or prevent acknowledgement of bus requests by external peripherals. The bus
acknowledge only occurs at the end of the current ZDI operation (indicated by a High dur-
ing the single-bit byte separator). The default reset condition is for bus acknowledgement
to be disabled. To allow bus acknowledgement, the ZDI_BUSACK_EN must be written.
When an external bus request (BUSREQ pin asserted) is detected, ZDI waits until comple-
tion of the current operation before responding. ZDI acknowledges the bus request by
asserting the bus acknowledge (BUSACK) signal. If the ZDI block is not currently shift-
ing data, it acknowledges the bus request immediately. ZDI uses the single-bit byte separa-
tor of each data word to determine if it is at the end of a ZDI operation. If the bit is a
logical 0, ZDI does not assert BUSACK to allow additional data Read or Write operations.
If the bit is a logical 1, indicating completion of the ZDI commands, BUSACK is asserted.
Potential Hazards of Enabling Bus Requests During Debug Mode
There are some potential hazards that the user must be aware of when enabling external
bus requests during ZDI Debug mode. First, when the address and data bus are being used
by an external source, ZDI must only access ZDI registers and internal CPU registers to
prevent possible Bus contention. The bus acknowledge status is reported in the
ZDI_BUS_STAT register. The BUSACK output pin also indicates the bus acknowledge
state.
A second hazard is that when a bus acknowledge is granted, the ZDI is subject to any
WAIT states that are assigned to the device currently being accessed by the external
peripheral. To prevent data errors, ZDI should avoid data transmission while another
device is controlling the bus.
Finally, exiting ZDI Debug mode while an external peripheral controls the address and
data buses, as indicated by BUSACK assertion, may produce unpredictable results.
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ZDI Write-Only Registers
Table 90 lists the ZDI Write-Only registers. Many of the ZDI Write-Only addresses are
shared with ZDI Read-Only registers.
Table 90. ZDI Write-Only Registers
ZDI Address ZDI Register Name ZDI Register Function
Reset
Value
00h ZDI_ADDR0_L Address Match 0 Low Byte XXh
01h ZDI_ADDR0_H Address Match 0 High Byte XXh
02h ZDI_ADDR0_U Address Match 0 Upper Byte XXh
04h ZDI_ADDR1_L Address Match 1 Low Byte XXh
05h ZDI_ADDR1_H Address Match 1 High Byte XXh
06h ZDI_ADDR1_U Address Match 1 Upper Byte XXh
08h ZDI_ADDR2_L Address Match 2 Low Byte XXh
09h ZDI_ADDR2_H Address Match 2 High Byte XXh
0Ah ZDI_ADDR2_U Address Match 2 Upper Byte XXh
0Ch ZDI_ADDR3_L Address Match 3 Low Byte XXh
0Dh ZDI_ADDR3_H Address Match 3 High Byte XXh
0Eh ZDI_ADDR3_U Address Match 4 Upper Byte XXh
10h ZDI_BRK_CTL Break Control register 00h
11h ZDI_MASTER_CTL Master Control register 00h
13h ZDI_WR_DATA_L Write Data Low Byte XXh
14h ZDI_WR_DATA_H Write Data High Byte XXh
15h ZDI_WR_DATA_U Write Data Upper Byte XXh
16h ZDI_RW_CTL Read/Write Control register 00h
17h ZDI_BUS_CTL Bus Control register 00h
21h ZDI_IS4 Instruction Store 4 XXh
22h ZDI_IS3 Instruction Store 3 XXh
23h ZDI_IS2 Instruction Store 2 XXh
24h ZDI_IS1 Instruction Store 1 XXh
25h ZDI_IS0 Instruction Store 0 XXh
30h ZDI_WR_MEM Write Memory register XXh
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ZDI Read-Only Registers
Table 91 lists the ZDI Read-Only registers. Many of the ZDI Read-Only addresses are
shared with ZDI Write-Only registers.
ZDI Register Definitions
ZDI Address Match Registers
The four sets of address match registers are used for setting the addresses for generating
break points. When the accompanying BRK_ADDRx bit is set in the ZDI Break Control
register to enable the particular address match, the current eZ80L92 address is compared
with the 3-byte address set, {ZDI_ADDRx_U, ZDI_ADDRx_H, ZDI_ADDR_x_L}. If
the CPU is operating in ADL mode, the address is supplied by ADDR[23:0]. If the CPU is
operating in Z80 mode, the address is supplied by {MBASE[7:0], ADDR[15:0]}. If a
match is found, ZDI issues a BREAK to the eZ80L92 placing the processor in ZDI mode
pending further instructions from the ZDI interface block. If the address is not the first op-
code fetch, the ZDI BREAK is executed at the end of the instruction in which it is exe-
cuted. There are four sets of address match registers. They can be used in conjunction with
each other to break on branching instructions. See Table 92.
Table 91. ZDI Read-Only Registers
ZDI Address ZDI Register Name ZDI Register Function
Reset
Value
00h ZDI_ID_L eZ80 Product ID Low Byte register 06h
01h ZDI_ID_H eZ80 Product ID High Byte register 00h
02h ZDI_ID_REV eZ80 Product ID Revision register XXh
03h ZDI_STAT Status register 00h
10h ZDI_RD_L Read Memory Address Low Byte register XXh
11h ZDI_RD_H Read Memory Address High Byte register XXh
12h ZDI_RD_U Read Memory Address Upper Byte register XXh
17h ZDI_BUS_STAT Bus Status register 00h
20h ZDI_RD_MEM Read Memory Data Value XXh
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ZDI Break Control Register
The ZDI Break Control register is used to enable break points. ZDI asserts a BREAK
when the CPU instruction address, ADDR[23:0], matches the value in the ZDI Address
Match 3 registers, {ZDI_ADDR3_U, ZDI_ADDR3_H, ZDI_ADDR3_L}. Breaks only
occur on an instruction boundary. If the instruction address is not the beginning of an
instruction (that is, for multibyte instructions), then the BREAK occurs at the end of the
current instruction. The BRK_NEXT bit is set to 1. The BRK_NEXT bit must be reset to 0
to release the BREAK. See Table 93.
Table 92. ZDI Address Match Registers ZDI_ADDR0_L = 00h, ZDI_ADDR0_H
= 01h, ZDI_ADDR0_U = 02h, ZDI_ADDR1_L = 04h, ZDI_ADDR1_H = 05h,
ZDI_ADDR1_U = 06h, ZDI_ADDR2_L = 08h, ZDI_ADDR2_H = 09h,
ZDI_ADDR2_U = 0Ah, ZDI_ADDR3_L = 0Ch, ZDI_ADDR3_H = 0Dh, and
ZDI_ADDR3_U = 0Eh in the ZDI Register Write-Only Address Space
Bit 76543210
Reset XXXXXXXX
CPU Access WWWWWWWW
Note: W = Write-only.
Bit
Position Value Description
[7:0]
ZDI_ADDRx_L,
ZDI_ADDRx_H,
or
ZDI_ADDRx_U
00h–FFh The four sets of ZDI address match registers are used
for setting the addresses for generating break points.
The 24-bit addresses are supplied by {ZDI_ADDRx_U,
ZDI_ADDRx_H, ZDI_ADDRx_L, where x is 0, 1, 2, or 3.
Table 93. ZDI Break Control Register (ZDI_BRK_CTL = 10h in the ZDI Write-
Only Register Address Space)
Bit 76543210
Reset 00000000
CPU Access WWWWWWWW
Note: W = Write-only.
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Bit
Position Value Description
7
BRK_NEXT
0 The ZDI BREAK on the next CPU instruction is disabled.
Clearing this bit releases the CPU from its current BREAK
condition.
1 The ZDI BREAK on the next CPU instruction is enabled.
The CPU can use multibyte Op Codes and multibyte
operands. break points only occur on the first Op Code in a
multibyte Op Code instruction. If the ZCL pin is High and
the ZDA pin is Low at the end of RESET, this bit is set to 1
and a BREAK occurs on the first instruction following the
RESET. This bit is set automatically during ZDI BREAK on
address match. A BREAK can also be forced by writing a 1
to this bit.
6
brk_addr3
0 The ZDI BREAK, upon matching break address 3,
is disabled.
1 The ZDI BREAK, upon matching break address 3,
is enabled.
5
brk_addr2
0 The ZDI BREAK, upon matching break address 2,
is disabled.
1 The ZDI BREAK, upon matching break address 2,
is enabled.
4
brk_addr1
0 The ZDI BREAK, upon matching break address 1,
is disabled.
1 The ZDI BREAK, upon matching break address 1,
is enabled.
3
brk_addr0
0 The ZDI BREAK, upon matching break address 0,
is disabled.
1 The ZDI BREAK, upon matching break address 0,
is enabled.
2
ign_low_1
0The Ignore the Low Byte function of the ZDI Address Match
1 registers is disabled. If BRK_ADDR1 is set to 1, ZDI
initiates a BREAK when the entire 24-bit address,
ADDR[23:0], matches the 3-byte value {ZDI_ADDR1_U,
ZDI_ADDR1_H, ZDI_ADDR1_L}.
1The Ignore the Low Byte function of the ZDI Address Match
1 registers is enabled. If BRK_ADDR1 is set to 1, ZDI
initiates a BREAK when only the upper 2 bytes of the 24-bit
address, ADDR[23:8], match the 2-byte value
{ZDI_ADDR1_U, ZDI_ADDR1_H}. As a result, a BREAK
can occur anywhere within a 256-byte page.
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172
ZDI Master Control Register
The ZDI Master Control register provides control of the eZ80L92. It is capable of forcing
a RESET and waking up the eZ80L92 from the low-power modes (HALT or SLEEP). See
Table 94.
1
ign_low_0
0The Ignore the Low Byte function of the ZDI Address Match
1 registers is disabled. If BRK_ADDR0 is set to 1, ZDI
initiates a BREAK when the entire 24-bit address,
ADDR[23:0], matches the 3-byte value {ZDI_ADDR0_U,
ZDI_ADDR0_H, ZDI_ADDR0_L}.
1The Ignore the Low Byte function of the ZDI Address Match
1 registers is enabled. If the BRK_ADDR1 is set to 0, ZDI
initiates a BREAK when only the upper 2 bytes of the 24-bit
address, ADDR[23:8], match the 2 bytes value
{ZDI_ADDR0_U, ZDI_ADDR0_H}. As a result, a BREAK
can occur anywhere within a 256-byte page.
0
single_step
0 ZDI SINGLE STEP mode is disabled.
1 ZDI SINGLE STEP mode is enabled. ZDI asserts a BREAK
following execution of each instruction.
Table 94. ZDI Master Control Register (ZDI_MASTER_CTL = 11h in ZDI
Register Write Address Spaces)
Bit 76543210
Reset 00000000
CPU Access WWWWWWWW
Note: W = Write-only.
Bit
Position Value Description
7
ZDI_RESET
0 No action.
1 Initiate a RESET of the eZ80L92. This bit is
automatically cleared at the end of the RESET event.
[6:0] 0000000 Reserved.
Bit
Position Value Description
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173
ZDI Write Data Registers
These three registers are used in the ZDI Write-Only register address space to store the
data that is written when a Write instruction is sent to the ZDI Read/Write Control register
(ZDI_RW_CTL). The ZDI Read/Write Control register is located at ZDI address 16h
immediately following the ZDI Write Data registers. As a result, the ZDI Master is
allowed to write the data to {ZDI_WR_U, ZDI_WR_H, ZDI_WR_L} and the Write com-
mand in one data transfer operation. See Table 95.
ZDI Read/Write Control Register
The ZDI Read/Write Control register is used in the ZDI Write-Only Register address to
read data from, write data to, and manipulate the CPU’s registers or memory locations.
When this register is written, the eZ80L92 immediately performs the operation corre-
sponding to the data value written as described in Table 96.
When a Read operation is executed via this register, the requested data values are placed in
the ZDI Read Data registers {ZDI_RD_U, ZDI_RD_H, ZDI_RD_L}. When a Write oper-
ation is executed via this register, the Write data is taken from the ZDI Write Data registers
{ZDI_WR_U, ZDI_WR_H, ZDI_WR_L}. See Table 96. For more information on the
CPU registers, refer to the eZ80® CPU User Manual (UM0077).
Table 95. ZDI Write Data Registers (ZDI_WR_U = 13h, ZDI_WR_H = 14h, and
ZDI_WR_L = 15h in the ZDI Register Write-Only Address Space)
Bit 76543210
Reset XXXXXXXX
CPU Access WWWWWWWW
Note: X = Undefined; W = Write.
Bit
Position Value Description
[7:0]
ZDI_WR_L,
ZDI_WR_H,
or
ZDI_WR_L
00h–FFh These registers contain the data that is written during
execution of a Write operation defined by the
ZDI_RW_CTL register. The 24-bit data value is stored
as {ZDI_WR_U, ZDI_WR_H, ZDI_WR_L}. If less than
24 bits of data are required to complete the required
operation, the data is taken from the least significant
byte(s).
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Table 96. ZDI Read/Write Control Register Functions (ZDI_RW_CTL = 16h in
the ZDI Register Write-Only Address Space)
Hex
Value Command
Hex
Value Command
00 Read {MBASE, A, F}
ZDI_RD_U ← MBASE
ZDI_RD_H ← F
ZDI_RD_L ← A
80 Write {MBASE, A, F}
MBASE ← ZDI_WR_U
F ← ZDI_WR_H
A ← ZDI_WR_L
01 Read BC
ZDI_RD_U ← BCU
ZDI_RD_H ← B
ZDI_RD_L ← C
81 Write BC
BCU ← ZDI_WR_U
B ← ZDI_WR_H
C ← ZDI_WR_L
02 Read DE
ZDI_RD_U ← DEU
ZDI_RD_H ← D
ZDI_RD_L ← E
82 Write DE
DEU ← ZDI_WR_U
D ← ZDI_WR_H
E ← ZDI_WR_L
03 Read HL
ZDI_RD_U ← HLU
ZDI_RD_H ← H
ZDI_RD_L ← L
83 Write HL
HLU ← ZDI_WR_U
H ← ZDI_WR_H
L ← ZDI_WR_L
04 Read IX
ZDI_RD_U ← IXU
ZDI_RD_H ← IXH
ZDI_RD_L ← IXL
84 Write IX
IXU ← ZDI_WR_U
IXH ← ZDI_WR_H
IXL ← ZDI_WR_L
05 Read IY
ZDI_RD_U ← IYU
ZDI_RD_H ← IYH
ZDI_RD_L ← IYL
85 Write IY
IYU ← ZDI_WR_U
IYH ← ZDI_WR_H
IYL ← ZDI_WR_L
06 Read SP
In ADL mode, SP = SPL.
In Z80 mode, SP = SPS.
86 Write SP
In ADL mode, SP = SPL.
In Z80 mode, SP = SPS.
07 Read PC
ZDI_RD_U ← PC[23:16]
ZDI_RD_H ← PC[15:8]
ZDI_RD_L ← PC[7:0]
87 Write PC
PC[23:16] ← ZDI_WR_U
PC[15:8] ← ZDI_WR_H
PC[7:0] ← ZDI_WR_L
08 Set ADL
ADL ← 1
88 Reserved
Note: The eZ80 CPU’s alternate register set (A’, F’, B’, C’, D’, E’, HL’) cannot be read directly.
The ZDI programmer must execute the exchange instruction (EXX) to gain access to the
alternate eZ80 CPU register set.
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175
ZDI Bus Control Register
The ZDI Bus Control register controls bus requests during DEBUG mode. It enables or
disables bus acknowledge in ZDI DEBUG mode and allows ZDI to force assertion of the
BUSACK signal. This register must be written during ZDI Debug mode (that is, following
a BREAK). See Table 97.
09 Reset ADL
ADL ← 0
89 Reserved
0A Exchange CPU register sets
AF ← AF’
BC ← BC’
DE ← DE’
HL ← HL’
8A Reserved
0B Read memory from current PC
value, increment PC
8B Write memory from current PC
value, increment PC
Table 97. ZDI Bus Control Register (ZDI_BUS_CTL = 17h in the ZDI Register
Write-Only Address Space)
Bit 76543210
Reset 00000000
CPU Access WWWWWWWW
Note: W = Write-only.
Table 96. ZDI Read/Write Control Register Functions (ZDI_RW_CTL = 16h in
the ZDI Register Write-Only Address Space) (Continued)
Hex
Value Command
Hex
Value Command
Note: The eZ80 CPU’s alternate register set (A’, F’, B’, C’, D’, E’, HL’) cannot be read directly.
The ZDI programmer must execute the exchange instruction (EXX) to gain access to the
alternate eZ80 CPU register set.
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Instruction Store 4:0 Registers
The ZDI Instruction Store registers are located in the ZDI Register Write-Only address
space. They can be written with instruction data for direct execution by the CPU. When
the ZDI_IS0 register is written, the eZ80L92 exits the ZDI BREAK state and executes a
single instruction. The Op Codes and operands for the instruction come from these
Instruction Store registers. The Instruction Store Register 0 is the first byte fetched,
followed by Instruction Store registers 1, 2, 3, and 4, as necessary.
Only the bytes the processor requires to execute the instruction must be stored in these
registers. Some eZ80 instructions, when combined with the MEMORY mode suffixes
(.SIS, .SIL, .LIS, or .LIL), require 6 bytes to operate. These 6-byte instructions cannot be
executed directly using the ZDI Instruction Store registers. See Table 98.
The Instruction Store 0 register is located at a higher ZDI address than the other
Instruc-
tion Store
registers. This feature allows the use of the ZDI auto-address increment func-
tion to load and execute a multibyte instruction with a single data stream from the ZDI
master. Execution of the instruction commences with writing the final byte to ZDI_IS0.
Bit
Position Value Description
7
ZDI_BUSAK_EN
0 Bus requests by external peripherals using the BUSREQ
pin are ignored. The bus acknowledge signal, BUSACK, is
not asserted in response to any bus requests.
1 Bus requests by external peripherals using the BUSREQ
pin are accepted. A bus acknowledge occurs at the end of
the current ZDI operation. The bus acknowledge is
indicated by asserting the BUSACK pin in response to a
bus request.
6
ZDI_BUSAK
0 Deassert the bus acknowledge pin (BUSACK) to return
control of the address and data buses back to ZDI.
1 Assert the bus acknowledge pin (BUSACK) to pass control
of the address and data buses to an external peripheral.
[5:0] 000000 Reserved.
Note:
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ZDI Write Memory Register
A Write to the ZDI Write Memory register causes the eZ80L92 to write the 8-bit data to
the memory location specified by the current address in the program counter. In Z80
MEMORY mode, this address is {MBASE, PC[15:0]}. In ADL MEMORY mode, this
address is PC[23:0]. The program counter, PC, increments after each data Write. However,
the ZDI register address does not increment automatically when this register is accessed.
As a result, the ZDI master is allowed to write any number of data bytes by writing to this
address one time followed by any number of data bytes. See Table 99.
Table 98. Instruction Store 4:0 Registers (ZDI_IS4 = 21h, ZDI_IS3 = 22h,
ZDI_IS2 = 23h, ZDI_IS1 = 24h, and ZDI_IS0 = 25h in the ZDI Register Write-
Only Address Space)
Bit 76543210
Reset XXXXXXXX
CPU Access WWWWWWWW
Note: X = Undefined; W = Write.
Bit
Position Value Description
[7:0]
ZDI_IS4,
ZDI_IS3,
ZDI_IS2,
ZDI_IS1,
or
ZDI_IS0
00h–FFh These registers contain the Op Codes and operands
for immediate execution by the CPU following a Write
to ZDI_IS0. The ZDI_IS0 register contains the first Op
Code of the instruction. The remaining ZDI_ISx
registers contain any additional Op Codes or operand
dates required for execution of the required instruction.
Table 99. ZDI Write Memory Register (ZDI_WR_MEM = 30h in the ZDI
Register Write-Only Address Space)
Bit 76543210
Reset XXXXXXXX
CPU Access WWWWWWWW
Note: X = Undefined; W = Write.
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178
eZ80® Product ID Low and High Byte Registers
The eZ80 Product ID Low and High Byte registers combine to provide a means for an
external device to determine the particular eZ80 product being addressed. For the
eZ80L92, these two bytes, {ZDI_ID_H, ZDI_ID_L} return the value {00h, 06h}. See
Tables 100 and 101.
Bit
Position Value Description
[7:0]
zdi_wr_mem
00h–FFh The 8-bit data that is transferred to the ZDI slave
following a Write to this address is written to the address
indicated by the current program counter. The program
counter is incremented following each 8 bits of data. In
Z80 MEMORY mode, ({MBASE, PC[15:0]}) ← 8 bits of
transferred data. In ADL MEMORY mode, (PC[23:0]) ←
8 bits of transferred data.
Table 100. eZ80® Product ID Low Byte Register (ZDI_ID_L = 00h in the ZDI
Register Read-Only Address Space)
Bit 76543210
Reset 00000110
CPU Access RRRRRRRR
Note: R = Read-only.
Bit
Position Value Description
[7:0]
zdi_id_l
06h {ZDI_ID_H, ZDI_ID_L} = {00h, 06h} indicates the eZ80L92
product.
Table 101. eZ80® Product ID High Byte Register (ZDI_ID_H = 01h in the ZDI
Register Read-Only Address Space)
Bit 76543210
Reset 00000000
CPU Access RRRRRRRR
Note: R = Read-only.
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eZ80® Product ID Revision Register
The eZ80 Product ID Revision register identifies the current revision of the eZ80L92
product. See Table 102.
ZDI Status Register
The ZDI Status register provides current information about the eZ80L92 and the eZ80
CPU. See Table 103.
Bit
Position Value Description
[7:0]
zdi_id_H
00h {ZDI_ID_H, ZDI_ID_L} = {00h, 06h} indicates the eZ80L92
product.
Table 102. eZ80® Product ID Revision Register (ZDI_ID_REV = 02h in the ZDI
Register Read-Only Address Space)
Bit 76543210
Reset XXXXXXXX
CPU Access RRRRRRRR
Note: X = Undetermined; R = Read-only.
Bit
Position Value Description
[7:0]
zdi_id_rev
00h–FFh Identifies the current revision of the eZ80L92 product.
Table 103. ZDI Status Register (ZDI_STAT = 03h in the ZDI Register Read-
Only Address Space)
Bit 76543210
Reset 00000000
CPU Access RRRRRRRR
Note: R = Read-only.
PS013014-0107 ZiLOG Debug Interface
eZ80L92 MCU
Product Specification
180
ZDI Read Registers—Low, High, and Upper
The ZDI register Read-Only address space offers Low, High, and Upper functions, which
contain the value read by a Read operation from the ZDI Read/Write Control register
(ZDI_RW_CTL). This data is valid only while in ZDI BREAK mode and only if the
instruction is read by a request from the ZDI Read/Write Control register. See Table 104.
Bit
Position Value Description
7
zdi_active
0 The CPU is not functioning in ZDI mode.
1 The CPU is currently functioning in ZDI mode.
6 0 Reserved.
5
halt_SLP
0 eZ80L92 is not currently in HALT or SLEEP mode.
1 eZ80L92 is currently in HALT or SLEEP mode.
4
ADL
0 The CPU is operating in Z80 MEMORY mode.
(ADL bit = 0).
1 The CPU is operating in ADL MEMORY mode.
(ADL bit = 1).
3
MADL
0 The CPU’s Mixed-Memory mode (MADL) bit is reset to 0.
1 The CPU’s Mixed-Memory mode (MADL) bit is set to 1.
2
IEF1
0 The CPU’s Interrupt Enable Flag 1 is reset to 0. Maskable
interrupts are disabled.
1 The CPU’s Interrupt Enable Flag 1 is set to 1. Maskable
interrupts are enabled.
[1:0]
Reserved
00 Reserved.
Table 104. ZDI Read Registers—Low, High and Upper (ZDI_RD_L = 10h,
ZDI_RD_H = 11h, and ZDI_RD_U = 12h in the ZDI Register Read-Only
Address Space)
Bit 76543210
Reset 00000000
CPU Access RRRRRRRR
Note: R = Read-only.
PS013014-0107 ZiLOG Debug Interface
eZ80L92 MCU
Product Specification
181
ZDI Bus Status Register
The ZDI Bus Status register monitors BUSACKs during DEBUG mode. See Table 105.
Bit
Position Value Description
[7:0]
ZDI_RD_L,
ZDI_RD_H,
or
ZDI_RD_U
00h–FFh Values read from the memory location as requested by
the ZDI Read Control register during a ZDI Read
operation. The 24-bit value is supplied by {ZDI_RD_U,
ZDI_RD_H, ZDI_RD_L}.
Table 105. ZDI Bus Control Register (ZDI_BUS_STAT = 17h in the ZDI
Register Read-Only Address Space)
Bit 76543210
Reset 00000000
CPU Access RRRRRRRR
Note: R = Read-only.
Bit
Position Value Description
7
ZDI_BUSAcK_En
0 Bus requests by external peripherals using the
BUSREQ pin are ignored. The bus acknowledge signal,
BUSACK, is not asserted.
1 Bus requests by external peripherals using the
BUSREQ pin are accepted. A bus acknowledge occurs
at the end of the current ZDI operation. The bus
acknowledge is indicated by asserting the BUSACK pin.
6
ZDI_BUS_STAT
0 Address and data buses are not relinquished to an
external peripheral. bus acknowledge is deasserted
(BUSACK pin is High).
1 Address and data buses are relinquished to an external
peripheral. bus acknowledge is asserted (BUSACK pin
is Low).
[5:0] 000000 Reserved.
PS013014-0107 ZiLOG Debug Interface
eZ80L92 MCU
Product Specification
182
ZDI Read Memory Register
When a Read is executed from the ZDI Read Memory register, the
eZ80L92
fetches the
data from the memory address currently pointed to by the program counter, PC; the pro-
gram counter is then incremented. In Z80 MEMORY mode, the memory address is
{MBASE, PC[15:0]}. In ADL MEMORY mode, the memory address is PC[23:0]. Refer
to the eZ80® CPU User Manual (UM0077) for more information regarding Z80 and ADL
MEMORY modes.
The program counter, PC, increments after each data Read. However, the ZDI register
address does not increment automatically when this register is accessed. As a result, the
ZDI master can read any number of data bytes out of memory through the ZDI Read
Memory register. See Table 106.
Table 106. ZDI Read Memory Register (ZDI_RD_MEM = 20h in the ZDI
Register Read-Only Address Space)
Bit 76543210
Reset 00000000
CPU Access RRRRRRRR
Note: R = Read-only.
Bit
Position Value Description
[7:0]
zdi_rd_mem
00h–FFh 8-bit data read from the memory address indicated by
the CPU’s program counter. In Z80 MEMORY mode,
8-bit data is transferred out from address {MBASE,
PC[15:0]}. In ADL Memory mode, 8-bit data is
transferred out from address PC[23:0].
PS013014-0107 On-Chip Instrumentation
eZ80L92 MCU
Product Specification
183
On-Chip Instrumentation
On-Chip Instrumentation1 (OCI™) for the ZiLOG eZ80 CPU core enables powerful
debugging features. The OCI provides run control, memory and register visibility, com-
plex breakpoints, and trace history features.
The OCI employs all the functions of the ZiLOG Debug Interface (ZDI) as described in
the ZDI section. It also adds the following debug features:
•
Control through a 4-pin JTAG port that conforms to IEEE Standard 1149.1 (Test Ac-
cess Port and Boundary-Scan Architecture)2.
•
Complex break-point trigger functions.
•
Break-point enhancements, such as the ability to:
–
Define two break-point addresses that form a range.
–
Break on masked data values.
–
Start or stop trace.
–
Assert a trigger output signal.
•
Trace history buffer.
•
Software break-point instruction.
OCI has the following sections:
1. JTAG interface.
2. ZDI debug control.
3. Trace buffer memory.
4. Complex triggers.
OCI Activation
The OCI features clock initialization circuitry so that external debug hardware can be
detected during power up. The external debugger must drive the OCI clock pin (TCK)
Low at least two system clock cycles prior to the end of the RESET to activate the OCI
block. If TCK is High at the end of the RESET, the OCI block shuts down so that it does
not draw power in normal product operation. When the OCI is shut down, ZDI is enabled
directly and can be accessed through the clock (TCK) and data (TDI) pins. For more infor-
mation on ZDI, see ZiLOG Debug Interface on page 160.
1. On-Chip Instrumentation and OCI are trademarks of First Silicon Solutions, Inc.
2. The eZ80L92 MCU does not contain the boundary scan register required for 1149.1 compliance.
PS013014-0107 On-Chip Instrumentation
eZ80L92 MCU
Product Specification
184
OCI Interface
There are five dedicated pins on the eZ80L92 MCU for the OCI interface. Four pins
(TCK, TMS, TDI, and TDO) are required for IEEE Standard 1149.1-compatible JTAG
ports. The TRIGOUT pin provides additional testability features. Table 107 lists these five
OCI pins.
Table 107. OCI Pins
Symbol Name Type Description
TCK Clock. Input Asynchronous to the primary eZ80L92 system clock.
The TCK period but must be at least twice the system
clock period. During RESET, this pin is sampled to
select either OCI or ZDI DEBUG modes. If Low
during RESET, the OCI is enabled. If High during
RESET, the OCI is powered down and ZDI DEBUG
mode is enabled. When ZDI DEBUG mode is active,
this pin is the ZDI clock. On-chip pull-up ensures a
default value of 1 (High).
TMS Test Mode Select Input This serial test mode input controls JTAG mode
selection. On-chip pull-up ensures a default value of
1 (High). The TMS signal is sampled on the rising
edge of the TCK signal.
TDI Data In Input
(OCI enabled)
Serial test data input. On-chip pull-up ensures a
default value of 1 (High). This pin is input-only when
the OCI is enabled. The input data is sampled on the
rising edge of the TCK signal.
I/O
(OCI disabled)
When the OCI is disabled, this pin functions as the
ZDA (ZDI Data) I/O pin.
TDO Data Out Output The output data changes on the falling edge of the
TCK signal.
TRIGOUT Trigger Output Output Generates an active High trigger pulse when valid
OCI trigger events occur. Output is tristate when no
data is being driven out.
PS013014-0107 On-Chip Instrumentation
eZ80L92 MCU
Product Specification
185
OCI Information Requests
For additional information regarding On-Chip Instrumentation, or to order OCI debug
tools, please contact:
First Silicon Solutions, Inc.
5440 SW Westgate Drive, Suite 240
Portland, OR 97221
Phone: (503) 292-6730
Fax: (503) 292-5840
www.fs2.com
PS013014-0107 eZ80® CPU Instruction Set
eZ80L92 MCU
Product Specification
186
eZ80® CPU Instruction Set
Table 108 through Table 108 indicate the eZ80 CPU instructions available for use with the
eZ80L92 MCU. The instructions are grouped by class. A detailed information is available
in the eZ80 CPU User Manual.
Table 108. Arithmetic Instructions
Mnemonic Instruction
ADC Add with Carry
ADD Add without Carry
CP Compare with Accumulator
DAA Decimal Adjust Accumulator
DEC Decrement
INC Increment
MLT Multiply
NEG Negate Accumulator
SBC Subtract with Carry
SUB Subtract without Carry
Table 108. Bit Manipulation Instructions
Mnemonic Instruction
BIT Bit Test
RES Reset Bit
SET Set Bit
Table 108. Block Transfer and Compare Instructions
Mnemonic Instruction
CPD (CPDR) Compare and Decrement (with Repeat)
CPI (CPIR) Compare and Increment (with Repeat)
PS013014-0107 eZ80® CPU Instruction Set
eZ80L92 MCU
Product Specification
187
LDD (LDDR) Load and Decrement (with Repeat)
LDI (LDIR) Load and Increment (with Repeat)
Table 108. Exchange Instructions
Mnemonic Instruction
EX Exchange registers
EXX Exchange CPU Multibyte register banks
Table 108. Input/Output Instructions
Mnemonic Instruction
IN Input from I/O
IN0 Input from I/O on Page 0
IND (INDR) Input from I/O and Decrement (with Repeat)
INDRX Input from I/O and Decrement Memory Address
with Stationary I/O Address
IND2 (IND2R) Input from I/O and Decrement (with Repeat)
INDM (INDMR) Input from I/O and Decrement (with Repeat)
INI (INIR) Input from I/O and Increment (with Repeat)
INIRX Input from I/O and Increment Memory Address
with Stationary I/O Address
INI2 (INI2R) Input from I/O and Increment (with Repeat)
INIM (INIMR) Input from I/O and Increment (with Repeat)
OTDM (OTDMR) Output to I/O and Decrement (with Repeat)
OTDRX Output to I/O and Decrement Memory Address
with Stationary I/O Address
OTIM (OTIMR) Output to I/O and Increment (with Repeat)
OTIRX Output to I/O and Increment Memory Address
with Stationary I/O Address
OUT Output to I/O
Table 108. Block Transfer and Compare Instructions
Mnemonic Instruction
PS013014-0107 eZ80® CPU Instruction Set
eZ80L92 MCU
Product Specification
188
OUT0 Output to I/O on Page 0
OUTD (OTDR) Output to I/O and Decrement (with Repeat)
OUTD2 (OTD2R) Output to I/O and Decrement (with Repeat)
OUTI (OTIR) Output to I/O and Increment (with Repeat)
OUTI2 (OTI2R) Output to I/O and Increment (with Repeat)
TSTIO Test I/O
Table 108. Load Instructions
Mnemonic Instruction
LD Load
LEA Load Effective Address
PEA Push Effective Address
POP Pop
PUSH Push
Table 108. Logical Instructions
Mnemonic Instruction
AND Logical AND
CPL Complement Accumulator
OR Logical OR
TST Test Accumulator
XOR Logical Exclusive OR
Table 108. Processor Control Instructions
Mnemonic Instruction
CCF Complement Carry Flag
DI Disable Interrupts
Table 108. Input/Output Instructions
Mnemonic Instruction
PS013014-0107 eZ80® CPU Instruction Set
eZ80L92 MCU
Product Specification
189
EI Enable Interrupts
HALT Halt
IM Interrupt Mode
NOP No Operation
RSMIX Reset Mixed-Memory Mode Flag
SCF Set Carry Flag
SLP Sleep
STMIX Set Mixed-Memory Mode Flag
Table 108. Program Control Instructions
Mnemonic Instruction
CALL Call Subroutine
CALL cc Conditional Call Subroutine
DJNZ Decrement and Jump if Nonzero
JP Jump
JP cc Conditional Jump
JR Jump Relative
JR cc Conditional Jump Relative
RET Return
RET cc Conditional Return
RETI Return from Interrupt
RETN Return from Nonmaskable interrupt
RST Restart
Table 108. Rotate and Shift Instructions
Mnemonic Instruction
RL Rotate Left
RLA Rotate Left–Accumulator
Table 108. Processor Control Instructions
Mnemonic Instruction
PS013014-0107 eZ80® CPU Instruction Set
eZ80L92 MCU
Product Specification
190
RLC Rotate Left Circular
RLCA Rotate Left Circular–Accumulator
RLD Rotate Left Decimal
RR Rotate Right
RRA Rotate Right–Accumulator
RRC Rotate Right Circular
RRCA Rotate Right Circular–Accumulator
RRD Rotate Right Decimal
SLA Shift Left Arithmetic
SRA Shift Right Arithmetic
SRL Shift Right Logical
Table 108. Rotate and Shift Instructions
Mnemonic Instruction
PS013014-0107 Opcode Map
eZ80L92 MCU
Product Specification
191
Opcode Map
Table 109 through Table 115 indicate the hex values for the eZ80 instructions.
Table 109. Opcode Map—First Opcode
Lower Nibble (Hex)
0123456789ABCDEF
Upper Nibble (Hex)
0NOP
LD
BC,
Mmn
LD
(BC),A
INC
BC
INC
B
DEC
B
LD
B,n RLCA EX
AF,AF’
ADD
HL,BC
LD
A,(BC)
DEC
BC
INC
C
DEC
C
LD
C,n RRCA
1DJNZ
d
LD
DE,
Mmn
LD
(DE),A
INC
DE
INC
D
DEC
D
LD
D,n RLA JR
d
ADD
HL,DE
LD
A,(DE)
DEC
DE
INC
E
DEC
E
LD
E,n RRA
2JR
NZ,d
LD
HL,
Mmn
LD
(Mmn),
HL
INC
HL
INC
H
DEC
H
LD
H,n DAA JR
Z,d
ADD
HL,HL
LD
HL,
(Mmn)
DEC
HL
INC
L
DEC
L
LD
L,n CPL
3JR
NC,d
LD
SP,
Mmn
LD
(Mmn),
A
INC
SP
INC
(HL)
DEC
(HL)
LD
(HL),n SCF JR
CF,d
ADD
HL,SP
LD
A,
(Mmn)
DEC
SP
INC
A
DEC
A
LD
A,n CCF
4.SIS
suffix
LD
B,C
LD
B,D
LD
B,E
LD
B,H
LD
B,L
LD
B,(HL)
LD
B,A
LD
C,B
.LIS
suffix
LD
C,D
LD
C,E
LD
C,H
LD
C,L
LD
C,(HL)
LD
C,A
5LD
D,B
LD
D,C
.SIL
suffix
LD
D,E
LD
D,H
LD
D,L
LD
D,(HL)
LD
D,A
LD
E,B
LD
E,C
LD
E,D
.LIL
suffix
LD
E,H
LD
E,L
LD
E,(HL)
LD
E,A
6LD
H,B
LD
H,C
LD
H,D
LD
H,E
LD
H,H
LD
H,L
LD
H,(HL)
LD
H,A
LD
L,B
LD
L,C
LD
L,D
LD
L,E
LD
L,H
LD
L,L
LD
L,(HL)
LD
L,A
7LD
(HL),B
LD
(HL),C
LD
(HL),D
LD
(HL),E
LD
(HL),H
LD
(HL),L HALT LD
(HL),A
LD
A,B
LD
A,C
LD
A,D
LD
A,E
LD
A,H
LD
A,L
LD
A,(HL)
LD
A,A
8ADD
A,B
ADD
A,C
ADD
A,D
ADD
A,E
ADD
A,H
ADD
A,L
ADD
A,(HL)
ADD
A,A
ADC
A,B
ADC
A,C
ADC
A,D
ADC
A,E
ADC
A,H
ADC
A,L
ADC
A,(HL)
ADC
A,A
9SUB
A,B
SUB
A,C
SUB
A,D
SUB
A,E
SUB
A,H
SUB
A,L
SUB
A,(HL)
SUB
A,A
SBC
A,B
SBC
A,C
SBC
A,D
SBC
A,E
SBC
A,H
SBC
A,L
SBC
A,(HL)
SBC
A,A
AAND
A,B
AND
A,C
AND
A,D
AND
A,E
AND
A,H
AND
A,L
AND
A,(HL)
AND
A,A
XOR
A,B
XOR
A,C
XOR
A,D
XOR
A,E
XOR
A,H
XOR
A,L
XOR
A,(HL)
XOR
A,A
BOR
A,B
OR
A,C
OR
A,D
OR
A,E
OR
A,H
OR
A,L
OR
A,(HL)
OR
A,A
CP
A,B
CP
A,C
CP
A,D
CP
A,E
CP
A,H
CP
A,L
CP
A,(HL)
CP
A,A
CRET
NZ
POP
BC
JP
NZ,
Mmn
JP
Mmn
CALL
NZ,
Mmn
PUSH
BC
ADD
A,n
RST
00h
RET
ZRET
JP
Z,
Mmn
Table
110
CALL
Z,
Mmn
CALL
Mmn
ADC
A,n
RST
08h
DRET
NC
POP
DE
JP
NC,
Mmn
OUT
(n),A
CALL
NC,
Mmn
PUSH
DE
SUB
A,n
RST
10h
RET
CF EXX
JP
CF,
Mmn
IN
A,(n)
CALL
CF,
Mmn
Table
111
SBC
A,n
RST
18h
ERET
PO
POP
HL
JP
PO,
Mmn
EX
(SP),HL
CALL
PO,
Mmn
PUSH
HL
AND
A,n
RST
20h
RET
PE
JP
(HL)
JP
PE,
Mmn
EX
DE,HL
CALL
PE,
Mmn
Table
112
XOR
A,n
RST
28h
FRET
P
POP
AF
JP
P,
Mmn
DI
CALL
P,
Mmn
PUSH
AF
OR
A,n
RST
30h
RET
M
LD
SP,HL
JP
M,
Mmn
EI
CALL
M,
Mmn
Table
113
CP
A,n
RST
38h
Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.
AND
4
A
Lower opcode Nibble
Mnemonic
Second Operand
Upper
opcode
Nibble
First Operand
A,H
Legend
PS013014-0107 Opcode Map
eZ80L92 MCU
Product Specification
192
Table 110. Opcode Map—Second Opcode after 0CBh
Lower Nibble (Hex)
0123456789ABCDEF
Upper Nibble (Hex)
0RLC
B
RLC
C
RLC
D
RLC
E
RLC
H
RLC
L
RLC
(HL)
RLC
A
RRC
B
RRC
C
RRC
D
RRC
E
RRC
H
RRC
L
RRC
(HL)
RRC
A
1RL
B
RL
C
RL
D
RL
E
RL
H
RL
L
RL
(HL)
RL
A
RR
B
RR
C
RR
D
RR
E
RR
H
RR
L
RR
(HL)
RR
A
2SLA
B
SLA
C
SLA
D
SLA
E
SLA
H
SLA
L
SLA
(HL)
SLA
A
SRA
B
SRA
C
SRA
D
SRA
E
SRA
H
SRA
L
SRA
(HL)
SRA
A
3SRL
B
SRL
C
SRL
D
SRL
E
SRL
H
SRL
L
SRL
(HL)
SRL
A
4BIT
0,B
BIT
0,C
BIT
0,D
BIT
0,E
BIT
0,H
BIT
0,L
BIT
0,(HL)
BIT
0,A
BIT
1,B
BIT
1,C
BIT
1,D
BIT
1,E
BIT
1,H
BIT
1,L
BIT
1,(HL)
BIT
1,A
5BIT
2,B
BIT
2,C
BIT
2,D
BIT
2,E
BIT
2,H
BIT
2,L
BIT
2,(HL)
BIT
2,A
BIT
3,B
BIT
3,C
BIT
3,D
BIT
3,E
BIT
3,H
BIT
3,L
BIT
3,(HL)
BIT
3,A
6BIT
4,B
BIT
4,C
BIT
4,D
BIT
4,E
BIT
4,H
BIT
4,L
BIT
4,(HL)
BIT
4,A
BIT
5,B
BIT
5,C
BIT
5,D
BIT
5,E
BIT
5,H
BIT
5,L
BIT
5,(HL)
BIT
5,A
7BIT
6,B
BIT
6,C
BIT
6,D
BIT
6,E
BIT
6,H
BIT
6,L
BIT
6,(HL)
BIT
6,A
BIT
7,B
BIT
7,C
BIT
7,D
BIT
7,E
BIT
7,H
BIT
7,L
BIT
7,(HL)
BIT
7,A
8RES
0,B
RES
0,C
RES
0,D
RES
0,E
RES
0,H
RES
0,L
RES
0,(HL)
RES
0,A
RES
1,B
RES
1,C
RES
1,D
RES
1,E
RES
1,H
RES
1,L
RES
1,(HL)
RES
1,A
9RES
2,B
RES
2,C
RES
2,D
RES
2,E
RES
2,H
RES
2,L
RES
2,(HL)
RES
2,A
RES
3,B
RES
3,C
RES
3,D
RES
3,E
RES
3,H
RES
3,L
RES
3,(HL)
RES
3,A
ARES
4,B
RES
4,C
RES
4,D
RES
4,E
RES
4,H
RES
4,L
RES
4,(HL)
RES
4,A
RES
5,B
RES
5,C
RES
5,D
RES
5,E
RES
5,H
RES
5,L
RES
5,(HL)
RES
5,A
BRES
6,B
RES
6,C
RES
6,D
RES
6,E
RES
6,H
RES
6,L
RES
6,(HL)
RES
6,A
RES
7,B
RES
7,C
RES
7,D
RES
7,E
RES
7,H
RES
7,L
RES
7,(HL)
RES
7,A
CSET
0,B
SET
0,C
SET
0,D
SET
0,E
SET
0,H
SET
0,L
SET
0,(HL)
SET
0,A
SET
1,B
SET
1,C
SET
1,D
SET
1,E
SET
1,H
SET
1,L
SET
1,(HL)
SET
1,A
DSET
2,B
SET
2,C
SET
2,D
SET
2,E
SET
2,H
SET
2,L
SET
2,(HL)
SET
2,A
SET
3,B
SET
3,C
SET
3,D
SET
3,E
SET
3,H
SET
3,L
SET
3,(HL)
SET
3,A
ESET
4,B
SET
4,C
SET
4,D
SET
4,E
SET
4,H
SET
4,L
SET
4,(HL)
SET
4,A
SET
5,B
SET
5,C
SET
5,D
SET
5,E
SET
5,H
SET
5,L
SET
5,(HL)
SET
5,A
FSET
6,B
SET
6,C
SET
6,D
SET
6,E
SET
6,H
SET
6,L
SET
6,(HL)
SET
6,A
SET
7,B
SET
7,C
SET
7,D
SET
7,E
SET
7,H
SET
7,L
SET
7,(HL)
SET
7,A
Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.
RES
4
A
Lower Nibble of 2nd cpcode
Mnemonic
Second Operand
Upper
cpcode
First Operand
4,H
of Second
Nibble
Legend
PS013014-0107 Opcode Map
eZ80L92 MCU
Product Specification
193
Table 111. Opcode Map—Second Opcode After 0DDh
Lower Nibble (Hex)
0123456789ABCDEF
Upper Nibble (Hex)
0LD BC,
(IX+d)
ADD
IX,BC
LD
(IX+d),
BC
1LD DE,
(IX+d)
ADD
IX,DE
LD
(IX+d),
DE
2
LD
IX,
Mmn
LD
(Mmn),
IX
INC
IX
INC
IXH
DEC
IXH
LD
IXH,n
LD HL,
(IX+d)
ADD
IX,IX
LD
IX,
(Mmn)
DEC
IX
INC
IXL
DEC
IXL
LD
IXL,n
LD
(IX+d),
HL
3LD IY,
(IX+d)
INC
(IX+d)
DEC
(IX+d)
LD (IX
+d),n
LD IX,
(IX+d)
ADD
IX,SP
LD
(IX+d),
IY
LD
(IX+d),
IX
4LD
B,IXH LD B,IXL LD B,
(IX+d)
LD
C,IXH LD C,IXL LD C,
(IX+d)
5LD
D,IXH LD D,IXL LD D,
(IX+d)
LD
E,IXH LD E,IXL LD E,
(IX+d)
6LD
IXH,B
LD
IXH,C
LD
IXH,D
LD
IXH,E
LD
IXH,IXH
LD
IXH,IXL
LD H,
(IX+d)
LD
IXH,A LD IXL,BLD IXL,CLD IXL,DLD IXL,E LD
IXL,IXH
LD
IXL,IXL
LD L,
(IX+d) LD IXL,A
7LD
(IX+d),B
LD
(IX+d),C
LD
(IX+d),D
LD
(IX+d),E
LD
(IX+d),H
LD
(IX+d),L
LD
(IX+d),A
LD
A,IXH LD A,IXL LD A,
(IX+d)
8ADD
A,IXH
ADD
A,IXL
ADD A,
(IX+d)
ADC
A,IXH
ADC
A,IXL
ADC A,
(IX+d)
9SUB
A,IXH
SUB
A,IXL
SUB A,
(IX+d)
SBC
A,IXH
SBC
A,IXL
SBC A,
(IX+d)
AAND
A,IXH
AND
A,IXL
AND A,
(IX+d)
XOR
A,IXH
XOR
A,IXL
XOR A,
(IX+d)
BOR
A,IXH
OR
A,IXL
OR A,
(IX+d)
CP
A,IXH
CP
A,IXL
CP A,
(IX+d)
CTable
114
D
EPOP
IX
EX
(SP),IX
PUSH
IX
JP
(IX)
FLD
SP,IX
Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.
LD
9
FMnemonic
Second Operand
First Operand
SP,IX
Lower Nibble of 2nd opcode
Upper
opcode
of Second
Nibble
Legend
PS013014-0107 Opcode Map
eZ80L92 MCU
Product Specification
194
Table 112. Opcode Map—Second Opcode After 0EDh
Lower Nibble (Hex)
0123456789ABCDEF
Upper Nibble (Hex)
0IN0
B,(n)
OUT0
(n),B
LEA BC,
IX+d
LEA BC,
IY+d
TST
A,B
LD BC,
(HL)
IN0
C,(n)
OUT0
(n),C
TST
A,C
LD (HL),
BC
1IN0
D,(n)
OUT0
(n),D
LEA DE,
IX+d
LEA DE,
IY+d
TST
A,D
LD DE,
(HL)
IN0
E,(n)
OUT0
(n),E
TST
A,E
LD(HL),
DE
2IN0
H,(n)
OUT0
(n),H
LEA HL
,IX+d
LEA HL
,IY+d
TST
A,H
LD HL,
(HL)
IN0
L,(n)
OUT0
(n),L
TST
A,L
LD (HL),
HL
3LD IY,
(HL)
LEA IX
,IX+d
LEA IY
,IY+d
TST
A,(HL)
LD IX,
(HL)
IN0
A,(n)
OUT0
(n),A
TST
A,A
LD
(HL),IY
LD (HL),
IX
4IN
B,(BC)
OUT
(BC),B
SBC
HL,BC
LD
(Mmn),
BC
NEG RETN IM 0 LD
I,A
IN
C,(C)
OUT
(C),C
ADC
HL,BC
LD
BC,
(Mmn)
MLT
BC RETI LD
R,A
5IN
D,(BC)
OUT
(BC),D
SBC
HL,DE
LD
(Mmn),
DE
LEA IX,
IY+d
LEA IY,
IX+d IM 1 LD
A,I
IN
E,(C)
OUT
(C),E
ADC
HL,DE
LD
DE,
(Mmn)
MLT
DE IM 2 LD
A,R
6IBN
H,(C)
OUT
(BC),H
SBC
HL,HL
LD
(Mmn),
HL
TST
A,n
PEA
IX+d
PEA
IY+d RRD IN
L,(C)
OUT
(C),L
ADC
HL,HL
LD
HL,
(Mmn)
MLT
HL
LD
MB,A
LD
A,MB RLD
7SBC
HL,SP
LD
(Mmn),
SP
TSTIO
nSLP IN
A,(C)
OUT
(C),A
ADC
HL,SP
LD
SP,
(Mmn)
MLT
SP STMIX RSMIX
8 INIM OTIM INI2 INDM OTDM IND2
9 INIMR OTIMR INI2R INDMR OTDMR IND2R
A LDI CPI INI OUTI OUTI2 LDD CPD IND OUTD OUTD2
B LDIR CPIR INIR OTIR OTI2R LDDR CPDR INDR OTDR OTD2R
C INIRX OTIRX INDRX OTDRX
D
E
F
Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement
SBC
2
4Mnemonic
Second Operand
First Operand
HL,BC
Lower Nibble of 2nd opcode
Upper
opcode
of Second
Nibble
Legend
PS013014-0107 Opcode Map
eZ80L92 MCU
Product Specification
195
Table 113. Opcode Map—Second Opcode After 0FDh
Lower Nibble (Hex)
0123456789ABCDEF
Upper Nibble (Hex)
0LD BC,
(IY+d)
ADD
IY,BC
LD (IY
+d),BC
1LD DE,
(IY+d)
ADD
IY,DE
LD (IY
+d),DE
2LD
IY,Mmn
LD
(Mmn),I
Y
INC
IY
INC
IYH
DEC
IYH
LD
IYH,n
LD HL,
(IY+d)
ADD
IY,IY
LD
IY,
(Mmn)
DEC
IY
INC
IYL
DEC
IYL
LD
IYL,n
LD (IY
+d),HL
3LD IX,
(IY+d)
INC
(IY+d)
DEC
(IY+d)
LD (IY
+d),n
LD IY,
(IY+d)
ADD
IY,SP
LD (IY
+d),IX
LD (IY
+d),IY
4LD
B,IYH LD B,IYL LD B,
(IY+d)
LD
C,IYH
LD
C,IYL
LD C,
(IY+d)
5LD
D,IYH
LD
D,IYL
LD D,
(IY+d)
LD
E,IYH LD E,IYL LD E,
(IY+d)
6LD
IYH,B
LD
IYH,C
LD
IYH,D
LD
IYH,E
LD
IYH,IYH
LD
IYH,IYL
LD H,
(IY+d)
LD
IYH,A LD IYL,B LD
IYL,C
LD
IYL,D LD IYL,E LD
IYL,IYH
LD
IYL,IYL
LD L,
(IY+d) LD IYL,A
7LD (IY
+d),B
LD (IY
+d),C
LD (IY
+d),D
LD (IY
+d),E
LD (IY
+d),H
LD (IY
+d),L
LD (IY
+d),A
LD
A,IYH LD A,IYL LD A,
(IY+d)
8ADD
A,IYH
ADD
A,IYL
ADD A,
(IY+d)
ADC
A,IYH
ADC
A,IYL
ADC A,
(IY+d)
9SUB
A,IYH
SUB
A,IYL
SUB A,
(IY+d)
SBC
A,IYH
SBC
A,IYL
SBC A,
(IY+d)
AAND
A,IYH
AND
A,IYL
AND A,
(IY+d)
XOR
A,IYH
XOR
A,IYL
XOR A,
(IY+d)
BOR
A,IYH
OR
A,IYL
OR A,
(IY+d)
CP
A,IYH
CP
A,IYL
CP A,
(IY+d)
CTable
115
D
EPOP
IY
EX
(SP),IY
PUSH
IY
JP
(IY)
FLD
SP,IY
Notes: n = 8-bit data; Mmn = 16- or 24-bit addr or data; d = 8-bit two’s-complement displacement.
LD
9
FMnemonic
Second Operand
First Operand
SP,IY
Lower Nibble of 2nd opcode
Upper
opcode
of Second
Nibble
Legend
PS013014-0107 Opcode Map
eZ80L92 MCU
Product Specification
196
Table 114. Opcode Map—Fourth Byte After 0DDh, 0CBh, and dd
Lower Nibble (Hex)
0123456789ABCDEF
Upper Nibble (Hex)
0RLC
(IX+d)
RRC
(IX+d)
1RL
(IX+d)
RR
(IX+d)
2SLA
(IX+d)
SRA
(IX+d)
3SRL
(IX+d)
4BIT 0,
(IX+d)
BIT 1,
(IX+d)
5BIT 2,
(IX+d)
BIT 3,
(IX+d)
6BIT 4,
(IX+d)
BIT 5,
(IX+d)
7BIT 6,
(IX+d)
BIT 7,
(IX+d)
8RES 0,
(IX+d)
RES 1,
(IX+d)
9RES 2,
(IX+d)
RES 3,
(IX+d)
ARES 4,
(IX+d)
RES 5,
(IX+d)
BRES 6,
(IX+d)
RES 7,
(IX+d)
CSET 0,
(IX+d)
SET 1,
(IX+d)
DSET 2,
(IX+d)
SET 3,
(IX+d)
ESET 4,
(IX+d)
SET 5,
(IX+d)
FSET 6,
(IX+d)
SET 7,
(IX+d)
Notes: d = 8-bit two’s-complement displacement.
BIT
6
4
Lower Nibble of 4th Byte
Mnemonic
Second Operand
Upper
Byte
First Operand
0,(IX+d)
of Fourth
Nibble
Legend
PS013014-0107 Opcode Map
eZ80L92 MCU
Product Specification
197
Table 115. Opcode Map—Fourth Byte After 0FDh, 0CBh, and dd*
Lower Nibble (Hex)
0123456789ABCDEF
Upper Nibble (Hex)
0RLC
(IY+d)
RRC
(IY+d)
1RL
(IY+d)
RR
(IY+d)
2SLA
(IY+d)
SRA
(IY+d)
3SRL
(IY+d)
4BIT 0,
(IY+d)
BIT 1,
(IY+d)
5BIT 2,
(IY+d)
BIT 3,
(IY+d)
6BIT 4,
(IY+d)
BIT 5,
(IY+d)
7BIT 6,
(IY+d)
BIT 7,
(IY+d)
8RES 0,
(IY+d)
RES 1,
(IY+d)
9RES 2,
(IY+d)
RES 3,
(IY+d)
ARES 4,
(IY+d)
RES 5,
(IY+d)
BRES 6,
(IY+d)
RES 7,
(IY+d)
CSET 0,
(IY+d)
SET 1,
(IY+d)
DSET 2,
(IY+d)
SET 3,
(IY+d)
ESET 4,
(IY+d)
SET 5,
(IY+d)
FSET 6,
(IY+d)
SET 7,
(IY+d)
Notes: d = 8-bit two’s-complement displacement.
BIT
6
4
Lower Nibble of 4th Byte
Mnemonic
Second Operand
Upper
Byte
First Operand
0,(IY+d)
of Fourth
Nibble
Legend
PS013014-0107 On-Chip Oscillators
eZ80L92 MCU
Product Specification
198
On-Chip Oscillators
The eZ80L92 MCU features two on-chip oscillators for use with an external crystal.
The primary oscillator generates the system clock for the internal CPU and for the major-
ity of the on-chip peripherals. Alternatively, the XIN input pin can accept a CMOS-level
clock input signal. If an external clock generator is used, the XOUT pin must be left
disconnected. The secondary oscillator can drive a 32 kHz crystal to generate the
time-base for the real time clock.
20 MHz Primary Crystal Oscillator Operation
Figure 44 illustrates a recommended configuration for connection with an external
20 MHz, fundamental-mode, and parallel-resonant crystal. Table 116 lists recommended
crystal specifications. Resistor R1 limits total power dissipation by the crystal. Printed
circuit board layout must add not more than 4 pF of stray capacitance to either the XIN or
XOUT pins. If oscillation does not occur, reduce the values of capacitors C1 and C2 to
decrease loading.
Figure 44. Recommended Crystal Oscillator Configuration (20 MHz operation)
X
C = 22 pF
IN XOUT
2
R = 220 ‰
1
R = 100 K‰
2
C = 22 pF
2
20 MHz Crystal
(Fundamental Mode)
On-Chip Oscillator
PS013014-0107 On-Chip Oscillators
eZ80L92 MCU
Product Specification
199
32 kHz Real Time Clock Crystal Oscillator Operation
Figure 45 illustrates a recommended configuration for connecting the real time clock
oscillator with an external 32 kHz, fundamental-mode, parallel-resonant crystal. Table 117
lists the recommended crystal specifications. A printed circuit board layout must add no
more than 4 pF of stray capacitance to either the RTC_XIN or RTC_XOUT pins. If oscilla-
tion does not occur, reduce the values of capacitors C1 and C2 to decrease loading.
An on-chip MOS resistor sets the crystal drive current limit. This configuration does not
requires an external bias resistor across the crystal. An on-chip MOS resistor provides the
biasing.
Table 116. Recommended Crystal Oscillator Specifications
(20 MHz Operation)
Parameter Value Units Comments
Frequency 20 MHz
Resonance Parallel
Mode Fundamental
Series Resistance (RS)25
ΩMaximum
Load Capacitance (CL)20pFMaximum
Shunt Capacitance (C0) 7 pF Maximum
Drive Level 1 mW Maximum
Figure 45. Recommended Crystal Oscillator Configuration (32 kHz operation)
RTC_X
C = 18 pF
IN RTC_XOUT
2
R = 220 ‰
1
C = 18 pF
2
32 kHz Crystal
(Fundamental Mode)
On-Chip Oscillator
PS013014-0107 On-Chip Oscillators
eZ80L92 MCU
Product Specification
200
Table 117. Recommended Crystal Oscillator Specifications
(32 kHz Operation)
Parameter Value Units Comments
Frequency 32 kHz 32768 Hz
Resonance Parallel
Mode Fundamental
Series Resistance (RS)40 kΩMaximum
Load Capacitance (CL) 12.5 pF Maximum
Shunt Capacitance (C0) 3 pF Maximum
Drive Level 1 µW Maximum
PS013014-0107 Electrical Characteristics
eZ80L92 MCU
Product Specification
201
Electrical Characteristics
Absolute Maximum Ratings
A stress greater than listed in Table 118 may or may not cause permanent damage to the
device. Operation of the device at any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. For improved reliability,
unused inputs should be tied to one of the supply voltages (VDD or VSS).
DC Characteristics
Table 119 lists the DC characteristics of the eZ80L92 MCU. Figure 46 and Figure 47 plot
supply current values against CPU frequency and wait states.
Table 118. Absolute Maximum Ratings
Parameter
Min
Stress
Max
Stress Units Notes
Ambient temperature under bias (ºC) –40 +105 C 1
Storage temperature (ºC) –65 +150 C
Voltage on any pin with respect to VSS –0.3 +6.0 V 2
Voltage on VDD pin with respect to VSS –0.3 +6.0 V
Total power dissipation 520 mW
Maximum current out of VSS 145 mA
Maximum current into VDD 145 mA
Maximum current on input and/or inactive output pin –15 +15 µA
Maximum output current from active output pin –8 +8 mA
Notes:
1. Operating temperature is specified in DC Characteristics.
2. This voltage applies to all pins except where noted otherwise.
PS013014-0107 DC Characteristics
eZ80L92 MCU
Product Specification
202
Table 119. DC Characteristics
Symbol Parameter
TA =
0 ºC to 70 ºC
TA =
–40 ºC to 105 ºC
Units ConditionsMin Max Min Max
VDD Supply Voltage 3.0 3.6 3.0 3.6 V
VIL Low Level
Input Voltage
–0.3 0.8 –0.3 0.8 V
VIH High Level
Input Voltage
0.7 x VDD 5.5 0.7 x VDD 5.5 V
VOL Low Level
Output Voltage
0.4 0.4 V VDD = 3.0 V;
IOL = 1 mA
VOH High Level
Output Voltage
2.4 2.4 V VDD = 3.0 V;
IOH = –1 mA
IIL Input Leakage
Current
–10 +10 –10 +10 µA VDD = 3.6V;
VIN = VDD or VSS1
ITL Tristate Leakage
Current
–10 +10 –10 +10 µA VDD = 3.6 V
IDD Power Dissipation
(normal operation)
100 100 mA F = 20 MHz
145 145 mA F = 50 MHz
Power Dissipation
(HALT mode)
10 10 mA F = 20 MHz
20 20 mA F = 50 MHz
Power Dissipation
(SLEEP mode)
10 25 µA Internal clocks
stopped
RTC_VDD RTC Supply
Voltage
3.0 3.6 3.0 3.6 V
IRTC RTC Supply
Current
2.5
typical
10 2.5
typical
10 µA Supply current into
RTC_VDD
Notes:
1. This condition excludes all pins with on-chip pull-ups when driven Low.
PS013014-0107 AC Characteristics
eZ80L92 MCU
Product Specification
203
AC Characteristics
The section provides information on the AC characteristics and timing. All AC timing
information assumes a standard load of 50 pF on all outputs. See Table 120.
Figure 46. ICC vs. Frequency (Typical at 3.3 V, 25 ºC)
Figure 47. ICC vs. WAIT (Typical at 3.3 V, 25 ºC)
0
20
40
60
80
100
120
140
0 102030405060
0 WAIT
2 WAIT
7 WAIT
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
012345678
WAIT States
Curre nt ( mA )
10 MHz
20 MHz
30 MHz
40 MHZ
50 MHZ
Log. (10 MHz)
Log. (50 MHZ)
PS013014-0107 AC Characteristics
eZ80L92 MCU
Product Specification
204
Table 120. AC Characteristics
Symbol Parameter
TA =
0 ºC to 70 ºC
TA =
–40 ºC to 105 ºC
Units ConditionsMin Max Min Max
TXIN System Clock
Cycle Time
20 20 ns VDD = 3.0 – 3.6 V
TXINH System Clock
High Time
10 10 ns VDD = 3.0 – 3.6 V;
TCLK = 50 ns
TXINL System Clock
Low Time
10 10 ns VDD = 3.0 – 3.6 V;
TCLK = 50 ns
TXINR System Clock
Rise Time
33nsV
DD = 3.0 – 3.6 V;
TCLK = 50 ns
TXINF System Clock
Fall Time
33nsV
DD = 3.0 – 3.6 V;
TCLK = 50 ns
PS013014-0107 AC Characteristics
eZ80L92 MCU
Product Specification
205
External Memory Read Timing
Figure 48 and Table 121 illustrate the timing for external Reads.
Figure 48. External Memory Read Timing
Table 121. External Read Timing
Parameter Description
20 MHz (ns) 50 MHz (ns)
Min Max Min Max
T1Clock Rise to ADDR Valid Delay — 10.2 — 10.2
T2Clock Rise to ADDR Hold Time 2.4 — 2.4 —
T3Input DATA Valid to Clock Rise Setup Time 1.0 — 1.0 —
T4DATA Hold Time from Clock Rise 2.4 — 2.4 —
T5Clock Rise to CSx Assertion Delay 3.2 10.3 3.2 10.3
T6Clock Rise to CSx Deassertion Delay 2.9 9.7 2.9 9.7
T7Clock Rise to MREQ Assertion Delay 2.8 9.6 2.8 9.6
X
ADDR[23:0]
DATA[7:0]
(input)
CSx
MREQ
RD
IN
T1T2
T3T4
T8
T6
T10
T7
T5
T9
TCLK
PS013014-0107 AC Characteristics
eZ80L92 MCU
Product Specification
206
External Memory Write Timing
Figure 49 and Table 122 illustrate the timing for external Writes.
T8Clock Rise to MREQ Deassertion Delay 2.6 6.9 2.6 6.9
T9Clock Rise to RD Assertion Delay 3.0 9.8 3.0 9.8
T10 Clock Rise to RD Deassertion Delay 2.6 7.1 2.6 7.1
Figure 49. External Memory Write Timing
Table 121. External Read Timing (Continued)
Parameter Description
20 MHz (ns) 50 MHz (ns)
Min Max Min Max
X
ADDR[23:0]
DATA[7:0]
(output)
CSx
MREQ
WR
IN
T1T2
T3T4
T8
T6
T10
T7
T5
T9
TCLK
PS013014-0107 AC Characteristics
eZ80L92 MCU
Product Specification
207
Table 122. External Write Timing
Parameter Description
20 MHz (ns) 50 MHz (ns)
Min Max Min Max
T1Clock Rise to ADDR Valid Delay — 10.2 — 10.2
T2Clock Rise to ADDR Hold Time 2.4 — 2.4 —
T3Clock Fall to Output DATA Valid Delay — 6 — 6
T4DATA Hold Time from Clock Rise 2.4 — 2.4 —
T5Clock Rise to CSx Assertion Delay 3.2 10.3 3.2 10.3
T6Clock Rise to CSx Deassertion Delay 2.9 9.7 2.9 9.7
T7Clock Rise to MREQ Assertion Delay 2.8 9.6 2.8 9.6
T8Clock Rise to MREQ Deassertion Delay 2.6 6.9 2.6 6.9
T9Clock Fall to WR Assertion Delay 1.5 5.0 1.5 5.0
T10 Clock Rise to WR Deassertion Delay* 1.4 3.6 1.4 3.6
Note: *At the conclusion of a Write cycle, de-assertion of WR always occurs before any change to ADDR, DATA, CSx,
or MREQ. In certain applications, the de-assertion of WR can be concurrent with ADDR, DATA, CSx, or MREQ
when buffering is used off-chip.
PS013014-0107 AC Characteristics
eZ80L92 MCU
Product Specification
208
External I/O Read Timing
Figure 50 and Table 123 diagram the timing for external I/O Reads.
Figure 50. External I/O Read Timing
Table 123. External I/O Read Timing
Parameter Description
20 MHz (ns) 50 MHz (ns)
Min Max Min Max
T1Clock Rise to ADDR Valid Delay — 6.9 — 6.9
T2Clock Rise to ADDR Hold Time 2.2 — 2.2 —
T3Input DATA Valid to Clock Rise Setup Time 0.4 — 0.4 —
T4Clock Rise to DATA Hold Time 1.3 — 1.3 —
T5Clock Rise to CSx Assertion Delay 2.6 10.8 2.6 10.8
T6Clock Rise to CSx Deassertion Delay 2.4 8.8 2.4 8.8
T7Clock Rise to IORQ Assertion Delay 2.6 7.0 2.6 7.0
T8Clock Rise to IORQ Deassertion Delay 2.3 6.3 2.3 6.3
X
ADDR[23:0]
DATA[7:0]
(input)
CSx
IORQ
RD
IN
T1T2
T3T4
T8
T6
T10
T7
T5
T9
TCLK
PS013014-0107 AC Characteristics
eZ80L92 MCU
Product Specification
209
External I/O Write Timing
Figure 51 and Table 124 diagram the timing for external I/O Writes.
T9Clock Rise to RD Assertion Delay 2.7 7.0 2.7 7.0
T10 Clock Rise to RD Deassertion Delay 2.4 6.3 2.4 6.3
Figure 51. External I/O Write Timing
Table 123. External I/O Read Timing (Continued)
Parameter Description
20 MHz (ns) 50 MHz (ns)
Min Max Min Max
X
ADDR[23:0]
DATA[7:0]
(output)
CSx
IORQ
WR
IN
T1T2
T3T4
T8
T6
T10
T7
T5
T9
TCLK
PS013014-0107 AC Characteristics
eZ80L92 MCU
Product Specification
210
Table 124. External I/O Write Timing
Parameter Description
20 MHz (ns) 50 MHz (ns)
Min Max Min Max.
T1Clock Rise to ADDR Valid Delay — 7.7 — 7.7
T2Clock Rise to ADDR Hold Time 2.2 — 2.2 —
T3Clock Fall to Output DATA Valid Delay — 6 — 6
T4Clock Rise to DATA Hold Time 2.3 — 2.3 —
T5Clock Rise to CSx Assertion Delay 2.6 10.8 2.6 10.8
T6Clock Rise to CSx Deassertion Delay 2.4 8.8 2.4 8.8
T7Clock Rise to IORQ Assertion Delay 2.6 7.0 2.6 7.0
T8Clock Rise to IORQ Deassertion Delay 2.3 6.3 2.3 6.3
T9Clock Fall to WR Assertion Delay 1.8 4.5 1.8 4.5
T10 Clock Rise to WR Deassertion Delay* 1.6 4.4 1.6 4.4
WR Deassertion to ADDR Hold Time 0.4 — 0.4 —
WR Deassertion to DATA Hold Time 0.5 — 0.5 —
WR Deassertion to CSx Hold Time 1.2 — 1.2 —
WR Deassertion to IORQ Hold Time 0.5 — 0.5 —
Note: *At the conclusion of a Write cycle, deassertion of WR always occurs before any change to ADDR, DATA, CSx,
or IORQ. In certain applications, the deassertion of WR can be concurrent with ADDR, DATA, CSx, or MREQ
when buffering is used off-chip.
PS013014-0107 AC Characteristics
eZ80L92 MCU
Product Specification
211
Wait State Timing for Read Operations
Figure 52 illustrates the extension of the memory access signals using a single WAIT state
for a Read operation. This WAIT state is generated by setting CS_WAIT to 001 in the
Chip Select Control Register.
Figure 52. Wait State Timing for Read Operations
TCLK WAIT
TCSx_WAIT
X
ADDR[23:0]
DATA[7:0]
(input)
CSx
MREQ
RD
IN
INSTRD
T
PS013014-0107 AC Characteristics
eZ80L92 MCU
Product Specification
212
Wait State Timing for Write Operations
Figure 53 illustrates the extension of the memory access signals using a single WAIT state
for a Write operation. This WAIT state is generated by setting CS_WAIT to 001 in the
Chip Select Control Register.
Figure 53. Wait State Timing for Write Operations
TCLK TCLK
X
ADDR[23:0]
DATA[7:0]
(output)
CSx
MREQ
WR
IN
PS013014-0107 AC Characteristics
eZ80L92 MCU
Product Specification
213
General Purpose I/O Port Input Sample Timing
Figure 54 illustrates timing of the GPIO input sampling. The input value on a GPIO port
pin is sampled on the rising edge of the system clock. The port value is then available to
the CPU on the second rising clock edge following the change of the port value.
General Purpose I/O Port Output Timing
Figure 55 and Table 125 provide timing information for GPIO port pins.
Figure 54. Port Input Sample Timing
Figure 55. GPIO Port Output Timing
TCLK
System
Clock
GPIO Pin
Input Value
GPIO Input
Data Latch
GPIO Data
READ on Data Bus
Port Value
Changes to 0
0 Latched
Into GPIO
Data Register
GPIO Data Register
Value 0 Read
by eZ80
TCLK
EXTAL
Port Output
T1T2
PS013014-0107 AC Characteristics
eZ80L92 MCU
Product Specification
214
External Bus Acknowledge Timing
Table 126 provides information about the external bus acknowledge timing.
External System Clock Driver (PHI) Timing
Table 127 lists timing information for the PHI pin. The PHI pin allows external peripher-
als to synchronize with the internal system clock driver on the eZ80L92 MCU.
Table 125. GPIO Port Output Timing
Parameter Description
20 MHz (ns) 50 MHz (ns)
Min Max Min Max
T1Clock Rise to Port Output Valid Delay — 9.3 — 9.3
T2Clock Rise to Port Output Hold Time 2.0 — 2.0 —
Table 126. Bus Acknowledge Timing
Parameter Description
20 MHz (ns) 50 MHz (ns)
Min Max Min Max
T1Clock Rise to BUSACK Assertion Delay 2.8 9.3 2.8 9.3
T2Clock Rise to BUSACK Deassertion Delay 2.5 6.5 2.5 6.5
Table 127. PHI System Clock Timing
Parameter Description
20 MHz (ns) 50 MHz (ns)
Min Max Min Max
T1Clock Rise to PHI Rise 1.6 4.6 1.6 4.6
T2Clock Fall to PHI Fall 1.8 4.3 1.8 4.3
PS013014-0107 Ordering Information
eZ80L92 MCU
Product Specification
216
Ordering Information
Table 137 lists the product specification index code part number, part number and a brief
description of each eZ80L92 part.
For valuable information about customer and technical support as well as hardware and
software development tools, visit the ZiLOG web site at www.zilog.com. The latest
released version of ZDS can be downloaded from this site.
Part Number Description
ZiLOG part numbers consist of a number of components, as indicated in the following
example:
Table 137. Ordering Information
Part PSI Description
eZ80L92 eZ80L92AZ020SC,
eZ80L92AZ020SG
100-pin LQFP, 20 MHz, Standard Temperature
eZ80L92 eZ80L92AZ020EC,
eZ80L92AZ020EG
100-pin LQFP, 20 MHz, Extended Temperature
eZ80L92 eZ80L92AZ050SC,
eZ80L92AZ050SG
100-pin LQFP, 50 MHz, Standard Temperature
eZ80L92 eZ80L92AZ050EC,
eZ80L92AZ050EG
100-pin LQFP, 50 MHz, Extended Temperature
ZiLOG Base Products
eZ80 ZiLOG eZ80® CPU
L92 Product Number
AZ Package
050 Speed
S or E Temperature
C or G Environmental Flow
PS013014-0107 Ordering Information
eZ80L92 MCU
Product Specification
217
For example, part number eZ80L92AZ020SC is an eZ80® CPU product in the LQFP
package, operating with a 20 MHz external clock frequency over a 0 ºC to +70 ºC
temperature range, and built using the Plastic Standard environmental flow.
Package AZ = LQFP (also known as VQFP)
Speed 050 = 50 MHz
Standard Temperature S = 0 ºC to +70 ºC
Extended Temperature E = –40 ºC to +105 ºC
Environmental Flow C = Plastic Standard; G = Lead-Free
eZ80L92 MCU
Product Specification
PS013014-0107 Index
218
Index
Numerics
100-pin LQFP package
4, 21
20 MHz Primary Crystal Oscillator Operation
198
32 KHz Real-Time Clock Crystal Oscillator
Operation
199
A
Absolute Maximum Ratings
201
Absolute maximum ratings
201
AC Characteristics
203
ACK
141, 145, 146, 147, 148, 149, 151, 156
Acknowledge
141
ADDR0
5, 21
ADDR1
5, 21
ADDR10
6, 21
ADDR11
7, 21
ADDR12
7, 21
ADDR13
7, 21
ADDR14
7, 21
ADDR15
7, 21
ADDR16
8, 21
ADDR17
8, 21
ADDR18
8, 21
ADDR19
8, 21
ADDR2
5, 21
ADDR20
8, 22
ADDR21
9, 22
ADDR22
9, 22
ADDR23
9, 22
ADDR3
5, 21
ADDR4
5, 21
ADDR5
5, 21
ADDR6
6, 21
ADDR7
6, 21
ADDR8
6, 21
ADDR9
6, 21
Address Bus
5, 6, 7, 8, 9
address bus
45, 50, 53, 54, 56, 57, 58, 61, 64, 65,
68, 69, 90, 167, 176, 181
address bus, 24-bit
25
Addressing
151
Arbitration
143
Architectural Overview
1
asynchronous serial data
13, 15, 16
B
Baud Rate Generator
104, 108
Baud Rate Generator Functional Description
133
Block Diagram
3
BRG Control Registers
109
Bus Arbitration Overview
139
Bus Mode Controller
53
Bus Requests During ZDI Debug Mode
167
BUSACK
12, 23, 53, 167, 175, 181, 214
BUSREQ
12, 23, 53, 167, 176, 181
Byte Format
141
C
Characteristics, electrical
Absolute maximum ratings
201
Chip Select Registers
67
Chip Select x Bus Mode Control Register
71
Chip Select x Control Register
70
Chip Select x Lower Bound Register
67
Chip Select x Upper Bound Register
69
Chip Select/Wait State Generator block
5, 6, 7, 8, 9
Chip Selects and Wait States
48
Chip Selects During Bus Request/Bus
Acknowledge Cycles
53
Clear to Send
14, 16, 121
Clock Peripheral Power-Down Registers
35
eZ80L92 MCU
Product Specification
PS013014-0107 Index
219
Clock Synchronization
142
Clocking Overview
139
Continuous Mode
79
CPHA
129, 135
CPHA bit
132
CPOL
130, 135
CPOL bit
132
CS0
9, 22, 48, 49, 50, 51
CS1
9, 22, 48, 49, 50, 51
CS2
9, 22, 48, 50, 51
CS3
9, 22, 48, 50, 51
CTS
118, 121
CTS0
14, 125
CTS1
16
Customer Feedback Form
225
D
DATA bus
61
Data Bus
10
data bus
53, 56, 57, 58, 65, 71, 90, 167, 176, 181
Data Carrier Detect
15, 17, 121
Data Set Ready
14, 17, 121
Data Terminal Ready
14, 17, 118
Data Transfer Procedure with SPI configured as a
Slave
134
Data Transfer Procedure with SPI Configured as the
Master
133
data transfer, SPI
136
Data Validity
140
DATA0
10, 22
DATA1
10, 22
DATA2
10, 22
DATA3
10, 22
DATA4
10, 22
DATA5
10, 22
DATA6
10, 22
DATA7
10, 22
DC Characteristics
201
DCD
118, 121
DCD0
15, 125
DCD1
17
DCTS
121
DDCD
121
DDSR
121
DSR
118, 121
DSR0
14, 125
DSR1
17
DTACK
64, 65
DTR
118, 121
DTR0
14, 125
DTR1
17
E
Edge-Triggered Interrupts
41
EI, Op Code Map
191
Electrical Characteristics
201
Enabling and Disabling the WDT
74
Event Counter
81
External Bus Acknowledge Timing
214
External I/O Read Timing
208
External I/O Write Timing
209
External Memory Read Timing
205
External Memory Write Timing
206
External System Clock Driver (PHI) Timing
214
eZ80 CPU
33, 34, 51, 53, 57, 58, 64, 65, 123, 169,
183
eZ80 CPU Core
31
eZ80 Product ID Low and High Byte Registers
178
eZ80 Product ID Revision Register
179
eZ80 Webserver-i
1, 4, 5, 10, 11, 12, 20, 25, 33, 34,
38, 44, 45, 48, 50, 73, 77, 80, 107, 109, 151,
158, 161, 162, 163, 165, 166, 169, 172, 173,
176, 177, 178, 179, 182, 186, 201, 203, 214, 216
eZ80 Webserver-i Block Diagram
3
eZ80L92 MCU
3
F
f
21, 22, 54, 57
FAST mode
139, 158
Features
1
Features, eZ80 CPU Core
31
full-duplex transmission
131
Functional Description, Infrared Encoder/Decoder
123
eZ80L92 MCU
Product Specification
PS013014-0107 Index
220
G
General Purpose I/O Port Input Sample Timing
213
General Purpose I/O Port Output Timing
213
General-Purpose Input/Output
38
GND
2
GPIO Control Registers
42
GPIO Interrupts
41
GPIO Operation
38
H
HALT
12, 172, 180, 189
HALT instruction
34
HALT Mode
34
HALT mode
1, 35
HALT, Op-Code Map
191
I
I/O Chip Select Operation
50
I/O space
5, 6, 7, 8, 9, 11, 48, 50
I2C Clock Control Register
157
I2C Control Register
153
I2C Data Register
153
I2C General Characteristics
139
I2C Registers
151
I2C Slave Address Register
151
I2C Software Reset Register
159
I2C Status Register
155
IEF1
45, 46, 180
IEF2
45, 46
IM 0, Op Code Map
194
IM 1, Op Code Map
194
IM 2, Op Code Map
194
Infrared Encoder/Decoder
123
Infrared Encoder/Decoder Register
126
Infrared Encoder/Decoder Signal Pins
125
INSTRD
11, 22
Instruction Store 4
0 Registers
176
Intel-
53
Intel Bus Mode
56
Intel Bus Mode (Separate Address and Data Buses)
57
internal pull-up
39
Interrupt Controller
44
interrupt enable
12
Interrupt Enable bit
153
interrupt enable bit
89, 106
Interrupt Enable Flag
180
Interrupt Enable flags
47
Interrupt Input
126
interrupt input
13, 14, 15, 16, 17, 18, 19, 20
IORQ
11, 12, 22, 51, 53, 54, 57, 58, 61
IORQ Assertion Delay
208, 210
IORQ Deassertion Delay
208, 210
IORQ Hold Time
210
IrDA
123
IrDA Encoder/Decoder
126
IrDA encoder/decoder
13
IrDA endec
36
IrDA Receive Data
13
IrDA specifications
123
IrDA standard baud rates
123
IrDA transceiver
126
IrDA Transmit Data
13
irq_en
82, 132, 135
irq_en bit
80
J
Jitter, Infrared Encoder/Decoder
125
JTAG Test Mode
12
L
Level-Triggered Interrupts
41
Loopback Testing, Infrared Encoder/Decoder
126
Low-Power Modes
34
M
Maskable Interrupts
44
MASTER mode
130, 139, 154, 156, 157, 158
Master mode
150, 155
master mode
149
Master Mode Start bit
153
eZ80L92 MCU
Product Specification
PS013014-0107 Index
221
Master Mode Stop bit
154
MASTER mode, SPI
132
Master Receive
139, 147
Master Transmit
144
MASTER TRANSMIT mode
139
master_en bit
132
Master-In, Slave-Out
129
Master-Out, Slave-In
129
Memory and I/O Chip Selects
48
Memory Chip Select Example
49
Memory Chip Select Operation
48
Memory Chip Select Priority
49
Memory Request
11
memory space
48, 50
MISO
20, 129, 130, 131, 132
Mode Fault
132
mode fault
136
Mode Fault error flag
129
Mode Fault flag
132
Modem status signal
14, 15, 16, 17
MODF
129, 132, 136
MOSI
129, 130, 131, 132
Motorola Bus Mode
63
Motorola-compatible
53
MREQ
11, 12, 22, 48, 53, 54, 57, 58, 61
multimaster conflict
132, 136
N
NACK
141, 145, 146, 147, 148, 149, 154, 156
New and Improved Instructions, eZ80 CPU Core
31
NMI
12, 22, 31, 35, 47, 73, 74, 75
Nonmaskable Interrupts
47
Not Acknowledge
141
O
OCI Activation
183
OCI Information Requests
185
OCI Interface
184
On-Chip Instrumentation
183
On-Chip Oscillators
198
Op Code maps
191
Open-Drain output
39
open-drain output
139
open-source output
13, 14, 15, 16, 17, 18, 19, 20
Operating Modes
144
Operation of the eZ80 Webserver-i during ZDI
BREAKpoints
166
Ordering Information
216
P
Packaging
215
Part Number Description
216
PB0
18, 24, 80
PB1
18, 24, 81
PB2
19, 24
PB3
19, 24
PB4
19, 24, 40, 81
PB5
19, 24, 81
PB6
20, 24
PB7
20, 24, 38
PC0
15, 23
PC1
16, 23
PC2
16, 23
PC3
16, 23
PC4
17, 24
PC5
17, 24
PC6
17, 24
PC7
17, 24, 40
PD0
13, 126
PD1
13, 23, 126
PD2
14, 23, 126
PD3
14, 23
PD4
14, 23
PD5
14, 23
PD6
15, 23
PD7
15, 23, 126
Pin Characteristics
21
Pin Description
4
POP, Op Code Map
191, 193, 195
Port x Alternate Register 1
43
Port x Alternate Register 2
43
Port x Data Direction Registers
43
Port x Data Registers
42
Power connections
2
Programmable Reload Timer Operation
77
eZ80L92 MCU
Product Specification
PS013014-0107 Index
222
Programmable Reload Timer Registers
82
Programmable Reload Timers
77
pull-up resistor, external
39, 139
PUSH, Op Code Map
191, 193, 195
R
RD
11, 22, 48, 51, 53, 57, 58, 61
RD Assertion Delay
209
RD Deassertion Delay
209
Reading the Current Count Value
80
Real-Time Clock
88
Real-Time Clock Alarm
88
Real-Time Clock Alarm Control Register
102
Real-Time Clock Alarm Day-of-the-Week Register
101
Real-Time Clock Alarm Hours Register
100
Real-Time Clock Alarm Minutes Register
99
Real-Time Clock Alarm Seconds Register
98
Real-Time Clock Battery Backup
89
Real-Time Clock Century Register
97
Real-Time Clock Control Register
102
Real-Time Clock Day-of-the-Month Register
94
Real-Time Clock Day-of-the-Week Register
93
Real-Time Clock Hours Register
92
Real-Time Clock Minutes Register
91
Real-Time Clock Month Register
95
Real-Time Clock Oscillator and Source Selection
89
Real-Time Clock Recommended Operation
89
Real-Time Clock Registers
90
Real-Time Clock Seconds Register
90
Real-Time Clock Year Register
96
Receive, Infrared Encoder/Decoder
124
Recommended Usage of the Baud Rate Generator
109
Register Map
25
Request to Send
14, 16, 118
RESET
11, 22, 34, 35, 39, 48, 73, 74, 75, 89, 90,
102, 109, 126, 133, 134, 171, 172, 183, 184
Reset
33
RESET event
38
RESET Operation
33
RESET Or NMI Generation
74
Reset States
49
Resetting the I2C Registers
151
RI
106, 118, 121
RI0
15, 125
RI1
17, 40
Ring Indicator
15, 17, 121
RTS
118, 121, 125
RTS0
14
RTS1
16
RxD0
13
RxD1
16
S
Schmitt Trigger
11
SCK
19, 129, 130
SCK Idle State
131
SCK pin
132, 136
SCK Receive Edge
131
SCK signal
132
SCK Transmit Edge
131
SCL
20, 24, 139, 140, 141, 157
SCL line
142, 143, 144
SDA
20, 24, 139, 140, 141, 143, 150
serial bus, SPI
137
Serial Clock
130, 139
Serial Clock, I2C
20
Serial Clock, SPI
19, 129
Serial Data
139
serial data
129
Serial Data, I2C
20
Serial Peripheral Interface
128
Setting Timer Duration
77
Single Pass Mode
78
SLA
146, 148, 152, 190
SLA, Op Code Map
196, 197
SLA, Op Code map
192
SLAVE mode
139, 154, 156
slave mode
150, 151, 152
SLAVE mode, SPI
132
Slave Receive
139, 150
Slave Select
129
Slave Transmit
139, 149
SLEEP Mode
34
eZ80L92 MCU
Product Specification
PS013014-0107 Index
223
SPI
1, 36, 44, 128, 129, 132
SPI Baud Rate Generator
133
SPI Baud Rate Generator Register
27
SPI Baud Rate Generator Registers—Low Byte and
High Byte
134
SPI Block
27
SPI Control Register
27, 135
SPI Data Rate
133
SPI Flags
132
SPI Functional Description
131
SPI interrupt service routine
44
SPI Master device
134
SPI master device
20
SPI MASTER mode
132
SPI mode
19
SPI Receive Buffer Register
27, 137
SPI Registers
134
SPI serial bus
137
SPI Serial Clock
19
SPI Signals
129
SPI slave device
20
SPI SLAVE mode
132
SPI Status Register
27, 136
SPI Status register
132
SPI Transmit Shift Register
27, 134, 137
SPI Transmit Shift register
133
SPIF
131
spiF
136
SPIF bit
137
SPIF flag
132
SPIF status bit
137
SRA
190
SRA, Op Code Map
192, 196
SS
19, 129, 131, 132, 133, 136
STA
153
standard mode
139
START and STOP Conditions
140
Supply Voltage
202
supply voltage
1, 39, 139, 201
Switching Between Bus Modes
67
system clock cycles
11, 51, 53, 54, 58, 62, 74, 183
System Clock Oscillator Input
18
System Clock Oscillator Output
18
T
TERI
121
Test Mode
184
Time-Out Period Selection
74
Timer Control Register
82
Timer Data Register—High Byte
84
Timer Data Register—Low Byte
83
Timer Input Source Select Register
86
Timer Input Source Selection
80
Timer Output
81
Timer Reload Register—High Byte
86
Transferring Data
141
Transmit, Infrared Encoder/Decoder
124
TxD0
13
TxD1
15
U
UART Baud Rate Generator Register —Low and
High Bytes
109
UART FIFO Control Register
114
UART Functional Description
105
UART Interrupt Enable Register
112
UART Interrupt Identification Register
113
UART Interrupts
106
UART Line Control Register
115
UART Line Status Register
118
UART Modem Control
106
UART Modem Control Register
117
UART Modem Status Interrupt
107
UART Modem Status Register
120
UART Receive Buffer Register
111
UART Receiver
105
UART Receiver Interrupts
106
UART Recommended Usage
107
UART Registers
110
UART Scratch Pad Register
122
UART Transmit Holding Register
111
UART Transmitter
105
UART Transmitter Interrupt
106
Universal Asynchronous Receiver/Transmitter
104
eZ80L92 MCU
Product Specification
PS013014-0107 Index
224
V
VCC
2
W
WAIT
1, 11, 22, 58, 61, 64, 65
WAIT Input Signal
51
WAIT pin, external
53, 54
WAIT state
54, 62, 211, 212
Wait State Timing for Read Operations
211
Wait State Timing for Write Operations
212
WAIT states
45, 58, 61, 70, 167
Wait States
51
Watch-Dog Timer
73
Watch-Dog Timer Control Register
75
Watch-Dog Timer Operation
74
Watch-Dog Timer Registers
75
Watch-Dog Timer Reset Register
76
WCOL
132, 133
wcOl
136
WR
11, 22, 48, 51, 54, 58, 61, 210
Write Collision
133
write collision
132
write collision, SPI
136
Z
Z80-
53
Z80 Bus Mode
53
ZCL
162, 164, 171
ZDA
162, 171, 184
ZDI Address Match Registers
169
ZDI Block Read
166
ZDI BLOCK WRITE
165
ZDI BREAK Control Register
170
ZDI Bus Control Register
175
ZDI Bus Status Register
181
ZDI Clock and Data Conventions
162
ZDI Master Control Register
172
ZDI Read Memory Register
182
ZDI Read Operations
165
ZDI Read Register Low, High, and Upper
180
ZDI Read/Write Control Register
173
ZDI Read-Only Registers
169
ZDI Register Addressing
163
ZDI Register Definitions
169
ZDI Single-Byte Read
165
ZDI SINGLE-BYTE WRITE
164
ZDI Start Condition
162
ZDI Status Register
179
ZDI Write Data Registers
173
ZDI Write Memory Register
177
ZDI Write Operations
164
ZDI Write-Only Registers
168
ZDI_BUS_STAT
167, 169, 181
ZDI_BUSACK_EN
167
ZDI_BUSAcK_En
181
ZDI-Supported Protocol
161
ZiLOG Debug Interface
160
PS013014-0107 Customer Support
eZ80L92 MCU
Product Specification
225
Customer Support
For answers to technical questions about the product, documentation, or any other issues
with ZiLOG’s offerings, please visit ZiLOG’s
Knowledge Base at http://www.zilog.com/kb.
For any comments, detail technical questions, or reporting problems, please visit ZiLOG’s
Technical Support at http://support.zilog.com.
