T5753-6AQJ-66 - Atmel - Datasheet.Directory

Features

•Integrated PLL Loop Filter

•ESD Protection also at ANT1/ANT2

(4 kV HBM/200 V MM; Except Pin 2: 4 kV HBM/100 V MM)

•High Output Power (8.0 dBm) with Low Supply Current (9.0 mA)

•Modulation Scheme ASK/FSK

– FSK Modulation is Achieved by Connecting an Additional Capacitor Between the

XTAL Load Capacitor and the Open Drain Output of the Modulating Microcontroller

•Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply

•Single Li-cell for Power Supply

•Supply Voltage 2.0V to 4.0V in the Temperature Range of –40°C to +85°C/125°C

•Package TSSOP8L

•Single-ended Antenna Output with High Efficient Power Amplifier

•CLK Output for Clocking the Microcontroller

•One-chip Solution with Minimum External Circuitry

•125°C Operation for Tire Pressure Systems

1. Description

The T5753 is a PLL transmitter IC which has been developed for the demands of RF

low-cost transmission systems at data rates up to 32 kBaud. The transmitting

frequency range is 310 MHz to 350 MHz. It can be used in both FSK and ASK

systems.

Figure 1-1. System Block Diagram

Micro-

controller

PLL

UHF ASK/FSK

Remote control receiver

UHF ASK/FSK

Remote control transmitter

T5753 U3741B/

U3745B/

T5743/

T5744

LNA VCO

PLL XTO

LNA

VCO

Antenna

Demod

IF Amp

Control 1 to 3

Encoder

ATARx9x

XTO

1 Li cell

Keys

Antenna

UHF ASK/FSK

Transmitter

T5753

4510J–RKE–12/08

T5753

2. Pin Configuration

Figure 2-1. Pinning TSSOP8L

ENABLE

GND

T5753

XTAL

CLK

PA_ENABLE

ANT2

ANT1

Table 2-1. Pin Description

Pin Symbol Function Configuration

1CLK

Clock output signal for microcontroller

The clock output frequency is set by the

crystal to fXTAL/4

2 PA_ENABLE Switches on power amplifier, used for

ASK modulation

ANT2

ANT1

Emitter of antenna output stage

Open collector antenna output

100Ω

100Ω CLK

50 kΩ

20 µA

REF

= 1.1V PA_ENABLE

ANT1

ANT2

4510J–RKE–12/08

T5753

Figure 2-2. Block Diagram

5 XTAL Connection for crystal

6 VS Supply voltage See ESD protection circuitry (see Figure 4-5 on page 9)

7 GND Ground See ESD protection circuitry (see Figure 4-5 on page 9)

8 ENABLE Enable input

Table 2-1. Pin Description (Continued)

Pin Symbol Function Configuration

1.5 kΩ1.2 kΩ

182 µA

XTAL

VS VS

200 kΩ

ENABLE

T5753

Power up/down

PDF

XTAL

GND

ENABLE

ANT1

ANT2

PA_ENABLE

CLK 1

PA VCO

PLL

XTO

4510J–RKE–12/08

T5753

3. General Description

This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature transmit-

ters to be assembled. The VCO is locked to 32 fXTAL hence a 9.8438 MHz crystal is needed for a

315 MHz transmitter. All other PLL and VCO peripheral elements are integrated.

The XTO is a series resonance oscillator so that only one capacitor together with a crystal con-

nected in series to GND are needed as external elements.

The crystal oscillator together with the PLL needs typically < 3 ms until the PLL is locked and the

CLK output is stable. There is a wait time of ≥3 ms until the CLK is used for the microcontroller

and the PA is switched on.

The power amplifier is an open-collector output delivering a current pulse which is nearly inde-

pendent from the load impedance. The delivered output power is hence controllable via the

connected load impedance.

This output configuration enables a simple matching to any kind of antenna or to 50 Ω. A high

power efficiency of η=P

out/(IS,PA V

S) of 40% for the power amplifier results when an optimized

load impedance of ZLoad = (255 + j192) Ω is used at 3 V supply voltage.

4. Functional Description

If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only a very

small amount of current so that a lithium cell used as power supply can work for several years.

With ENABLE = H the XTO, PLL and the CLK driver are switched on. If PA_ENABLE remains L

only the PLL and the XTO is running and the CLK signal is delivered to the microcontroller. The

VCO locks to 32 times the XTO frequency.

With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver and the power amplifier are

on. With PA_ENABLE the power amplifier can be switched on and off, which is used to perform

the ASK modulation.

4.1 ASK Transmission

The T5753 is activated by ENABLE = H. PA_ENABLE must remain L for typically ≥3ms, then

the CLK signal can be taken to clock the microcontroller and the output power can be modulated

by means of Pin PA_ENABLE. After transmission PA_ENABLE is switched to L and the micro-

controller switches back to internal clocking. The T5753 is switched back to standby mode with

ENABLE = L.

4.2 FSK Transmission

The T5753 is activated by ENABLE = H. PA_ENABLE must remain L for typically ≥3ms, then

the CLK signal can be taken to clock the microcontroller and the power amplifier is switched on

with PA_ENABLE = H. The chip is then ready for FSK modulation. The microcontroller starts to

switch on and off the capacitor between the XTAL load capacitor and GND with an open-drain

output port, thus changing the reference frequency of the PLL. If the switch is closed, the output

frequency is lower than if the switch is open. After transmission PA_ENABLE is switched to L

and the microcontroller switches back to internal clocking. The T5753 is switched back to

standby mode with ENABLE = L.

The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the fol-

lowing tolerances are considered.

4510J–RKE–12/08

T5753

Figure 4-1. Tolerances of Frequency Modulation

Using C4=8.2pF±5%, C

5= 10 pF ±5%, a switch port with CSwitch = 3 pF ±10%, stray capaci-

tances on each side of the crystal of CStray1 =C

Stray2 = 1 pF ±10%, a parallel capacitance of the

crystal of C0= 3.2 pF ±10% and a crystal with CM= 13 fF ±10%, an FSK deviation of ±21.5 kHz

typical with worst case tolerances of ±16.25 kHz to ±28.01 kHz results.

4.3 CLK Output

An output CLK signal is provided for a connected microcontroller, the delivered signal is CMOS

compatible if the load capacitance is lower than 10 pF.

4.3.1 Clock Pulse Take-over

The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel®’s

ATARx9x has the special feature of starting with an integrated RC-oscillator to switch on the

T5753 with ENABLE = H, and after 3 ms to assume the clock signal of the transmission IC, so

that the message can be sent with crystal accuracy.

4.3.2 Output Matching and Power Setting

The output power is set by the load impedance of the antenna. The maximum output power is

achieved with a load impedance of ZLoad,opt = (255 + j192)Ω. There must be a low resistive path

to VS to deliver the DC current.

The delivered current pulse of the power amplifier is 9 mA and the maximum output power is

delivered to a resistive load of 400Ω if the 1.0 pF output capacitance of the power amplifier is

compensated by the load impedance.

An optimum load impedance of:

ZLoad =400Ω|| j/(2 ×π1.0pF)=(255+j192)Ω thus results for the maximum output power of

8dBm.

The load impedance is defined as the impedance seen from the T5753’s ANT1, ANT2 into the

matching network. Do not confuse this large signal load impedance with a small signal input

impedance delivered as input characteristic of RF amplifiers and measured from the application

into the IC instead of from the IC into the application for a power amplifier.

Less output power is achieved by lowering the real parallel part of 400Ω where the parallel imag-

inary part should be kept constant.

Output power measurement can be done with the circuit of Figure 4-2. Note that the component

values must be changed to compensate the individual board parasitics until the T5753 has the

right load impedance ZLoad,opt = (255 + j192)Ω. Also the damping of the cable used to measure

the output power must be calibrated out.

XTAL

Crystal equivalent circuit

Switch

Stray1

Stray2

4510J–RKE–12/08

T5753

Figure 4-2. Output Power Measurement at f = 315 MHz

Note: For 345 MHz C2 has to be changed to 2.7 pF

4.4 Application Circuit

For the blocking of the supply voltage a capacitor value of C3= 68 nF/X7R is recommended

(see Figure 4-3 on page 7 and Figure 4-4 on page 8). C1 and C2 are used to match the loop

antenna to the power amplifier where C1 typically is 22 pF/NP0 and C2 is 10.8 pF/NP0

(18 pF + 27 pF in series); for C2 two capacitors in series should be used to achieve a better tol-

erance value and to have the possibility to realize the ZLoad,opt by using standard valued

capacitors.

C1 forms together with the pins of T5753 and the PCB board wires a series resonance loop that

suppresses the 1st harmonic, hence the position of C1 on the PCB is important. Normally the

best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and

ANT2.

The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop

antenna is too high.

L1 ([50 nH to 100 nH) can be printed on PCB. C4 should be selected that the XTO runs on the

load resonance frequency of the crystal. Normally, a value of 12 pF results for a 15 pF

load-capacitance crystal.

1 nF

3.3 pF

56 nH

ANT2

ANT1

Lopt

Power

meter

50Ω

Z = 50Ω

4510J–RKE–12/08

T5753

Figure 4-3. ASK Application Circuit

ATARx9x

T5753

Power up/down

PDF

VDD

BPXY

VSS

XTAL XTAL

GND

ENABLE

ANT1

Loop

Antenna

C2 ANT2

PA_ENABLE

OSC1

BPXY

CLK

PA VCO

PLL

XTO

4510J–RKE–12/08

T5753

Figure 4-4. FSK Application Circuit

ATARx9x

T5753

Power up/down

PDF

VDD

BPXY

VSS

XTAL XTAL

GND

ENABLE

ANT1

Loop

Antenna

C2 ANT2

PA_ENABLE

OSC1

BPXY

CLK

PA VCO

PLL

XTO

BP42/T2O

4510J–RKE–12/08

T5753

Figure 4-5. ESD Protection Circuit

CLK

GND

PA_ENABLE XTALANT2 ENABLE

ANT1

5. Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters Symbol Minimum Maximum Unit

Supply voltage VS5V

Power dissipation Ptot 100 mW

Junction temperature Tj150 °C

Storage temperature Tstg –55 125 °C

Ambient temperature Tamb –55 125 °C

Input voltage VmaxPA_ENABLE –0.3 (VS + 0.3)(1) V

Note: 1. If VS + 0.3 is higher than 3.7V, the maximum voltage will be reduced to 3.7V.

6. Thermal Resistance

Parameters Symbol Value Unit

Junction ambient RthJA 170 K/W

7. Electrical Characteristics

VS = 2.0V to 4.0V, Tamb = –40°C to 125°C unless otherwise specified.

Typical values are given at VS= 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7).

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Supply current

Power down,

VENABLE < 0.25 V, -40°C to 85°C

VPA- EN ABLE < 0.25 V, -40°C to +125°C

VPA- EN ABLE < 0.25 V, 25°C

(100% correlation tested)

IS_Off <10

350

µA

Supply current Power up, PA off, VS= 3 V,

VENABLE >1.7V, V

PA-ENABLE <0.25V IS3.7 4.8 mA

Supply current Power up, VS= 3.0 V,

VENABLE >1.7V, V

PA-ENABLE >1.7V IS_Transmit 911.6mA

Output power VS=3.0V, T

amb = 25°C,

f = 315 MHz, ZLoad = (255 + j192)W PRef 6.0 8.0 10.5 dBm

Note: 1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V.

4510J–RKE–12/08

T5753

Output power variation for the full

temperature range

Tamb = –40°C to +85°C,

VS = 3.0V

VS = 2.0V

ΔPRef

–1.5

–4.0

Output power variation for the full

temperature range

Tamb = –40°C to +125°C,

VS = 3.0V

VS = 2.0V,

POut = PRef + ΔPRef

ΔPRef

–2.0

–4.5

Achievable output-power range Selectable by load impedance POut_typ 08.0dBm

Spurious emission

fCLK = f0/128

Load capacitance at pin CLK = 10 pF

fO ±1 ×fCLK

fO ±4 ×fCLK

other spurious are lower

–55

–52

dBc

Oscillator frequency XTO

(= phase comparator frequency)

fXTO = f0/32

fXTAL = resonant frequency of the XTAL,

CM ≤10 fF, load capacitance selected

accordingly

Tamb = –40°C to +85°C,

Tamb = –40°C to +125°C

fXTO

–30

–40

fXTAL +30

+40

ppm

PLL loop bandwidth 250 kHz

Phase noise of phase comparator Referred to fPC = fXT0,

25 kHz distance to carrier –116 –110 dBc/Hz

In loop phase noise PLL 25 kHz distance to carrier –86 –80 dBc/Hz

Phase noise VCO at 1 MHz

at 36 MHz

–94

–125

–90

–121

dBc/Hz

Frequency range of VCO fVCO 310 350 MHz

Clock output frequency (CMOS

microcontroller compatible) f0/128 MHz

Voltage swing at pin CLK CLoad ≤10 pF V0h

V0l VS

× 0.8 VS

× 0.2 V

Series resonance R of the crystal Rs 110 Ω

Capacitive load at pin XT0 7pF

FSK modulation frequency rate Duty cycle of the modulation signal = 50% 0 32 kHz

ASK modulation frequency rate Duty cycle of the modulation signal = 50% 0 32 kHz

ENABLE input

Low level input voltage

High level input voltage

Input current high

VIl

VIh

IIn

1.7

0.25

µA

PA_ENABLE input

Low level input voltage

High level input voltage

Input current high

VIl

VIh

IIn

1.7

0.25

VS(1)

µA

7. Electrical Characteristics (Continued)

VS = 2.0V to 4.0V, Tamb = –40°C to 125°C unless otherwise specified.

Typical values are given at VS= 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7).

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Note: 1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V.

4510J–RKE–12/08

T5753

9. Package Information

8. Ordering Information

Extended Type Number Package Remarks

T5753-6AQJ TSSOP8L Taped and reeled, Marking: T573, Pb-free

T5753-6APJ TSSOP8L Taped and reeled, Marking: T573, small reel, Pb-free

Note: 1. J = –40°C to +125°C + lead-free

3±0.1

0.85±0.05

0.1±0.05

specifications

according to DIN

technical drawings

Issue: 2; 15.03.04

Drawing-No.: 6.543-5083.01-4 14

Package: TSSOP 8L

Dimensions in mm

0.65 nom.

3 x 0.65 = 1.95 nom.

0.31-0.07

+0.06

0.15

-0.02

+0.05

1-0.15

+0.05

3.8±0.3

4.9±0.1

3±0.1

4510J–RKE–12/08

T5753

10. Revision History

Please note that the following page numbers referred to in this section refer to the specific revision

mentioned, not to this document.

Revision No. History

4510J-RKE-12/08 • Put datasheet in the newest template

• Section 4.3.1 “Clock Pulse Take-over” on page 5 changed

4510I-RKE-02/07 • Put datasheet in the newest template

• Pb-free Logo on page 1 deleted

4510H-RKE-09/05 • Pb-free Logo on page 1 added

4510G-RKE-02/05

• Put datasheet in the newest template

• Section 1 “Description” on page 1 changed

• Figure title Figure 4-2 on page 6 changed

• Table “Electrical Characteristics” on pages 9 to 10 changed

• Table “Ordering Information” on page 11 changed

4510F-RKE-02/05

• Table “Absolute Maximum Ratings” (page 8): row “Input voltage” added

• Table “Absolute Maximum Ratings” (page 8): table note 1 added

• Table “Electrical Characteristics” (page 10): row “PA_ENABLE input“ changed

• Table “Electrical Characteristics” (page 10): table note 1 added

• Table “Ordering Information” (page 11): Remarks changed

4510J–RKE–12/08

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