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EN6338QI 3A PowerSoC
Step-Down DC-DC Switching Converter with Integrated Inductor
DESCRIPTION
The EN6338QI is a Power System on a Chip
(PowerSoC) DC-DC converter. It integrates MOSFET
switches, small-signal circuits, compensation, and the
inductor in an advanced 3.75mm x 3.75mm x 1.9mm
19-pin aEASI package.
The EN6338QI is specifically designed to meet the
precise voltage and fast transient requirements of
present and future high-performance, low-power
processor, DSP, FPGA, memory boards and system
level applications in distributed power architecture.
The device’s advanced circuit techniques, ultra high
switching frequency, and proprietary integrated
inductor technology deliver high-quality, ultra
compact, non-isolated DC-DC conversion.
The Intel Enpirion power solution significantly helps
in system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, a reduction in the number
of vendors required for the complete power solution
helps to enable an overall system cost savings.
All Enpirion products are RoHS compliant and lead-
free manufacturing environment compatible.
FEATURES
• High Efficiency (Up to 96%)
• Light Load Mode Operation (LLM)
• Excellent Ripple and EMI Performance
• Up to 3A Continuous Operating Current
• 2.7V to 6.6V Input Voltage Range
• 1.5% VOUT Accuracy (Line, Load, Temp)
• 1.9MHz Switching Frequency
• 45mm2 Optimized Total Solution Size
• Programmable Soft-Start
• Power OK Indicator
• Thermal, Over-Current, Short Circuit and Under-
Voltage Protection
• RoHS Compliant, MSL Level 3, 260°C Reflow
APPLICATIONS
• Point of Load Regulation for FPGAs, Distributed
Power Architectures, Low-Power ASICs, Multi-
Core, Communication Processors and DSPs
• Space Constrained Applications Needing High
Power Density
• 5V/3.3V Bus Architectures Needing High Efficiency
Figure 1: Simplified Applications Circuit
Figure 2: Efficiency at VIN = 5V
DataSheeT
– enpirion® power solutions
0
10
20
30
40
50
60
70
80
90
100
00.5 11.5 22.5 3
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.0V
VOUT = 0.75V
CONDITIONS
V
IN
= 5V
EN6338QI
VOUT
VIN
2x
10µF
0805
VOUT
AVIN
AGND
SS
PVIN
EN
PGND PGND
EN6338QI
10nF
VFB
R
A
R
B
C
A
PGTE BTMP
VDDB
BGND
47nF
47nF
15nF
2x
22µF
0805
10Ω
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Datasheet | Intel® Enpirion® Power Solutions: EN6338QI
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ORDERING INFORMATION
Part Number Package
Markings TJ Rating Package Description
EN6338QI EN6338QI -40°C to +125°C 19-pin (3.75mm x 3.75mm x 1.9mm) aEASI
EVB-EN6338QI EN6338QI aEASI Evaluation Board
Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html
PIN FUNCTIONS
Figure 3: Pin Diagram (Top View)
NOTE A: NF pins are non-functional and unconnected internally. Area under NF pin locations may be used for vias to
route VFB, POK and SYNC signals. NF pins do not require landing pads.
NOTE B: White ‘dot’ on top left is pin 1 indicator on top of the device package.
AVIN NF
AGND NF
SS VFB
RLLM NF
EN POK
BGND S YNC
V DD B NF
BTMP PGTE
VOUT
P VI N
PGND
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17
18
19
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Datasheet | Intel® Enpirion® Power Solutions: EN6338QI
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PIN DESCRIPTIONS
PIN NAME TYPE FUNCTION
1 AVIN Power Input power supply for the controller. Connect to input
voltage at a quiet point.
2, 4, 8, 14 NF -
NON FUNCTIONAL – These pins are not internally connected
and do not require landing pads. Area below these pins may
be used for vias to route VFB, POK and SYNC signals to other
layers.
3 AGND Ground Analog Ground. This is the controller ground return. Connect
to a quiet ground.
5 SS Analog
Soft-Start node. The soft-start capacitor is connected
between this pin and AGND. The value of this capacitor
determines the startup time.
6 VFB Analog
This is the external feedback input pin. A resistor divider
connects from the output to AGND. The mid-point of the
resistor divider is connected to VFB. A feed-forward
capacitor (CA) and resistor (RC) are required parallel to the
upper feedback resistor (RA). The output voltage regulation is
based on the VFB node voltage equal to 0.600V.
7 RLLM Analog
Programmable LLM engage resistor to AGND allows for
adjustment of load current at which Light-Load Mode
engages. Can be left open for PWM only operation.
9 EN Analog Input Enable. Applying logic high enables the output and
initiates a soft-start. Applying logic low disables the output.
10 POK Digital
Power OK is an open drain transistor used for power system
state indication. POK is logic high when VOUT is within -10%
of VOUT nominal.
11 BGND Ground Ground for VDDB. Do not connect to external ground.
12 SYNC Analog
Dual function pin providing LLM Enable and External Clock
Synchronization (see Application Section). At static Logic
HIGH, device will allow automatic engagement of light load
mode. At static logic LOW, the device is forced into PWM
only. A clocked input to this pin will synchronize the internal
switching frequency to the external signal. If this pin is left
floating, it will pull to a static logic high, enabling LLM.
13 VDDB Analog Internal regulated voltage used for the internal control
circuitry.
15 BTMP Ground Bottom plate ground for PGTE.
16 PGTE Analog PMOS gate.
17 PGND Ground
Input/Output power ground. Connect to the ground
electrode of the input and output filter capacitors. See VOUT
and PVIN pin descriptions for more details.
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PIN NAME TYPE FUNCTION
18 PVIN Power Input power supply. Connect to input power supply.
Decouple with input capacitor to PGND pin.
19 VOUT Power Regulated converter output. Connect to the load and place
output filter capacitor(s) between these pins and PGND pins.
ABSOLUTE MAXIMUM RATINGS
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended
operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device
life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Absolute Maximum Pin Ratings
PARAMETER SYMBOL MIN MAX UNITS
PVIN, AVIN, VOUT -0.3 7.0 V
EN, POK, SYNC -0.3 VIN+0.3 V
VFB, SS, RLLM, PGTE, VDDB -0.3 2.5 V
Absolute Maximum Thermal Ratings
PARAMETER CONDITION MIN MAX UNITS
Maximum Operating Junction
Temperature +150 °C
Storage Temperature Range -65 +150 °C
Reflow Peak Body
Temperature (10 Sec) MSL3 JEDEC J-STD-020A +260 °C
Absolute Maximum ESD Ratings
PARAMETER CONDITION MIN MAX UNITS
HBM (Human Body Model) ±2000 V
CDM (Charged Device Model) ±500 V
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL MIN MAX UNITS
Input Voltage Range VIN 2.7 6.6 V
Output Voltage Range VOUT 0.75 VIN – VDO (1) V
Output Current Range IOUT 3 A
Operating Junction Temperature TJ -40 +125 °C
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THERMAL CHARACTERISTICS
PARAMETER SYMBOL TYPICAL UNITS
Thermal Shutdown TSD 160 °C
Thermal Shutdown Hysteresis TSDH 25 °C
Thermal Resistance: Junction to Ambient (0 LFM) (2) θJA 30 °C/W
Thermal Resistance: Junction to Case (0 LFM) θJC 3 °C/W
(1) VDO (dropout voltage) is defined as (ILOAD x Droput Resistance). Please refer to Electrical Characteristics Table.
(2) Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high
thermal conductivity boards.
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ELECTRICAL CHARACTERISTICS
NOTE: VIN = PVIN = AVIN = 5V, Minimum and Maximum values are over operating ambient temperature range
unless otherwise noted. Typical values are at TA = 25°C.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Operating Input
Voltage VIN PVIN = AVIN 2.7 6.6 V
Under Voltage Lock-
Out – VIN Rising VUVLOR Voltage above which UVLO is
not asserted 2 2.3 2.45 V
Under Voltage Lock-
Out – VIN Falling VUVLOF Voltage below which UVLO is
asserted 1.7 2.1 2.3 V
Under Voltage Lock-
Out Hysteresis VUVLO_HYS 200 mV
Shut-Down Supply
Current IS EN = 0V 40 60 µA
AVIN Quiescent Current IAVINQ LLM/SYNC = High
VOUT = 0.75V
650 900 µA
No Load Quiescent
Current IVINQ PVIN and AVIN
VOUT = 1.2V
40 mA
Feedback Pin Voltage (3) VFB VOUT = 0.75V
ILOAD = 0, TA =25°C
0.7425 0.75 0.7575 V
Feedback Pin Voltage
(Load, Temp.) VFB 0A ≤ ILOAD ≤ 3A
-40°C ≤ TJ ≤ 125°C
0.739 0.75 0.761 V
Feedback Pin Voltage
(Line, Load, Temp.) VFB
2.7V ≤ VIN ≤ 6.6V
0A ≤ ILOAD ≤ 3A
-40°C ≤ TJ ≤ 125°C
0.735 0.75 0.765 V
Feedback pin Input
Leakage Current (4) IFB VFB pin input leakage current -10 10 nA
VOUT Rise Time Range (4) tRISE Capacitor programmable 0.8 8 ms
Soft Start Capacitance
Range (4) CSS_RANGE Recommended CSS range 10 100 nF
Soft-Start Charging
Current ISS 3.5 10 15 µA
Drop-Out Resistance (4) RDO Input to output resistance 50 80 mΩ
Drop-Out Voltage (4) VDO IOUT = 3A 150 240 mV
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PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Output
Current IOUT 0 3 A
Over Current Trip Level IOCP VIN = 5V, VOUT = 1.2V 4 6.5 A
Disable Threshold VDISABLE EN pin logic going low 1.2 1.34 1.48 V
EN Threshold VEN EN pin logic going high 1.22 1.36 1.5 V
EN Pin Input Current IEN VEN = 5V; EN pin has ~250kΩ
pull down 20 35 µA
EN Pull-Down
Resistance REN_DOWN VEN = 5V;
Not a passive resistance
250 kΩ
Switching Frequency FSW Free running clock frequency 1.6 1.9 2.2 MHz
SYNC Input Threshold
– Low VSYNC_LO SYNC Clock Logic Level 0.8 V
SYNC Input Threshold
– High (5) VSYNC_HI SYNC Clock Logic Level 1.8 2.5 V
POK High Threshold POK_HI Percentage of VOUT nominal
when POK is asserted high 90 %
POK Low Voltage VPOKL 4mA sink into POK 0.4 V
POK High Voltage VPOKH 2.7V ≤ VIN ≤ 6.6V VIN V
POK Pin Leakage
Current (4) IPOKH POK is high 1 µA
LLM Headroom (4) Minimum VIN - VOUT 800 mV
LLM Logic Low
(LLM/SYNC PIN) VLLM_LO LLM Static Logic Level 0.3 V
LLM Logic High
(LLM/SYNC PIN) VLLM_HI LLM Static Logic Level 1.5 V
LLM/SYNC Pin Current LLM/SYNC Pin is <2.5V <100 nA
(3) The VFB pin is a sensitive node. Do not touch VFB while the device is in regulation.
(4) Parameter not production tested but is guaranteed by design.
(5) High logic for frequency synchronization with SYNC pin must be below 2.5V.
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TYPICAL PERFORMANCE CURVES
0
10
20
30
40
50
60
70
80
90
100
00.5 11.5 22.5 3
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.0V
VOUT = 0.75V
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
00.5 11.5 22.5 3
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
VOUT = 1.0V
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
00.5 11.5 22.5 3
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
V
OUT
= 1.2V
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TYPICAL PERFORMANCE CURVES (CONTINUED)
1.480
1.485
1.490
1.495
1.500
1.505
1.510
1.515
1.520
00.5 11.5 22.5 3
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
VOUT = 1.5V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
00.5 11.5 22.5 3
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
V
OUT
= 1.8V
2.480
2.485
2.490
2.495
2.500
2.505
2.510
2.515
2.520
00.5 11.5 22.5 3
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
V
OUT
= 2.5V
3.280
3.285
3.290
3.295
3.300
3.305
3.310
3.315
3.320
00.5 11.5 22.5 3
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 5.0V
CONDITIONS
V
OUT
= 3.3V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.4 33.6 4.2 4.8 5.4 66.6
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
CONDITIONS
Load = 0A
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.4 33.6 4.2 4.8 5.4 66.6
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
CONDITIONS
Load = 1A
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TYPICAL PERFORMANCE CURVES (CONTINUED)
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.4 33.6 4.2 4.8 5.4 66.6
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
CONDITIONS
Load = A
CONDITIONS
Load = 2A
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.4 33.6 4.2 4.8 5.4 66.6
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
CONDITIONS
Load = A
CONDITIONS
Load = 3A
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-40 -15 10 35 60 85
GUARANTEED OUTPUT CURRENT (A)
AMBIENT TEMPERATURE(°C)
No Thermal Derating
CONDITIONS
V
IN
= 5.0V
V
OUT
= 1.0V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-40 -15 10 35 60 85
GUARANTEED OUTPUT CURRENT (A)
AMBIENT TEMPERATURE(°C)
No Thermal Derating
CONDITIONS
V
IN
= 5.0V
V
OUT
= 3.3V
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
30 300
LEVEL (dBµV/m)
FREQUENCY (MHz)
EMI Performance (Horizontal Scan)
CONDITIONS
V
IN
= 5.0V
V
OUT_NOM
= 1.5V
LOAD = 0.5Ω
CISPR 22 Class B 3m
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
30 300
LEVEL (dBµV/m)
FREQUENCY (MHz)
EMI Performance (Vertical Scan)
CONDITIONS
V
IN
= 5.0V
V
OUT_NOM
= 1.5V
LOAD = 0.5Ω
CISPR 22 Class B 3m
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TYPICAL PERFORMANCE CHARACTERISTICS
VOUT 1.0V
( AC Coupl ed)
Output Ri pple a t 20 M Hz Ba ndwidt h
CONDITIONS
VIN = 3.3V,IOUT = 0A
CIN = 2 x 10µF (0805)
COUT = 2 x 22 µF (0805)
VOUT 1.8V
( AC Coupl ed)
VOUT 2.5V
( AC Coupl ed)
VOUT 1.0V
( AC Coupl ed)
Output Ri pple a t 2 0 MHz Ba ndwidt h
CONDITIONS
VIN = 3.3V,IOUT = 3A
CIN = 2 x 10µF (0805)
COUT = 2 x 22 µF (0805)
VOUT 1.8V
( AC Coupl ed)
VOUT 2.5V
( AC Coupl ed)
VOUT 1.0V
( AC Coupl ed)
Output Ri pple a t 2 0 MHz Ba ndwidt h
CONDITIONS
VIN = 5V, IOUT = 0A
CIN = 2 x 10µF (0805)
COUT = 2 x 22 µF (0805)
VOUT 1.8V
( AC Coupl ed)
VOUT 3.3V
( AC Coupl ed)
VOUT 1.0V
( AC Coupl ed)
Output Ri pple a t 2 0 MHz Ba ndwidt h
CONDITIONS
VIN = 5V, IOUT = 3A
CIN = 2 x 10µF (0805)
COUT = 2 x 22 µF (0805)
VOUT 1.8V
( AC Coupl ed)
VOUT 3.3V
( AC Coupl ed)
VOUT
(AC Coupled)
LLM Output Ripple at 100mA
CONDITIONS
VIN = 3.3V
VO UT = 1 V
IOUT = 100mA
CIN = 2 x 22µF (0805)
COUT = 2 x 47 µF (0805)
VOUT
(AC Coupled)
LLM Output Ripple at 100mA
CONDITIONS
VIN = 5 V
VO UT = 1 V
IOUT = 100mA
CIN = 2 x 22µF (0805)
COUT = 2 x 47 µF (0805)
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TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
ENABLE
Enable Powe r Up/ Down
CONDITIONS
VIN = 5.5V, VOUT = 3.3V
NO LOAD, Css = 15nF
CIN = 2 x 22µF (0805)
COUT = 2 x 47 µF (0805)
VOUT
POK
LOAD
ENABLE
Enable Powe r Up/ Down
CONDITIONS
VIN = 5.5V, VOUT = 3.3V
LOAD=1.1Ω, Css = 15nF
CIN = 2 x 22µF (0805)
COUT = 2 x 47 µF (0805)
VOUT
POK
LOAD
VOUT
(AC Coupled)
LLM Load T ransient from 0.01 to 3A
CONDITIONS
LLM = ENABLED
VIN = 5 V
VO UT = 1 V
CIN = 2 x 22µF (0805)
COUT = 2 x 47 µF (0805)
LOAD
VOUT
(AC Coupled)
LLM Load T ransient from 0.01 to 3A
CONDITIONS
LLM = ENABLED
VIN = 5 V
VO UT = 3 V
CIN = 2 x 22µF (0805)
COUT = 2 x 47 µF (0805)
LOAD
VOUT
(AC Coupled)
PWM Load Transie nt from 0 to 3A
CONDITIONS
LLM = DISABLED
VIN = 5 V
VO UT = 1 V
CIN = 2 x 22µF (0805)
COUT = 2 x 47 µF (0805)
LOAD
VOUT
(AC Coupled)
PWM Load Transie nt from 0 to 3A
CONDITIONS
LLM = DISABLED
VIN = 5 V
VO UT = 3 V
CIN = 2 x 22µF (0805)
COUT = 2 x 47 µF (0805)
LOAD
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FUNCTIONAL BLOCK DIAGRAM
Figure 4: Functional Block Diagram
FUNCTIONAL DESCRIPTION
Synchronous DC-DC Step-Down PowerSoC
The EN6338QI is a synchronous DC-DC buck regulator with integrated internal MOSFETs. The nominal input
voltage range is 2.7V to 6.6V. The output voltage is programmed using an external resistor divider network.
The control loop is voltage-mode with a type III compensation network. Much of the compensation circuitry is
internal to the device, but a phase-lead capacitor and resistor are required to complete the compensation
network. The type III voltage mode architecture with integrated compensation maximizes loop bandwidth
without increasing complexity. This architecture is designed to maintain stability with excellent gain and phase
margin and improve transient response. The enhanced voltage mode architecture also provides high noise
immunity at light load and maintains excellent line and load regulation. Up to 3A of continuous output current
(+)
(-)
Error
Amp
VFB
VOUT
P-Drive
N-Drive
UVLO
Thermal Limit
Soft-Start
PLL/Sawtooth
Generator
(+)
(-)PWM
Comp
PVIN
EN
PGND
Logic
Compensation
Network
AGND
AVIN
Internal
Regulator
Internal
Reference
SS
Power
OK POK
Cur rent Limit
LDO
BGND
VDDB
PGTEBTMP
RLLM
SYNC
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can be drawn from this converter. The 1.9MHz switching frequency allows the use of smaller case size input
and output capacitors within a small footprint.
The EN6338QI architecture includes the following features.
Operational Features:
• Automatic Light Load Mode (LLM) or Forced PWM mode selection
• Soft-start circuit allowing controlled startup and shutdown
• Power OK circuit indicating the output voltage is greater than 90% of programmed value
Protection Features:
• Over-current protection from short circuit or excessive load current
• Thermal shutdown with hysteresis to prevent over temperature stress
• Under-voltage lockout protection to prevent under-voltage operation
Light Load Mode (LLM) Operation
The EN6338QI uses a proprietary Light Load Mode (LLM) to provide high efficiency at low output currents.
When the LLM/SYNC pin is asserted high, the device is in automatic LLM “Detection” mode. When the
LLM/SYNC pin is low, the device is forced into PWM mode. In automatic LLM “Detection” mode, when a low
output current condition is detected, the device will:
(1) Step VOUT up by approximately 1.0% above the nominal operating output voltage setting, VNOM and as low
as -0.5% below VNOM, and then
(2) Shut down unnecessary circuitry, and then
(3) Monitor VOUT
When VOUT falls below VNOM, the device will repeat (1), (2), and (3). The voltage step-up, or pre-positioning,
improves transient droop when a load transient causes a transition from LLM mode to PWM mode. If a load
transient occurs, causing VOUT to fall below the threshold VMIN, the device will exit LLM operation and begin
normal PWM operation. Figure 5 demonstrates VOUT behavior during the transition into and out of LLM
operation.
Figure 5: Light Load Mode Operation Illustration
IOUT
VMA X
VMI N
VOUT_NOM
LLM
Ripple
PW M
Ripple
Load
Step
Time
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Many multi-mode DCDC converters suffer from a condition that occurs when the load current increases only
slowly so that there is no load transient driving VOUT below the VMIN threshold. In this condition, the device
would never exit LLM operation. This could adversely affect efficiency and cause unwanted ripple. To prevent
this from occurring, the EN6338QI periodically exits LLM mode into PWM mode and measures the load current.
If the load current is above the LLM threshold current, the device will remain in PWM mode. If the load current
is below the LLM threshold, the device will re-enter LLM operation. There may be a small overshoot or
undershoot in VOUT when the device exits and re-enters LLM. The load current at which the device will enter
LLM mode is a function of input and output voltage, and the RLLM pin resistor. For PWM only operation, the
RLLM pin can be left open. There is a minimum headroom between input and output of 800mV in order to
engage into LLM mode.
Figure 6: LLM to PWM Transition Point with Various RLLM Values
Enable Operation
The enable (EN) pin provides a mean to startup or to shutdown the device. When the EN pin is asserted high,
the device will undergo a normal soft-start where the output will rise monotonically into regulation. Asserting
a logic low on this pin will deactivate the device by initiating a soft-shutdown. The soft-shutdown time is
approximately 5 times faster than the soft-start time. The EN pin is internally pulled low by a non-passive
ressitance of 250kΩ.
Soft-Start Operation
The soft-start circuitry will reduce inrush current during startup as the regulator charges the output voltage up
to nominal level gradually. The output rise time is controlled by the soft-start capacitor, which is placed
between the SS pin and the AGND pin. When the part is enabled, the soft-start (SS) current generator charges
the SS capacitor in a linear manner. Once the voltage on the SS capacitor reaches 0.75V, the controller selects
the intenral bandgap voltage as the reference. The voltage across the SS capacitor will continue ramping up
until it reaches around 1.36V. The rise time is defined as the time needed by the output voltage to go from
zero to the programmed value. The rise time (tRISE) is given by the following equation:
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
010 20 30 40 50 60 70 80 90 100
LLM TO PWM CURRENT (A)
RLLM RESISTOR (kΩ)
LLM to PWM Current vs. RLLM
VIN = 5V, VOUT = 3.3V
VIN = 3.3V, VOUT = 2.5V
VIN = 5V, VOUT = 1V
VIN = 3.3V, VOUT = 1V
CONDITIONS
T
A
= 25°C
L = 470nH
15043 August 10, 2018 Rev A
Datasheet | Intel® Enpirion® Power Solutions: EN6338QI
Page 16
tRISE [ms] = Css [nF] x 0.08
With a 15nF soft-start capacitance on the SS pin, the soft-start rise time will be set to 1.2ms. The recommended
range for the value of the SS capacitor is between 10nF and 100nF. Note that excessive bulk capacitance on
the output can cause an over current event on startup if the soft-start time is too low. Refer to the
Compensation and Transient Response section for details on proper bulk capacitance usage.
POK Operation
The Power OK (POK) is an open drain signal to indicate if the output voltage is within the specified range. POK
is asserted high when the rising output voltage exceeds 90% of the programmed output voltage. An external
resistor (10k) should be connected to the intput in order to pull POK high. If the nominal output voltage falls
below 90%, the POK signal will be asserted low by an internal 4mA pull-down transistor.
Over-Current Protection (OCP)
The current limit function is achieved by sensing the peak current flowing through the topside power PFET.
When the sensed current exceeds the over current trip point (see Electrical Characteristics Table), both power
FETs are turned off for the remainder of the switching cycle. If the over-current condition is removed, the over-
current protection circuit will enable normal PWM operation. If the over-current condition persists, the soft
start capacitor will gradually discharge causing the output voltage to fall. When the OCP fault is removed, the
output voltage will ramp back up to the desired voltage. This cycle can continue indefinitely as long as the over
current condition persists. The OCP circuit will disable operation and protect the device from excessive current
during operation without compromising the full load capability of the device.
Thermal Protection
The thermal shutdown circuit disables the device operation (switching stops) when the junction temperature
exceeds 160°C. When the junction temperature drops by approximately 25°C, the converter will re-start with
a normal soft-start. By preventing operation at excessive temperatures, the thermal shutdown circuit will
protect the device from overstress.
Input Under-Voltage Lock-Out (UVLO)
When the device input voltage falls below UVLO, switching is disabled to prevent operation at insufficient
voltage levels. During startup, the UVLO circuit ensures that the converter will not start switching until the
input voltage is above the specified minimum voltage. Hysteresis and input de-glitch circuits are
incorporated in order to ensure high noise immunity and prevent a false trigger in the UVLO voltage region.
15043 August 10, 2018 Rev A
Datasheet | Intel® Enpirion® Power Solutions: EN6338QI
Page 17
APPLICATION INFORMATION
Output Voltage Setting
The EN6338QI output voltage is programmed using a simple resistor divider network (RA and RB). Figure 7
shows the resistor divider configuration.
Figure 7: VOUT Resistor Divider & Compensation Capacitor
The recommended RA resistor value is 200kΩ and the feedback voltage is typically 0.75V. Depending on the
output voltage (VOUT), the RB resistor value may be calculated as shown in Figure 7. Since the accuracy of the
output voltage setting is dependent upon the feedback voltage and the external ressitors, 1% or better
resistors are recommended. The external compensation capacitor (CA) is also required in parallel with RA.
Depending on input and output voltage, the recommended external compensation values are shown in Table
1.
Table 1: External Compensation Recommendations
VIN VOUT RB CA RA COUT (0805)
2.7V – 6.6V
0.75V OPEN 27pF
200kΩ 2 x 22µF
0.9V 1MΩ 27pF
1.0V 604kΩ 22pF
1.2V 332kΩ 22pF
1.5V 200kΩ 18pF
1.8V 143kΩ 18pF
2.5V 84.5kΩ 15pF
3.3V 59kΩ 15pF
VOUT
VOUT
PGND
VFB
R
A
C
A
C
OUT
V
FB
= 0.75V
EN6338QI
R
B
R
A
0.75V
0.75V
V
OUT
x
-
=
AGND
(47µF – 400µF) (15pF – 68pF)200k
15043 August 10, 2018 Rev A
Datasheet | Intel® Enpirion® Power Solutions: EN6338QI
Page 18
Compensation and Transient Response
The EN6338QI uses an enhanced type III voltage mode control architecture. Most of the compensation is
internal, which simplifies the design. In some applications, improved transient performance may be desired
with additional output capacitors (COUT). In such an instance, the phase-lead capacitor (CA) can be adjusted
depending on the total output capacitance. Using Table 1 as the reference for CA, if COUT is increased, then the
CA should also be increased. The relationship is linearly shown below:
ΔCOUT ≈ +100µF ΔCA ≈ +10pF
As COUT increases and the CA value is adjusted, the device bandwidth will reach its optimization level (at around
1/10th of the switching frequency). As shown in Table 1, the recommended CA value is lower for the 5V input
than 3.3V input. This is to ensure that the loop bandwidth is not over extended due to the increased gain at
the higher input voltage range. The CA value may be extrapolated for other input voltages. The limitation for
adjusting the compensation is based on diminished return. Further adjustments by increasing COUT and
increasing CA may not yield better transient response or in some situations cause lower gain and phase margin.
Over compensating with excessive output capacitance may also cause the device to trigger current limit on
startup due to the energy required to charge the output up to regulation level. Due to such limitations, the
recommended maximum output capacitance (COUT_MAX) is 400µF and the recommended maximum phase-lead
capacitance (CA_MAX) is 68pF. Note that lower output voltages can accommodate a higher Ca value.
Input Capacitor Selection
The input of synchronous buck regulators can be very noisy and should be decoupled properly in order to
ensure stable operation. In addition, input parasitic line inductance can attribute to higher input voltage ripple.
The EN6338QI requires a minimum of 2 x 10µF 0805 or 1 x 22µF 1206 size with sufficient voltage rating. As
the distance of the input power source to the input of the EN6338QI is increased, it is recommended to
increase input capacitance in order to mitigate the line inductance from the source. Low-ESR ceramic
capacitors should be used. The dielectric must be X5R or X7R rated and the size must be at least 0805 (EIA)
due to derating. Y5V or equivalent dielectric formulations must not be used as these lose too much
capacitance with frequency, temperature and bias voltage. In some applications, lower value capacitors are
needed in parallel with the larger capacitors in order to provide high frequency decoupling. Larger electrolytic
or tantalum bulk capacitors may be used in conjunction to increase total input capacitance but should not be
used solely as a replacement for the ceramic capacitors.
Table 3: Recommended Minimum Input Capacitors
DESCRIPTION MFG P/N
10µF ±20%, 10V
X5R, 0805
Taiyo Yuden LMK212BJ106KG-T
Murata GRM21BR61A106KE19L
TDK C2012X5R1A106M125AB
22µF ±20%, 10V
X5R, 1206
Taiyo Yuden LMK316BJ226ML-T
Murata GRM31CR61A226ME19L
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Datasheet | Intel® Enpirion® Power Solutions: EN6338QI
Page 19
Output Capacitor Selection
The output ripple of a synchronous buck converter can be attributed to its inductance, switching frequency
and output decoupling. The EN6338QI requires a minimum of 2 x 22µF 0805 output capacitors or 1 x 47µF
1206 size. Low ESR ceramic capacitors should be used. The dielectric must be X5R or X7R rated and the size
must be at least 0805 (EIA) due to derating. Y5V or equivalent dielectric formulations must not be used as
these lose too much capacitance with frequency, temperature and bias voltage.
Table 4: Recommended Output Capacitors
DESCRIPTION MFG P/N
22µF ±20%, 10V
X5R, 0805
Taiyo Yuden LMK212BBJ226MG-T
Murata GRM21BR61A226ME51
TDK C2012X5R1A226M125AB
47µF ±20%, 10V
X5R, 1206
Taiyo Yuden JMK316BJ476ML-T
Murata GRM31CR60J476ME19L
TDK C3216X5R1A476M160AB
Output ripple voltage is determined by the aggregate output capacitor impedance. Output impedance,
denoted as Z, is comprised of effective series resistance (ESR) and effective series inductance (ESL):
Z = ESR + ESL
The resonant frequency of a ceramic capacitor is inversely proportional to the capacitance. Lower capacitance
corresponds to higher resonant frequency. When two capacitors are placed in parallel, the benefit of both are
combined. It is beneficial to decouple the output with capacitors of various capacitance and size. Placing them
all in parallel reduces the impedance and will hence result in lower output ripple.
n
Total
ZZZ
Z1
...
111
21
+++=
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Datasheet | Intel® Enpirion® Power Solutions: EN6338QI
Page 20
THERMAL CONSIDERATIONS
Thermal considerations are important elements of power supply design. Whenever there are power losses in
a system, the heat that is generated by the power dissipation needs to be taken into account. The Intel Enpirion
PowerSoC technology helps alleviate some of those concerns.
The EN6338QI DC-DC converter is packaged in a 3.75mm x 3.75mm x 1.9mm 19-pin aEASI package. The aEASI
package is constructed with copper lead frames that have exposed thermal pads. The exposed thermal pad
on the package should be soldered directly on to a copper ground pad on the printed circuit board (PCB) to
act as a heat sink. The recommended maximum junction temperature for continuous operation is 125°C.
Continuous operation above 125°C may reduce long-term reliability. The device has a thermal overload
protection circuit designed to turn off the device at an approximate junction temperature value of 160°C.
The following example and calculations illustrate the thermal performance of the EN6338QI with the following
parameters:
VIN = 5V
VOUT = 3.3V
IOUT = 3A
First, calculate the output power.
POUT = VOUT x IOUT = 3.3V x 3A = 9.9W
Next, determine the input power based on the efficiency (η) shown in Figure 8.
Figure 8: Efficiency vs. Output Current
For VIN = 5V, VOUT = 3.3V at 3A, η ≈ 94.3%
η = POUT / PIN = 94.3% = 0.943
PIN = POUT / η
PIN ≈ 9.9W / 0.943 ≈ 10.5W
0
10
20
30
40
50
60
70
80
90
100
0.01 0.1 110
EFFICIENCY (%)
OUTPUT CURRENT (A)
LLM Efficiency vs. Output Current
VOUT = 3.3V LL M
VOUT = 3.3V P WM
CONDITIONS
VIN = 5V
LLM
PWM
15043 August 10, 2018 Rev A
Datasheet | Intel® Enpirion® Power Solutions: EN6338QI
Page 21
The power dissipation (PD) is the power loss in the system and can be calculated by subtracting the output
power from the input power.
PD = PIN – POUT
= 10.5W – 9.9W ≈ 0.6W
With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA
value (θJA). The θJA parameter estimates how much the temperature will rise in the device for every watt of
power dissipation. The EN6338QI has a θJA value of 30°C/W without airflow.
Determine the change in temperature (ΔT) based on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 0.6W x 30°C/W ≈ 18°C
The junction temperature (TJ) of the device is approximately the ambient temperature (TA) plus the change in
temperature. We assume the initial ambient temperature to be 25°C.
TJ = TA + ΔT
TJ ≈ 25°C + 18°C ≈ 43°C
The maximum operating junction temperature (TJMAX) of the device is 125°C, so the device can operate at a
higher ambient temperature. The maximum ambient temperature (TAMAX) allowed can be calculated.
TAMAX = TJMAX – PD x θJA
≈ 125°C – 18°C ≈ 107°C
The maximum ambient temperature the device can reach is 107°C given the input and output conditions. Note
that the efficiency will be slightly lower at higher temperatures and this calculation is an estimate.
15043 August 10, 2018 Rev A
Datasheet | Intel® Enpirion® Power Solutions: EN6338QI
Page 22
APPLICATION CIRCUITS
Figure 9: Smallest Solution Size Application Circuit for VOUT = 1.8V
Figure 10: Improved Transient Response Application Circuit for VOUT = 1.8V
2x
10µF
0805
VOUT
AVIN
AGND
SS
PVIN
EN
PGND PGND
EN6338QI
10nF
VFB
PGTE BTMP
VDDB
BGND
47nF
47nF
15nF
2x
22µF
0805
10Ω
1.8V @ 3A
5V
200k18pF
143k
2x
10µF
0805
VOUT
AVIN
AGND
SS
PVIN
EN
PGND PGND
EN6338QI
10nF
VFB
PGTE BTMP
VDDB
BGND
47nF
47nF
15nF
2x
22µF
0805
10Ω
1.8V @ 3A
5V
3x
100µF
0805
47pF
200k
143k
15043 August 10, 2018 Rev A
Datasheet | Intel® Enpirion® Power Solutions: EN6338QI
Page 23
LAYOUT RECOMMENDATIONS
Figure 11 shows critical components and layer 1 traces of a recommended minimum footprint EN6338QI
layout. EN and other small signal pins need to be connected and routed according to specific customer
application. Visit the Enpirion Power Solutions website at www.altera.com/powersoc for more information
regarding layout. Please refer to this Figure 11 while reading the layout recommendations in this section.
Figure 11: Top PCB Layer Critical Components and Copper for Minimum Footprint (Top View)
Recommendation 1: The input and output filter capacitors should be placed on the same side of the PCB, and
as close to the EN6338QI package as possible. The filter capacitors should be connected to the device with
very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the
respective nodes. The Voltage and GND traces between the capacitors and the EN6338QI should be as close
to each other as possible so that the gap between the two nodes is minimized, even under the capacitors.
Recommendation 2: The system ground plane should be on the 2nd layer (below the surface layer). This
ground plane should be continuous and un-interrupted.
Recommendation 3: The ground thermal pad underneath the device must be connected to the system ground
plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias must
have at least 1-oz. copper plating on the inside wall, making the finished hole size around 0.2mm to 0.26mm.
Do not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the
path for heat dissipation from the converter. Please see Figure 11.
Recommendation 4: Multiple small vias (the same size as the thermal vias discussed in recommendation 4
should be used to connect ground terminal of the input capacitor and output capacitors to the system ground
15043 August 10, 2018 Rev A
Datasheet | Intel® Enpirion® Power Solutions: EN6338QI
Page 24
plane. Put the vias under the capacitors along the edge of the GND copper closest to the Voltage copper.
Please see Figure 11. These vias connect the input/output filter capacitors to the GND plane, and help reduce
parasitic inductances in the input and output current loops. If the vias cannot be placed under CIN and COUT,
then put them just outside the capacitors along the GND slit separating the two components. Do not use
thermal reliefs or spokes to connect these vias to the ground plane.
Recommendation 5: AVIN is the power supply for the internal small-signal control circuits. It should be
connected to the input voltage at a quiet point. In Figure 11 this connection is made at the input capacitor
furthest from the PVIN pin and on the input source side. Avoid connecting AVIN near the PVIN pin even though
it is the same node as the input ripple is higher there.
Recommendation 6: The VOUT sense point should be connected at the last output filter capacitor furthest from
the VOUT pins (near C6). Keep the sense trace as short as possible in order to avoid noise coupling into the
control loop.
Recommendation 7: Keep RA, CA, RC and RB close to the VFB pin (see Figure 11). The VFB pin is a high-
impedance, sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect RB
directly to the AGND pin instead of going through the GND plane. The AGND should connect to the PGND at a
single point from the AGND pin to the PGND plane on the 2nd layer.
15043 August 10, 2018 Rev A
Datasheet | Intel® Enpirion® Power Solutions: EN6338QI
Page 25
Figure 12: Landing Pattern with Solder Stencil (Top View)
The solder stencil aperture for the thermal PGND pad is shown in Figure 12 and is based on Enpirion power product
manufacturing specifications.
15043 August 10, 2018 Rev A
Datasheet | Intel® Enpirion® Power Solutions: EN6338QI
Page 26
PACKAGE DIMENSIONS
Figure 13: EN6338QI Package Dimensions
Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html
15043 August 10, 2018 Rev A
Datasheet | Intel® Enpirion® Power Solutions: EN6338QI
WHERE TO GET MORE INFORMATION
For more information about Intel® and Enpirion® PowerSoCs, visit:
www.altera.com/enpirion
© 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel
Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and
services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
* Other marks and brands may be claimed as the property of others.
Page 27
REVISION HISTORY
Rev Date Change(s)
A June, 2018 Initial Release
15043 August 10, 2018 Rev A