MICRON TECHNOLOGY INC MICRON iter elke aso MT4C4001J 1 MEG x 4DRAM DRAM T46-234AB 1 MEG x 4DRAM FAST PAGE MODE FEATURES * Industry standard x4 pinout, timing, functions and packages High-performance, CMOS silicon-gate process Single +5V +10% power supply Low power, 3mW standby; 225mW active, typical All inputs, outputs and clocks are fully TTL compatible 1,024-cycle refresh distributed across 16ms * Refresh modes: RAS-ONLY, CAS-BEFORE-RAS (CBR) and HIDDEN FAST PAGE MODE access cycle e*e8686068} OPTIONS MARKING Timing 60ns access -6 70ns access -7 80ns access -8 * Packages Plastic SOJT (300 mil) DJ Plastic TSOP (300 mil)* TG Plastic ZIP (350 mil) Zz NOTE: Available in die form (commercial or military) or military ceramic packages. Please consult factory for die data sheets or refer to Microns Military Data Book. * Operating Temperature, T , Commercial (0C to +70C) None Industrial (-40C to +85C) IT Part Number Example: MT4C4001JDJ-6 GENERAL DESCRIPTION . The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized ina x4 configu- ration. During READ or WRITE cycles, each bit is uniquely addressed through the 20 address bits, which are entered 10 bits (AO-A9) at a time. RAS is used to latch the first 10 bits and CAS the latter 10 bits. READ and WRITE cycles are selected with the WE input. A logic HIGH on WE dictates READ mode while a logic LOW on WE dictates WRITE mode. During a WRITE cycle, data in (D) is latched by the falling edge of WE or CAS, whichever occursiast. If WE goes LOW prior to CAS going LOW, the output pin(s) remain open (High-Z) until the next CAS cycle. If WE goes LOW after data reaches the output pin(s), The Qs are activated and retain the selected cell data as long as CAS remains low PIN ASSIGNMENT (Top View) 20-Pin SOJ 20-Pin ZIP 20-Pin TSOP (R-1) *Consult factory on availability of reverse pinout TSOP packages (regardless of WE or RAS). This late WE pulse results in a READ-WRITE cycle. The four data inputs and four data outputs are routed through four pins using common I/O, and pin direction is controlled by WE and OE. FAST PAGE MODE operations allow faster data opera- tions (READ, WRITE or READ-MODIFY-WRITE) within a row address (A0-A9) defined page boundary. The FAST PAGE'MODE cycle is always initiated with a row address strobed-in by RAS followed by a column address strobed- in by CAS. CAS may be toggled-in by holding RAS LOW and strobing-in different column addresses, thus executing faster memory cycles. Returning RAS HIGH terminates the FAST PAGE MODE operation. Returning RAS and CAS HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for thenext cycle during the RAS high time. Memory cell data is retained in its correct state by maintaining power and executing any RAS cycle (READ, WRITE, RAS-ONLY, CAS-BEFORE-RAS (CBR) or HIDDEN refresh) so that all 1,024 combinations of RAS addresses (A0-A9) are executed atleastevery 16ms, regard- less of sequence. The CBR refresh cycle will invoke the internal refresh counter for automatic RAS addressing. MT4C40010 REV. 4/92 1-133 Micron Technology, Inc., reserves the tight to change products or specifications without notice. 1992, Micron Technology, Inc. SSE D MM 6111549 0004294 949 BEMRN INVMICRON TECHNOLOGY IVa INC 55E D MM 6113549 0004295 485 MEMRN vat 1 MEG x 4DRAM we CAS AO Al Ag Aa AS AG AT Ag TRUTH TABLE NO. 2 CLOCK GENERATOR COLUMN ADDRESS BUFFER REFRESH REFRESH COUNTER ROW ADDRESS BUFFERS NO. 4 CLOCK GENERATOR CONTROLLER T-46-23-18 FUNCTIONAL BLOCK DIAGRAM FAST PAGE MODE DATA IN BUFFER Dai paz Das "EARLY-WRITE baa DETECTION CIRCUIT DATA OUT BUFFER COLUMN DECODER ~ Veo 1024 * Ves SENSE 1024 x 4 MEMORY ARRAY ROW DECODER 3 tS cS *NOTE: WE LOW prior io CAS LOW, EW detection circuit output is a HIGH (EARLY-WRITE) TAS LOW prior to WE LOW, EW detection circuit output is a LOW (LATE-WRITE) ADDRESSES DATA IN/OUT FUNCTION RAS tAS WE OE 'R c DO1-D04 Standby H H-X Xx x Xx x High-Z READ L L H AL ROW COL Data Out EARLY-WRITE L L L xX ROW COL Data In READ-WRITE L L HL L-H ROW COL | Data Out, Data In FAST-PAGE-MODE | 1st Cycle L HL H L ROW COL Data Out READ . 2nd Cycle L HL H L n/a COL Data Out FAST-PAGE-MODE | ist Cycle L HoL L ROW COL Data In EARLY-WRITE 2nd Cycle Loo} Heb L X n/a | COL Data In FAST-PAGE-MODE | ist Cycle L H=L HL L-H ROW COL | Data Out, Data in READ-WRITE 2nd Cycle L H>L Hoi L-H n/a COL | Data Out, Data In RAS-ONLY REFRESH L H X X ROW n/a High-Z HIDDEN READ L-H=L L H L ROW COL - Data Out REFRESH WRITE L>H-L L L X ROW COL ~ Data In CAS-BEFORE-RAS REFRESH H=L L H x xX x High-Z MTac4001d REV. 4/92 Micron Technology, Inc., raserves the right 1a change products or specifications without notice. 1992, Micran Technology, Inc.MICRON TECHNOLOGY INC S5E D MM 63433549 ooo0425b 24) MENMRN MT4C4001J 1 MEG x 4 DRAM 1-46-23-1g ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under Absolute Maxi- Voltage on Any Pin Relative to VSS westerns -1V to +7V "mum Ratings may cause permanent damage to the device. Operating Temperature, T, (Ambient) ......... 0C to +70C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification isnotimplied. Exposure to absolute maximum rating conditions for ex- tended periods may affect reliability. Storage Temperature (Plastic) Power Dissipation ..........-00- Short Circuit Output Current VHC | ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (Notes: 1, 3, 4, 6, 7) (Vcc = 5V +10%) PARAMETER/CONDITION SYMBOL | MIN | MAX | UNITS | NOTES Supply Voltage Voo 45 | 55 v 1 Input High (Logic 1) Voltage, All Inputs VIH 2.4 | Vec+1 Vv 1 Input Low (Logic 0) Voltage, All Inputs . VIL -1.0 | 08 V 1 INPUT LEAKAGE CURRENT Any Input OV < Vin < 6.5V It -2 2 pA (All other pins not under test = OV) OUTPUT LEAKAGE CURRENT (Q is disabled, OV < Vout < 5.5V) loz -10 10 HA OUTPUT LEVELS Vou 2.4 , Vv Output High Voltage (lout = -5mA) Output Low Voltage (lout = 4.2mA) VoL 0.4 Vv MAX PARAMETER/CONDITION SYMBOL - | -7 | -8 |UNITS | NOTES STANDBY CURRENT: (TTL) . . (RAS = CAS = Vin) lect 2 2 2 mA STANDBY CURRENT: (CMOS) (RAS = CAS = Other Inputs = Voc -0. 2V) Icc2 1 1 1 mA . OPERATING CURRENT: Random READ/WRITE . Average power supply current Icc3 110 | 100] 90 | mA 3,4 (RAS, CAS, Address Cycling: RC = RC (MIN)) OPERATING CURRENT: FAST PAGE MODE Average power supply current loca 80.) 70 | 60 | mA 3,4 (RAS = Vi, CAS, Address Cycling: 'PC = PC (MIN)) REFRESH CURRENT: RAS-ONLY Average power supply current : lecs 110 |} 100}; 90 | mA 3 (RAS Cycling, CAS = Vin: *RC = "RC (MIN)) REFRESH CURRENT: CAS-BEFORE-RAS mas eee power supply current Iece 110 | 100] 90 | mA 3,5 (RAS, CAS, Address Cycling: RC = 'RC (MIN)) MT4C4001J 1-135 Micron Technology, Inc., reserves the right to change products or specifications without notice. REV. 4/92 7 1992, Micron Technology, Inc.MICRON TECHNOLOGY INC SSE D MM 6131549 000429? 658 BRN MT4C4001J MICRON 1 MEG x 4 DRAM T-46-23-18 CAPACITANCE PARAMETER . SYMBOL | MIN MAX | UNITS | NOTES 0 Input Capacitance: A0-A9 . cu 5 pF 2 wu input Capacitance: RAS, CAS, WE, OE . Ciz 7 pF 2 = Input/Output Capacitance: DQ Clo 7 pF 2 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Voc = 5V +10%) AC CHARACTERISTICS 6 7 -8 PARAMETER SYM MIN MAX MIN MAX MIN MAX UNITS NOTES Random READ or WRITE cycle time 'RC 110 130 150 ns READ-WRITE cycle time RWC 145 185 205 ns FAST-PAGE-MODE tec 40 40 45 ns READ or WRITE cycle time FAST-PAGE-MODE 'IPRWC 90 95 100. ns READ-WRITE cycle time Access time from RAS TRAC 60 70 80 ns 14 Access time from CAS ICAC 15 20 . 20 ns 15 Output Enable OE 15 20 20 ns 23 Access time from column address TAA 30 35 40 ns Access time from CAS precharge CPA 35 40 45 ns RAS pulse width RAS 60 100,000 70 100,000 80 400,000 ns RAS pulse width (FAST PAGE MODE) tRASP 60 100,000 70 100,000 80 160,000 ns RAS hold time RSH 15 20 20 ns RAS precharge time AP 40 50 60 ns CAS pulse width CAS 15 100,000 20 100,000 20 100,000 ns CAS hold time cSH 60 70 80 ns CAS precharge time CPN 10 10 10 ns 16 CAS precharge time (FAST PAGE MODE){ CP 10 10 10 ns RAS to CAS delay time ACD 20 45 20 50 20 60 ns 17 CAS to RAS precharge time 'CRP 10 10 10 ns Row address setup time 'ASR 0 0 0 ns Row address hold time 'RAH 10 10 10 ns RAS to.column tRAD 15 30 | 15 35 15 40 ns 18 address delay time . Column address setup time ASC 0 0 0 ns | Column address hold time CAH 10 15 15 ns Column address hold time | tAR 50 55 60 ns (referenced to RAS) Column address to RAL 30 35 40 ns RAS lead time . Read command setup time 'RCS ) 0 ) ns Read command hold time 'RCH 0 0 0 ns 19 (referenced to CAS) Read command hold time 'RRH 0 0 0 ns 19 (referenced to RAS) CAS to output in Low-Z 1CLZ 0 0 0 ns Output buffer turn-off delay OFF - 0 15 0 20 0 20 ns 20 MT4C4001. : Micron Technology, Inc., reserves the right to change products or specifications without naties. 1-136 REV. 4/92 1992, Micron Technology, Inc.MICRON TECHNOLOGY INC 5S5E ) bLL15449 goow24a 594 BEMRN MT4C4001J 1 MEG x 4 DRAM | T-46-23-18 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vcc = 5V 410%) AC CHARACTERISTICS 6 7 8 PARAMETER SYM MIN MAX MIN MAX MIN | max [UNITS | Noves | JJ WE command setup time wcs 0 0 0 ns 21, 27 > Write command hold time 'WCH 10 15 15 ns = Write command hold time 'WCR 45 55 60 ns (referenced to RAS) . Write command pulse width twP 10 15 15 . ns Write command to RAS lead time 'RWL 15 20 20 ns Write command to CAS lead time 'CWL 15 20 20 ns Data-in setup time os 0 ) 0 ns 22 Data-in hold time DH 10 15 15 ns 22 Data-in hold time 'DHR 45 55 60 ns (referenced to RAS) : RAS to WE delay time 'RWD 85 100 110 ns 21 Column address tAWD 60 65 70 ns 21 to WE delay time . CAS to WE delay time ICWD 45 50 50 ns at. Transition time (rise or fall) tT 3 50 3 50 3 50 ns 9, 10 Refresh period (1,024 cycles) REF . 16 16 . 16 ms RAS to CAS precharge time tRPC 0 0 0 ns CAS setup time CSR 10 10 10 ns 5 (CAS-BEFORE-RAS refresh) . CAS hold time 'CHR 15 15 15 : ns 5 (CAS-BEFORE-RAS refresh) . WE hold time WRH 10 10 10 ns 25, 28 (CAS-BEFORE-RAS refresh) WE setup time 'WRP 10 10 10 ns 25, 28 (CAS-BEFORE-RAS refresh) WE hoid time WTH 10 10 10 Ff ns 25, 28 (WCBR test cycle) WE setup time wTs 10 10 10 ns 25, 28 (WCBR test cycle) OE setup prior to RAS during ORD 0 0 0 ns HIDDEN REFRESH cycle : : Output disable top 15 20 . 20 ns 27 OE hold time from WE during 'OEH 15 20 20 ns 26 READ-MODIFY-WRITE cycle . IMT4C40018 . 1 1 37 Micron Technology, inc., reserves the right to change products or specilications without notice. - 1992, Micron Technology, Inc.MICRON TECHNOLOGY INC Vdd Na amt TN Bice oR Ch A ed 5SE D) MM 6222549 0004299 420 MMRN Naeton ttn 1 MEG x 4 DRAM NOTES 1 2. 3. 4 10. 11. 12. 13, 14. 15. 16. 17. 18. All voltages referenced to Vss. . This parameter is sampled. Vcc = 5V +10%,f = 1 MHz. Icc is dependent on cycle rates. . Icc is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. Enables on-chip refresh and address counters. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is assured. . An initial pause of 100s is required after power-up followed by eight RAS refresh cycles (RAS-ONLY or CBR with WE HIGH) before proper device operation is assured. The eight RAS cycle wake-up should be repeated any time the 'REF refresh requirement is exceeded. AC characteristics assume 'T = 5ns. Vui (MIN) and Vit (MAX) are reference levels for measuring timing of input signals. Transition times are measured between Vin and Vit (or between VIL and Vin). In addition to meeting the transition rate specifica- tion, all input signals must transit between Vin and Vit. (or between Vit and Vin) in a monotonic manner. If CAS = Vin, data output is High-Z. If CAS = Vi, data output may contain data from the last valid READ cycle. Measured with a load equivalent to 2 TTL gates and 100pF. Assumes that RCD < *RCD (MAX). If RCD is greater than th maximum recommended value shown in this table, RAC will increase by the amount that RCD exceeds the value shown. , Assumes that RCD 2 RCD (MAX). If CAS is LOW at the falling edge of RAS, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data out buffer, CAS must be pulsed HIGH for 'CPN. ; Operation within the RCD (MAX) limit ensures that *RAC (MAX) can be met. "RCD (MAX) is specified as a reference point only; if RCD is greater than the specified RCD (MAX) limit, then access time is controlled exclusively by CAC. Operation within the RAD (MAX) limit ensures that tRAC (MIN) and tCAC (MIN) can be met. RAD (MAX) is specified as a reference point only; if RAD is greater than the specified RAD (MAX) limit, then access time is controlled exclusively by AA. T~46-23-18 _ 19. Either RCH or *RRH must be satisfied for a READ cycle. 20. OFF (MAX) defines the time at which the output achieves the open circuit condition, and is not referenced to Vou or VOL. 21. WCS, RWD, AWD and tCWD are not restrictive operating parameters. WCS applies to EARLY- WRITE cycles. *RWD, AWD and 'CWD apply to READ-MODIFY-WRITE cycles. If WCS = 'WCS (MIN), the cycle is an EARLY-WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If RWD 2 'RWD (MIN), tAWD > tAWD (MIN) and CWD 2 'CWD (MIN), the cycle is a READ-MODIFY-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of data out is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW results in a LATE-WRITE (OE controlled) cycle. 'WCS, RWD, CWD and tAWD are not applicable in a LATE-WRITE cycle. .22. These parameters are referenced to CAS leading edge in EARLY-WRITE cycles and WE leading edge in LATE-WRITE or READ-MODIFY-WRITE cycles. 23, If OF is tied permanently LOW, LATE-WRITE or READ-MODIFY-WRITE operations are not possible. 24. A HIDDEN REFRESH may also be performed after.a WRITE cycle. In this case, WE = LOW and OE = HIGH. 25. WTS and 'WTH are setup and hold specifications for the WE pin being held LOW to enable the JEDEC test mode (with CBR timing constraints). These two parameters are the inverts of tWRP and 'WRH in the CBR refresh cycle. 26, LATE-WRITE and READ-MODIFY-WRITE cycles must have both OD and OEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if CAS remains LOW and OE is taken back LOW after OEH is met. If CAS goes HIGH prior to OE going back LOW, the DQs will remain open. / 27. The DQs open during READ cycles once OD or OFF occur. If CAS goes HIGH first, OE becomes a dont care. If OF goes HIGH and CAS stays LOW, OE is nota dont care; and the DQs will provide the previously read data if OE is taken back LOW (while CAS remains LOW). 28. JEDEC test version only. MT4C40010 REV. 4/92 5 | 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. - 1992, Micron Technology, Inc.MICRON TECHNOLOGY INC S5E D MM 6111549 g004300 T?2 MEMRN Lh so e] N MT4C4001J 1 MEG x 4 DRAM T-46-23-18 READ CYCLE Vino fas vit > WVvYad om WHT Vv ADDR vi COLUMN wr Vin me ve - VALID DATA vi oe Oy! EARLY-WRITE CYCLE Vy ~ Ras vit cas (VIK - Vi = v ADOR vi : _ COLUMN We vik We yjH ba Wok VALID DATA, = WL, DON'T CARE BY unperinep MT4C40015 : . 1 9 Micton Technology, inc., reserves the right to change products or specifications without notice. REV. 4/92 -41 3 1992, Micron Technology, inc.MICRON TECHNOLOGY INC 5S5E D Mm 61441545 0004301 909 MMNRN MT4C4001J ele re em ee er T-46-23-18 READ-WRITE CYCLE (LATE-WRITE and READ-MODIFY-WRITE CYCLES) Vn - mas vit _ INVUC V = os YZ Vv appr yt COLUMN = Vv we yt po igh VALIDDoyy ff VALID Diy = (V co vit . FAST-PAGE-MODE READ CYCLE = FAS vi = as v ADDR yi COLUMN = Vi we Ye vi = va yiOH = V a Me DONT CARE RRQ unpered MT4Ca001J 1 1 4 0 Micron Technology, Inc., rasarves the right to change products or specifications without notice. REV. 4/92 > 1992, Micron Technolagy, Inc.MICRON TECHNOLOGY INC 55E D MM 6311549 0004302 645 MEMRN MICRON | Mere (lean 1 MEG x 4 DRAM T-46-23-18 FAST-PAGE-MODE EARLY-WRITE CYCLE a ae (VH ~ cas yt WVYad v ADDR vit COLUMN oe me te y De yiS# VALID DATA VALID DATA VALID DATA EM LEE. Hy, FAST-PAGE-MODE READ-WRITE CYCLE (LATE-WRITE and READ-MODIFY-WRITE CYCLES) a Vin =a - cas yi > vy appr vit COLUMN COLUMN _ vy me pa YIOH OPEN _ . | foo ; toe | toe} | toe | L_toen Mt LLL } . ZA vont care PC is for LATE-WRITE only. 3 UNDEFINED MTC40010 1-144 Micron Technology, Inc., reserves the right to change products or specifications without nolica, REV. 4/92 - 1992, Micron Technology, inc.MICRON TECHNOLOGY INC SSE D MM 6111549 0004303 741 MMR | MT4C4001J elem ee ear RAS-ONLY REFRESH CYCLE ~-46-23-18 (ADDR = A0-A9; WE = DON'T CARE) 0 tac BY = = Yc . > FAS vy | tone IRPg | = er Yu Gs yt Tt } x f tase "RAH as wom TDR en UTE TK pa YoH = OPER CAS-BEFORE-RAS REFRESH CYCLE (AO-AQ, and OE = DONT CARE) tap, tras : < Va RS vit S q RPC. % fopn | csr tcHR < Vino os YT pa = 01 wre] |_!wRH twrp] | {WRH, wet LL CLL Li LLL HIDDEN REFRESH CYCLE ** (WE = HIGH; OF = LOW) (READ) (REFRESH) == ViH- Ras yi CAS ADDA COLUMN: ca y{Q8 = VALID DATA CF iE DON'T CARE under Ineo MT4C4001, Micron Technology, Inc., resarves the right to change products or Specificalions without notice. REV. 4/92 - 1-142 1992, Micron Tachnology, Inc.MICRON TECHNOLOGY INC MICRON Bisel sel Reler a Te ne Ter. Tale | 1 MEG x 4 DRAM 4 MEG POWER-UP AND REFRESH CONSTRAINTS The EIA /JEDEC 4 Meg DRAM introduces two potential incompatibilities compared to the previous generation 1 Meg DRAM. The incompatibilities involve refresh and power-up. Understanding these incompatibilities and pro- viding for them will offer the designer and system user greater compatibility between the 1 Meg and 4 Meg. REFRESH The most commonly used refresh mode of the 1 Meg is the CBR (CAS-BEFORE-RAS) REFRESH cycle. The CBR for the 1 Meg specifies the WE pin as a dontcare. The 4 Meg, on the other hand, specifies the CBR REFRESH mode with the WE pin held at a voltage HIGH level. A CBR cycle with WE LOW will put the 4 Meg into the JEDEC specified test mode (WCBR). WCBR TEST MODE: WE ) 4MEG DRAM CBR REFRESH: WE YH 7, 46-23-18 POWER-UP 1-46-23 The 4 Meg JEDEC test mode constraint may introduce another problem. The 1 Meg POWER-UP cycle requires a 100ps delay followed by any eight RAS cycles. The 4 Meg POWER -UP is more restrictive in that eight RAS-ONLY or CBR REFRESH (WE held HIGH) cycles must be used. The restriction is needed since the 4 Meg may power-up in the JEDEC specified test mode and must exit out of the test mode. The only way to exit the 4 Meg JEDEC test mode is witheithera RAS-ONLY oraCBR REFRESH cycle (WEheld HIGH). SUMMARY i. The 1 Meg CBR REFRESH allows the WE pin to be dont care while the 4 Meg CBR requires WE to be HIGH. 2. The eight RAS wake-up cycles on the 1 Meg may be any valid RAS cycle while the 4 Meg may only use RAS- ONLY or CBR REFRESH cycles (WE held HIGH). 1MEG DRAM ee MMM DON'T CARE COMPARISON OF 4 MEG TEST MODE AND WCER TO 1 MEG CBR MTSC4aatJ REV. 4/92 1-143 Micron Technology, Inc., raserves the right ta change products or spacificalions without notice. 1992, Micron Technology, Inc. 55E D MM 6121549 0004304 418 BNRN Wvud