Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Block Diagram
Pin Configuration
Recommended Application:
VIA Mobile PL133T and PLE133T Chipsets.
Output Features:
• 2 - CPU clocks @ 2.5V
• 1 - Pairs of differential CPU clocks @ 3.3V
• 7 - PCI including 1 free running @ 3.3V
• 7 - SDRAM @ 3.3V
• 1 - 48MHz @ 3.3V fixed
• 1 - 24_48MHz selectable @ 3.3V
• 2 - REF @ 3.3V, 14.318MHz
Features/Benefits:
• Programmable output frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz crystal.
Key Specifications:
•CPU Output Jitter <200ps
• CPU Output Skew <175ps
• PCI to PCI Output Skew <500ps
Programmable Timing Control Hub™ for PII/III™
* Inter nal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
48-Pin SSOP & TSSOP
GND
*FS2/REF1
REF0
Vtt_PWRGD#
VDDREF
GND
X1
X2
VDDPCI
*FS4/PCICLK_F
*FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
SDRAM_IN
*CPU_STOP#
*PCI_STOP#
*PD#
**MULTISEL
GND
SDATA
CPUCLK0
CPUCLK1
VDDCPU_2.5
VDDCPU_3.3
CPUCLKT
CPUCLKC
GND
RESET#
I REF
SDRAM6
GND
SDRAM0
SDRAM1
VDDSDRAM
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDRAM
AVDD48
48MHz/FS0*
24_48MHz/FS1*
SCLK
ICS950602
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Host Swing Select Functions
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2
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Pin Description
The ICS950602 is a single chip clock solution for VIA Mobile PL133T and PLE133T chipsets. It provides all necessar y clock
signals for such a system.
The ICS950602 is par t of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With
all these programmable features, ICS' TCH makes motherboard testing, tuning and improvement very simple.
General Description
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3
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
General I2C serial interface information
How to Write:
•Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
*See notes on the following page.
ICS (Slave/Receiver)
T
WR ACK
ACK
ACK
ACK
ACK
PstoP bit
X Byte
Index Bloc k Write Ope ration
Slave Address D2(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3(H)
Index Block Read Operation
Slave Address D2(H)
Beginning Byte = N ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
4
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Byte 0: Functionality and frequency select register (Default=0)
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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00001 00.09100.83daerpsretnec%52.0-/+
00010 00.08100.63daerpsretnec%52.0-/+
00011 00.07100.43daerpsretnec%52.0-/+
00100 00.66102.33daerpsretnec%52.0-/+
00101 00.06100.23daerpsretnec%52.0-/+
00110 00.05105.73daerpsretnec%52.0-/+
00111 00.54103.63daerpsretnec%52.0-/+
01000 00.04100.53daerpsretnec%52.0-/+
01001 00.63100.43daerpsretnec%52.0-/+
01010 00.03105.23daerpsretnec%52.0-/+
01011 00.42100.13daerpsretnec%52.0-/+
01100 02.7606.33daerpsretnec%52.0-/+
01101 09.00136.33daerpsretnec%52.0-/+
01110 00.81103.93daerpsretnec%52.0-/+
01111 04.43106.33daerpsretnec%52.0-/+
10000 00.7605.33daerpsretnec%52.0-/+
1000 1 05.00105.33daerpsretnec%52.0-/+
10010 00.51103.83daerpsretnec%52.0-/+
10011 09.33174.33daerpsretnec%52.0-/+
10 100 08.6604.33daerpsretnec%52.0-/+
10 10 1 02.00104.33daerpsretnec%52.0-/+
10 110 00.01107.63daerpsretnec%52.0-/+
10 111 06.33104.33daerpsretnec%52.0-/+
11000 00.50100.53daerpsretnec%52.0-/+
11001 00.0900.03daerpsretnec%52.0-/+
11010 00.5803.82daerpsretnec%52.0-/+
11011 00.8700.93daerpsretnec%52.0-/+
11100 06.6603.33daerpsretnec%52.0-/+
11101 00.00103.33daerpsnwod%5.0-ot0
11110 00.5705.73daerpsretnec%52.0-/+
11111 03.33103.33daerpsnwod%5.0-ot0
3tiB stupnidehctal,tceleserawdrahybdetcelessiycneuqerF-0 4:7,2tiBybdetcelessiycneuqerF-1 0
0tiB lamroN-0 elbanemurtcepsdaerpS-1 0
7tiB stupnihctalybdetceleseblliwycneuqerfefasgodhctaW-0 )0:4(tib01etyBybdemmargorpeblliwycneuqerfefasgodhctaW-1 0
5
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Byte 4: Output Control Register
(1 = enable, 0 = disable)
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7tiB-X kcabdaeR4SF
6tiB-X kcabdaeR3SF
5tiB-X kcabdaeR2SF
4tiB-X kcabdaeR1SF
3tiB-X kcabdaeR0SF
2tiB841 0KLCUPC
1tiB741 1KLCUPC
0tiB34,441 CKLCUPC,TKLCUPC
tiB#niPDWPnoitpircseD
7tiB931 6MARDS
6tiB011 F_KLCICP
5tiB711 5KLCICP
4tiB611 4KLCICP
3tiB511 3KLCICP
2tiB411 2KLCICP
1tiB311 1KLCICP
0tiB111 0KLCICP
tiB#niPDWPnoitpircseD
7tiB-0 elbasiD=0,elbanE=1tcetedtfihsraegTESER
6tiB-0 84=1,42=0:84_42LES
5tiB721 zHM84
4tiB621 zHM84_42
3tiB-0 devreseR
2tiB03,131 )5:4(MARDS
1tiB33,431 )3:2(MARDS
0tiB63,731 )1:0(MARDS
tiB#niPDWPnoitpircseD
7tiB-X kcabdaeRLESTLUM
6tiB-X devreseR
5tiB-X devreseR
4tiB-X devreseR
3tiB-X devreseR
2tiB-X devreseR
1tiB-X devreseR
0tiB-X devreseR
6
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Byte 7: Byte Count Read Back Register
Byte 8: Vendor ID Register
Byte 5: Output Control Register
(1 = enable, 0 = disable)
Byte 6: Reserved Register
(1 = enable, 0 = disable)
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7tiB7etyB0
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6tiB6etyB0
5tiB5etyB0
4tiB4etyB0
3tiB3etyB1
2tiB2etyB1
1tiB1etyB1
0tiB0etyB1
tiBemaNDWPnoitpircseD
7tiB3tiBDInoisiveRX
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6tiB2tiBDInoisiveRX
5tiB1tiBDInoisiveRX
4tiB0tiBDInoisiveRX
3tiB3tiBDIrodneV0)devreseR(
2tiB2tiBDIrodneV0)devreseR(
1tiB1tiBDIrodneV0)devreseR(
0tiB0tiBDIrodneV1)devreseR(
tiB#niPDWPnoitpircseD
7tiB-0 devreseR
6tiB-0 devreseR
5tiB-0 devreseR
4tiB-0 devreseR
3tiB-0 devreseR
2tiB-0 devreseR
1tiB-0 devreseR
0tiB-0 devreseR
tiB#niPDWPnoitpircseD
7tiB-0 devreseR
6tiB-0 devreseR
5tiB-0 devreseR
4tiB-0 ,lortnocgninnureerF0KLCUPC gninnureerF=1gninnureerftoN=0
3tiB-0 ,lortnocgninnureerF1KLCUPC gninnureerF=1gninnureerftoN=0
2tiB-0 ,lortnocgninnureerFC/TKLCUPC gninnureerF=1gninnureerftoN=0
1tiB211FER
0tiB310FER
7
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Byte 10: Programming Enable bit 8 Watchdog Control Register
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Byte 9: Watchdog Timer Count Register
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7tiB7DW0
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6tiB6DW0
5tiB5DW0
4tiB4DW1
3tiB3DW0
2tiB2DW0
1tiB1DW0
0tiB0DW0
tiBemaNDWPnoitpircseD
7tiB8vidNX 8tibredividN
6tiB6vidMX
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5tiB5vidMX
4tiB4vidMX
3tiB3vidMX
2tiB2vidMX
1tiB1vidMX
0tiB0vidMX
tiBemaNDWPnoitpircseD
7tiB7vidNX
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6tiB6vidNX
5tiB5vidNX
4tiB4vidNX
3tiB3vidNX
2tiB2vidNX
1tiB1vidNX
0tiB0vidNX
tiBemaNDWPnoitpircseD
7tiB margorP elbanE 0tibelbanEgnimmargorP 10etyBrosehctalWHybdetceleseraseicneuqerF.gnimmargorpon=0 Illaelbane=
2
.gnimargorpC
6tiBelbanEDW0 .tibelbanEgodhctaW .elbanE=1,elbasid=0.eulavdehctalNEDWetirwrevolliwtibsihT
5tiBmralADW0 sutatsmrala=1lamron=0sutatSmralAgodhctaW
4tiB4FS1
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3tiB3FS1
2tiB2FS1
1tiB1FS1
0tiB0FS1
8
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Byte 14: Spread Spectrum Control Register
Byte 13: Spread Spectrum Control Register
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7tiB7SSX
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6tiB6SSX
5tiB5SSX
4tiB4SSX
3tiB3SSX
2tiB2SSX
1tiB1SSX
0tiB0SSX
tiBemaNDWPnoitpircseD
7tiBdevreseRXdevreseR
6tiBdevreseRXdevreseR
5tiBdevreseRXdevreseR
4tiB21SSX 21tiBmurtcepSdaerpS
3tiB11SSX 11tiBmurtcepSdaerpS
2tiB01SSX 01tiBmurtcepSdaerpS
1tiB9SSX 9tiBmurtcepSdaerpS
0tiB8SSX 8tiBmurtcepSdaerpS
9
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses abov e those listed under
Absolute Maximum Ratings
ma y cause permanent damage to the device. These r atings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Outpu t Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage VIH 2V
DD + 0.3 V
Input Low Voltage VIL VSS - 0.3 0.8 V
Input High Current IIH VIN = VDD -5 5 mA
IIL1 VIN = 0 V; Inputs wit h no pull-up resi s tors -5 mA
IIL2 VIN = 0 V; Inputs wit h pull-up res istors -200
CL = 0 pF; Select @ 67 MHz 100
CL =Full load, SDRAM not running 144 280
IREF = 2.32 mA 20
IREF = 5 mA 22 37
Input Fr equency FiVDD = 3.3 V 14.32 MHz
Pin Inductance L
p
in 7nH
CIN Logic Inputs 5 pF
COUT Output pin capacitance 6 pF
CINX X1 & X2 pins 27 45 pF
Transition time1Ttrans To 1st crossing of target frequency 3 ms
Settling time1TsF r om 1st cros s i ng to 1% target frequency 3 ms
Clk Stabilization1TSTAB From VDD = 3.3 V to 1% target frequency 3 ms
tPZH,tPZL Output enable delay (all outputs) 1 10 ns
tPHZ,tPLZ Output disable delay (all outputs) 1 10 ns
1Guaranteed by design, not 100% test ed in pro duc tion.
Delay1
Input Capacitance1
Input Low Current
Powerdown Current
Oper ating Supply
Current
IDD3.3PD mA
mA
IDD3.3OP
10
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Electrical Characteristics - CPUCLK(T,C)
TA = 0 - 70°C; VDD=3.3V +/-5%; loads from Intel CK408B spec, Rev 1.1 (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Current Source
Output Impedance1
Output High Voltage VOH2A 0.71 1.2 V
Output High Current IOH32A -13.92 mA
Rise Time1tr2A VOL = -0.35V, VOH = 0.35V 175 220 467 ps
Fall Time1tf2A VOH = 0.35V, VOL = -0.35V 175 230 467 ps
Differential Crossover
Voltage1V2A Rs = 33.2Ω, Rp = 63.4Ω to gnd, RT-C = 475Ω510 700 900 mV
Duty Cycle1dt2A VT = crossing point 45 49 55 %
VT (CPU) = crossing point, VT (PCI) = 1.25 V 100 MHz 250 300
133 MHz 170 200
Skew, CPUT ,C to PCI 1tsk2A1 VT (CPU) = crossing point, VT (PCI) = 1.5 V 23.24 ns
Jitter, Cycle to cycle1tjcyc-cyc2A VT = crossing point CPU,SD = 100MHz 50 200 ps
1Guaranteed by design, not 100% tested in production.
VR = 475Ω +1%; IREF = 2.32 mA; IOH = 6*IREF
Skew, CPUT,C to CP U1tsk2A ps
Ω
ZO2A VO = Vx3000
Electrical Characteristics - CPUCLK(1:0)
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Out
p
ut Im
p
edance1RDSP2B VO = VDD*(0.5) 13.5 45
Out
p
ut Im
p
edance1RDSN2B VO = VDD*(0.5) 13.5 45
Output High Voltage VOH2B IOH = -1 mA 2
Output Low Voltage VOL2B IOL = 1 mA 0.4
Output High Current IOH2B VOH@MIN = 1.0 V, VOH@MAX = 2.375 V -27 27
Output Low Current IOL2B VOL@MIN = 1.2 V, VOL@MIN = 0.3 V 27 30
Rise Time1tr2B VOL = 0.4V, VOH = 2.0V 0.7
Fall Tim e1tf2B VOH = 2.0V VOL = 0.4V 0.8
VT = 50% 100MHz 50
133 MHz 54
Skew, CPU to CPU1tsk2B VT = 1.25 V 60 175 ps
Skew, CPU to PCI1tsk2B1 VT (CPU) = 1.25 V, VT (PCI) = 1.5 V 23.24ns
VT = 1.25V CPU,SD = 100MHz 140 250
CPU,SD = 133 MHz 100 250
CPU = 100, SD = 133 MHz 220 275
1Guaranteed by design, not 100% tested in production.
0.4 1.6
V
Ω
V
ns
%
Jitter, Cycle to cycle1tjcyc-cyc2B ps
Duty Cycle1dt2B 45 55
11
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Electrical Characteristics - PCICLK
TA = 0 - 70°C; V DD=3.3V +/-5%; CL = 10-30 pF (unless ot herwise spec i fied)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Out put F requenc y F O1 33.33 MHz
Out put Im pedanc e RDSP11VO = VD
D
*(0.5) 12 55 Ω
Ou tp ut Hi gh Vo l tage V OH11IOH = -1 mA 2.4 V
Out put Low V ol tage V OL11IOL = 1 m A 0. 55 V
Out put Hi gh Current IOH11V OH@MIN = 1.0 V , V OH@MAX = 3. 135 V -33 -33 m A
Out put Low Current IOL11VOL @MIN = 1. 95 V, VOL @MAX = 0.4 V 30 38 m A
Ri se Ti me tr11VOL = 0.4 V , V OH = 2.4 V 0.5 2. 4 2.5 ns
Fall Time tf11VOH = 2. 4 V , V OL = 0.4 V 0.5 2.25 2.5 ns
Duty Cycle dt11V
T
= 1.5 V 45 53 55 %
Skew tsk11V
T
= 1.5 V 220 500 ps
Jitter,cycle to cycle tjcyc-cyc1VT = 1.5 V 300 450 ps
1Guarant eed by desi
g
n, not 100% tes ted i n product i on.
Electrical Characteristics - 48MHz, 24_48MHz
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Frequency FO3148 MHz
Output Impedance RDSP31VO = VDD*(0.5) 12 55 Ω
Output H igh Voltage VOH31IOH = -1 mA 2.4 V
Ou tput Low Vo ltage VOL31IOL = 1 mA 0.55 V
Output High Current IOH31V OH@MIN = 1.0 V, V OH@MAX = 3.135
V
-29 -23 mA
Output Low Current IOL31VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 27 mA
Rise Time tr3A1VOL = 0.4 V, VOH = 2.4 V 1 1.1 2 ns
Fall Time tf3B1VOH = 2.4 V, VOL = 0.4 V 1 1.25 2 ns
Duty Cycle dt3A1VT = 1.5 V 45 52 55 %
Jitter, cycle-to-cycle tjcyc-cyc3
1
VT = 1.5 V 200 350 ps
1Guaranteed by design, not 100% tested in production.
12
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Electrical Characteristi cs - SDRAM
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance1RDSP5 Vo=VDD*(0.5) 10 24 Ω
Output Impedance1RDSN5 Vo=VDD*(0.5) 10 24 Ω
Outp ut High Voltage VOH5 IOH = -1 mA 2.4 V
Output Low Voltage VOL5 IOL = 1 mA 0.4 V
VOH@MIN = 2 V -46
VOH@MAX = 3.135V -54
VOL@MIN = 1 V 54
VOL@MAX =0.4V 53
Rise Time tr51VOL = 0.4 V, VOH = 2.4 V 0.4 1.1 1.6 ns
Fal l Time tf51VOH = 2.4 V, VOL = 0.4 V 0.4 0.75 1.6 ns
Duty Cycle dt51VT = 1.5 V 45 50 55 %
Skew tsk51VT = 1.5 V 30 250 ps
Propagation delay
SDRAM_IN to
SDRAM tpdel51VT = 1.5 V 2.95 4 ns
1Guaranteed by design, not 100% tested in production.
Output High Current IOH5 mA
Output Low Curre nt IOL5 mA
Electrical Characteristics - REF
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Frequency FO4114.318 MHz
Output Impedance RDSP41VO = VDD*(0.5) 20 60 Ω
Output High Voltage VOH41IOH = -1 mA 2.4 V
Output Low Voltage VOL41IOL = 1 mA 0.4 V
Output High Current IOH41V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 -23 mA
Output Low Current IOL41VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 27 mA
Rise Time tr41VOL = 0.4 V, VOH = 2.4 V 1 1.85 4 ns
Fall Time tf41VOH = 2.4 V, VOL = 0.4 V 1 1.95 4 ns
Duty Cycle dt11VT = 1.5 V 45 55.7 56 %
Jitter, cycle-to-cycle tjcyc-cyc4
1
VT = 1.5 V 365 550 ps
1Guaranteed by design, not 100% tested in production.
13
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
8.2K
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
14
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
VCO Internal
0ns
12
25ns 50ns
CPU 100MHz
3.3V 66MHz
PCI 33MHz
APIC 16.7MHz
PD#
SDRAM 100MHz
REF 14.318MHZ
48MHZ
Integrated
Circuit
Systems, Inc.
15
ICS950602
0469B—12/18/02
Ordering Information
ICS950602yFT
Designation for tape and reel packaging
Packag e Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - T
300 mil SSOP Package
MIN MAX MIN MAX
A 2.41 2.80 .095 .110
A1 0.20 0.40 .008 .016
b 0.20 0.34 .008 .0135
c 0.13 0.25 .005 .010
D
E 10.03 10.68 .395 .420
E1 7.40 7.60 .291 .299
e
h 0.38 0.64 .015 .025
L 0.50 1.02 .020 .040
N
0° 8° 0° 8°
MIN MAX MIN MAX
48 15.75 16.00 .620 .630
10-0034
SYMBOL In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
SEE VARIATIONS SEE VARIATIONS
0.635 BASIC 0.025 BASIC
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS SEE VARIATIONS
ND mm. D (inch)
INDEX
AREA
INDEX
AREA
12
1 2
N
D
h x 45°
h x 45°
E1 E
α
SEATING
PLANE
SEATING
PLANE
A1
A
e
-C-
- C -
b
.10 (.004) C
.10 (.004) C
c
L
16
Integrated
Circuit
Systems, Inc.
ICS950602
0469B—12/18/02
Ordering Information
ICS950602yGT
Designation for tape and reel packaging
Packag e Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y G - T
6.10 mm. Body , 0.50 mm. pitch TSSOP
(240 mil) (20 mil)
MIN MAX MIN MAX
A--1.20--.047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
α0° 8° 0° 8°
aaa -- 0.10 -- .004
VARIATIONS
MIN MAX MIN MAX
48 12.40 12.60 .488 .496
10-0039
ND mm. D (inch)
Reference Doc.: JEDEC Publicat ion 95, MO-153
0.50 BASIC 0.020 BASIC
SEE VARIATIONS SEE VARIATIONS
SEE VARIATIONS SEE VARIATIONS
8.10 BASIC 0.319 BASIC
SYMBOL In Millim eters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1 E
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa
C