HV9110
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Features
► 10 to 120V input voltage range
► Current-mode control
► High efficiency
► Up to 1.0MHz internal oscillator
► Internal start-up circuit
► Low internal noise
► 50% maximum duty cycle
Applications
► DC/DC converters
► Distributed power systems
► ISDN equipment
► PBX systems
► Modems
General Description
The Supertex HV9110 is a BiCMOS/DMOS single-output,
pulse width modulator IC intended for use in high-speed,
high-efficiency switch mode power supplies. It provides all the
functions necessary to implement a single-switch current mode
PWM, in any topology, with a minimum of external parts.
Because the HV9110 utilizes Supertex’s proprietary BiCMOS/
DMOS technology, it requires less than one tenth of the operating
power of conventional bipolar PWM ICs, and can operate at
more than twice their switching frequency. The dynamic range
for regulation is also increased, to approximately 8 times that
of similar bipolar parts. It starts directly from any DC input
voltage between 10 and 120VDC, requiring no external power
resistor. The output stage is push-pull CMOS and thus requires
no clamping diodes for protection, even when significant lead
length exists between the output and the external MOSFET. The
clock frequency is set with a single external resistor.
Accessory functions are included to permit fast remote shutdown
(latching or nonlatching) and under voltage shutdown.
For similar ICs intended to operate directly from up to 450VDC
input, please consult the data sheets for the HV9120 and
HV9123.
For detailed circuit and application information, please refer to
application notes AN-H13 and AN-H21 to AN-H24.
High-Voltage Current-Mode PWM Controller
Functional Block Diagram
+
–
+
–
+
–
REF
GEN
+
–
+
–
Modulator
Comparator
OSC
R
S
Q
Current Limit
Comparator
COMP
OSC
IN
OSC
OUT
FB
VREF
BIAS
VDD
+VIN
Pre-regulator/Startup
8.6V
8.1V
Undervoltage
Comparator S
R
Q
VDD
-VIN
Error
Amplifier
4V
To
Internal
Circuits
1.2V
Current
Sources
To VDD
2V T Q
4
5
3
11
12
2
6
1
10
14 13 8 7
SHUTDOWN
RESET
SENSE
OUTPUT
2
HV9110
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
BIAS
OUTPUT
+VIN
SENSE
-VIN
FB
VDD
OSC OUT
SHUTDOWN
OSC IN
VREF
NC
RESET
COMP
Ordering Information
Device
14-Lead Narrow Body SOIC
8.65x3.90mm body
1.75mm height (max)
1.27mm pitch
HV9110 HV9110NG-G
Absolute Maximum Ratings
Parameter Value
Input voltage, VIN 120V
Logic voltage, VDD 15.5V
Logic linear input,
FB and sense input voltage -0.3V to VDD +0.3V
Storage temperature -65°C to +150°C
Power dissipation 750mW
Stresses beyond those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
-G indicates package is RoHS compliant (‘Green’)
Pin Configuration
Product Marking
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
HV9110NG
YWW LLLLLLLL
CCCCCCCCC AAA
14-Lead Narrow Body SOIC (NG)
14-Lead Narrow Body SOIC (NG)
Electrical Characteristics
(Unless otherwise specified, VDD = 10V, +VIN = 48V, -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ, TA = 25°C.)
Sym Parameter # Min Typ Max Units Conditions
Reference
VREF Output voltage
- 3.92 4.00 4.08
V
RL = 10MΩ
- 3.82 4.00 4.16 RL = 10MΩ,
TA = -55°C to 125°C
ZOUT Output impedance # 15 30 45 KΩ ---
ISHORT Short circuit current - - 125 250 μA VREF = -VIN
ΔVREF Change in VREF with temperature # - 0.25 - mV/°C TA = -55°C to 125°C
Oscillator
fMAX Oscillator frequency - 1.0 3.0 - MHz ROSC = 0MΩ
fOSC Initial accuracy1- 80 100 120 KHz ROSC = 330KΩ
- 160 200 240 ROSC = 150KΩ
- Voltage stability - - - 15 % 9.5V< VDD <13.5V
- Temperature coefficient # - 170 - ppm/°C TA = -55°C to 125°C
Notes:
# Guaranteed by design.
1. Stray capacitance on OSC In pin must be ≤5.0pF.
3
HV9110
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Electrical Characteristics (cont.)
(Unless otherwise specified, VDD = 10V, +VIN = 48V, -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ, TA = 25°C.)
Sym Parameter # Min Typ Max Units Conditions
PWM
DMAX Maximum duty cycle # 49.0 49.4 49.6 % ---
DMIN
Minimum duty cycle - - - 0 % ---
Maximum pulse width before
pulse drops out # - 80 125 ns ---
Current Limit
Maximum input signal - 1.0 1.2 1.4 V VFB = 0V
tDDelay to output # - 80 120 ns VSENSE = 1.5V, VCOMP ≤ 2.0V
Error Amplifier
VFB Feedback voltage - 3.96 4.00 4.04 V VFB shorted to COMP
IIN Input bias current - - 25 500 nA VFB = 4.0V
VOS Input offset voltage - nulled during trim - ---
AVOL Open loop voltage gain # 60 80 - dB ---
GB Unity gain bandwidth # 1.0 1.3 - MHz ---
ZOUT Out impedance # see Fig. 1 Ω ---
ISOURCE Output source current - -1.4 -2.0 - mA VFB = 3.4V
ISINK Output sink current - 0.12 0.15 - mA VFB = 4.5V
PSRR Power supply rejection # see Fig. 2 dB ---
Pre-regulator/Startup
+VIN Input voltage - 10 - 120 V IIN < 10µA; VCC > 9.4V
+IIN Input leakage current - - - 10 μA VDD > 9.4V
VTH
VDD pre-regulator turn-off
threshold voltage - 8.0 8.7 9.4 V IPREREG = 10µA
VLOCK Undervoltage lockout - 7.0 8.1 8.9 V ---
Supply
IDD Supply current - - 0.75 1.0 mA CL < 75pF
IQQuiescent supply current - - 0.55 - mA SHUTDOWN = -VIN
IBIAS Nominal bias current - - 20 - μA ---
VDD Operating range - 9.0 - 13.5 V ---
Note:
# Guaranteed by design.
4
HV9110
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Electrical Characteristics (cont.)
(Unless otherwise specified, VDD = 10V, +VIN = 48V, -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ, TA = 25°C.)
Shutdown Logic
tSD SHUTDOWN delay # - 50 100 ns CL = 500pF, VSENSE = -VIN
tSW SHUTDOWN pulse width # 50 - - ns
tRW RESET pulse width # 50 - - ns ---
tLW Latching pulse width # 25 - - ns SHUTDOWN and
RESET low
VIL Input low voltage - - - 2.0 V ---
VIH Input high voltage - 7.0 - - V ---
IIH Input current, input high voltage - - 1.0 5.0 μA VIN = VDD
IIL Input current, input low voltage - - -25 -35 μA VIN = 0V
Output
VOH Output high voltage
- VDD -0.25 - -
V
IOUT = 10mA
- VDD -0.3 - - IOUT = 10mA,
TA = -55°C to 125°C
VOL Output low voltage
- - - 0.2
V
IOUT = -10mA
- - - 0.3 IOUT = -10mA,
TA = -55°C to 125°C
ROUT Output resistance
Pull up - - 15 25 Ω IOUT = ±10mA
Pull down - - 8.0 20
Pull up - - 20 30 ΩIOUT = ±10mA,
TA = -55°C to 125°C
Pull down - - 10 30
tRRise time # - 30 75 ns CL = 500pF
tFFall time # - 20 75 ns CL = 500pF
Note:
# Guaranteed by design.
Sym Parameter # Min Typ Max Units Conditions
SHUTDOWN RESET Output
H H Normal operation
H H → L Normal operation, no change
L H Off, not latched
L L Off, latched
L → H L Off, latched, no change
Truth Table
5
HV9110
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Test Circuits
Detailed Description
Preregulator
The preregulator/startup circuit for the HV9110 consists of a
high-voltage, n-channel, depletion-mode, DMOS transistor
driven by an error amplifier to form a variable current path
between the VIN terminal and the VDD terminal. The maxi-
mum current (about 20mA) occurs when VDD = 0, with current
reducing as VDD rises. This path shuts off altogether when
VDD rises to somewhere between 7.8 and 9.4V, so that if VDD
is held at 10 or 12V by an external source (generally the
supply the chip is controlling), no current other than leakage
is drawn through the high voltage transistor. This minimizes
dissipation.
An external capacitor between VDD and VSS is generally
required to store energy used by the chip in the time be-
tween shutoff of the high voltage path and the VDD supply’s
output rising enough to take over powering the chip. This
capacitor should have a value of 100X or more the effective
gate capacitance of the MOSFET being driven, i.e.,
CSTORAGE ≥ 100 x (gate charge of FET at 10V)
as well as very good high frequency characteristics. Stacked
polyester or ceramic caps work well. Electrolytic capacitors
are generally not suitable.
A common resistor divider string is used to monitor VDD for
both the under voltage lockout circuit and the shutoff circuit
of the high voltage FET. Setting the under voltage sense
point about 0.6V lower on the string than the FET shutoff
point guarantees that the under voltage lockout always re-
leases before the FET shuts off.
Bias Circuit
An external bias resistor, connected between the BIAS pin
and VSS is required by the HV9110 to set currents in a se-
ries of current mirrors used by the analog sections of the
chip. The nominal external bias current requirement is 15 to
20µA, which can be set by a 390KΩ to 510KΩ resistor if a
10V VDD is used, or a 510kΩ to 680KΩ resistor if VDD will be
12V. A precision resistor is not required; ± 5% is fine.
Clock Oscillator
The clock oscillator of the HV9110 consists of a ring of
CMOS inverters, timing capacitors, and a frequency dividing
flip-flop. A single external resistor between the OSC IN and
OSC OUT is required to set the oscillator frequency (see
graph). One major difference exists between the Supertex
HV9110 and competitive 9110s. On the Supertex part, the
oscillator is shut off when a shutoff command is received.
This saves about 150µA of quiescent current, which aids in
the construction of power supplies that meet CCITT specifi-
cation I-430, and in other situations where an absolute mini-
mum of quiescent power dissipation is required.
+
–
Reference
V1
V2
0.1V swept 10Hz – 1MHz
0.1µF
10.0V
4.00V
100K1%
100K1%
PSRR
+
–
Reference V1V2
60.4K
40.2K
1.0V swept 100Hz – 2.2MHz
Tektronix
P6021
(1 turn
secondary)
0.1µF
+10V
(VDD)
GND
(–VIN)
(FB)
NOTE:
Set Feedback Voltage so that VCOMP = VDIVIDE ± 1.0mV before
connecting transformer
Error Amp ZOUT
6
HV9110
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Reference
The Reference of the HV9110 consists of a stable bandgap
reference followed by a buffer amplifier which scales the
voltage up to approximately 4.0V. The scaling resistors of
the reference buffer amplifier are trimmed during manufac-
ture so that the output of the error amplifier, when connected
in a gain of –1 configuration, is as close to 4.0V as possible.
This nulls out any input offset of the error amplifier. As a con-
sequence, even though the observed reference voltage of a
specific part may not be exactly 4.0V, the feedback voltage
required for proper regulation will be.
A ≈ 50KΩ resistor is placed internally between the output of
the reference buffer amplifier and the circuitry it feeds (refer-
ence output pin and non-inverting input to the error ampli-
fier). This allows overriding the internal reference with a low
impedance voltage source ≤6.0V. Using an external refer-
ence reinstates the input offset voltage of the error amplifier,
and its effect of the exact value of feedback voltage required.
Because the reference of the HV9110 is a high impedance
node, and usually there will be significant electrical noise
near it, a bypass capacitor between the reference pin and
VSS is strongly recommended. The reference buffer ampli-
fier is intentionally compensated to be stable with a capaci-
tive load of 0.01 to 0.1µF.
Error Amplifier
The error amplifier in the HV9110 is a true low-power dif-
ferential input operational amplifier intended for around the
amplifier compensation. It is of mixed CMOS-bipolar con-
struction: A PMOS input stage is used so the common mode
range includes ground and the input impedance is very high.
This is followed by bipolar gain stages which provide high
gain without the electrical noise of all-MOS amplifiers. The
amplifier is unity gain stable.
Current Sense Comparators
The HV9110 uses a true dual comparator system with in-
dependent comparators for modulation and current limiting.
This allows the designer greater latitude in compensation
design, as there are no clamps (except ESD protection) on
the compensation pin. Like the error amplifier, the compara-
tors are of low-noise BiCMOS construction.
Remote SHUTDOWN
The SHUTDOWN and RESET pins of the 9110 can be used
to perform either latching or non-latching shutdown of a con-
verter as required. These pins have internal current source
pull-ups so they can be driven from open drain logic. When
not used they should be left open, or connected to VDD.
Output Buffer
The output buffer of the HV9110 is of standard CMOS con-
struction (P-channel pull-up, N-channel pull-down). Thus the
body-drain diodes of the output stage can be used for spike
clipping if necessary, and external Schottky diode clamping
of the output is not required.
Shutdown Timing Waveforms
V
DD
50%
0
t
d
OUTPUT
SENSE
1.5V
0
t
SD
50%
90%90%
V
DD
OUTPUT
0
SHUTDOWN
V
DD
0
t
LW
50%
50%
t
SW
50%
50%
t
RW
RESET
0
V
DD
SHUTDOWN
0
V
DD
50%
t
R
, t
F
≤ 10ns
t
F
≤ 10ns
t
R
≤ 10ns
7
HV9110
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Typical Performance Curves
PSRR — Error Amplifier and Reference
1M10K100 100K1K10
Output Switching Frequency
vs. Oscillator Resistance
1M
100 k
10k
10k
R
OSC
(Ω)
)zH( f
TUO
80
70
60
50
40
30
20
10
0
-10
100 1K 10K
Error Amplifier
Open Loop Gain/Phase
100K 1M
)B
d
( ni
a
G
(
e
s
a
hP °)
180
120
60
0
-60
-120
-180
Frequency (Hz)
10
6
10
5
10
4
10
3
10
2
10
1
.1
10MHz
1MHz
100Hz 1KHz 10KHz
Error Amplifier Output Impedance (Z0)
100KHz
0
-10
-20
-30
-40
-50
-60
-70
-80
100k
1M
Bias Resistance (Ω)
10
7
10
6
10
5
1
(
tn
e
rru
C
sa
i
B µ )A
10
100
V
DD
= 10V
V
DD
= 12V
)
Bd
(
PSRR
Frequency (Hz)
Z
O
( Ω)
Frequency
Fig. 1
Fig. 2 Fig. 5
Fig. 3
Fig. 4
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com.
©2008 All rights reserved. Unauthorized use or reproduction is prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
8
HV9110
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV9110
A120308
14-Lead SOIC (Narrow Body) Package Outline (NG)
8.65x3.90mm body, 1.75mm height (max), 1.27mm pitch
Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1
Dimension
(mm)
MIN 1.35* 0.10 1.25 0.31 8.55* 5.80* 3.80*
1.27
BSC
0.25 0.40
1.04
REF
0.25
BSC
0O5O
NOM - - - - 8.65 6.00 3.90 - - - -
MAX 1.75 0.25 1.65* 0.51 8.75* 6.20* 4.00* 0.50 1.27 8O15O
JEDEC Registration MS-012, Variation AB, Issue E, Sept. 2005.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
Drawings are not to scale.
Supertex Doc. #: DSPD-14SOICNG, Version E101708.
D
Seating
Plane
Gauge
Plane
L
L1
L2
Top View
Side View View A-A
View B
View
B
θ1
θ
E1 E
AA2
A1
A
A
Seating
Plane
eb
h
h
14
1
Note 1
(Index Area
D/2 x E1/2)
Note 1
Note:
This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be:
a molded mark/identifier; an embedded metal marker; or a printed indicator.
1.
