SHARP | SPEC No. |] ELO9X134 | ISSUE: Oct 21 1997 To; SPECIFICATIONS Product Type 8Mbit Flash Memory LH28F800BGHE-TL85 Model No. (LHF 80B25) This specifications contains 49 pages including the cover and appendix. If you have any objections, please contact us before issuing purchasing order. CUSTOMERS ACCEPTANCE . DATE: BY: PRESENTED By: Shea T. MINOTO Dept. General Manager REVIEWED BY: PREPARED BY: 4 F . TO Flash Dept. 1 Menory Engineering Center Tenri Integrated Circuits Group SHARP CORPORATIONSHARP LHF80B25 @Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. @When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). eOffice electronics elnstrumentation and measuring equipment eMachine tools eAudiovisual equipment eHome appliance eCommunication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. Control and safety devices for airplanes, trains, automobiles, and other transportation equipment : eMainframe computers - eTraffic control systems eGas leak detectors and automatic cutoff devices eRescue and security equipment -eOther safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. eAerospace equipment eCommunications equipment for trunk lines eControl equipment for the nuclear power industry Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. @Please direct all queries regarding the products covered herein to a sales representative of the company. Rev. 1.0SHARP LHF80B25 1 CONTENTS PAGE PAGE 1 INTRODUCTION . 00000... eeseceeeeseeeeeeeceeeetteneeeenes 3 5 DESIGN CONSIDERATIONS ........00..0.. ccc 20 1.1 New Features... cccccsececscsssenssceesssererssneessseeee 3 5.1 Three-Line Output Control oo eeccceeseeeeseseees 20 1.2 Product OVErview.............:esccceseesecceesseeseeeseereees 3 5.2 RY/BY# and Block Erase and Word Write PONG... eee ecesesecseceneerteensnnsteceasersensessesenessenes 20 2 PRINCIPLES OF OPERATION................cc:ccccceseeree 7 5.3 Power Supply Decoupling............cccccccssssssesees 20 2.1 Data Protection 0... cee ccseecseseeseeseeeeseeeeseseee 8 5.4 Vpp Trace on Printed Circuit Boards.................. 20 5.5 Voc, Vpp, RP# Transitions... cece 21 3 BUS OPERATION. ...000.... cee ceeeceseeeeeeesseeseceeneeeeceeeaees 8 5.6 Power-Up/Down PFOLECTION .......eeeeseeeretereseneeeeees 21 B.1 ROA ooo... ceeceeeecceecesecceeaecnsecenseceeneceeeseoeeseaeeenneess 8 5.7 Power Dissipation ..........ccccsccsscsssseesseeressssnseace 21 3.2 Output Disable 00.0.0... cescseeeceserecesensensecesesseseass 8 3.3 Standby 2.0... ee ccessenceceseeesseeseeeseteeeeeateneereesneses 8 6ELECTRICAL SPECIFICATIONS...........000000000. 22 3.4 Deep Power-DOown ........ccccseeeceeeecesesseeceseessseaeneees 8 6 1 Absolute Maximum Ratings ...........c:cccscecceeeeeee 22 3.5 Read Identifier Codes Operation..............cccceeee 9 6.2 Operating Conditions ............:cceeseessseeseeeseeseeeene 22 3.6 WHITE... ccecceesssssneeerceecescsessaecessessesserseescenersereeas 9 6.2.1 Capacitance .........cesecccsstsessceecessencesesenseeeres 22 6.2.2 AC Input/Output Test Conditions.................. 23 4 COMMAND DEFINITIONS... eeceeeeeeeeeeeeeees 9 6.2.3 DC Characteristics..........ccccsseseeeseseesseses 24 4.1 Read Array Command...........ceeeeceeseeeceeteseeeees 12 6.2.4 AC Characteristics - Read-Only Operations .26 4.2 Read Identifier Codes Command ..............2::0+ 12 6.2.5 AC Characteristics - Write Operations.......... 29 4.3 Read Status Register Command................ 12 6.2.6 Alternative CE#-Controlled Writes................ 32 4.4 Clear Status Register Command..................+ 12 6.2.7 Reset Operations ........ ee ceeeseeseecseeeseeeens 35 4.5 Block Erase COMMANG.............:secccssceeessreessnees 12 6.2.8 Block Erase and Word Write Configuration 4.6 Word Write Command.......... sc ecesscsececceeeeseerenees 13 P@rfOrMance........cesccecssccecssessseseessecssesseesses 36 4.7 Block Erase Suspend Command...............:s000 13 4.8 Word Write Suspend Commanid................: 14. 7 ADDITIONAL INFORMATION ..............0...0 cue 38 7.1 Ordering Information ..........0..cccccssssscesesseeseeseees 38 8 PACKAGE AND PACKING SPECIFICATIONS .....39 Rev. 1.0SHARP LHF80B25 2 LH28F800BGHE-TL85 8M-BIT (512KB x 16) SmartVoltage Flash MEMORY = SmartVoltage Technology M Extended Cycling Capability 2.7V, 3.3V or 5V Vcc 100,000 Block Erase Cycles 2.7V, 3.3V, 5V or 12V Vpp M@ Enhanced Automated Suspend Options M High-Performance Access Time Word Write Suspend to Read 85ns(5V+0.25V), 90ns(5V+0.5V), Block Erase Suspend to Word Write 100ns(3.3V+0.3V), 120ns(2.7V-3.6V) Block Erase Suspend to Read @ Enhanced Data Protection Features @ Low Power Management Absolute Protection with Vpp=GND Deep Power-Down Mode Block Erase/Word Write Lockout Automatic Power Savings Mode during Power Transitions Decreases Ic in Static Mode Boot Blocks Protection with ; WP#=Vi. M@ Industry-Standard Packaging 48-Lead TSOP M@ Optimized Array Blocking Architecture Two 4k-word Boot Blocks m@ SRAM-Compatible Write Interface Si - ter Block . . Fifteen 32k-word Main Blocks m_ETOXTM" V Nonvolatile Flash Technology Top Boot Location Automated Word Write and Block Erase = Not designed or rated as radiation Command User Interface hardened Status Register SHARPs LH28F800BGHE-TL85 Flash memory with SmartVoltage technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. LH28F800BGHE-TL85 can operate at Voec=2.7V and Vpp=2.7V. Its low voltage operation capability realize battery life and suits for cellular phone application. Its Boot, Parameter and Main-blocked architecture, flexible voltage and extended cycling provide for highly flexible component suitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F800BGHE-TL85 offers two levels of protection: absolute protection with Vpp at GND, selective hardware boot block locking. These alternatives give designers ultimate control of their code security needs. The LH28F800BGHE-TL85 is manufactured on SHARPs 0.4um ETOX V process technology. It come in industry-standard package: the 48-lead TSOP ideal for board constrained applications. *ETOX is a trademark of Intel Corporation. - . Rev. 1.0SHARP LHF80B25 3 1 INTRODUCTION This datasheet contains LH28F800BGHE-TL85 specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4 and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. 1.1 New Features Key enhancements of LH28F800BGHE-TL85 | SmartVoltage Flash memory are: eSmartVoltage Technology eEnhanced Suspend Capabilities eBoot Block Architecture Please note following important differences: *Vpp_ix has been lowered to 1.5V to support 2.7V, 3.3V and 5V block erase and word write operations. Designs that switch Vpp off during read operations should make sure that the Vpp voltage transitions to GND. eTo take advantage of SmartVoltage technology, allow Vpp connection to 2.7V, 3.3V or 5V. 1.2 Product Overview The LH28F800BGHE-TL85 is a high-performance 8- Mbit SmartVoltage Flash memory organized as 512K-word of 16 bits. The 512K-word of data is arranged in two 4K-word boot blocks, six 4K-word parameter blocks and fifteen 32K-word main blocks which are individually erasable in-system. The memory map is shown in Figure 3. SmartVoltage technology provides a choice of Voc and Vpp combinations, as shown in Table 1, to meet system performance and power expectations. 2.7V Veco consumes approximately one-fifth the power of 5V Voc: But, 5V Veo provides the highest read performance. Vpp at 2.7, 3.3V and 5V eliminates the . the dedicated Vpp pin gives complete data protection , when Vpp < VppiK: need for a separate 12V converter, while Vpp=12V maximizes block erase and word write performance. In addition to flexible erase and program voltages, Table 1. Voc and Vpp Voltage Combinations Offered by SmartVoitage Technology Voc Voltage Vpp Voltage 2.7V 2.7V, 3.3V, 5V, 12V 3.3V 3.3V, 5V, 12V 5V 5V, 12V Internal Vog and Vpp_ detection Circuitry automatically configures the device for optimized read and write operations. A Command User Interface (CU!) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CU! initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and word write operations. A block erase operation erases one of the devices 32K-word blocks typically within 0.39s (5V Vog, 12V Vpp), 4K-word blocks typically within 0.25s (5V Vog, 12V Vpp) independent of other blocks. Each biock can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. Writing memory data is performed in word increments of the devices 32K-word blocks typically within 8.4us (5V Voc, 12V Vpp), 4K-word blocks typically within 17ys (5V Voc, 12V Vpp). Word write suspend mode enables the system to read data or execute code from any other flash memory array location. Rev. 1.0SHARP LHF80B25 4 The boot blocks can be locked for the WP# pin. Block erase or word write for boot block must not be carried out by WP# to Low and RP# to Vy. The status register indicates when the WSMs block erase or word write operation is finished. The RY/BY# output gives an additional indicator of WSM activity by providing both a hardware signal of Status (versus software polling) and status masking {interrupt masking for background block erase, for example). Status polling using RY/BY# minimizes both CPU everhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase or word write. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and word write is inactive), word write is suspended, or the device is in deep power-down mode. The access time is 85 ns (tayqy) over the commercial temperature range (-40C to +85C) and Vcc supply voltage range of 4.75V-5.25V. At lower Vcc voltages, - substantially reduces active current when the device the access times are 90 ns (4.5V-5.5V), 100 ns (3.0V-3.6V) and 120 ns (2.7V-3.6V). The Automatic Power Savings (APS) feature is in static mode (addresses not switching). In APS mode, the typical loop current is 1 mA at 5V Vo. When CE# and RP# pins are at Voo, the log CMOS standby mode is enabled. When the RP# pin is at GND, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tpygy) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (toy) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. The device is available in 48-lead TSOP (Thin Small Outline Package, 1.2 mm thick). Pinout is shown in Figure 2. Rev. 1.0SHARP LHF80B25 5 DQo-DOi5 Output Buttder . Identifier Vee 5 x Register 2 CE# 3 Status We# Register OE# RP# _ WP# Data Comparator aan Wa RY/BY# ho-Ave Y-Gating State Ver Machine Voltage Switch S 5 ae Veo 2/2 32K-Word S| :e| Main blocks end =|3 Figure 1. Block Diagram Ay Co 1 48 Aig Ay C2 C) 47-= NC Aw C= 3 46>- GND Aw Coo4 45(T DQis Ay Go 5 4c DQ, Ai CM) 6 43 = 7 DQi4 Ag C7 420c 7 DQ As C8 41= 7 :~~DQis3 NC C249 40-7 DQ; NC C1] 10 48-LEAD TSOP 39-1 DQ ,2 WE# C 11 38 SOG, RP# Co 12 STANDARD PINOUT 37 EE \~Veco Vep C13 36) SODQy, wee C14 12mm x 20mm 35 DO, RY/BY# Co 15 TOP V 34 = DQis Ais Co 16 0 lEW 337 ~DQ: Ay CX] 17 32-7 DQ, Ay Co 18 31- DQ, Ag Co 19 30=_ DQ; As Co 20 29-7 DQ Ag C1 21 28-=_OE# A3 Co} 22 27 ()_-~GND Ag Co 23 ~ 265-7 CE# A; Co 24 25-= Ao Figure 2. TSOP 48-Lead Pinout ~ Rev. 1.0SHARP LHF80B25 6 Table 2. Pin Descriptions Type Name and Function INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle. INPUT/ OUTPUT DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data during memory array, status register and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. INPUT CHIP ENABLE: Activates the devices control logic, input buffers, decoders and sense amplifiers. CE#-high deselects the device and reduces power consumption to standby levels. RP# INPUT RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations which provides data protection during power transitions. Exit from deep power-down sets the device to read array mode. With RP#=V,4y,, block erase or word write can operate to all blocks without WP# state. Block erase or word write with Vin<RP#<V 144, produce spurious results and should not be attempted. OE# INPUT OUTPUT ENABLE: Gates the device's outputs during a read cycle. WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks, Addresses and data are latched on the rising edge of the WE# pulse. WP# INPUT WRITE PROTECT: Master control for boot blocks locking. When V/,, locked boot blocks cannot be erased and programmed. RY/BY# OUTPUT READY/BUSY?#: Indicates the status of the internal WSM. When low, the WSM is performing an internal operation (block erase or word write). RY/BY#-high indicates that the WSM is ready for new commands, block erase is suspended, and word write is inactive, word write is suspended, or the device is in deep power-down mode. RY/BY# is always active and does not float when the chip is deselected or data outputs are disabled. SUPPLY BLOCK ERASE AND WORD WRITE POWER SUPPLY: For erasing array blocks or writing words. With Vpp<Vpp, x, Memory contents cannot be altered. Block erase and word write with an invalid Vpp (see DC Characteristics) produce spurious results and should not be attempted. SUPPLY DEVICE POWER SUPPLY: Internal detection configures the device for 2.7V, 3.3V or 5V operation. To switch from one voltage to another, ramp Voc down to GND and then ramp Voc to the new voltage. Do not float any power pins. With VocSV; Ko, all write attempts to the flash memory are inhibited. Device operations at invalid Veg voltage (see DC Characteristics) produce spurious results and should not be attempted. GND SUPPLY GROUND: Do not float any ground pins. NC _. NO CONNECT: Lead is not internal connected; it may be driven or floated. Rev. 1.0SHARP LHF80B25 7 2 PRINCIPLES OF OPERATION The LH28F800BGHE-TL85 SmartVoltage Flash Top Boot memory includes an on-chip WSM to manage block 7EFFR 4K-word Boot Block 0 erase and word write functions. It allows for: 100% Freee TTL-level control inputs, fixed power supplies during 7E000 4K-word Boot Block 1 block erasure and word write, and minimal processor 7DFFF overhead with RAM-like interface timings. 70000 4K-word Parameter Block 0 7CFFF After initial device power-up or return from deep 7C000 4K-word Parameter Block 1 power-down mode (see Bus Operations), the device 7BFFF 4K-word Parameter Block 2 defaults to read array mode. Manipulation of external 7Bo00 | memory control pins allow array read, standby and 4K-word Parameter Block 3 output disable operations. 7OrPP 79000 4K-word Parameter Block 4 Status register and identifier codes can be accessed 78FFF 4K-word Parameter Block 5 through the CUI independent of the Vpp voltage. High 78000 voltage on Vpp enables successful block erasure and T7FFF 32K-word Main Block 0 word writing. All functions associated with altering enree memory contentsblock erase, word write, status 32K-word Main Block 1 and identifier codesare accessed via the CUI and e7FFP ; verified through the status register. 60000 32K-word Main Block 2 SFFFF Commands are written using standard 58000 82K word Main Block 3 microprocessor write timings. The CUI contents serve S7FFF 32K-word Main Block 4 as input to the WSM, which controls the block erase aeeee and word write. The internal algorithms are regulated 32K-word Main Block 5 by the WSM, including pulse repetition, internal a7 ; verification and margining of data. Addresses and 40000 32K-word Main Block 6 data are internally latch during write cycles. Writing SFFFF 32K-word Main Block 7 the appropriate command outputs array data, 38000 accesses the identifier codes or outputs status 32K-word Main Block 8 register data. reer 32K-word Main Block 9 Interface software that initiates and polls progress of STEEP block erase and word write can be stored in any 20000 32K-word Main Block = 10 block. This code is copied to and executed from 1FFFF 32K-word Main Block 11 system RAM during flash memory updates. After 8009 successful completion, reads are again possible via 32K-word Main Block 42 the Read Array command. Biock erase suspend oer allows system software to suspend a block erase to osooo 32K-word Main Block 13 read/write data from/to blocks other than that which is O7FFF ; suspend. Word write suspend allows system 00000 32K-word Main Block = 14 software to suspend a word write to read data from any other flash memory array location. Figure 3. Memory Map Rev. 1.0SHARP LHF80B25 8 2.1 Data Protection Depending on the application, the system designer may choose to make the Vpp power supply switchable (available only when memory block erases or word writes are required) or hardwired to VppH1/2/3- The device accommodates either design practice and encourages optimization of the processor-memory interface. When VppSVppi,~, memory contents cannot be altered. The CUI, with two-step biock erase or word | write command sequences, provides protection from unwanted operations even when high voltage is applied to Vpp. All write functions are disabled when Vec is below the write lockout voltage V, ,o or when RP# is at V,. The devices boot blocks locking capability for WP# provides additional protection from inadvertent code or data alteration by block erase and word write operations. 3 BUS OPERATION The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes or status register independent of the Vpp voltage. RP# can be at either Vj4 or Vip. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. Five control pins dictate the data flow in and out of the component: CE#, OE#, WE#, RP# and WP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ9-DQ,5) control and when active drives the selected memory data onto the I/O bus. WE# must be at V,,, and RP# must be at Vj, or Vun: Figure 13 illustrates read cycle. 3.2 Output Disable With OE# at a logic-high level (Vj), the device _outputs are disabled. Output pins (DQ,-DQ,.) are - placed in a high-impedance state. 3.3 Standby CE# at a logic-high level (Vj) places the device in standby mode which substantially reduces device power consumption. DQ,-DQ,., outputs are placed in a high-impedance state independent of OE#. If deselected during block erase or word write, the device continues functioning, and consuming active power until the operation completes. 3.4 Deep Power-Down RP# at V), initiates the deep power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. RP# must be held low for a minimum of 100 ns. Time tpyay is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase or word write modes, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tpyyw, is required after RP# goes to logic-high (V),,) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase or word write modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARPs flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this applicati6n, RP# is controlled by the same RESET# signal that resets the system CPU. Rev. 1.0SHARP LHF80B25 9 3.5 Read Identifier Codes Operation The read identifier codes operation outputs the manufacturer code and device code (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. 7FFFF | 00002 00001 Device Code 00000 Manufacturer Code Figure 4. Device Identifier Code Memory Map 3.6 Write Writing commands to the CUI! enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When Vee=Vecraa4 aNd = Vpp=Vppyyja3, the CUI additionally controls block erasure and word write. The Block Erase command requires appropriate - command data and an address within the block to be erased. The Word Write command requires the command and address of the location to be written. The CUI does not occupy an addressable memory location. It is written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Figures 14 and 15 illustrate WE# and CE# controlled write operations. 4 COMMAND DEFINITIONS When the Vpp voltage < Vpp;,, Read operations from the status register, identifier codes, or blocks are enabled. Placing Vppyj4//3 ON Vpp enables successful block erase and word write operations. Device operations are selected by writing specific commands into the CU!. Table 4 defines these commands. Rev. 1.0SHARP LHF80B25 10 Table 3. Bus Operations Mode Notes | RP# CE# | OE# | WE# | Address| Vpp DQai5 | RY/BY# Read 1,2,3,8 yer Vi | Vel Vw X X | Dour x Output Disable 3 nor Vi | Vie | Vig Xx X | HighZ X Standby Wer} vw fx x x x | Highz | x Deep Power-Down 4 Vi x xX - x x x High Z Vou * Vip OF See Read identifier Codes Vern Vir Vit Vin Figure 4 x Note 5 Von |] Write 3.67.8) SH | va | Vin | Vi x x Diy x NOTES: 1, Refer to DC Characteristics. When VppsVpp; x, memory contents can be read, but not altered. 2. X can be Vy, or Vj, for control pins and addresses, and Vpp, OF Vppy4/2/3 for Vpp. See DC Characteristics for VPPLK and VppH1/2/3 voltages. 3. RY/BY# is Vo_ when the WSM is executing internal block erase or word write algorithms. It is Voy, during when the WSM is not busy, in block erase suspend mode (with word write inactive), word write suspend mode or deep power-down mode. : 4. RP# at GND+0.2V ensures the lowest deep power-down current. 5. See Section 4.2 for read identifier code data. 6. Command writes involving block erase or word write are reliably executed when Vpp=Vppy4/93 and Voc=Voc1/2/3/4- Block erase or word write with Vi,4<RP#<V,,,, produce spurious results and should not be attempted. . 7. Refer to Table 4 for valid Dj,, during a write operation. 8. Never hold OE# low and WE# low at the same timing. Rev. 1.0SHARP LHF80B25 1 Table 4. Command Definitions(7) Bus Cycles First Bus Cycle Second Bus Cycle Command Req'd. | Notes | Oper(!) | Addr?) | Data) | Oper() | Addr) | Data) Read Array/Reset 1 Write x FFH Read Identifier Codes 22 4 Write - X 90H Read IA ID Read Status Register 2 Write X 70H Read X SRD Clear Status Register 1 Write X 50H Block Erase 2 5 Write BA 20H Write BA DOH Word Write 2 5,6 | Write | WA OOH Write | WA wD Block Erase and Word Write . Suspend 1 5 Write X BOH ||Block Erase and Word Write . Resume 1 5 Write Xx DOH NOTES: 1. BUS operations are defined in Table 3. 2. X=Any valid address within the device. iA=Identifier Code Address: see Figure 4. BA=Address within the block being erased. WAz=Address of memory location to be written. 3. SRD=Data read from status register. See Table 7 for a description of the status register bits. WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). iD=Data read from identifier codes. 4. Following the Read Identifier Codes command, read operations access manufacturer and device codes. See Section 4.2 for read identifier code data. 5. If the block is boot block, WP# must be at V,,, or RP# must be at V,,, to enable block erase or word write operations. Attempts to issue a block erase or word write to a boot block while WP# is V,,, or RP# is Vi. 6. Either 40H or 10H are recognized by the WSM as the word write setup. 7. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. Rev. 1.0SHARP LHF80B25 12 4.1 Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase or word write, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Word Write Suspend command. The Read Array | command functions independently of the Vpp voltage and RP# can be Vj or Vin. 4.2 Read Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 4 retrieve the manufacturer and device codes (see Table 5 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the Vpp voltage and RP# can be Vy, or Vi. Following the Read Identifier Codes command, the following information can be read: Table 5. identifier Codes Code Address Data Manufacture Code Q0000H OOBOH Device Code 00001H QO60H 4.3 Read Status Register Command The status register may be read to determine when a block erase or word write is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or CE#, whichever occurs. OE# or CE# must toggle to V,,, before further reads to update the status register latch. The Read Status Register command functions independently of the Vpp voltage. RP# can be Vin or Vin: 4.4 Clear Status Register Command Status register bits SR.5, SR.4, SR.3 or SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 7). By allowing system software to reset these bits, several operations (such as cumulatively erasing multiple blocks or writing several words in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied Vpp Voltage. RP# can be Vj, or Vii. This command is not functional during biock erase or word write suspend modes. 4.5 Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFFFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 5). The CPU can detect block erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CU! remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when Voc=Vecrjya4 and Vpp=Vppx1/2/3- In the absence of this high voltage, block contents are protected against erasure. if block erase is attempted while Vpp<Vpp; x, SR.3 and SR.5 will be set to "1". Successful block erase for boot blocks requires that the corresponding if set, that WP#=V,,, or RP#=Vip. If block erase is attempted to boot block when the corresponding WP#=V,_ or RP#=V,,, SR.1 and SR.5 will be set to "1". Block erase operations with V,4<RP#<Viy, produce spurious results and should not be attempted. Rev. 1.0SHARP LHF80B25 13 4.6 Word Write Command command requests that the WSM suspend the block erase sequence at a predetermined point in the Word write is executed by a two-cycle command algorithm. The device outputs status register data sequence. Word write setup (standard 40H or when read after the Block Erase Suspend command alternate 10H) is written, followed by a second write : is written. Polling status register bits SR.7 and SR.6 that specifies the address and data (latched on the can determine when the block erase operation has rising edge of WE#). The WSM then takes over, been suspended (both will be set to "1"). RY/BY# will controlling the word write and write verify algorithms also transition to Voy. Specification twp. defines internally. After the word write sequence is written, the block erase suspend latency. the device automatically outputs status register data ; when read (see Figure 6). The CPU can detect the At this point, a Read Array command can be written completion of the word write event by analyzing the to read data from blocks other than that which is | RY/BY# pin or status register bit SR.7. suspended. A Word Write command sequence can also be issued during erase suspend to program data When word write is complete, status register bit SR.4 in other blocks. Using the Word Write Suspend should be checked. If word write error is detected, the command (see Section 4.8), a word write operation Status register should be cleared. The internal WSM can also be suspended. During a word write verify only detects errors for "1"s that do not operation with block erase suspended, status register successfully write to "O"s. The CU! remains in read bit SR.7 will return to "O" and the RY/BY# output will Status register mode until it receives another transition to Vo_. However, SR.6 will remain "1" to command. indicate block erase suspend status. Reliable word writes can only occur when The only other valid commands while block erase is Vec=Vec12/4/4 ANd Vpp=Vppy4/9/3- In the absence of suspended are Read Status Register and Block this high voltage, memory contents are protected Erase Resume. After a Block Erase Resume against word writes. If word write is attempted while command is written to the flash memory, the WSM VppSVpp x, Status register bits SR.3 and SR.4 will be will continue the block erase process. Status register set to "1". Successful word write for boot blocks bits SR.6 and SR.7 will automatically clear and requires that the corresponding if set, that WP#=V,,, RY/BY# will retum to Vo,. After the Erase Resume or RP#=V,,. If word write is attempted to boot block command is written, the device automatically outputs when the corresponding WP#=V,, or RP#=V,,,, SR.1 Status register data when read (see Figure 7). Vpp and SR.4 will be set to "1". Word write operations must remain at Veprt/o3 (the same Vpp level used with Vij<RP#<V,4, produce spurious results and for block erase) while block erase is suspended. RP# should not be attempted. must also remain at Vj, or Vii4 (the same RP# level used for block erase). WP# must also remain at Vj, or Vi (the same WP# level used for block erase). Block erase cannot resume until word write operations initiated during block erase suspend have completed. a7 Block Erase Suspend Command The Block Erase Suspend command allows block- erase interruption to read or word-write data in another block of memory. Once the block-erase process starts, writing the Block Erase Suspend Rev. 1.0SHARP LHF80B25 14 4.8 Word Write Suspend Command The Word Write Suspend command allows word write interruption to read data in other flash memory locations. Once the word write process starts, writing the Word Write Suspend command requests that the WSM suspend the word write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Word Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the word write operation has been | suspended (both will be set to "1"). RY/BY# will also transition to Voy. Specification twury, defines the word write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while word write is suspended are Read Status Register and Word Write Resume. After Word Write Resume command is written to the flash memory, the WSM : will continue the word write process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to Vo,. After the Word Write Resume command is written, the device automatically outputs status register data when read (see Figure 8). Vpp must remain at Vppyy4/0/3 (the same Vpp level used for word write) while in word write suspend mode. RP# must also remain at Vj, or Vin (the same RP# level used for word write). WP# must also remain at V,, or Vj (the same WP# level used for word write). Table 6. Write Protection Alternatives Operation Vpp RP# WP# Effect Vi X X All Blocks Locked. Word Write Vi xX All Blocks Locked. or Vw x All Blocks Unlocked. Block Erase >Vppik Vu 2 Boot Blocks Locked. Vie Vin All Blocks Unlocked. Rev. 1.0SHARP SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE STATUS (ES) 1 = Error in Block Erasure 0 = Successful Block Erase SR.4 = WORD WRITE STATUS (WWS) 1 = Error in Word Write O = Successful Word Write SR.3 = Vpp STATUS (VPPS) 1 = Vpp Low Detect, Operation Abort 0 = Vpp OK SR.2 = WORD WRITE SUSPEND STATUS (WWSS) 1 = Word Write Suspended 0 = Word Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = WP# or RP# Lock Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) LHF80B25 15 Table 7. Status Register Definition | WSMS | ESS | ES | WWS VPPS | Wwss_ | DPS | R | 7 6 5 4 3 2 1 0 NOTES: Check RY/BY# or SR.7 to determine block erase or word write completion. SR.6-0 are invalid while SR.7="0". If both SR.5 and SR.4 are "1"s after a block erase attempt, an improper command sequence was entered. SR.3 does not provide a continuous indication of Vpp level. The WSM interrogates and indicates the Vpp level only after Block Erase or Word Write command sequences. SR.3 is not guaranteed to reports accurate feedback only when Vpp#Vppy4/0/3- The WSM interrogates the WP# and RP# only after Block Erase or Word Write command sequences. It informs the system, depending on the attempted operation, if the WP# is not Vj, RP# is not Vin. SR.0 is reserved for future use and should be masked out when polling the status register. Rev. 1.0SHARP Start Bus Command Comments Operation i, Data=20H Write 20H, Write Erase Setup . Block Address Addr=Within Block to be Erased Write Erase Data=DOH m Confirm AddreWithin Block to be Erased Read Status Register Data Read Status Register - Suspend Block Check SR.7 Erase Loo Standby 1=WSM Ready P O=WSM Busy Repeat for subsequent block erasures. : Full status check can be done after each block erase or after a sequence of block erasures. Write FFH atter the last operation to place device in read array mode. Bus : Command Comments Operation Standby Check SR.3 1=Vpp Error Detect Check SR.1 Standby 1=Device Protect Detect Check SR.45 * Stand indby Both 1=<Command Sequence Error Device Protect Error Standby Check SR.5 1=Block Erase Error SR.5,SR.4,SR.3 and SR.1 are only cleared by the Ciear Status Register Command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting ratry or other error racovery. Biock Erase Error Block Erase Successful Figure 5. Automated Block Erase Flowchart ~ Rev. 1.0SHARP LHF80B25 17 Start Bus Command Comments Operation * Data=40H or 10H - Wri Write Write 40H or 10H, Write Setup Word AddreLocation to Be Written Address Write Word Write Cata=Data to Be Written n ora AddreLocation to Be Written : Read Status Register Data Read = Suspend Word Check SR.7 Write Loo Standby 1=WSM Ready P O=WSM Busy Repeat for subsequent byte writes. SR full status check can be done after each word write, or after a sequence of word writes, Write FFH after the last word write operation to place device in read array mode. Full Status Check if Desired Word Write Complete FULL STATUS CHECK PROCEDURE - Comments Cheek SR.3 1=Vpp Error Detect Check SR.1 1=Device Protect Detect Read Status Register Bus Data(See Above) . Command Operation Standby Vpp Range Error Standby Standby Check SR.4 . 1=Data Write Error Device Protect Error full status is checked. retry or other error recovery. SA.4,SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before {f error is detected, clear the Status Register before attempting Word Write Error Word Write Successful Figure 6. Automated Word Write Flowchart Rev. 1.0SHARP Coos) ou] commune t Operation - Erase Data=BOH Write BoH Waite Suspend Addr=X Status Register Data Read Addr=aX Status Register Check SR.7 Standby 1mWSM Ready O=zWSM Busy - Check SR.6 Standby 1=Block Erase Suspended 1 OmBlock Erase Compieted . Erase DatazDOH Write Resume Addr=aX Block Erase Compieted Read Word Write Read Array Data Word Write Loop " No - Yes | Write DOH | | Write FFH | (stock Erase Resumed )) Read Array Data | e Figure 7. Block Erase Suspend/Resume Flowchart Rev. 1.0SHARP LHF80B25 19 Cos) oo | command comment Operation Write Word Write Data=BOH Write BOH Suspend Addrax oe Data - Status Regist o_o Check SR.7 - Standby t=WSM Ready O=WSM Busy Check SR.2 Standby 1=Word Write Suspended 4 O=Word Write Completed Write Read Array Data=FFH Addr=X Word Write Completed R Read Amay locations other 1 than that being written, . Word Write DatasDOH ; Write Write FFH Resume AddraX Read Array Data x Reading Yes | Write DOH | | Write FFH | v (word Write Resume) Read Aray Data Figure 8. Word Write Suspend/Resume Flowchart . Rev. 1.0SHARP LHF80B25 20 5 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three- line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the systems READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. 5.2 RY/BY#, Block Erase and Word Write Polling RY/BY# is a full CMOS output that provides a hardware method of detecting block erase and word write completion. It transitions low after block erase or word write commands and returns to Vo, when the WSM has finished executing the internal algorithm. RY/BY# can be connected to an interrupt input of the system CPU or controller. It is active at all times. RY/BY# is also Vo, when the device is in block erase suspend (with word write inactive), word write suspend or deep power-down modes. _ 3.3 Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Transient current magnitudes depend on the device outputs capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 uF ceramic capacitor connected between its Voc and GND and between its Vpp and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 uF electrolytic capacitor should be placed at the arrays power supply connection between Vo, and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5.4 Vpp Trace on Printed Circuit Boards Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the Vpp Power supply trace. The Vpp pin supplies the memory cell current for word writing and block erasing. Use similar trace widths and layout considerations given to the Voc power bus. Adequate Vpp supply traces and decoupling will decrease Vpp voltage spikes and overshoots. Rev. 1.0SHARP LHF80B25 21 5.5 Voc, Vpp, RP# Transitions Block erase and word write are not guaranteed if Vpp falls outside of a valid Vppy4/o/3 range, Voc falls outside of a valid Vogy/oyqq Tange, or RP##V), or Vur- If Vpp error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to Vy, during block erase or word write, RY/BY# will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data | partially altered. Therefore, the command sequence must be repeated after normal operation is restored. Device power-off or RP# transitions to V, clear the Status register. The CUI latches commands issued by system software and is not altered by Vpp or CE# transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep power-down or after Voc transitions below V, ko. After block erase or word write, even after Vpp transitions down to Vpp,,, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block erasure or word writing during power transitions. Upon power-up, the device is indifferent as to which power supply (Vpp or Voc) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for Voc voltages above Vino when Vpp is active. Since both WE# and CE# must be low for a command write, driving either to V,4 will inhibit writes. _ The CUIls two-step command sequence architecture provides added level of protection against data alteration. WP# provide additional protection from inadvertent code or data alteration. The device is disabled while RP#=V,, regardless of its control inputs state. 5.7 Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memorys nonvolatility increases usabie battery life because data is retained when system power is removed. In addition, deep power-down mode ensures extremely low power consumption even when system power is applied. For example, portable computing products and other power sensitive applications that use an array of devices for solid-state storage can consume negligible power by lowering RP# to Vy standby or sleep modes. If access is again needed, the devices can be read following the tpyoqy and tpywt wake-up cycles required after RP# is first raised to Vij. See AC Chatacteristics- Read Only and Write Operations and Figures 13, 14 and 15 for more information. , Rev. 1.0SHARP LHF80B25 22 6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Commercial Operating Temperature During Read, Block Erase and Word Write ....... ce seeeeeeeees vaeeeee 40C to +85C) Temperature under Bias............... -40C to +85C Storage Temperature... -65C to +125C | Voltage On Any Pin (except Voc, Vpp, and RP#).......-2.0V to +7.0V) Voc Supply Voltage ......ssccseseceeeee -2.0V to +7.0V(2) Vpp Update Voltage during Block Erase and Word Write . -2.0V to +14.0V(2.3) RP# Voltage .......ccceeceeseeseeteereee -2.0V to +14.0V(2.3) Output Short Circuit Current... 100maA(4) 6.2 Operating Conditions NOTICE: This datasheet contains information on products in the design phase of development. Do not finalize a design with this information. Revised {information will be published when the product is available. Verify with your local SHARP Sales office that you have the latest datasheet before finalizing a design. "WARNING: Stressing the device beyond the Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on Veco and Vpp pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins and Vcoe iS Vect+0.5V_ which, during transitions, may overshoot to Voc+2.0V for periods <2Ons. 3. Maximum DC voltage on Vpp and RP# may overshoot to +14.0V for periods <20ns. 4. Output shorted for no more than one second. No more than one output shorted at a time. Temperature and V-.-. Operating Conditions 1. Sampled, not 100% tested. Symbol Parameter Min. Max. Unit Test Condition Ta - | Operating Temperature -40 +85 C Ambient Temperature Voc Ver Supply Voitage (2.7V-3.6V) 2.7 3.6 Vv Vero Ver Supply Voltage (3.3V+0.3V) 3.0 3.6 Vv Vers Ve Supply Voltage (5V+0.25V) 4.75 5.25 Vv Vora Ver Supply Voltage (5V+0.5V) 4.50 5.50 Vv 6.2.1 CAPACITANCE() Tg=+25C, f=1MHz ~ Symbol Parameter Typ. Max. Unit Condition Cw Input Capacitance 7 10 ~ pF Vin=0.0V Caiut Output Capacitance 9 12 pF Voy7=0.0V NOTE: Rev. 1.0SHARP LHF80B25 23 6.2.2 AC INPUT/OUTPUT TEST CONDITIONS 2.7 yy INPUT Xe TEST POINTS _}> 1.35 OUTPUT 0.0 SS AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% to 90%) <10 ns. Figure 9. Transient Input/Output Reference Waveform for V.=2.7V-3.6V 3.0 LS INPUT Xs <<? TEST POINTS _> & 15 OUTPUT 0.0 S AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10 ns. Figure 10. Transient Input/Output Reference Waveform for Vo=3.3V+0.3V and Vo,=5V+0.25V (High Speed Testing Configuration) CC 2.0 9 2.0 INPUT > TEST POINTS <o OUTPUT 0.45 0.8 SS 0.8 AC test inputs are driven at Von (2.4 Vr.) for a Logic "1" and Vo, (0.45 Vrt_) for a Logic "0." Input timing begins at Viq (2.0 Vrq_) and Vi, (0.8 Vrr_). Output timing ends at Vi, and Vic. input rise and fall times (10% to 90%) <10 ns. 2.4 Figure 11. Transient Input/Output Reference Waveform for V=5V+0.5V (Standard Testing Configuration) Test Configuration Capacitance Loading Value Test Configuration C, (pF) 1.3V Vec=3.3V20.3V, 2.7V-3.6V 50 i Ven=5Vt0.25V 30 1N914 Vec=5V+0.5V 100 Ry=3.3kQ. DEVICE UNDER () OUT - TEST C, includes Jig 7~ CL Capacitance Figure 12. Transient Equivalent Testing Load Circuit Rev. 1.0SHARP LHF80B25 24 6.2.3 DC CHARACTERISTICS DC Characteristics Ven=2.7V-3.6V | Ve-=5V20.5V Test Sym. Parameter Notes | Typ. | Max. | Typ. Max. | Unit Conditions | Input Load Current 1 Voec=VecMax, +0.5 a1 | PA | yocvacor GND | Output Leakage Current 1 Voc=VccMax, LO ; +0.5 +10 pA VeveaVen or GND locs | Vec Standby Current 1,3,6 CMOS Inputs 25 50 30 100 HA Voc=VecMax CE#=RP#=Vpn-+0.2V TTL Inputs 0.2 2 0.4 2 mA Vec=VecMax CE#=RP#=Vi,, | Ver Deep Power-Down 1 RP#=GND+0.2V CP | current 4 | 0 20 | HAL ioue(RY/BY#)=0mA lecr Vec Read Current 1,5,6 CMOS Inputs | Vec=VecMax, CE#=GND 15 25 50 mA | f=5MHz(3.3V, 2.7V), 8MHz(5V) leur=OMA TTL Inputs Vec=VoecMax, CE#=GND 30 65 mA | f=5MHZz(3.3V, 2.7V), 8MH2(5V) lour=OmA locw Voc Word Write 1 7 5 17 _ mA Vpp=2.7V-3.6V Current 5 17 35 MA_ | Vpp=4.5V-5.5V 5 12 30 mA | Vpp=11.4V-12.6V loce Vee Block Erase 1,7 4 17 _ _ mA Vpp=2.7V-3.6V Current 4 17 30 MA | Vpp=4.5V-5.5V 4 12 25 mA_ | Vpp=11.4V-12.6V | Vee Word Write or Block 1,2 rows Erase Suspend Current 1 6 1 10 mA | CE#=Viy Ipps =| Vpp Standby or Read 1 +2 +15 +2 +15 HA | VepSVec lppa Current 10 200 10 200 HA Vop>Ver lppD | Vpp Deep Power-Down | 1 | 94 | 5 | o4 | 5 | pA | RP#=GND:0.2V Current Ippw | Vpp Word Write 1,7 12 40 MA _ | Vpp=2.7V-3.6V Current 40 40 MA | Vpp=4.5V-5.5V 30 30 MA _| Vpp=11.4V-12.6V lppe | Vpp Block Erase 1,7 8 25 _ _ MA _| Vpp=2.7V-3.6V Current 25 25 MA | Vpp=4.5V-5.5V 20 20 MA | Vpp=11.4V-12.6V | Vpp Word Write or Block 1 ones Erase Suspend Current 10 200 10 200 HA | Vep=VepHia3 Rev. 1.0SHARP LHF80B25 25 DC Characteristics (Continued) Vee=2.7V-3.6V Vec=5V20.5V 1. 2. 3. . Block erases and word writes are inhibited when Vpp<Vpp; x, and not guaranteed in the range between Sym. Parameter Notes | Min. Max. Min. | Max. | Unit Test Conditions Vi Input Low Voltage 7 -0.5 0.8 .| -0.5 0.8 Vv Vin Input High Voltage 7 Veo" Voc 20 | 45 | 2 | sos | Y Vo. | Output Low Voltage 3,7 Vec=Vee Min, 0.4 0.45 Vs | lo =5.8mA(5V) lo, =2.0MA(2.7V,3.3V) Von; | Output High Voltage 3,7 Voc=Vec Min, (TTL) 2.4 2.4 Vi | loy=-2.5mA(5V) lon=-2.0MA(2.7V,3.3V) . Vone Output High Voltage 3,7 0.85 0.85 V Voc=Vec Min, (CMOS) Ver Ver lqy=-2.5mA Voc Veco vy | Yoc=Vec Min, -0.4 -0.4 low=-100LA VepLk | Vpp Lockout during 4,7 Normal Operations 1.5 15 V VeppH1 | Vpp during Word Write or _ Block Erase Operations 27 3.6 7 Vv Vppre | Vpp during Word Write or Block Erase Operations 45 5.5 4.5 5.5 Vv Vppy3 | Vpp during Word Write or Block Erase Operations 11.4 12.6 11.4 12.6 Vv Vixo | Vec Lockout Voltage 2.0 2.0 Vv Vin RP# Unlock Voltage 8,9 11.4 12.6 11.4 12.6 Vv Unavailable WP# NOTES: All currents are in RMS unless otherwise noted. Typical values at nominal Voc voltage and T,=+25C. These currents are valid for all product versions (packages and speeds). lccws 4nd Iccgs are specified with the device de-selected. If read or word written while in erase suspend mode, the devices current draw is the sum of Ioows OF Ioces and Ioer OF Icy, respectively. Includes RY/BY#. Vepr(max) and VepyHy(min), between VeppHi (max) and VepHa(min), between VeppHo(max) and Vppy3(min), and above Vpp3(max). . Automatic Power Savings (APS) reduces typical Icgp to 1MA at 5V Veg and 3mA at 2.7V and 3.3V Vz in static operation. . CMOS inputs are either Voo+0.2V or GND+0.2V. TTL inputs are either Vj, or Vi. . Sampled, not 100% tested. . Boot biock erases and word writes are inhibited when the corresponding RP#=V,,, or WP#=V,,. Block erase and word write operations are not guaranteed with Vc<2.7V or Vi4<RP#<V,4, and should not be attempted. . RP# connection to a V4, supply is allowed for a maximum cumulative period of 80 hours. . Rev. 1.0SHARP See 5.0V Voc Read-Only Operations for notes 1 through 4. LHF80B25 26 6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS(1) Voec=2.7V-3.6V, T,=-40C to +85C Versions(4) . LH28F800BGH-L120 Sym. Parameter : Notes Min. Max. Unit tavay Read Cycle Time 120 ns tavoy __| Address to Output Delay 120 ns ter ov CE# to Output Delay 2 120 ns teyov RP# High to Output Delay 600 ns teray OE# to Output Delay 2 50 ns tercy _ | CE# to Output in Low Z 3 0 ns tepqz | CE# High to Output in High Z 3 55 ns \Lteroxy | OE# to Output in Low Z 3 0 ns teunz | OE# High to Output in High Z 3 20 ns ton Output Hold from Address, CE# or OE# Change, 3 0 Whichever Occurs First ns NOTE: See 5.0V Voc Read-Only Operations for notes 1 through 4. Vec=3.3V20.3V, T,=-40C to +85C Versions) LH28F800BGH-L100 Sym. Parameter Notes Min. Max. Unit tavay Read Cycle Time 100 ns tayoy | Address to Output Delay 100 ns teraqy _| CE# to Output Delay 2 100 ns tpyoy RP# High to Output Delay 600 ns tar ay OE# to Output Delay 2 50 ns ter ay CE# to Output in Low Z 3 0 ns teunz CE# High to Output in High Z 3 55 ns teroxy | OE# to Output in Low Z 3 0 ns taunz | OE# High to Output in High Z 3 20 ns ton Output Hold from Address, CE# or OE# Change, 3 0 ns Whichever Occurs First NOTE: Rev. 1.0SHARP aon > o See AC Input/Output Reference Waveform for maximum allowable input slew rate. . OE# may be delayed up to te, qy-te_ay after the falling edge of CE# without impact on te, gy- Sampied, not 100% tested. See Ordering information for device speeds (valid operational combinations). See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed Configuration) for testing characteristics. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing characteristics. LHF80B25 27 Vec=5V+0.5V, 5V+0.25V, T,=-40C to +85C Voceo.25v | N2ArSneGH Versions(4) Vect0.5V aia eal Sym. Parameter Notes Min. Max. Min. Max. Unit tavay Read Cycle Time 85 90 ns tavoy Address to Output Delay 85 90 ns te1qy ._ | CE# to Output Delay 2 85 90 ns tpunqy | RP# High to Output Delay 400 400 ns ter qy | OE# to Output Delay 2 40 45 ns terpy _| CE# to Output in Low Z 3 0 0 ns || teraz | CE# High to Output in High Z 3 55 55 ns taroy _| OE# to Output in Low Z 3 0 0 ns tanoz | OE# High to Output in High Z 3 10 10 ns tou Output Hold from Address, CE# or 3 0 0 ns OE# Change, Whichever Occurs First NOTES: Rev. 1.0SHARP LHF80B25 28 Device , Vv Standby Address Selection Data Valid Vit sansannons < tavav a Viw CE#(E)- JS \ / \ t Vit Cote aaeeEs ag EHOZ, Vin OE#(G) JS \ Vit Na 2s [iGHOZ, | \ Vin eastnerare WE#(W) S teow \ Vit teLav > terax; teLox ton Vou HIGH Z Oreesaneen T HIGH Z DATA(D/Q} r . (DQ_-DQ)5) Valid Output yee Vot . tavoy sensensnse Veo S \ tpHov Vin ecceoncnes RP#(P) | Va * \ Figure 13. AC Waveform for Read Operations Rev. 1.0SHARP LHF80B25 29 6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS(1) Veco=2.7V-3.6V, T,=-40C to +85C Versions() . LH28F800BGH-L120 Sym. Parameter Notes Min. Max. Unit tavav Write Cycle Time 120 ns touwi RP# High Recovery to WE# Going Low 2 1 us tel wi CE# Setup to WE# Going Low 10 ns twi wy _| WE# Pulse Width 50 ns touwi | RP#Vi4 Setup to WE# Going High 2 100 ns topwe | WP#V)4 Setup to WE# Going High 2 100 ns typwe - Vpp Setup to WE# Going High 2 100 ns tavwy | Address Setup to WE# Going High 3 50 ns tovwH _| Data Setup to WE# Going High 3 50 ns twuny | Data Hold from WE# High 5 ns twuax _| Address Hold from WE# High 5 ns twuen | CE# Hold from WE# High 10 ns twHwi | WE# Pulse Width High 30 ns twur | WE# High to RY/BY# Going Low : 100 ns tw Write Recovery before Read 0 ns toy Vep Hold from Valid SRD, RY/BY# High 2,4 0 ns tovey _| RP# Vi, Hold from Valid SRD, RY/BY# High 2,4 0 ns tovei WP# Vi, Hoid from Valid SRD, RY/BY# High 2,4 0 ns NOTE: See 5.0V Voc AC Characteristics - Write Operations for notes 1 through 5. Veco=3.3V20.3V, T,=-40C to +85C Versions(5) LH28F800BGH-L100 Sym. Parameter Notes Min. Max. Unit tayvay _| Write Cycle Time 100 ns tpuwi RP# High Recovery to WE# Going Low 2 1 us ter wi CE# Setup to WE# Going Low 10 ns twiwyH _| WE# Pulse Width 50 ns tou | RP# Vi Setup to WE# Going High 2 100 ns tonwiy | WP#V).4, Setup to WE# Going High 2 100 ns tvpw | Vpp Setup to WE# Going High 2 100 ns tavwy | Address Setup to WE# Going High 3 50 ns t 47 _| Data Setup to WE# Going High 3 50 ns twunx | Data Hold from WE# High 5 ns twrax | Address Hold from WE# High 5 ns tween | CE# Hold from WE# High 10 ns twrwe | WE# Pulse Width High 30 ns fwel WE# High to RY/BY# Going Low 100 ns tw) Write Recovery before Read 0 ns tev) Vpp Hold from Valid SRD, RY/BY# High 2,4 0 ns toven _| RP# Via Hold from Valid SRD, RY/BY# High 2,4 0 ns toye: WP# V,., Hold from Valid SRD, RY/BY# High 2,4 0 ns NOTE: See 5.0V Voc AC Characteristics - Write Operations for notes for notes 1 through 5. ~ Rev. 1.0