EDI816256CA HI-RELIABILITY PRODUCT 256Kx16 MONOLITHIC SRAM FEATURES 256Kx16 bit CMOS Static The EDI816256CA is a 4 megabit Monolithic CMOS Static RAM. Random Access Memory The EDI816256CA uses 16 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device allows upper and lower byte access by use of the data byte control pins (LB, UB). * Access Times of 17, 20, 25, 35ns * Data Retention Function (LPA version) * TTL Compatible Inputs and Outputs The devices are available in a fully hermetic 44 lead ceramic SOJ and a 44 lead Ceramic Flatpack. The Ceramic SOJ is pin for pin compatible with the commercially available plastic SOJ. This allows the user the luxury of designing a board that can be used for both the commercial and military market. * Fully Static, No Clocks 44 lead JEDEC Approved Revolutionary Pinout * Ceramic SOJ (Package 322) * Ceramic Flatpack (Package 323) A Low Power version with Data Retention (EDI816256LPA) is also available for battery backed applications. Military product is available compliant to Appendix A of MIL-PRF-38535. Single +5V (10%) Supply Operation PIN CONFIGURATION TOP VIEW A0 A1 A2 A3 A4 CS I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A5 A6 A7 A8 A9 September 2000 Rev. 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 PIN DESCRIPTION A17 A16 A15 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 1 A0-17 Address Inputs LB (I/O1-8) Lower-Byte Control (I/O1-8) UB (I/O9-16) Upper-Byte Control (I/O9-16) I/O1-16 Data Input/Output CS Chip Select OE Output Enable WE Write Enable VCC +5.0V Power VSS Ground NC No Connection White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 EDI816256CA TRUTH TABLE ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Unit V CS WE OE LB UB Mode -0.5 to 7.0 C -40 to +85 C H L L X H X X H X Military -55 to +125 C Storage Temperature, Plastic -65 to +125 C L H L 1.5 W Output Current 20 mA Junction Temperature, T J 175 C L L X X X H L H L L H L X X H H L L H L L Not Select 0 to +70 Operating Temperature T A (Ambient) Commercial Industrial Power Dissipation NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Read Write Data Out High Z High Z Data Out Data Out Data Out Data In High Z High Z Data In Data In Data In ICC1 ICC1 Sym Min Typ Max Units Supply Voltage VCC 4.5 5.0 5.5 V Supply Voltage VSS 0 0 0 V VIH 2.2 -- Vcc +0.5 V VIL -0.3 -- 0.8 V Symbol Condition Max Unit CI VIN = Vcc or Vss, f = 1.0MHz 12 pF Input Low Voltage CD/Q VIN = Vcc or Vss, f = 1.0MHz 14 pF Data Lines Output Disable Parameter Input High Voltage Address Lines Supply Current ICC2, ICC3 RECOMMENDED OPERATING CONDITIONS CAPACITANCE (TA = +25C) Parameter Data I/O I/O1-8 I/O9-16 High Z High Z These parameters are sampled, not 100% tested. DC CHARACTERISTICS (VCC = 5V, VSS = 0V, TA = -55C to +125C) Parameter Symbol Conditions Units Min Input Leakage Current ILI VIN = 0V to VCC Max 10 Output Leakage Current ILO VI/O = 0V to VCC 10 A Operating Power Supply Current ICC1 WE, CS = VIL, II/O = OmA, Min Cycle 300 mA Standby (TTL) Power Supply Current ICC2 CS VIH, VIN VIL, VIN VIH Full Standby Power Supply Current ICC3 CS VCC -0.2V CA -- VIN Vcc -0.2V or VIN 0.2V LPA -- Output Low Voltage VOL IOL = 8.0mA Output High Voltage VOH IOH = -4.0mA A 60 mA 25 mA 16 mA 0.4 V 2.4 V NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V AC TEST CONDITIONS Figure 1 Figure 2 Vcc 480 Q Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Vcc 480 NOTE: For tEHQZ , tGHQZ and t WLQZ, CL = 5pF Figure 2) Q 255 30pF 255 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 5pF 2 VSS to 3.0V 5ns 1.5V Figure 1 EDI816256CA AC CHARACTERISTICS - READ CYCLE (VCC = 5.0V, VSS = 0V, TA = -55C to +125C) Parameter Symbol JEDEC Alt. Min 17ns Read Cycle Time tAVAV tRC 17 Address Access Time tAVQV tAA Chip Enable Access Time tELQV tACS Chip Enable to Output in Low Z (1) tELQX tCLZ 2 Chip Disable to Output in High Z (1) tEHQZ tCHZ 0 Output Hold from Address Change tAVQX tOH 0 20ns Max Min 20 20 17 tGLQV tOE Output Enable to Output in Low Z (1) tGLQX tOLZ 0 Output Disable to Output in High Z(1) tGHQZ tOHZ 0 LB, UB Access Time tUBLQV tLBLQV tBA LB, UB Enable to Low Z Output tUBLQX tLBLQX tBLZ LB, UB Disable to High Z Output tUBHQZ tLBHQZ tBHZ 0 7 0 10 0 7 8 35 ns 35 ns ns 0 10 0 15 0 8 ns ns 12 0 Units 5 0 0 Max ns 25 0 10 Min 35 5 0 7 35ns Max 25 20 5 7 Min 25 17 Output Enable to Output Valid 25ns Max ns ns 0 10 ns 10 10 12 15 ns 0 0 0 0 0 ns 0 7 10 ns Max Units 0 7 0 8 0 NOTE: 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS - WRITE CYCLE (VCC = 5.0V, VSS = 0V, TA = -55C to +125C) Parameter Symbol JEDEC Alt. Min 25ns Min Max Min Write Cycle Time tAVAV tWC 17 20 25 35 Chip Enable to End of Write tELWH tELEH tCW tCW ns 14 14 15 15 17 17 20 20 ns ns Address Setup Time tAVWL tAVEL tAVUBL tAS tAS tAS 0 0 0 0 0 0 0 0 0 0 0 0 ns ns ns Address Valid to End of Write tAVWH tAVEH tAVUBH tAW tAW tAW 14 14 14 15 15 15 17 17 17 20 20 20 ns ns ns Write Pulse Width tWLWH tWP 14 14 15 17 ns tWLEH tWP 14 14 15 17 ns Write Recovery Time tWHAX tEHAX tWR tWR 0 0 0 0 0 0 0 0 ns ns Data Hold Time tWHDX tEHDX tDH tDH 0 0 0 0 0 0 0 0 ns ns Write to Output in High Z (1) tWLQZ tWHZ 0 Data to Write Time tDVWH tDVEH tDW tDW 10 10 tWHQX tWLZ 0 0 0 0 ns tLBLLBH tUBLUBH tBW 14 16 18 20 ns Output Active from End of Write (1) LB, UB Valid to End of Write 17ns 20ns Max 8 Min 0 10 10 Max 8 0 12 12 8 35ns 0 15 15 10 ns ns ns NOTE: 1. This parameter is guaranteed by design but not tested. 3 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 EDI816256CA tAVAV TIMING WAVEFORM - READ CYCLE ADDRESS tAVQV CS tAVAV tELQV tELQX tEHQZ tGLQV tGLQX tGHQZ OE ADDRESS ADDRESS 1 ADDRESS 2 DATA I/O tAVQX tAVQV DATA I/O DATA 1 tLBLQX tUBLQX tLBLQV tUBLQV DATA 2 LB, UB READ CYCLE 1 (WE HIGH; OE, CS LOW) tLBHQZ tUBHQZ READ CYCLE 2 (WE HIGH) WRITE CYCLE - WE CONTROLLED tAVAV ADDRESS tAVWH tELWH tWHAX CS tLBLLBH tUBLUBH LB, UB tAVWL tWLWH WE tDVWH DATA IN tWHDX DATA VALID tWLQZ tWHQX HIGH DATA OUT WRITE CYCLE 1, WE CONTROLLED WRITE CYCLE - CS CONTROLLED WRITE CYCLE - LB, UB CONTROLLED tAVAV tAVAV ADDRESS ADDRESS tAVEH tELEH WS32K32-XHX tEHAX CS CS tAVEL tAVUBL tWLEH tAVUBH tUBLUBH WE tDVEH LB, UB tWLWH tDVWH DATA VALID DATA IN HIGH DATA OUT HIGH Z DATA UNDEFINED HIGH Z WRITE CYCLE 3, LB, UB CONTROLLED WRITE CYCLE 2, CS CONTROLLED 4 tWHDX DATA VALID tWLQX tLBLLBH tUBLUBH White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 tWHAV tAVWH tEHDX WE DATA IN DATA OUT tUBHAV LB, UB EDI816256CA DATA RETENTION CHARACTERISTICS (EDI816256LPA ONLY) (TA = -55C to +125C) Characteristic Low Power Version only Data Retention Voltage Sym VDD Data Retention Quiescent Current ICCDR Chip Disable to Data Retention Time (1) TCDR VIN VDD -0.2V Operation Recovery Time (1) TR Conditions Min Typ VDD = 2.0V 2 - - V CS VDD -0.2V - - 2.2 mA or VIN 0.2V Max Units 0 - - ns TAVAV - - ns NOTE: 1. This parameter is guaranteed by design but not tested. * Read Cycle Time DATA RETENTION - CS CONTROLLED Data Retention Mode 4.5V Vcc WS32K32-XHX VDD 4.5V tCDR CS tR CS = VDD -0.2V DATA RETENTION, CS CONTROLLED 5 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 EDI816256CA PACKAGE 322: 44 LEAD, CERAMIC SOJ 0.050 Typ 0.445 0.435 1.130 1.110 0.155 0.120 DIMENSIONS ARE IN INCHES PACKAGE 323: 44 PIN, CERAMIC FLATPACK 1.130 1.110 0.007 0.003 0.515 0.505 0.395 0.385 1.00 Ref 0.038 0.032 Pin 1 0.045 0.015 0.370 0.250 0.019 0.015 0.050 Typ DIMENSIONS ARE IN INCHES White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520 6 0.115 Max. EDI816256CA ORDERING INFORMATION EDI 8 16 256 CA X X X WHITE ELECTRONIC DESIGNS SRAM ORGANIZATION, 256Kx16 TECHNOLOGY: CA = CMOS Standard Power LPA = Low Power ACCESS TIME (ns) PACKAGE TYPE: F44 = 44 pin Ceramic Flatpack (Package 323) N44 = 44 lead Ceramic SOJ (Package 322) DEVICE GRADE: B = MIL-STD-883 Compliant M = Military Screened -55C to +125C I = Industrial -40C to +85C C = Commercial 0C to +70C 7 White Electronic Designs Corporation * Phoenix, AZ * (602) 437-1520