Pin Functions
A0~A18 Address Inputs D0~D31 Data Inputs/Outputs
CS1~4 Chip Select OE Output Enable
WE1~4 Write Enable NC No Connect
VCC Power (+5V) GND Ground
512K x 32 SRAM MODULE
PUMA 2/77S16000/A - 020/025/35
Issue 4.2 : November 1998
D16~23
D0~7
D8~15
D24~31
CS1
CS2
CS3
CS4
A0~A18
512K x 8
SRAM 512K x 8
SRAM 512K x 8
SRAM 512K x 8
SRAM
WE
OE
Description
Available in PGA (PUMA 2 ) and Gullwing (PUMA 77)
footprints, the PUMA **S16000 is a 16 MBit SRAM
module user configurable as 512K x 32, 1M x 16 or 2M
x 8. The device is available with fast access times of
20,25 and 30ns. A low power standby and Data
Retention mode is available. The device may be
screened in accordance with MIL-STD-883.
16,777,216 bit CMOS High Speed Static RAM
Features
• 16MBit Fast SRAM Module.
• Fast Access times of 20/25/35ns.
• Configurable as 8 / 16 / 32 bit wide output.
• Operating Power 2130 / 2800 / 4150 mW (max).
Standby CMOS 220mW (max).
• Low voltage data retention.
• Single 5V±10% Power supply.
• TTL compatible inputs and outputs.
• May be screened in accordance with MIL-STD-883.
• PUMA 2 - 66 pin ceramic PGA
• PUMA77 - 68 pin ceramic Gullwing
Block Diagram
PUMA 77S16000
Block Diagram
PUMA 2S16000 and 77S16000A
WE4
WE3
WE2
WE1
D16~23
D0~7
D8~15
D24~31
CS1
CS2
CS3
CS4
A0~A18
512K x 8
SRAM 51 2K x 8
SRAM 51 2K x 8
SRAM 512K x 8
SRAM
OE
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
ISSUE 4.2 : November 1998 PUMA 2/77S16000/A - 020/025/35
2
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Voltage on any pin relative to Vss (2) VT-0.5V to +7.0 V
Power Dissipation PD4W
Storage Temperature TSTG -55 to +150 °C
Notes (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
(2) Pulse width:- 3.0V for less than 10ns.
Recommended Operating Conditions
Parameter Symbol min typ max units
Supply Voltage VCC 4.5 5.0 5.5 V
Input High Voltage VIH 2.2 - VCC+0.5 V
Input Low Voltage VIL -0.5 - 0.8 V
Operating Temperature TA0-70
°C
TAI -40 - 85 °C (Suffix I)
TAM -55 - 125 °C (Suffix M, MB)
DC Electrical Characteristics (VCC=5V±10%,TA=-55°C to +125°C)
Parameter Symbol Test Condition min typ
(1)
max Unit
Input Leakage Current Address,OE ILI1 VIN = 0V to VCC -8 - 8 µA
WE, CS ILI2 VIN = 0V to VCC -2 - 2 µA
Output Leakage Current ILO CS(2) = VIH or OE = VIH, VI/O = 0V to VCC -8 - 8 µA
WE(2) = VIL
Average Supply Current 32 bit ICC32 CS(2)=VIL, Minumum cycle, II/O = 0mA
WE(2)=VIL or WE(2)=OE=VIH, 100% duty. - - 720 mA
16 bit ICC16 As above - - 480 mA
8 bit ICC8 As above - - 360 mA
Standby Supply Current TTL levels ISB CS(2) = VIH ,VCC=5.5V - - 240 mA
CMOS levels ISB1 CS(2) ≥ VCC-0.2V, 0.2V ≥ VIN≥ VCC-0.2V - - 40 mA
Output Voltage Low VOL IOL = 8.0 mA - - 0.4 V
Output Voltage High VOH IOH = -4.0 mA 2.4 - - V
Notes: (1) Typical values are at VCC=5.0V,TA=25°C and specified loading.
(2) CS and WE above are accessed through CS1~4 and WE1~4 respectively. These inputs must be operated
simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode.
PUMA 2/77S16000 - 020/025/35 ISSUE 4.2 : November 1998
3
Operating Modes
The Table below shows the logic inputs required to control the operating modes of each of the SRAMs on the
device.
Mode CS OE WE V
CC
Current I/O Pin Reference Cycle
Not Selected 1 X X ISB1,ISB2 High Z Power Down
Output Disable 0 1 1 I CC High Z
Read 0 0 1 ICC DOUT Read cycle
Write 0 X 0 ICC DIN Write Cycle
Note: CS above is accessed through CS1~4 and WE is accessed through WE1~4. For correct operation, CS1~ 4 and
WE1~4 must operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or singly for 8 bit operation.
1 = VIH,
0 = VIL,
X = Don't Care
166
30pF
I/O Pin
1.76V
Ω
AC Test Conditions Output Load
*Input pulse levels: 0.0V to 3.0V
*Input rise and fall times: 3 ns
*Input and Output timing reference levels: 1.5V
*Vcc=5V±10%
*PUMA module is tested in 32 bit mode.
Low Vcc Data Retention Characteristics - L Version Only (TA=-55°C to +125oC)
Parameter Symbol Test Condition min typ max Unit
VCC for Data Retention VDR CS1~4 ≥ VCC-0.2V 2.0 - 5.5 V
Data Retention Current ICCDR VCC = 3.0V, CS1~4 ≥ VCC-0.2V,
0.2V ≥ VIN ≥ VCC-0.2V --28mA
Chip Deselect to Data Retention tCDR See Retention Waveform 0--ns
Operation Recovery Time tRSee Retention Waveform 5--ms
Capacitance (VCC=5V±10%,TA=25°C) Note: These parameters are calculated and not measured.
Parameter Symbol Test Condition typ max Unit
Input Capacitance Address, OE CIN1 VIN =0V - 34 pF
WE1~4, CS1~4 CIN2 VIN =0V - 6 pF
I/O Capacitance D0~31 CI/O VI/O=0V - 42 pF (8 bit mode)
ISSUE 4.2 : November 1998 PUMA 2/77S16000/A - 020/025/35
4
AC OPERATING CONDITIONS
Read Cycle
020 025 35
Parameter Symbol min max min max min max Units
Read Cycle Time tRC 20 - 25 - 35 - ns
Address Access Time tAA -20-25-35ns
Chip Select Access Time tACS -20-25-35ns
Output Enable to Output Valid tOE -10-15-15ns
Output Hold from Address Change tOH 5-5-5-ns
Chip Selection to Output in Low Z tCLZ 5-5-5-ns
Output Enable to Output in Low Z tOLZ 5-0-0-ns
Chip Deselection to Output in High Z(3) tCHZ -10010010ns
Output Disable to Output in High Z(3) tOHZ 010010010ns
Write Cycle
020 025 35
Parameter Symbol min max min max min max Unit
Write Cycle Time tWC 20 - 25 - 35 - ns
Chip Selection to End of Write tCW 15 15 - 15 - ns
Address Valid to End of Write tAW 15 - 15 - 15 - ns
Address Setup Time tAS 0-0-0-ns
Write Pulse Width tWP 15 - 15 - 15 - ns
Write Recovery Time tWR 0-0-0-ns
Write to Output in High Z tWHZ 010010010ns
Data to Write Time Overlap tDW 10 - 10 - 10 - ns
Data Hold from Write Time tDH 0-0-0-ns
Output Active from End of Write tOW 5-5-5-ns
PUMA 2/77S16000 - 020/025/35 ISSUE 4.2 : November 1998
5
Notes:
(1) During the Read Cycle, WE is high for the module.
(2) Address valid prior to or coincident with CS transition Low.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
Read Cycle Timing Waveform (1,2)
Write Cycle No.1 Timing Waveform
t
AS(3)
t
AW
t
CW(4)
t
WC
A0~A18
OE
CS1~4
t
WP(1)
t
OHZ(3,9)
WE1~4
D0~31out
tt
DW DH
D0~31in
(6)
t
WR (2)
t
OW
High-Z
High-Z
t
t
tt
RC
AA
OE OH
Address
OE
CS1~4
t
OHZ(3)
t
OLZ
t
ACS
t
CLZ
t
CHZ(3)
Data Valid
D0~31
High-Z
ISSUE 4.2 : November 1998 PUMA 2/77S16000/A - 020/025/35
6
Write Cycle No.2 Timing Waveform (5)
CS1~4
tWR(2)
tCW (4)
(6)
tAW
tWC
A0~A18
t
t
t
WP(1)
DW tDH
WE1~4
D0~31out
D0~31in
WHZ(3,9)
tAS(3)
tOW
tOH
(7)(8)
High-Z
High-Z
AC Characteristics Notes
(1) A write occurs during the overlap (tWP) of a low CS and a low WE.
(2) tWR is measured from the earlier of CS or WE going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain
in a high impedance state.
(5) OE is continuously low. (OE=VIL)
(6) DOUT is in the same phase as written data of this write cycle.
(7) DOUT is the read data of next address.
(8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(9) tWHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
Low VCC Data Retention Timing Waveform
t
R
t
CDR
4.5V
2.2V
4.5V
2.2V
0V
DATA RE T ENTION MO DE
Vcc
CS1~4
V
DR
CS1~4 Vcc- 0. 2V
PUMA 2/77S16000 - 020/025/35 ISSUE 4.2 : November 1998
7
Package Details
PUMA 2S16000
0.10 ( 0.004)
24.13 (0.950) sq.
20.57 (0.810) sq.
1.27
(0.050)
0.43
(0.017)
1.78
(0.070)
5.4 4
(0 .214) ma x
25.15 (0.990) sq.
22.61 (0.890) sq. 0.76
(0.030)
24.67 (0.970) sq.
22.10 (0.870) sq.
20.10 (0.790) sq.
23.62 (0.930) sq.
PUMA 77S16000
SOLDER OVER 50 TO 350 µINCH NICKEL
LEAD FINISH IS 300 µINCH MINIMUM
15.24
(
0.60
)
t
y
p
27.69
(
1.090
)
s
q
uare 4.83
(
0.190
)
4.32
(
0.170
)
1.27
(
0.050
)
1.52
(
0.060
)
27.08
(
1.066
)
s
q
uare
6.86
(
0.270
)
max
1.27
(
0.050
)
1.66
(
0.026
)
10.67
(
0.420
)
10.16
(
0.400
)
2.54
(
0.010
)
3.81
(
0.150
)
ref
2.54
(
0.010
)
1.02
(
0.040
)
0.53
(
0.021
)
0.38
(
0.015
)
Pin Definitions
PUMA 77S16000 PUMA 77S16000A
112 23
VIEW
FROM
ABOVE
213 24
314 25
415 26
516 27
617 28
718 29
819 30
920 31
10 21 32
11 22 33
34 45 56
35 46 57
36 47 58
37 48 59
38 49 60
39 50 61
40 51 62
41 52 63
42 53 64
43 54 65
44 55 66
D8 WE2 D15
D9 CS2 D14
D10 GND D13
A13 D11 D12
A14 A10 OE
A15 A11 A17
A16 A12 WE1
A18 VCC D7
D0 CS1 D6
D1 NC D5
D2 D3 D4
D24 VCC D31
D25 CS4 D30
D26 WE4 D29
A6 D27 D28
A7 A3 A0
NC A4 A1
A8 A5 A2
A9 WE3 D23
D16 CS3 D22
D17 GND D21
D18 D19 D20
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
NC
A0
A1
A2
A3
A4
A5
GND
A6
A7
A8
A9
A10
Vcc
CS3
CS4
9876543216867666564636261
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
OE
CS2
A18
GND
Vcc
A11
A12
A13
A14
A15
A16
CS1
NC
A17
WE2
WE3
WE4
WE1
VIEW
FROM
ABOVE
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
NC
A0
A1
A2
A3
A4
A5
GND
A6
A7
A8
A9
A10
Vcc
CS3
CS4
9876543216867666564636261
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
OE
CS2
A18
GND
Vcc
A11
A12
A13
A14
A15
A16
CS1
NC
A17
NC
NC
NC
WE
VIEW
FROM
ABOVE
PUMA 2S16000
Military Screening Procedure
MultiChip Screening Flow for high reliability product in accordance with Mil-883 method 5004 shown below
Visual and Mechanical
Internal visual 2017 Condition B or manufacturers equivalent 100%
Temperature cycle 1010 Condition B (10 Cycles,-55°C to +125°C) 100%
Constant acceleration 2001 Condition E (Y1 only) (10,000g) 100%
Burn-In
Pre-Burn-in electrical Per applicable device specifications at TA=+25°C 100%
Burn-in Method 1015,Condition D,TA=+125°C,160hrs min 100%
Final Electrical Tests Per applicable Device Specification
Static (dc) a) @ TA=+25°C and power supply extremes 100%
b) @ temperature and power supply extremes 100%
Functional a) @ TA=+25°C and power supply extremes 100%
b) @ temperature and power supply extremes 100%
Switching (ac) a) @ TA=+25°C and power supply extremes 100%
b) @ temperature and power supply extremes 100%
Percent Defective allowable (PDA) Calculated at post burn-in at TA=+25°C 10%
Hermeticity 1014
Fine Condition A 100%
Gross Condition C 100%
Quality Conformance Per applicable Device Specification Sample
External Visual 2009 Per vendor or customer specification 100%
SCREEN TEST METHOD LEVEL
MB MULTICHIP MODULE SCREENING FLOW
ISSUE 4.2 : November 1998 PUMA 2/77S16000/A - 020/025/35
10
Ordering Information
PUMA 2S16000AMB-020
Speed 020 = 20 ns
025 = 25 ns
35 = 35 ns
Temp. range/screeningBlank = Commercial Temperature
I = Industrial Temperature
M = Military Temperature
MB = May be processed in
accordance with MIL-STD-883
WE Option Blank = Single WE (PUMA 77 only)
WE1~4 (PUMA 2 only)
A = WE1~4(PUMA 77 only)
Organisation 16000 = 512Kx 32, user confiurable as
1M x 16 and 2M x 8
Technology S = SRAM MEMORY
Package PUMA 2 = JEDEC 66 Pin Ceramic PGA
package
PUMA 77 = JEDEC 68 Leaded Gull Wing
Ceramic Surface Mount package
Note :
Although this data is believed to be accurate, the information contained herein is not intended to and does not create any
warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval of
a company director.
