CM3205 - California Micro Devices

05/08/06 490 N. McCarthy Blvd., Milpitas, CA 95035-51 12 lTel: 408.263.3214 lFax: 408.263.7846 lwww.cmd.com 1

CM3205

PRELIMINARY

Features

• 5A continuous current from VDDQ

• 1.8V to 2.6V adjustable VDDQ output voltage

•600-mV typical VDDQ dropout voltage at 5A

•V

TT tracking at 50% of VDDQ

• Source and sink up to 2A VTT current

• Excellent load and line regulation, low noise

• Fast transient response

• Meets JEDEC DDR-I SDRAM power spec.

• Linear regulator design requires no inductors and

has low external component count

• Integrated power MOSFETs

• Dual purpose ADJ/Shutdown pin

• Built-in over-current limit with short-circuit foldback

and thermal shutdown for VDDQ and VTT

• 5mA quiescent current

• TO252 andTO263 packages for high performance

thermal dissipation and easy PC board layout

• Optional RoHS Compliant Lead-free packaging

Applications

• DDR memory and active termination buses

• Desktop Computers, Servers

• Residential and Enterprise Gateways

• DSL Modems

• Routers and Switchers

• DVD recorders

• 3D AGP cards

• LCD TV and STB

Product Description

The CM3205 is a dual-output, low noise linear regula-

tor designed to meet SSTL-2 and SSTL-3 specifica-

tions for DDR-SDRAM VDDQ supply and termination

voltage VTT supply. With integrated power MOSFET’s,

the CM3205 can source up to 5A of VDDQ current, and

source or sink up to 2A VTT current. The typical drop-

out voltage for VDDQ is 600-mV at 5A load current.

The CM3205 provides fast response to transient load

changes. Load regulation is excellent, less than 1%,

from no load to full load. It also has built-in over-current

limits and thermal shutdown at 170°C.

The CM3205 is packaged in an easy-to-use 5-pin

D2PAK (TO263-5) and DPAK (TO252-5). Low thermal

resistance (48°C/W) allows it to withstand 1.7W (1) dis-

sipation at 85°C ambient. It can operate over the indus-

trial ambient temperature range of –40°C to 85°C.

15432

2.50V, 5A

DL0

VDDQ

Chip

Set

DLn

DDR

Memory

REF

845

887

VDDQ

RT0

RTn

680u

3.3V

1.25V, 2.5A

S/D

4.7u

ADJSD

GND

VDDQ

VTT

VIN

CM3205

REF

Typical Application

DDR V

DDQ

and Termination Voltage Regulator

2490 N. McCarthy Blvd., Milpitas, CA 95035-5112 lTel: 408.263.3214 lFax: 408.263.7846 lwww.cmd.com 05/08/06

CM3205

PRELIMINARY

Ordering Information

Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.

Specifications

PACKAGE / PINOUT DIAGRAM

Note: This drawing is not to scale.

5-Lead TO-252-5 Package

To p V i ew

ADJSD

VDDQ

GND

VIN

VTT

CM3205-00TP

5-Lead TO-263-5 Package

Top View

ADJSD

VDDQ

GND

VIN

VTT

CM3205-00TN

PART NUMBERING INFORMATION

Pins Package

Lead-free Finish

Ordering Part Number1Part Marking

5 TO-263-5 CM3205-00TN

5 TO-252-5 CM3205-00TP

ABSOLUTE MAXIMUM RATINGS

PARAMETER RATING UNITS

VIN to GND [GND - 0.3] to +6.0 V

Pin Voltages

VDDQ ,VTT to GND

ADJSD to GND

[GND - 0.3] to +6.0

Storage Temperature Range -65 to +150 °C

Operating Temperature Range -40 to +85 °C

Lead Temperature (Soldering, 10s) 300 °C

Package Pinout

05/08/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 lTel: 408.263.3214 lFax: 408.263.7846 lwww.cmd.com 3

CM3205

PRELIMINARY

ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)

VIN = 3.3V, typical values are at TA = 25°C (unless otherwise specified)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

VIN

VIN Supply Voltage Range 3.15 3.30 3.50 V

VUVLO Under-voltage Lockout All outputs are no load 2.4 2.7 2.9 V

UVLO Hysterisis 100 mV

IQQuiescent Current VDDQ = 0V, VTT = 0V,

ADJSD = 3.3V (shutdown)

3mA

VDDQ = 2.5V, VTT = 1.25V, (no load) 5mA

VDDQ Regulator

Output Current Limit VOUT = 2.5V 6.0 8.0 A

VREF Reference Voltage 1.203 1.215 1.227 V

IBIAS Input Bias Current (IADJ)VADJSD = V

REF 30 200 nA

VR LOAD Load Regulation IO = 10 mA to 5A 1 %

VR LINE Line Regulation VIN = 3.15V to 3.5V, IO = 10 mA 0.5 %

VDROPOUT Dropout Voltage VIN = 3.15V, IO = 5A 600 mV

VTT Regulator

Output Current Limit (Source) VOUT = 1.25V 2 2.5 A

Output Current Limit (Sink) VOUT = 1.25V 2 2.5 A

VR VTTLOAD Load Regulation IO = 0A to 2A 1 %

IO = 0A to -2A 1 %

Over Temperature Protection

Thermal Shutdown Temperature 170 °C

Thermal Shutdown Hysteresis 50 °C

Specifications (cont’d)

4490 N. McCarthy Blvd., Milpitas, CA 95035-5112 lTel: 408.263.3214 lFax: 408.263.7846 lwww.cmd.com 05/08/06

CM3205

PRELIMINARY

VD DQ v s. T e mpe r at ure

2.49

2.495

2.5

2.505

2.51

-40 -20 0 20 40 60 80 100 120 140

Temperature oC

VDDQ (V)

VDDQ vs. Load Current

0.5

1.5

2.5

0246810

IDDQ (A)

VDDQ (V)

Ta=25 o

Vin=3.3V

VDDQ Dropout vs. IDDQ

100

200

300

400

500

600

012345

IDDQ (A)

Dropout Voltage (mV)

VTT vs. Load Current

0.0

0.5

1.0

1.5

2.0

2.5

-4 -2 0 2 4

ITT (A)

VTT (V)

Source

VTT v s. VDDQ

0.75

0.85

0.95

1.05

1.15

1.25

1.35

1.45

1.55

1.65

1.5 1.75 2 2.25 2.5 2.75 3 3.25

VDDQ (V)

VTT (V)

Sink

Vin

VDDQ

VTT

1ms/div

1V/div

UVLO

Startup into Full Load

VDDQ=2.5V

Ta=25oC

Typical Operating Curves

05/08/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 lTel: 408.263.3214 lFax: 408.263.7846 lwww.cmd.com 5

CM3205

PRELIMINARY

Pin Descriptions

VDDQ Transient Response VTT Transient Response

VIN =3.3V

IOUT Step: 10mA ~ 3A

VTT

VDDQ

IOUT IOUT

VIN =3.3V

IOUT Step: -2.5A ~ +2.5A

PIN DESCRIPTIONS

PIN(S) NAME DESCRIPTION

1ADJSD

This pin is for VDDQ output voltage adjustment. The VDDQ output voltage is set using an

external resistor divider connected to ADJSD. The output voltage is determined by the

following formula:

where R1 is the ground-side resistor and R2 is the upper resistor of the divider.

Connect these resistors to the VDDQ output at the point of regulation.

In addition, this input functions as a shutdown pin. Apply a voltage higher than VIN-1.2V

to this pin to simultaneously shutdown both VDDQ and VTT outputs. The outputs are

restored when the voltage on this pin falls below VIN-1.2V. A low-leakage diode in

series with the shutdown input signal is recommended to avoid interference with the

voltage adjustment setting.

2VDDQ VDDQ regulator output voltage pin.

3GND

GROUND reference pin. The back tab is also ground and serves as the package

heatsink. It should be soldered to the circuit board copper to remove excess heat from

the IC.

4VIN Input voltage pin, typically 3.3V from the power supply.

5VTT VTT regulator output voltage pin, which is preset to 50% of VDDQ.

VDDQ 1.215V R1 R2+

---------------------

×=

Typical Operating Characteristics

6490 N. McCarthy Blvd., Milpitas, CA 95035-5112 lTel: 408.263.3214 lFax: 408.263.7846 lwww.cmd.com 05/08/06

CM3205

PRELIMINARY

Application Information

Powering DDR Memory

Double-Data-Rate (DDR) memory has provided a huge

step in performance for personal computers, servers

and graphic systems. As is apparent in its name, DDR

operates at double the data rate of earlier RAM, with

two memory accesses per cycle versus one. DDR

SDRAM's transmit data at both the rising falling edges

of the memory bus clock.

DDR’s use of Stub Series Terminated Logic (SSTL)

topology improves noise immunity and power-supply

rejection, while reducing power dissipation. To achieve

this performance improvement, DDR requires more

complex power management architecture than previ-

ous RAM technology.

Unlike the conventional DRAM technology, DDR

SDRAM uses differential inputs and a reference volt-

age for all interface signals. This increases the data

bus bandwidth, and lowers the system power con-

sumption. Power consumption is reduced by lower

operating voltage, a lower signal voltage swing associ-

ated with Stub Series Terminated Logic (SSTL_2) and

by the use of a termination voltage, VTT

. SSTL_2 is an

industry standard, defined in JEDEC document

JESD8-9. SSTL_2 maintains high-speed data bus sig-

nal integrity by reducing transmission reflections.

JEDEC further defines the DDR SDRAM specification

in JESD79C.

DDR memory requires three tightly regulated voltages:

VDDQ, VTT

, and VREF (see Figure 1). In a typical

SSTL_2 receiver, the higher current VDDQ supply volt-

age is normally 2.5V with a tolerance of ±200-mV. The

active bus termination voltage, VTT

, is half of VDDQ.

VREF is a reference voltage that tracks half of VDDQ, ±

1%, and is compared with the VTT terminated signal at

the receiver. VTT must be within ±40-mV of VREF

Figure 1. Typical DDR terminations, Class II

9,1

3.3V

9''4

1.22V

977

*1'

2.50V, 5A

$'-6'

5 5

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Down

CM3205

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Transmitter

VDDQ VTT (=VDDQ/2) VDDQ

Receiver

Rs = 25

Line

Rt = 25

VREF (=VDDQ/2)

Functional Block Diagram

05/08/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 lTel: 408.263.3214 lFax: 408.263.7846 lwww.cmd.com 7

CM3205

PRELIMINARY

The VTT power requirement is proportional to the num-

ber of data lines and the resistance of the termination

resistor, but does not vary with memory size. In a typi-

cal DDR data bus system each data line termination

may momentarily consume 16.2-mA to achieve the

405-mV minimum over VTT needed at the receiver:

A typical 128 Mbyte SSTL-2 memory system, with 192

terminated lines, has a worst-case maximum VTT sup-

ply current up to ±3.11A. However, a DDR memory

system is dynamic, and the theoretical peak currents

only occur for short durations, if they ever occur at all.

These high current peaks can be handled by the VTT

external capacitor. In a real memory system, the con-

tinuous average VTT current level in normal operation

is less than ±200 mA.

The VDDQ power supply, in addition to supplying cur-

rent to the memory banks, could also supply current to

controllers and other circuitry. The current level typi-

cally stays within a range of 2.0A to 3.0A, with peaks

up to 4.0A or more, depending on memory size and the

computing operations being performed.

The tight tracking requirements and the need for VTT to

sink, as well as source, current provide unique chal-

lenges for powering DDR SDRAM.

CM3205 Regulator

The CM3205 dual output linear regulator provides all of

the power requirements of DDR memory by combining

two linear regulators into a single TO-263 or TO-252 5-

lead package. The VDDQ regulator can supply up to 5A

continuous current, and the two-quadrant VTT termina-

tion regulator has current sink and source capability to

±2A. The VDDQ linear regulator uses a PMOS pass

element for a very low dropout voltage, typically 600mV

at a 5A output. The output voltage of the VDDQ regula-

tor can be set by an external voltage divider. The sec-

ond output, VTT

, is regulated at VDDQ/2 by an internal

resistor divider. The VTT regulator can source, as well

as sink, up to 2A continuous current. The CM3205 is

designed for optimal operation from a nominal 3.3VDC

bus, but can work with VIN as high as 5V. When operat-

ing at higher VIN voltages, attention must be given to

the increased package power dissipation and propor-

tionally increased heat generation.

VREF is typically routed to inputs with high impedance,

such as a comparator, with little current draw. An ade-

quate VREF can be created with a simple voltage

divider of precision, matched resistors from VDDQ to

ground. A small ceramic bypass capacitor can also be

added for improved noise performance.

Input and Output Capacitors

The CM3205 requires that at least a 680μF electrolytic

capacitor be located near the VIN pin for stability and to

maintain the input bus voltage during load transients.

An additional 4.7μF ceramic capacitor between the VIN

(pin 4) and the GND (pin 5), located as close as possi-

ble to those pins, is recommended to ensure stability.

A minimum of a 680μF electrolytic capacitor is recom-

mended for the VDDQ output. An additional 4.7μF

ceramic capacitor between the VDDQ (pin 2) and GND,

located very close to those pins, is recommended.

A minimum of a 680μF, electrolytic capacitor is recom-

mended for the VTT output. This capacitor should have

low ESR to achieve best output transient response. SP

or OSCON capacitors provide low ESR at high fre-

quency, and thus are a good choice. In addition, place

a 4.7μF ceramic capacitor between the VTT pin (pin 5)

and GND, located very close to those pins. The total

ESR must be low enough to keep the transient within

the VTT window of 40-mV during the transition for

source to sink. An average current step of ±0.5A

requires:

Both outputs will remain stable and in regulation even

during light or no load conditions.

Adjusting VDDQ Output Voltage

The CM3205 internal bandgap reference is set at

1.215V. The VDDQ voltage is adjustable by using a

resistor divider, R1 and R2:

Iterminaton 405mV

Rt 25Ω()

---------------------- 16.2mA==

ESR 40mV

---------------

<40mΩ=

VOUT VADJ 1R2

-------+

⎝⎠

⎛⎞

×=

Application Information (cont’d)

8490 N. McCarthy Blvd., Milpitas, CA 95035-5112 lTel: 408.263.3214 lFax: 408.263.7846 lwww.cmd.com 05/08/06

CM3205

PRELIMINARY

where VADJ = 1.215V (±-1%). For best regulator stabil-

ity, we recommend that R1 and R2 not exceed 10-kΩ

each.

Shutdown

Pin 1 (ADJSD) also serves as a shutdown pin. When

pin 1 is pulled high, > (VIN - 1.2V), the VDDQ output is

turned off and both source and sink MOSFET’s of the

VTT regulator are set to a high impedance state. During

shutdown, the quiescent current is reduced to less than

3mA, independent of output load.

It is recommended that a 1N91 4 or equivalent low leak-

age diode be placed between Pin 1 and an external

shutdown signal to prevent interference with the ADJ

pin’s normal opera tion. When the diode a node is pulled

low, or left open, the CM3205 is again enabled.

Current Limit, Foldback and Over-temperature Pro-

tection

The CM3205 features internal current limiting with ther-

mal protection. During normal operation, VDDQ limits

the output current to approximately 8A and VTT limits

the output current to approximately ±2A. When VTT is

current limiting into a hard short circuit, the output cur-

rent folds back to a lower level, about 1.5A, until the

over-current condition ends. While current limiting is

designed to prevent gross device failure, care should

be taken not to exceed the power dissipation ratings of

the package. If the junction temperature of the device

exceeds 170-°C (typical), the thermal protection cir-

cuitry triggers and shuts down both outputs. Once the

junction temperature has cooled to below about

120-°C, the CM3205 returns to normal operation.

Thermal Considerations

Both the TO-252 and the TO-263 packages provide a

very effective thermal conduction path from the silicon

junction into the PC board to which it is mounted. See

Figure 2 below. These surface mount packages have a

large metal tab that solders to the PC board, where the

ground plane can serve as heatsink. This metal tab

connects internally to GND (pin 3). A top-layer ground

plane is the best in terms of convection air-cooling, a

bottom-layer ground plane is less effective, and a mid-

dle layer ground plane of a multiple-layer PC board is

the least effective.

We recommend the metal tab of CM3205 be soldered

to a minimum of 3 square inches of ground plane on

the top side of the PC board. Use 20 or more plate-

through vias to connect the top layer ground plane to

ground planes on other layers.

When measured in accordance to JEDEC JESD51-3,

under natural convection without forced airflow, the

Theta junction-to-air (θja) resistance is approximately

48-°C/watt for the CM3205-00TN (TO-263-5), and

55-°C/watt for the CM3205-00TP (TO-252-5).

Figure 2. Thermal Layout

Ground

Plane

Vias (0.3mm

Diameter)

(TOP VIEW) (SIDE VIEW)

Bottom

Ground

Plane

Via

Top

Ground

Plane

Power Trace

Via (0.3mm

Diameter)

Application Information (cont’d)

05/08/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 lTel: 408.263.3214 lFax: 408.263.7846 lwww.cmd.com 9

CM3205

PRELIMINARY

TO-263-5 Mechanical Specifications

Dimensions for CM3205-00TN devices packaged in 5-

lead, standard TO-263 packages are presented below.

* This is an approximate amount which may vary.

Package Dimensions for Standard TO-263

PACKAGE DIMENSIONS

Package TO-263

Pins 5

Dimensions Millimeters Inches

Min Max Min Max

A4.34 4.60 0.171 0.181

b0.74 0.89 0.029 0.035

c0.33 0.43 0.013 0.017

D8.92 9.17 0.351 0.361

E10.16 10.67 0.400 0.420

e1.70 REF 0.067 REF

L14.61 15.88 0.575 0.625

L1 2.29 2.79 0.090 0.110

L2 1.14 1.40 0.045 0.055

M0.23 0.30 0.009 0.012

P1.14 1.40 0.045 0.055

S1.40 1.91 0.055 0.075

# per tape

and reel

750 pieces

Controlling dimension: inches

Mechanical Package Diagrams

TOP VIEW

SIDE VIEW

LEADFORM

123

18-22°L2

SEATING PLANE

-8

Pin 1

Marking

Mechanical Details

05/08/06 490 N. McCarthy Blvd., Milpitas, CA 95035-5112 lTel: 408.263.3214 lFax: 408.263.7846 lwww.cmd.com 10

CM3205

PRELIMINARY

TO-252-5 Mechanical Specifications

Dimensions for CM3205-00TP devices packaged in 5-

pin TO-252 packages are presented below.

Package Dimensions for TO252-5

PACKAGE DIMENSIONS

Package TO-252

Pins 5

Dimensions Millimeters Inches

Min Max Min Max

A6.40 6.80 0.252 0.268

B5.20 5.50 0.205 0.217

C6.80 7.20 0.268 0.283

D2.20 2.80 0.087 0.110

G0.40 0.60 0.016 0.024

H2.20 2.40 0.087 0.094

J0.45 0.55 0.018 0.022

K0 0.15 0 0.006

L0.90 1.50 0.035 0.059

M5.40 5.80 0.213 0.228

P1.27 REF 0.05 REF

S0.50 0.80 0.020 0.031

# per tape

and reel

750 pieces

Controlling dimension: inches

Mechanical Package Diagrams

FRONT VIEW

SIDE VIEW

LEADFORM

123

-15

SEATING PLANE

-10

Pin 1

Marking

BACK VIEW

Mechanical Details (cont’d)