CY7C63310 CY7C638xx enCoReTM II Low-Speed USB Peripheral Controller 1.0 Features * enCoReTM II USB--"enhanced Component Reduction" -- Crystalless oscillator with support for an external clock. The internal oscillator eliminates the need for an external crystal or resonator -- Two internal 3.3V regulators and internal USB pull-up resistor -- Configurable IO for real-world interface without external components * USB Specification Compliance -- Conforms to USB Specification, Version 2.0 -- Conforms to USB HID Specification, Version 1.1 -- Supports one Low-Speed USB device address -- Supports one control endpoint and two data endpoints -- Integrated USB transceiver with dedicated 3.3V regulator for USB signalling and D- pull up. * Enhanced 8-bit microcontroller -- Harvard architecture -- M8C CPU speed can be up to 24 MHz or sourced by an external clock signal * Internal memory -- Up to 256 bytes of RAM -- Up to eight Kbytes of Flash including EEROM emulation * Interface can autoconfigure to operate as PS/2 or USB -- No external components for switching between PS/2 and USB modes -- No GPIO pins needed to manage dual-mode capability * Low power consumption -- Typically 10 mA at 6 MHz -- 10 A sleep * In-system re-programmability -- Allows easy firmware update * General purpose I/O ports -- Up to 20 General Purpose I/O (GPIO) pins -- High current drive on GPIO pins. Configurable 8- or 50mA/pin current sink on designated pins -- Each GPIO port supports high-impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs, and CMOS output -- 4 I/O pins with 3.3V logic levels -- Each 3.3V pin supports high-impedance input, internal pull up, open drain output or traditional CMOS output * SPI serial communication -- Master or slave operation -- Configurable up to 4 Mbit/second transfers in the master mode -- Supports half duplex single data line mode for optical sensors * 2-channel 8-bit or 1-channel 16-bit capture timer registers. Capture timer registers store both rising and falling edge times -- Two registers each for two input pins -- Separate registers for rising and falling edge capture -- Simplifies interface to RF inputs for wireless applications * Internal low-power wake-up timer during suspend mode -- Periodic wake-up with no external components * 12-bit Programmable Interval Timer with interrupts * Advanced development tools based on Cypress MicroSystems PSoCTM tools * Watchdog timer (WDT) * Low-voltage detection with user-configurable threshold voltages * Operating voltage from 4.0V to 5.5VDC * Operating temperature from 0-70C * Available in 16/18-pin PDIP, 16/18/24-pin SOIC, 24-pin QSOP and 32-lead QFN packages * Industry standard programmer support 1.1 The CY7C63310/CY7C638xx is targeted for the following applications: * PC HID devices -- Mice (optomechanical, optical, trackball) * Gaming -- Joysticks -- Game pad * General-purpose -- Barcode scanners -- Maskable interrupts on all I/O pins * A dedicated 3.3V regulator for the USB PHY. Aids in signalling and D-line pull-up * 125 mA 3.3V voltage regulator can power external 3.3V devices * 3.3V I/O pins Cypress Semiconductor Corporation Document 38-08035 Rev. *I * Applications 198 Champion Court -- POS terminal -- Consumer electronics -- Toys -- Remote controls -- Security dongles * San Jose, CA 95134-1709 * 408-943-2600 Revised September 26, 2006 [+] Feedback CY7C63310 CY7C638xx 2.0 Introduction Cypress has reinvented its leadership position in the lowspeed USB market with a new family of innovative microcontrollers. Introducing enCoRe II USB -- "enhanced Component Reduction." Cypress has leveraged its design expertise in USB solutions to advance its family of low-speed USB microcontrollers, which enable peripheral developers to design new products with a minimum number of components. The enCoRe II USB technology builds on to the enCoRe family. The enCoRe family has an integrated oscillator that eliminates the external crystal or resonator, reducing overall cost. Also integrated into this chip are other external components commonly found in low-speed USB applications such as pullup resistors, wake-up circuitry, and a 3.3V regulator. All of this reduces the overall system cost. The enCoRe II is an 8-bit Flash-programmable microcontroller with integrated low-speed USB interface. The instruction set has been optimized specifically for USB and PS/2 operations, although the microcontrollers can be used for a variety of other embedded applications. The enCoRe II features up to 20 general-purpose I/O (GPIO) pins to support USB, PS/2 and other applications. The I/O pins are grouped into four ports (Port 0 to 3). The pins on Port 0 and Port 1 may each be configured individually while the pins on Ports 2 and 3 may only be configured as a group. Each GPIO port supports high-impedance inputs, configurable pull up, open drain output, CMOS/TTL inputs, and CMOS output with up to five pins that support programmable drive strength of up to 50 mA sink current. GPIO Port 1 features four pins that interface at a voltage level of 3.3 volts. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Each GPIO port has its own GPIO interrupt vector; in addition GPIO Port 0 has three dedicated pins that have independent interrupt vectors (P0.2 - P0.4). The enCoRe II features an internal oscillator. With the presence of USB traffic, the internal oscillator can be set to precisely tune to USB timing requirements (24 MHz 1.5%). Optionally, an external 12 MHz or 24 MHz clock can be used to provide a higher precision reference for USB operation. The clock generator provides the 12 MHz and 24 MHz clocks that remain internal to the microcontroller. The enCoRe II also has a 12-bit programmable interval timer and a 16-bit FreeRunning Timer with Capture Timer registers. In addition, the enCoRe II includes a Watchdog timer and a vectored interrupt controller The enCoRe II has up to eight Kbytes of Flash for user's code and up to 256 bytes of RAM for stack space and user variables. The Power-on reset circuit detects logic when power is applied to the device, resets the logic to a known state, and begins executing instructions at Flash address 0x0000. When power falls below a programmable trip voltage generates reset or may be configured to generate interrupt. There is a Lowvoltage detect circuit that detects when VCC drops below a programmable trip voltage. It may be configurable to generate an LVD interrupt to inform the processor about the low-voltage Document 38-08035 Rev. *I event. POR and LVD share the same interrupt. There is no separate interrupt for each. The Watchdog timer can be used to ensure the firmware never gets stalled in an infinite loop. The microcontroller supports 22 maskable interrupts in the vectored interrupt controller. Interrupt sources include a USB bus reset, LVR/POR, a programmable interval timer, a 1.024-ms output from the Free Running Timer, three USB endpoints, two capture timers, four GPIO Ports, three Port 0 pins, two SPI, a 16-bit free running timer wrap, an internal sleep timer, and a bus active interrupt. The sleep timer causes periodic interrupts when enabled. The USB endpoints interrupt after a USB transaction complete is on the bus. The capture timers interrupt whenever a new timer value is saved due to a selected GPIO edge event. A total of seven GPIO interrupts support both TTL or CMOS thresholds. For additional flexibility, on the edge sensitive GPIO pins, the interrupt polarity is programmable to be either rising or falling. The free-running 16-bit timer provides two interrupt sources: the 1.024 ms outputs and the free running counter wrap interrupt. The programmable interval timer can provide up to 1 sec resolution and provides an interrupt everytime it expires. These timers can be used to measure the duration of an event under firmware control by reading the desired timer at the start and at the end of an event, then calculating the difference between the two values. The two 8-bit capture timer registers save a programmable 8-bit range of the free-running timer when a GPIO edge occurs on the two capture pins (P0.5, P0.6). The two 8-bit captures can be ganged into a single 16-bit capture. The enCoRe II includes an integrated USB serial interface engine (SIE) that allows the chip to easily interface to a USB host. The hardware supports one USB device address with three endpoints. The USB D+ and D- pins can optionally be used as PS/2 SCLK and SDATA signals so that products can be designed to respond to either USB or PS/2 modes of operation. PS/2 operation is supported with internal 5 K pull-up resistors on P1.0 (D+) and P1.1 (D-) and an interrupt to signal the start of PS/2 activity. In USB mode, the integrated 1.5 K pull-up resistor on D- can be controlled under firmware. No external components are necessary for dual USB and PS/2 systems, and no GPIO pins need to be dedicated to switching between modes. The enCoRe II supports in-system programming by using the D+ and D- pins as the serial programming mode interface. The programming protocol is not USB. 3.0 Conventions In this document, bit positions in the registers are shaded to indicate which members of the enCoRe II family implement the bits. Available in all enCoRe II family members CY7C638xx only Page 2 of 74 [+] Feedback CY7C63310 CY7C638xx 4.0 Logic Block Diagram Figure 4-1. CY7C63310/CY7C638xx Block Diagram 3.3V Regulator Low-Speed USB/PS2 Transceiver and Pull-up Low-Speed USB SIE Interrupt Control 4 3VIO/SPI Pins Up to 14 Extended I/O Pins Up to 6 GPIO pins Wakeup Timer Internal 24 MHz Oscillator M8C CPU Clock Control RAM Up to 256 Byte Flash Up to 8K Byte 12-bit Timer 16-bit Free running timer External Clock Watchdog Timer Vdd POR / Low-Voltage Detect Document 38-08035 Rev. *I Page 3 of 74 [+] Feedback CY7C63310 CY7C638xx 5.0 Packages/Pinouts Figure 5-1. Package Configurations Top View CY7C63801 16-pin PDIP CY7C63310 16-pin PDIP SSEL/P1.3 SCLK/P1.4 SMOSI/P1.5 SMISO/P1.6 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CY7C63801 16-pin SOIC CY7C63310 16-pin SOIC P1.2 VCC P1.1/D- P1.0/D+ VSS P0.0 P0.1 P0.2/INT0 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 P0.1 P0.0 VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 16 15 14 13 12 11 10 9 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 P0.1 P0.0 VSS P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2 VCC P1.1/D- P1.0/D+ 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2/VREG VCC P1.1/D- P1.0/D+ CY7C63823 24-pin SOIC CY7C63813 18-pin PDIP SSEL/P1.3 SCLK/P1.4 SMOSI/P1.5 SMISO/P1.6 P1.7 P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 1 2 3 4 5 6 7 8 CY7C63803 16-pin SOIC CY7C63813 18-pin SOIC P1.2/VREG VCC P1.1/D- P1.0/D+ VSS P0.0 P0.1 P0.2/INT0 P0.3/INT1 P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 P0.1 P0.0 VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 P0.1 P0.0 P2.1 P2.0 VSS P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2/VREG VCC P1.1/D- P1.0/D+ 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P3.1 P3.0 P1.3/SSEL P1.2/VREG VCC P1.1/D- P1.0/D+ Document 38-08035 Rev. *I P1.6/MISO P1.7 NC NC NC NC 32 31 30 29 28 27 26 25 P0.6/TIO1 1 24 P1.5/SMOSI P0.5/TIO0 2 23 P1.4/SCLK P3.1 P0.4/INT2 3 22 P0.3/INT1 4 21 P3.0 P0.2/INT0 5 20 P1.3/SSEL P0.1 6 19 P0.0 7 18 P2.1 8 17 NC P1.2/VREG NC Vdd P1.1/D- P1.0/D+ Vss 9 10 11 12 13 14 15 16 NC P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P3.1 P3.0 P1.3/SSEL P1.2/VREG VCC P1.1/D- P1.0/D+ VSS NC 24 23 22 21 20 19 18 17 16 15 14 13 NC 1 2 3 4 5 6 7 8 9 10 11 12 P2.0 NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 P0.1 P0.0 P2.1 P2.0 NC P0.7 CY7C63823 24-pin QSOP NC CY7C63833 32-lead QFN Page 4 of 74 [+] Feedback CY7C63310 CY7C638xx 5.1 Pinouts Assignments Table 5-1. Pin Assignments 32 QFN 24 QSOP 24 SOIC 21 19 18 P3.0 22 20 19 P3.1 18 SIOC 18 PDIP 16 SOIC 16 PDIP Name Description GPIO Port 3 - configured as a group (byte) 9 11 11 P2.0 8 10 10 P2.1 GPIO Port 2 - configured as a group (byte) 14 14 13 10 15 9 13 P1.0/D+ GPIO Port 1 bit 0/USB D+[1] If this pin is used as a General Purpose output, it will draw current. This pin must be configured as an input to reduce current draw. 15 15 14 11 16 10 14 P1.1/D- GPIO Port 1 bit 1/USB D-[1] If this pin is used as a General Purpose output, it will draw current. This pin must be configured as an input to reduce current draw. 18 17 16 13 18 12 16 P1.2/VREG GPIO Port 1 bit 2--Configured individually. 3.3V if regulator is enabled. (The 3.3V regulator is not available in the CY7C63310 and CY7C63801.) A 1-F min, 2-F max capacitor is required on Vreg output. 20 18 17 14 1 13 1 P1.3/SSEL GPIO Port 1 bit 3--Configured individually. Alternate function is SSEL signal of the SPI bus TTL voltage thresholds. Although Vreg is not available with the CY7C63310, 3.3V I/O is still available. 23 21 20 15 2 14 2 P1.4/SCLK GPIO Port 1 bit 4--Configured individually. Alternate function is SCLK signal of the SPI bus TTL voltage thresholds. Although Vreg is not available with the CY7C63310, 3.3V I/O is still available. 24 22 21 16 3 15 3 P1.5/SMOSI GPIO Port 1 bit 5--Configured individually. Alternate function is SMOSI signal of the SPI bus TTL voltage thresholds. Although Vreg is not available with the CY7C63310, 3.3V I/O is still available. 25 23 22 17 4 16 4 P1.6/SMISO GPIO Port 1 bit 6--Configured individually. Alternate function is SMISO signal of the SPI bus TTL voltage thresholds. Although Vreg is not available with the CY7C63310, 3.3V I/O is still available. 26 24 23 18 5 7 9 9 8 13 7 6 8 8 7 12 5 7 7 6 4 6 6 3 5 5 P1.7 GPIO Port 1 bit 7--Configured individually. TTL voltage threshold. 11 P0.0 GPIO Port 0 bit 0--Configured individually. On CY7C638xx and CY7C63310, external clock input when configured as Clock In. 6 10 P0.1 GPIO Port 0 bit 1--Configured individually On CY7C638xx and CY7C63310, clock output when configured as Clock Out. 11 5 9 P0.2/INT0 GPIO port 0 bit 2--Configured individually Optional rising edge interrupt INT0 5 10 4 8 P0.3/INT1 GPIO port 0 bit 3--Configured individually Optional rising edge interrupt INT1 4 9 3 7 P0.4/INT2 GPIO port 0 bit 4--Configured individually Optional rising edge interrupt INT2 Note 1. P1.0(D+) and P1.1(D-) pins must be in I/O mode when used as GPIO and in Isb mode. Document 38-08035 Rev. *I Page 5 of 74 [+] Feedback CY7C63310 CY7C638xx Table 5-1. Pin Assignments (continued) 32 QFN 24 QSOP 24 SOIC 18 SIOC 18 PDIP 16 SOIC 16 PDIP 2 4 4 3 8 2 6 P0.5/TIO0 GPIO port 0 bit 5--Configured individually Alternate function Timer capture inputs or Timer output TIO0 1 3 3 2 7 1 5 P0.6/TIO1 GPIO port 0 bit 6--Configured individually Alternate function Timer capture inputs or Timer output TIO1 32 2 2 1 6 10 1 1 NC No connect 11 12 24 Name P0.7 Description GPIO port 0 bit 7--Configured individually Not present in the 16 pin PDIP or SOIC package NC No connect 12 NC No connect 17 NC No connect 19 NC No connect 27 NC No connect 28 NC No connect 29 NC No connect 30 NC No connect 31 NC No connect 16 16 15 12 17 11 15 Vcc Supply 13 13 12 9 14 8 12 VSS Ground 6.0 CPU Architecture This family of microcontrollers is based on a high performance, 8-bit, Harvard-architecture microprocessor. Five registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not directly accessible through the register space by the user. Table 6-1. CPU Registers and Register Names Register Register Name Flags CPU_F Program Counter CPU_PC Accumulator CPU_A Stack Pointer CPU_SP Index CPU_X The 16-bit Program Counter Register (CPU_PC) allows for direct addressing of the full eight Kbytes of program memory space. Document 38-08035 Rev. *I The Accumulator Register (CPU_A) is the general-purpose register that holds the results of instructions that specify any of the source addressing modes. The Index Register (CPU_X) holds an offset value that is used in the indexed addressing modes. Typically, this is used to address a block of data within the data memory space. The Stack Pointer Register (CPU_SP) holds the address of the current top-of-stack in the data memory space. It is affected by the PUSH, POP, LCALL, CALL, RETI, and RET instructions, which manage the software stack. It can also be affected by the SWAP and ADD instructions. The Flag Register (CPU_F) has three status bits: Zero Flag bit [1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global Interrupt Enable bit [0] is used to globally enable or disable interrupts. The user cannot manipulate the Supervisory State status bit [3]. The flags are affected by arithmetic, logic, and shift operations. The manner in which each flag is changed is dependent upon the instruction being executed (i.e., AND, OR, XOR). See Table 8-1. Page 6 of 74 [+] Feedback CY7C63310 CY7C638xx 7.0 CPU Registers 7.1 Flags Register The Flags Register can only be set or reset with logical instruction. Table 7-1. CPU Flags Register (CPU_F) [R/W] Bit # 7 Field 6 5 Reserved 4 3 2 1 0 XIO Super Carry Zero Global IE Read/Write - - - R/W R RW RW RW Default 0 0 0 0 0 0 1 0 Bit [7:5]: Reserved Bit 4: XIO Set by the user to select between the register banks 0 = Bank 0 1 = Bank 1 Bit 3: Super Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed directly by the user) 0 = User Code 1 = Supervisor Code Bit 2: Carry Set by CPU to indicate whether there has been a carry in the previous logical/arithmetic operation 0 = No Carry 1 = Carry Bit 1: Zero Set by CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation 0 = Not Equal to Zero 1 = Equal to Zero Bit 0: Global IE Determines whether all interrupts are enabled or disabled 0 = Disabled 1 = Enabled Note: CPU_F register is only readable with explicit register address 0xF7. The OR F, expr and AND F, expr instructions must be used to set and clear the CPU_F bits Table 7-2. CPU Accumulator Register (CPU_A) Bit # 7 6 5 Field 4 3 2 1 0 CPU Accumulator [7:0] Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 1 0 Bit [7:0]: CPU Accumulator [7:0] 8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode Table 7-3. CPU X Register (CPU_X) Bit # 7 6 5 4 Field 3 2 X [7:0] Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 2 1 0 Bit [7:0]: X [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode Table 7-4. CPU Stack Pointer Register (CPU_SP) Bit # 7 6 5 Field 4 3 Stack Pointer [7:0] Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit [7:0]: Stack Pointer [7:0] 8-bit data value holds a pointer to the current top-of-stack Document 38-08035 Rev. *I Page 7 of 74 [+] Feedback CY7C63310 CY7C638xx Table 7-5. CPU Program Counter High Register (CPU_PCH) Bit # 7 6 5 Field 4 3 2 1 0 Program Counter [15:8] Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 3 2 1 0 Bit [7:0]: Program Counter [15:8] 8-bit data value holds the higher byte of the program counter Table 7-6. CPU Program Counter Low Register (CPU_PCL) Bit # 7 6 5 Field 4 Program Counter [7:0] Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit [7:0]: Program Counter [7:0] 8-bit data value holds the lower byte of the program counter 7.2 Addressing Modes 7.2.1 Source Immediate Examples The result of an instruction using this addressing mode is placed in the A register, the F register, the SP register, or the X register, which is specified as part of the instruction opcode. Operand 1 is an immediate value that serves as a source for the instruction. Arithmetic instructions require two sources; the second one is the A or the X register specified in the opcode. Instructions using this addressing mode are two bytes in length. ADD A, [7] ;In this case, the; value in; the RAM memory location at; address 7 is added with the; Accumulator, and the result; is placed in the Accumulator. MOV X, REG[8] ;In this case, the value in; the register space at address; 8 is moved to the X register. Table 7-7. Source Immediate Opcode Operand 1 Instruction Immediate Value Examples ADD A, 7 ;In this case, the immediate value; of 7 is added with the Accumulator,; and the result is placed in the; Accumulator. MOV X, 8 ;In this case, the immediate value; of 8 is moved to the X register. AND F, 9 ;In this case, the immediate value; of 9 is logically ANDed with the F; register and the result is placed; in the F register. 7.2.2 Source Indexed The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is added to the X register forming an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 7-9. Source Indexed Opcode Instruction Source Direct The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two sources; the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 7-8. Source Direct Opcode Instruction 7.2.3 Operand 1 Source Index Examples ADD A, [X+7] ;In this case, the value in; the memory location at; address X + 7 is added with; the Accumulator, and the; result is placed in the; Accumulator. MOV X, REG[X+8] ;In this case, the value in; the register space at; address X + 8 is moved to; the X register. Operand 1 Source Address Document 38-08035 Rev. *I Page 8 of 74 [+] Feedback CY7C63310 CY7C638xx 7.2.4 Destination Direct The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is an address that points to the location of the result. The source for the instruction is either the A register or the X register, which is specified as part of the instruction opcode. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are two bytes in length. Table 7-10. Destination Direct Opcode Opcode Instruction Operand 1 Destination Address A A ;In this case, the value in; the memory location at; address 7 is added with the; Accumulator, and the result; is placed in the memory; location at address 7. The; Accumulator is unchanged. MOV REG[8], ;In this case, the Accumulator is moved to the register space location at address 8. The Accumulator is unchanged. 7.2.5 Destination Indexed ADD [7], 5 ;In this case, value in the memory location at address 7 is added to the immediate value of 5, and the result is placed in the memory location at address 7. MOV REG[8], 6 ;In this case, the immediate; value of 6 is moved into the; register space location at; address 8. 7.2.7 Destination Indexed Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register to form the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are three bytes in length. Table 7-13. Destination Indexed Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is added to the X register forming the address that points to the location of the result. The source for the instruction is the A register. Arithmetic instructions require two sources; the second source is the location specified by Operand 1 added with the X register. Instructions using this addressing mode are two bytes in length. Opcode Instruction Operand 1 Destination Index Destination Index [X+7], 5 ;In this case, the value in; the memory location at; address X+7 is added with; the immediate value of 5,; and the result is placed; in the memory location at; address X+7. MOV REG[X+8], 6 ;In this case, the immediate value of 6 is moved; into the location in the; register space at; address X+8. Example ADD 7.2.6 [X+7], A ;In this case, the value in the; memory location at address X+7; is added with the Accumulator,; and the result is placed in; the memory location at address; x+7. The Accumulator is; unchanged. Destination Direct Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source Document 38-08035 Rev. *I Immediate Value ADD Operand 1 Instruction Operand 2 Examples Table 7-11. Destination Indexed Opcode Operand 2 Immediate Value Examples Destination Address Examples [7], Table 7-12. Destination Direct Source Immediate Operand 1 Instruction ADD is the location specified by Operand 1. Instructions using this addressing mode are three bytes in length. 7.2.8 Destination Direct Source Direct The result of an instruction using this addressing mode is placed within the RAM memory. Operand 1 is the address of the result. Operand 2 is an address that points to a location in the RAM memory that is the source for the instruction. This addressing mode is only valid on the MOV instruction. The instruction using this addressing mode is three bytes in length. Table 7-14. Destination Direct Source Direct Opcode Instruction Operand 1 Destination Address Operand 2 Source Address Page 9 of 74 [+] Feedback CY7C63310 CY7C638xx 7.2.10 Example MOV 7.2.9 [7], [8] ;In this case, the value in the; memory location at address 8 is; moved to the memory location at; address 7. Source Indirect Post Increment The result of an instruction using this addressing mode is placed in the Accumulator. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the source of the instruction. The indirect address is incremented as part of the instruction execution. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. Refer to the PSoC Designer: Assembly Language User Guide for further details on MVI instruction. Destination Indirect Post Increment The result of an instruction using this addressing mode is placed within the memory space. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the destination of the instruction. The indirect address is incremented as part of the instruction execution. The source for the instruction is the Accumulator. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. Table 7-16. Destination Indirect Post Increment Opcode Operand 1 Instruction Destination Address Address Example Table 7-15. Source Indirect Post Increment Opcode Instruction Operand 1 Source Address Address Example MVI A, [8] MVI [8], A ;In this case, the value in; the memory location at; address 8 is an indirect; address. The Accumulator is; moved into the memory location pointed to by the indirect address. The indirect; address is then incremented. ;In this case, the value in the; memory location at address 8 is an indirect address. The memory location pointed to by the indirect address is moved into the Accumulator. The indirect address is then incremented. Document 38-08035 Rev. *I Page 10 of 74 [+] Feedback CY7C63310 CY7C638xx 8.0 Instruction Set Summary Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on the www.cypress.com web site). 2E 9 3 OR [expr], expr C, Z 2F 10 3 OR [X+expr], expr 2 ADD A, [X+expr] C, Z 30 9 1 HALT 2 ADD [expr], A C, Z 31 4 2 XOR A, expr Z 8 2 ADD [X+expr], A C, Z 32 6 2 XOR A, [expr] Z 5F 10 3 MOV [expr], [expr] 9 4 2 ADD A, expr 02 6 2 ADD A, [expr] 03 7 04 7 05 06 Instruction Format 5A 5 2 MOV [expr], X Z 5B 4 1 MOV A, X Z 5C 4 1 MOV X, A 5D 6 2 MOV A, reg[expr] Z 5E 7 2 MOV A, reg[X+expr] Z Flags Bytes C, Z 01 Flags Cycles Z 1 SSC Opcode Hex Cycles 2 OR [X+expr], A Instruction Format 00 15 Bytes Opcode Hex 8 Bytes 2D Cycles Opcode Hex The instruction set is summarized in Table 8-1 numerically and serves as a quick reference. If more information is needed, the Table 8-1. Instruction Set Summary Sorted Numerically by Opcode Order[2, 3] Instruction Format Flags Z 3 ADD [expr], expr C, Z 33 7 2 XOR A, [X+expr] Z 60 5 2 MOV reg[expr], A 07 10 3 ADD [X+expr], expr C, Z 34 7 2 XOR [expr], A Z 61 6 2 MOV reg[X+expr], A 08 4 1 PUSH A 35 8 2 XOR [X+expr], A Z 62 8 3 MOV reg[expr], expr 09 4 2 ADC A, expr C, Z 36 9 3 XOR [expr], expr Z 63 9 3 MOV reg[X+expr], expr 0A 6 2 ADC A, [expr] C, Z 37 10 3 XOR [X+expr], expr Z 64 4 1 ASL A C, Z 0B 7 2 ADC A, [X+expr] C, Z 38 5 2 ADD SP, expr 65 7 2 ASL [expr] C, Z 0C 7 2 ADC [expr], A C, Z 39 5 2 CMP A, expr 66 8 2 ASL [X+expr] C, Z 0D 8 2 ADC [X+expr], A C, Z 3A 7 2 CMP A, [expr] 67 4 1 ASR A C, Z 0E 9 3 ADC [expr], expr C, Z 3B 8 2 CMP A, [X+expr] 68 7 2 ASR [expr] C, Z 0F 10 3 ADC [X+expr], expr C, Z 3C 8 3 CMP [expr], expr 69 8 2 ASR [X+expr] C, Z 10 4 1 PUSH X 3D 9 3 CMP [X+expr], expr 6A 4 1 RLC A C, Z 11 4 2 SUB A, expr C, Z 3E 10 2 MVI A, [ [expr]++] 6B 7 2 RLC [expr] C, Z 12 6 2 SUB A, [expr] C, Z 3F 10 2 MVI [ [expr]++], A 6C 8 2 RLC [X+expr] C, Z 13 7 2 SUB A, [X+expr] C, Z 40 4 1 NOP 6D 4 1 RRC A C, Z 14 7 2 SUB [expr], A C, Z 41 9 3 AND reg[expr], expr Z 6E 7 2 RRC [expr] C, Z 15 8 2 SUB [X+expr], A C, Z 42 10 3 AND reg[X+expr], expr Z 6F 8 2 RRC [X+expr] C, Z 16 9 3 SUB [expr], expr C, Z 43 3 OR reg[expr], expr Z 70 4 2 AND F, expr C, Z 17 10 3 SUB [X+expr], expr C, Z 44 10 3 OR reg[X+expr], expr Z 71 4 2 OR F, expr C, Z 18 5 1 POP A 45 3 XOR reg[expr], expr Z 72 4 2 XOR F, expr C, Z 19 4 2 SBB A, expr C, Z 46 10 3 XOR reg[X+expr], expr Z 73 4 1 CPL A Z 1A 6 2 SBB A, [expr] C, Z 47 8 3 TST [expr], expr Z 74 4 1 INC A C, Z Z 9 9 if (A=B) Z=1 if (A