SPRS009C–JANUARY 1987–REVISED JULY 1991
TMS320C1x
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
Copyright 1991, Texas Instruments Incorporated
1
PRODUCTION DATA information is current as of
publication date. Products conform to specifications
per the terms of T exas Instruments standard warranty.
Production processing does not necessarily include
testing of all parameters.
•Performance Up to 8.77 MIPs
•All TMS320C1x Devices are Object Code
Compatible
•144/256-Word On-Chip Data RAM
•1.5K/4K/8K-W ord On-Chip Program ROM
•4K-Word On-Chip Program EPROM
(TMS320E14/P14/E15/P15/E17/P17)
•One-Time Programmable (OTP)
Versions A vailable (TMS320P14/P15/P17)
•EPROM Code Protection for Copyright
Security
•4K / 64K-Word Total External Memory at
Full Speed
•32-Bit ALU/Accumulator
•16 × 16-Bit Multiplier With a 32-Bit Product
•0 to 16-Bit Barrel Shifter
•Eight Input/Output Channels
•Dual-Channel Serial Port
•Simple Memory and I/O Interface
•5-V and 3.3-V Versions Available
(TMS320LC15/LC17)
•Commercial and Military Versions Available
•Operating Free-Air Temperature
. . . 0°C to 70°C
•Packaging: DIP, PLCC, Quad Flatpack, and
CER-QUAD
•CMOS Technology:
Device Cycle Time
— TMS320C10 200-ns. . . . . . . . . . . . . . . . . . .
— TMS320C10-14 280-ns. . . . . . . . . . . . . . . .
— TMS320C10-25 160-ns. . . . . . . . . . . . . . . .
— TMS320C14 160-ns. . . . . . . . . . . . . . . . . . .
— TMS320E14 160-ns. . . . . . . . . . . . . . . . . . .
— TMS320P14 160-ns. . . . . . . . . . . . . . . . . . .
— TMS320C15 200-ns. . . . . . . . . . . . . . . . . . .
— TMS320C15-25 160-ns. . . . . . . . . . . . . . . .
— TMS320E15 200-ns. . . . . . . . . . . . . . . . . . .
— TMS320E15-25 160-ns. . . . . . . . . . . . . . . .
— TMS320LC15 250-ns. . . . . . . . . . . . . . . . . .
— TMS320P15 200-ns. . . . . . . . . . . . . . . . . . .
— TMS320C16 114-ns. . . . . . . . . . . . . . . . . . .
— TMS320C17 200-ns. . . . . . . . . . . . . . . . . . .
— TMS320E17 200-ns. . . . . . . . . . . . . . . . . . .
— TMS320LC17 278-ns. . . . . . . . . . . . . . . . . .
— TMS320P17 200-ns. . . . . . . . . . . . . . . . . . .
introduction
The TMS32010 digital signal processor (DSP), introduced in 1983, was the first DSP in the TMS320 family. From
it has evolved this TMS320C1x generation of 16-bit DSPs. All ′C1x DSPs are object code compatible with the
TMS32010 DSP. The ′C1x DSPs combine the flexibility of a high-speed controller with the numerical capability
of an array processor, thereby offering an inexpensive alternative to multichip bit-slice processors. The highly
paralleled architecture and efficient instruction set provide speed and flexibility to produce a CMOS
microprocessor generation capable of executing up to 8.77 MIPS (million instructions per second) (′C16). These
′C1x devices utilize a modified Harvard architecture to optimize speed and flexibility , implementing functions in
hardware that other processors implement through microcode or software.
The ′C1x generation’s powerful instruction set, inherent flexibility, high-speed number-handling capabilities,
reduced power consumption, and innovative architecture have made these cost-effective DSPs the ideal
solution for many telecommunications, computer, commercial, industrial, and military applications.
This data sheet provides detailed design documentation for the ′C1x DSPs. It facilitates the selection of devices
best suited for various user applications by providing specifications and special features for each ′C1x DSP.
This data sheet is arranged as follows: introduction, quick reference table of device parameters and packages,
summary overview of each device, architecture overview , and the ′C1x device instruction set summary . These
are followed by data sheets for each ′C1x device providing available package styles, terminal function tables,
block diagrams, and electrical and timing parameters. An index is provided to facilitate data sheet usage.
DEVICE
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
TMS320C1x
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
2
T able 1 provides an overview of ′C1x processors with comparisons of memory, I/O, cycle timing, military support,
and package types. For specific availability, contact the nearest TI Field Sales Office.
Table 1. TMS320C1x Device Overview
MEMORY I/O CYCLE PACKAGE (1)
RAM ROM EPROM PROG. SERIAL PARALLEL (ns) DIP PLCC CER-QUAD
TMS320C10 (2) 144 1.5K — 4K — 8 ×16 200 40 44 —
TMS320C10-14 144 1.5K — 4K — 8 ×16 280 40 44 —
TMS320C10-25 144 1.5K — 4K — 8 ×16 160 40 44 —
TMS320C14 (3) 256 4K — 4K 1 7 ×16 (4) 160 — 68 —
TMS320E14 (3) 256 — 4K 4K 1 7 ×16 (4) 160 — — 68 CER
TMS320P14†256 — 4K 4K 1 7 ×16 (4) 160 — 68 —
TMS320C15 (3) 256 4K — 4K — 8 ×16 200 40 44 —
TMS320C15-25 256 4K — 4K — 8 ×16 160 40 44 —
TMS320E15 (3) 256 — 4K 4K — 8 ×16 200 40 — 44 CER
TMS320E15-25 256 — 4K 4K — 8 ×16 160 40 — 44 CER
TMS320LC15 256 4K — 4K — 8 ×16 250 40 44 —
TMS320P15†256 — 4K 4K — 8 ×16 200 40 44 —
TMS320C16 256 8K — 64K — 8 ×16 114 — — 64 QFP
TMS320C17 256 4K — — 2 6 ×16 (5) 200 40 44 —
TMS320E17 (5) 256 — 4K — 2 6 ×16 (5) 200 40 —44 CER
TMS320LC17 (5) 256 4K — — 2 6 ×16 (5) 278 40 44 —
TMS320P17 (5)†256 — 4K — 2 6 ×16 (5) 200 40 44
†One-time programmable (OTP) device is in a windowless plastic package and cannot be erased.
NOTES: 1. DIP = dual in-line package. PLCC = plastic-leaded chip carrier. CER = ceramic-leaded chip carrier. QFP = plastic quad flat pack.
2. Military version available.
3. Military versions planned; contact nearest TI Field Sales Office for availability.
4. On-chip 16-bit I/O, four capture inputs, and six compare outputs are available.
5. On-chip 16-bit coprocessor interface is optional by pin selection.
SPRS009C–JANUARY 1987–REVISED JULY 1991
TMS320C1x
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 3
description
TMS320C10
The ′C10 provides the core CPU used in all other ′C1x devices. Its microprocessor operates at 5 MIPS. It
provides a parallel I/O of 8 × 16 bits. Three versions with cycle times of 160, 200, and 280 ns are available as
illustrated in Table 1. The ′C10 versions are offered in plastic 40-pin DIP or a 44-lead PLCC packages.
TMS320C14/E14/P14
The ′C14/E14/P14 devices, using the ′C10 core CPU, offer expanded on-chip RAM, and ROM or EPROM
(′E14/P14), 16 pins of bit selectable parallel I/O, an I/O mapped asynchronous serial port, four 16-bit timers, and
external/internal interrupts. The ′C14 devices can provide for microcomputer/microprocessor operating modes.
Three versions with cycle times of 160-ns are available as illustrated in Table 1. These devices are offered in
68-pin plastic PLCC or ceramic CER-QUAD packages.
TMS320C15/E15/P15
The ′C15/E15/P15 devices are a version of the ′C10, offering expanded on-chip RAM, and ROM or EPROM
(′E15/P15). The ′P15 is a one-time programmable (OTP), windowless EPROM version. These devices can
operate in the microcomputer or microprocessor modes. Five versions are available with cycle times of 160 to
200 ns (see Table 1). These devices are offered in 40-pin DIP, 44-pin PLCC, or 44-pin ceramic packages.
TMS320LC15
The ′LC15 is a low-power version of the ′C15, utilizing a VDD of only 3.3-V . This feature results in a 2.3: 1 power
requirement reduction over the typical 5-V ′C1x device. It operates at a cycle time of 250 ns. The device is offered
in 40-pin DIP or 44-lead PLCC packages.
TMS320C16
The ′C16 offers on-chip RAM of 256-words, an expanded program memory of 64K-words, and a fast instruction
cycle time of 114 ns (8.77 MIPS). It is offered in a 64-pin quad flat-pack package.
TMS320C17/E17/P17
The ′C17/E17/P17 versions consist of five major functional units: the ′C15 microcomputer, a system control
register , a full-duplex dual channel serial port, µ-law/A-law companding hardware, and a coprocessor port. The
dual-channel serial port is capable of full-duplex serial communication and offers direct interface to two
combo-codecs. The hardware companding logic can operate in either µ-law or A-law format with either
sign-magnitude or twos complement numbers in either serial or parallel modes. The coprocessor port allows
the ′C17/E17/P17 to act as a slave microcomputer or as a master to a peripheral microcomputer.
The ′P17 utilizes a one-time programmable (OTP) windowless EPROM version of the ′E17.
TMS320LC17
The ′LC17 is a low-power version of the ′C17, utilizing a VDD of only 3.3-V. This feature results in a
2.3: 1 power requirement reduction over the typical 5-V ′C1x device. It operates at a cycle time of 278 ns.
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
TMS320C1x
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
4
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A1/PA1
A0/PA0
MC/MP
RS
INT
CLKOUT
X1
X2/CLKIN
BIO
VSS
D8
D9
D10
D11
D12
D13
D14
D15
D7
D6
A2/PA2
A3
A4
A5
A6
A7
A8
MEN
DEN
WE
VCC
A9
A10
A11
D0
D1
D2
D3
D4
D5
TMS320C10/C15/LC15/P15
N/JD Packages
(Top View)
TMS320C10/C15/E15/LC15/P15
FN/FZ Packages
(Top View)
CLKOUT
X1
X2/CLKIN
BIO
NC
VSS
D8
D9
D10
D11
D12
A7
A8
MEN
DEN
WE
VCC
A9
A10
A11
D0
D1
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INT
RS
MC/MP
A0/PA0
A1/PA1
A2/PA2
A3
A4
A5
A6
D13
D14
D15
D7
D6
D5
D4
D3
D2
CC
V
CC
V
VCC
NC
NC
A0/PA0
A1/PA1
A2/PA2
A3
A4
A5
A6
VSS
A7
A8
A9
A10
A11
A12
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A13
A14
NC
NC
RS
X1
X2/CLKIN
VSS
VSS
VSS
VSS
CLKOUT
D15
D14
NC
D13
D12
D11
D10
D9
NC
NC 20212223242526272829303132
64636261605958575655545352
D8
D7
D6
D5
D4
D3
D2
NC
D1
D0
A15
NC
BIO
INT
MC/MP
V
V
V
MEN
NC
IOEN
MWE
IOWE
VDD
DD
DD
DD
VDD
VSS
TMS320C16
PG Package
(Top View)
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PA1/RBLE
PA0/HI/LO
MC
RS
EXINT
CLKOUT
X1
X2/CLKIN
BIO
VSS
D8/LD8
D9/LD9
D10/Ld10
D11/LD11
D12/LD12
D13/LD13
D14/LD14
D15/LD15
D7/LD7
D6/LD6
PA2/TBLF
FSR
FSX
FR
DX1
DX0
SCLK
DR1
DEN/RD
WE/WR
VCC
DR0
XF
MC/PM
D0/LD0
D1/LD1
D2/LD2
D3/LD3
D4/LD4
D5/LD5
TMS320C17/E17/LC17/P17
N/JD Packages
(Top View)
D4
D5
D6
D7
IOP0
IOP1
IOP2
IOP3
IOP4
IOP5
D8
A9
CMP0
CMP1
A10
A11
CMP2
AMP4/CAP2/FSR
D0
D1
D9
RXD/DATA
TXD/CLK
D10
IOP6
IOP7
10
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12
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25
2627 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
9876543216867666564636261
TCLK/CLKR
TCLK2/CLKX
A8
A7
A6
WE
REN
RS
INT
CLKOUT
A5
A4
NMI/MC/MP
WDT
CLKIN
A3
A2
60
59
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A0
IOP15
IOP14
IOP13
IOP12
D14
IOP11
IOP10
D13
D12
IOP9
IOP8
D11
A1
D15
D3
D2
TMS320C14/E14/P14
FN/FZ Packages
(Top View)
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EXINT
RS
MC
PAO/HI/LO
PA1/RBLE
PA2/TBLF
FSR
FSX
FR
DX1
D13/LD13
D14/LD14
D15/LD15
D7/LD7
D6/LD6
D5/LD5
D4/LD4
D3/LD3
D2/LD2
SS
V
D1/LD1
VSS
CLKOUT
X1
X2/CLKIN
BIO
NC
VSS
D8
D9
D10
D11
D12
DX0
SCLK
DR1
DEN/RD
WE/WR
VCC
DR0
XF
MC/PM
D0/LD0
VSS
TMS320C17/E17
FN/FZ Packages
(Top View)
VCC1
VSS1
VCC2
VSS2
CMP3
CAP0
CAP1
CMP5/CAP3/FSX
SPRS009C–JANUARY 1987–REVISED JULY 1991
TMS320C1x
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 5
architecture
The ′C1x DSPs use a modified Harvard architecture for speed and flexibility. In a strict Harvard architecture,
program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch and one-cycle
execution. The ′C1x DSPs modification allows transfers between program and data spaces, thereby increasing
the flexibility of the device. This modification permits coefficients stored in program memory to be read into the
RAM, eliminating the need for a separate coefficient ROM.
32-bit accumulator
All ′C1x devices contain a 32-bit ALU and accumulator for support of double-precision, twos-complement
arithmetic. The ALU is a general-purpose arithmetic unit that operates on 16-bit words taken from the data RAM
or derived from immediate instructions. In addition to the usual arithmetic instructions, the ALU can perform
Boolean operations, providing the bit manipulation ability required of a high-speed controller . The accumulator
stores the output from the ALU and is often an input to the ALU. It operates with a 32-bit word length. The
accumulator is divided into a high-order word (bits 31 through 16) and a low-order word (bits 15 through 0).
Instructions are provided for storing the high- and low-order accumulator words in memory.
shifters
Two shifters are available for manipulating data. The ALU barrel shifter performs a left-shift of 0 to 16 places
on data memory words loaded into the ALU. This shifter extends the high-order bit of the data word and zero-fills
the low-order bits for twos-complement arithmetic. The accumulator parallel shifter performs a left-shift of 0, 1
or 4 places on the entire accumulator and places the resulting high-order accumulator bits into data RAM. Both
shifters are useful for scaling and bit extraction.
16 × 16-bit parallel multiplier
The multiplier performs a 16 × 16-bit twos-complement multiplication with a 32-bit result in a single instruction
cycle. The multiplier consists of three units: the T Register, P Register, and a multiplier array. The 16-bit T
Register stores the multiplicand, and the P Register stores the 32-bit product. Multiplier values either come from
the data memory or are derived immediately from the MPYK (multiply immediate) instruction word. The fast
on-chip multiplier allows the device to perform fundamental operations such as convolution, correlation, and
filtering.
data and program memory
Since the ′C1x devices use a Harvard type architecture, data and program memory reside in two separate
spaces. These DSP devices have 144-or 256-words of on-chip data RAM and 1.5K- to 8K-words of on-chip
program ROM. On-chip program EPROM of 4K-words is provided in the ′E14/E15/E17 devices. An on-chip
one-time programmable 4K-word EPROM is provided in the ′P14/P15/P17 devices. The EPROM cell utilizes
standard PROM programmers and is programmed identically to a 64K CMOS EPROM (TMS27C64).
(Reference Table 1.)
program memory expansion
All ′C1x devices except the ′C17/E17/LC17/P17 devices are capable of executing from off-chip external memory
at full speed for those applications requiring external program memory space. This allows for external
RAM-based systems to provide multiple functionality. The ′C17/E17/LC17/P17 devices provide no external
memory expansion. (Reference Table 1.)
microcomputer/microprocessor operating modes
All devices except the ′x17 offer two modes of operation defined by the state of the MC/MP pin: the
microcomputer mode (MC/MP = 1) or the microprocessor mode (MC/MP = 0 ). In the microcomputer mode,
on-chip ROM is mapped into the program memory space. In the microprocessor mode, all words of progam
memory are external.
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
TMS320C1x
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
6
interrupts and subroutines
All devices except the ′C16 contain a four-level stack for saving the contents of the program counter during
interrupts and subroutine calls. Because of the larger 64K program space, the ′C16’s hardware stack has been
increased to eight levels. Instructions are available for saving the device’s complete context. PUSH and POP
instructions permit a level of nesting restricted only by the amount of available RAM. The interrupts used in these
devices are maskable.
input/output
The 16-bit parallel data bus can be utilized to perform I/O functions in two cycles. The I/O ports are addressed
by the three LSBs on the address lines. In addition, a polling input for bit test and jump operations (BIO) and
an interrupt pin (INT) have been incorporated for multitasking. The bit selectable I/O of the ′C14 is suitable for
microcontroller applications.
serial port (TMS320C17/E17)
Two of the I/O ports on the ′C17/E17 are dedicated to the serial port and companding hardware. I/O port 0 is
dedicated to control register 0, which controls the serial port, interrupts, and companding hardware. I/O port 1
accesses control register 1, as well as both serial port channels, and companding hardware. The six remaining
I/O ports are available for external parallel interfaces.
serial port (TMS320C14/E14)
The ′C14/E14 devices include one I/O-mapped serial port that operates asynchronously. I/O-mapped control
registers are used to configure port parameters such as inter-processor communication protocols and baud
rate.
companding hardware (TMS320C17/E17)
On-chip hardware enables the ′C17/E17 to compand (COMpress/exP AND) data in either µ-law or A-law format.
The companding logic operation is configured via the system control register. Data may be companded in either
serial mode for operation on serial port data (converting between linear and logarithmic PCM) or a parallel mode
for computation inside the device. The ′C17/E17 allows the hardware companding logic to operate with either
sign-magnitude or twos-complement numbers.
coprocessor port (TMS320C17/E17)
The coprocessor port on the ′C17/E17 provides a direct connection to most microcomputers and
microprocessors. The port is accessed through I/O port 5 using IN and OUT instructions. The coprocessor
interface allows the device to act as a peripheral (slave) microcomputer to a microprocessor , or as a master to
a peripheral microcomputer . In the microcomputer mode, the 16 data lines are used for the 6 parallel 16-bit I/O
ports. In the coprocessor mode, the 16-bit parallel port is reconfigured to operate as a 16-bit latched bus
interface. For peripheral transfer, an 8-bit or 16-bit length of the coprocessor port can be selected.
SPRS009C–JANUARY 1987–REVISED JULY 1991
TMS320C1x
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 7
instruction set
A comprehensive instruction set supports both numeric-intensive operations, such as signal processing, and
general-purpose operations, such as high-speed control. All of the ′C1x devices are object-code compatible and
use the same 60 instructions. The instruction set consists primarily of single-cycle single-word instructions,
permitting execution rates of more than six million instructions per second. Only infrequently used branch and
I/O instructions are multicycle. Instructions that shift data as part of an arithmetic operation execute in a single
cycle and are useful for scaling data in parallel with other operations.
NOTE
The BIO pin on other ′C1x devices is not available for use in the ′C14/E14/P14. An attempt to execute the
BIOZ (Branch on BIO low) instruction will result in a two cycle NOP action.
Three main addressing modes are available with the instruction set: direct, indirect, and immediate addressing.
direct addressing
In direct addressing, seven bits of the instruction word concatenated with the 1-bit data page pointer form the
data memory address. This implements a paging scheme in which the first page contains 128 words, and the
second page contains up to 128 words.
indirect addressing
Indirect addressing forms the data memory address from the least-significant eight bits of one of the two auxiliary
registers, AR0-AR1. The Auxiliary Register Pointer (ARP) selects the current auxiliary register. The auxiliary
registers can be automatically incremented or decremented and the ARP changed in parallel with the execution
of any indirect instruction to permit single-cycle manipulation of data tables. Indirect addressing can be used
with all instructions requiring data operands, except for the immediate operand instructions.
immediate addressing
Immediate instructions derive data from part of the instruction word rather than from the data RAM. Some useful
immediate instructions are multiply immediate (MPYK), load accumulator immediate (LACK), and load auxiliary
register immediate (LARK).
instruction set summary
T able 2 lists the symbols and abbreviations used in T able 3, the instruction set summary . T able 3 contains a short
description and the opcode for each ′C1x instruction. The summary is arranged according to function and
alphabetized within each functional group.
Table 2. Instruction Symbols
SYMBOL MEANING
ACC Accumulator
DData memory address field
MAddressing mode bit
KImmediate operand field
PA 3-bit port address field
R1-bit operand field specifying auxiliary register
S4-bit left-shift code
X3-bit accumulator left-shift field
D
D
K
D
D
D
D
D
D
D
D
D
D
D
K
D
D
D
S
S
X
S
NO.
CYCLES
NO.
CYCLES NO.
WORDS
NO.
WORDS
D
D
D
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
TMS320C1x
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
8
Table 3. TMS320C1x Instruction Set Summary
ACCUMULATOR INSTRUCTIONS
OPCODE
MNEMONIC DESCRIPTION INSTRUCTION REGISTER
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABS Absolute value of accumulator 1 1 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0
ADD Add to accumulator with shift 1 1 0 000 M
ADDH Add to high-order accumulator bits 1 1 0 1100000M
ADDS Add to accumulator with no sign extension 1 1 0 1100001M
AND AND with accumulator 1 1 0 1111001M
LAC Load accumulator with shift 1 1 0 010 M
LACK Load accumulator immediate 1 1 0 1111110
OR OR with accumulator 1 1 0 1111010M
SACH Store high-order accumulator bits with shift 1 1 0 1011 M
SACL Store low-order accumulator bits 1 1 0 1010000M
SUB Subtract from accumulator with shift 1 1 0 001 M
SUBC Conditional subtract (for divide) 1 1 0 1100100M
SUBH Subtract from high-order accumulator bits 1 1 0 1100010M
SUBS Subtract from accumulator with no sign extension 1 1 0 1100011M
XOR Exclusive OR with accumulator 1 1 0 1111000M
ZAC Zero accumulator 1 1 0 111111110001001
ZALH Zero accumulator and load high-order bits 1 1 0 1100101M
ZALS Zero accumulator and load low-order bits with no sign extension 1 1 0 1100110M
AUXILIARY REGISTER AND DATA PAGE POINTER INSTRUCTIONS
OPCODE
MNEMONIC DESCRIPTION INSTRUCTION REGISTER
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAR Load auxiliary register 1 1 0 0 1 1 1 0 0 R M
LARK Load auxiliary register immediate 1 1 0 111000R
LARP Load auxiliary register pointer immediate 1 1 0 11010001000000K
LDP Load data memory page pointer 1 1 0 1101111M
LDPK Load data memory page pointer immediate 1 1 0 11011100000000K
MAR Modify auxiliary register and pointer 1 1 0 1101000M
SAR Store auxiliary register 1 1 0 0 1 1 0 0 0 R M
BRANCH ADDRESS
D
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
BRANCH ADDRESS
D
D
D
K
B Branch unconditionally 2 2
BANZ Branch on auxiliary register not zero 2 2
BGEZ Branch if accumulator ≥ 022
BGZ Branch if accumulator > 0 2 2
BIOZ Branch on BIO = 0 †22
BLEZ Branch if accumulator ≤ 0 2 2
BLZ Branch if accumulator < 0 2 2
BNZ Branch if accumulator ≠ 022
BV Branch on overflow 2 2
BZ Branch if accumulator = 0 2 2
CALA Call subroutine from accumulator
CALL Call subroutine immediately 2 2
RET Return from subroutine or interrupt routine
NO.
CYCLES
NO.
CYCLES NO.
WORDS
NO.
WORDS
SPRS009C–JANUARY 1987–REVISED JULY 1991
TMS320C1x
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 9
Table 3. TMS320C1x Instruction Set Summary (continued)
BRANCH INSTRUCTIONS
OPCODE
MNEMONIC DESCRIPTION INSTRUCTION REGISTER
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0
0000
1111010000000000
0000
1111110100000000
0000
1111110000000000
0000
1111011000000000
0000
1111101100000000
0000
1111101000000000
0000
1111111000000000
0000
1111010100000000
0000
1111111100000000
0000
2 1 0 111111110001100
1111100000000000
0000
2 1 0 111111110001101
T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS
OPCODE
MNEMONIC DESCRIPTION INSTRUCTION REGISTER
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APAC Add P register to accumulator 1 1 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1
LT Load T Register 1 1 0 1101010M
LTA LTA combines LT and APAC into one instruction 1 1 0 1101100M
LTD LTD combines LT, APAC, and DMOV into one instruction 1 1 0 1101011M
MPY Multiply with T register, store product in P register 1 1 0 1101101M
MPYK Multiply T register with immediate operand; store product
in P register 1 1 1 00
PAC Load accumulator from P register 1 1 0 111111110001110
SPAC Subtract P register from accumulator 1 1 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0
†This instruction is a NOP on the ′320C14/E14/P14.
D
D
D
D
D
PA
DPA
D
NO.
CYCLES NO.
WORDS
NO.
CYCLES NO.
WORDS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
TMS320C1x
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
10
Table 3. TMS320C1x Instruction Set Summary (concluded)
CONTROL INSTRUCTIONS
OPCODE
MNEMONIC DESCRIPTION INSTRUCTION REGISTER
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DINT Disable interrupt 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1
EINT Enable interrupt 1 1 0 111111110000010
LST Load status register 1 1 0 1111011M
NOP No operation 1 1 0 111111110000000
POP POP stack to accumulator 2 1 0 111111110011101
PUSH PUSH stack from accumulator 2 1 0 111111110011100
ROVM Reset overflow mode 1 1 0 111111110001010
SOVM Set overflow mode 1 1 0 111111110001011
SST Store status register 1 1 0 1111100M
I/O AND DATA MEMORY OPERATIONS
OPCODE
MNEMONIC DESCRIPTION INSTRUCTION REGISTER
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMOV Copy contents of data memory location into next higher location 1 1 0 1 1 0 1 0 0 1 M
IN Input data from port 2 1 0 1000 M
OUT Output data to port 2 1 0 1001 M
TBLR Table read from program memory to data RAM 3 1 0 1100111M
TBLW Table write from data RAM to program memory 3 1 0 1 1 1 1 1 0 1 M
Data (16)
Address (12)
144-W ord RAM
1.5K-Word ROM
32-Bit ALU/ACC
Multiplier
Shifters
Interrupt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A1/PA1
A0/PA0
MC/MP
RS
INT
CLKOUT
X1
X2/CLKIN
BIO
VSS
D8
D9
D10
D11
D12
D13
D14
D15
D7
D6
A2/PA2
A3
A4
A5
A6
A7
A8
MEN
DEN
WE
VCC
A9
A10
A11
D0
D1
D2
D3
D4
D5
TMS320C10
N/JD Package
CLKOUT
X1
X2/CLKIN
BIO
NC
VSS
D8
D9
D10
D11
D12
A7
A8
MEN
DEN
WE
VCC
A9
A10
A11
D0
D1
123456
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
INT
RS
MC/MP
A0/PA0
A1/PA1
A2/PA2
A3
A4
A5
A6
D13
D14
D15
D7
D6
D5
D4
D3
D2
TMS320C10
FN/FZ Package
CC
VSS
V
CC
V
+5 V GND
(Top View)(Top View)
SPRS009C–JANUARY 1987–REVISED JULY 1991
TMS320C10, TMS320C10-14, TMS320C10-25
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 11
Key Features: TMS320C10
•Instruction Cycle Timing
— 160-ns (TMS320C10-25)
— 200-ns (TMS32010)
— 280-ns (TMS320C10-14)
•144 Words of On-Chip Data RAM
•1.5K Words On-Chip Program ROM
•External Memory Expansion up to 4K
Words at Full Speed
•16 × 16-Bit Multiplier With 32-Bit Product
•0 to 16-Bit Barrel Shifter
•On-Chip Clock Oscillator
•Device Packaging:
— 40-Pin DIP
— 44-Lead PLCC
•Single 5-V Supply
•Operating Free-Air Temperature Range
...0°C to 70°C
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
TMS320C10, TMS320C10-14, TMS320C10-25
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
12
TERMINAL FUNCTIONS
NAME I/O†DEFINITION
A11-A0/PA2-PA0
BIO
CLKOUT
D15-D0
DEN
INT
MC/MP
MEN
NC
RS
VCC
VSS
WE
X1
X2/CLKIN
O
I
O
I/O
O
I
I
O
O
I
I
I
O
O
I
External address bus. I/O port address multiplexed over PA2-PA0.
External polling input
System clock output, 1/4 crystal/CLKIN frequency
16-bit parallel data bus
Data enable for device input data on D15-D0
External interrupt input
Memory mode select pin. High selects microcomputer mode. Low selects microprocessor mode.
Memory enable indicates that D15-D0 will accept external memory instruction.
No connection
Reset for initializing the device
+ 5 V supply
Ground
Write enable for device output data on D15-D0
Crystal output for internal oscillator
Crystal input internal oscillator or external system clock input
†Input/Output/High-impedance state.
SPRS009C–JANUARY 1987–REVISED JULY 1991
TMS320C10, TMS320C10-14, TMS320C10-25
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 13
functional block diagram
312
D15-D0
32
16
16 16
32
Shifter (0,1,4)
32
ACC (32)
32
ALU (32)
Data RAM
(144 Words)
Address
Data
32
32
MUX
32
16
P(32)
T(16)
Multiplier
Shifter
(0–16)
16
8
DP
7
MUX
8
8
AR1 (16)
AR0 (16)
ARP
16 16
Data Bus
16
16
16
Program Bus
A11-A0/
PA2-PA0
12
Instruction
Program
ROM/EPROM
(1.5K Words)
3
RS
INT
MC/MP
BIO
MEN
DEN
WE
Stack
4 × 12
12
12
PC (12)
12
12 LSB
MUX
16
X2/CLKINCLKOUT X1
Controller
MUX
MUX
Address
Legend:
ACC = Accumulator
ALU = Arithmetic Logic Unit
ARP = Auxiliary Register Pointer
AR0 = Auxiliary Register 0
AR1 = Auxiliary Register 1
DP = Data Page Pointer
P = P Register
PC = Program Counter
T = T Register
Program Bus
Data Bus
VIH High-level input voltage
VIL Low-level input voltage
TAOperating free-air temperature
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
TMS320C10, TMS320C10-14, TMS320C10-25
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
14
electrical specifications
This section contains the electrical specifications for all speed versions of the ′C10 Digital Signal Processors,
including test parameter measurement information.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range VCC (see Note 6) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation 0.5 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature: L suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A suffix – 40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature –55 °C to 150 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only , and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 6: All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.25 V
VSS Supply voltage 0 V
CLKIN 3 V
All remaining inputs 2 V
MC/MP 0.6 V
All remaining inputs 0.8 V
IOH High-level output current, all outputs –300 µA
IOL Low-level output current 2 mA
L suffix 0 70 °C
A suffix – 40 85 °C
V
µA
µA
pF
pF
VOH High-level output voltage
IOZ Off-state output current
CiInput capacitance
IIInput current
Co Output capacitance
f = 1 MHz, all other pins 0 V
VCC = VSS to VCC
VCC = MAX
SPRS009C–JANUARY 1987–REVISED JULY 1991
TMS320C10, TMS320C10-14, TMS320C10-25
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 15
electrical characteristics over specified temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
IOH = MAX 2.4 3
IOH = 20 µA (see Note 7) VCC – 0.4‡
VOL Low-level output voltage IOL = MAX 0.3 0.5 V
VO = 2.4 V 20
VO = 0.4 V –20
All inputs except CLKIN ±20
CLKIN ±50
Data bus 25‡
All others 15‡
Data bus 25‡
All others 10‡
†All typical values are at VCC = 5 V, TA = 25°C.
‡Values derived from characterization data and not tested.
NOTE 7: This voltage specification is included for interface to HC logic. However , note that all of the other timing parameters defined in this data
sheet are specified for TTL logic levels and will differ for HC logic levels.
INTERNAL CLOCK OPTION
C1 C2
Crystal
X1 X2/CLKIN
Figure 1. Internal Clock Option
PARAMETER MEASUREMENT INFORMATION
2.15 V
From Output
Under Test
RL = 825 Ω
Test
Point
CL = 100 pF
Figure 2. Test Load Circuit
ICC‡Supply current mA
Crystal frequency, fxMHz
RL = 825 Ω,
CL = 100 pF
(see Figure 2)
PARAMETER UNITTEST CONDITIONS
UNIT
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
TMS320C10, TMS320C10-25
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
16
electrical characteristics over specified temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS
(SEE FIGURE 2) MIN TYP†MAX UNIT
TMS320C10 f = 20.5 MHz, VCC = 5.5 V, TA = – 40°C to 85°C 33 55
TMS320C10-25 f = 25.6 MHz, VCC = 5.5 V TA = – 0°C to 70°C 40 65
†All typical values are at TA = 70°C and are used for thermal resistance calculations.
‡ICC characteristics are inversely proportional to temperature. For ICC dependence on temperature, frequency, and loading.
CLOCK CHARACTERISTICS AND TIMING
The ′C10/C10-25 can use either its internal oscillator or an external frequency source for a clock.
internal clock option
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency
of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and
parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and should be
specified at a load capacitance of 20 pF.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
TMS320C10 TA = – 40°C to 85°C 6.7 20.5
TMS320C10-25 TA = 0°C to 70°C 6.7 25.6
C1, C2 TA = – 40°C to 85°C 10 pF
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the table below.
switching characteristics over recommended operating conditions
TMS320C10 TMS320C10-25
MIN NOM MAX MIN NOM MAX
tc(C) CLKOUT cycle time§195.12 200 156.25 160 ns
tr(C) CLKOUT rise time 1010ns
tf(C) CLKOUT fall time 88ns
tw(CL) Pulse duration, CLKOUT low 9272ns
tw(CH) Pulse duration, CLKOUT high 9070ns
td(MCC) Delay time, CLKIN↑ to CLKOUT↓256025 50ns
§tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used).
Values derived from characterization data and not tested.
timing requirements over recommended operating conditions
TMS320C10 TMS320C10-25
MIN NOM MAX MIN NOM MAX
tc(MC) Master clock cycle time 48.78 50 150 39.06 40 150ns
tr(MC) Rise time, master clock input 510510ns
tf(MC) Fall time, master clock input 510510ns
tw(MCP) Pulse duration, master clock 0.4tc(MC)0.6tc(MC)0.45tc(MC)0.55tc(MC)ns
tw(MCL) Pulse duration, master clock low 2015ns
tw(MCH) Pulse duration, master clock high 20 15ns
Values derived from characterization data and not tested.
PARAMETER TEST
CONDITIONS UNIT
RL = 825 Ω
CL = 100 pF,
(see Figure 2)
SPRS009C–JANUARY 1987–REVISED JULY 1991
TMS320C10, TMS320C10-25
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 17
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions
TMS320C10 TMS320C10-25
MIN TYP MAX MIN TYP MAX
td1 Delay time, CLKOUT↓ to
address bus valid 10†50 10†40 ns
td2 Delay time, CLKOUT↓
to MEN↓1/4tc(C) –5
†1/4tc(C) +15 1/4tc(C) –5
†1/4tc(C) + 12 ns
td3 Delay time, CLKOUT↓
to MEN↑–10†15 –10†12 ns
td4 Delay time, CLKOUT↓
to DEN↓1/4tc(C) –5
†1
/4tc(C) +15 1/4tc(C) –5
†1/4tc(C) + 12 ns
td5 Delay time, CLKOUT↓
to DEN↑–10†15 –10†12 ns
td6 Delay time, CLKOUT↓ to WE↓1/2tc(C) –5
†1/2tc(C) + 15 1/2tc(C) –5†1/2tc(C) + 12 ns
td7 Delay time, CLKOUT↓ to WE↑–10†15 –10†12 ns
td8 Delay time, CLKOUT↓ to data
bus OUT valid 1/4tc(C) + 65 1/4t c(C) + 52†ns
td9 T ime after CLKOUT↓ that data
bus starts to be driven 1/4tc(C) –5
†1/4tc(C) –5
†ns
td10 T ime after CLKOUT↓that data
bus stops being driven 1/4tc(C) + 40†1/4tc(C) + 40†ns
tvData bus OUT valid after
CLKOUT↓1/4tc(C)–10 1/4tc(C)–10 ns
th(A-WMD) Address hold time after WE↑,
MEN↑, or DEN↑ (see Note 8) –10†–10†ns
tsu(A-MD) Address bus setup time prior
to MEN↓ or DEN↓1/4tc(C)–45 1/4tc(C)–35 ns
†Values derived from characterization data and not tested.
NOTE 8: For interfacing I/O devices, see Figure 3.
TEST CONDITION
RL = 825 Ω,
CL = 100 pF
(see Figure 2)
UNIT
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
TMS320C10, TMS320C10-25
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
18
timing requirements over recommended operating conditions
TMS320C10 TMS320C10-25
MIN NOM MAX MIN NOM MAX
tsu(D) Setup time, data bus valid prior to CLKOUT↓50 40 ns
th(D) Hold time, data bus held valid after CLKOUT↓
(see Note 9) 0 0 ns
NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓.
SUGGESTED I/O DECODE CIRCUIT
The circuit shown in Figure 3 is a design example for interfacing I/O devices to the ′C10/C10-25. This circuit
decodes the address for output operations using the OUT instruction. The same circuit can be used to decode
input and output operations if the inverter (’ALS04) is replaced with a NAND gate and both DEN and WE are
connected. Inputs and outputs can be decoded at the same port provided the output of the decoder (’AS137)
is gated with the appropriate signal (DEN or WE) to select read or write (using an ’ALS32). Access times can
be increased when the circuit shown in Figure 3 is repeated to support IN instructions with DEN connected rather
than WE.
The table write (TBLW) function requires a different circuit. A detailed discussion of an example circuit for this
function is described in the application report, “Interfacing External Memory to the TMS32010”, published in the
book,
Digital Signal Processing Applications with the TMS320 Famil
y (SPRA012A).
TMS320C10 74AS137
GL
A
B
C
G1
G2
4
1
2
3
6
5
2
1
40
PA0
PA1
PA2
74ALS04
32 Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7I/O Device
VCC
WE
Figure 3. I/O Decode Circuit
UNIT
UNIT
PARAMETER
UNIT
RL 825 Ω,
CL = 100 pF,
(see Figure 2)
SPRS009C–JANUARY 1987–REVISED JULY 1991
TMS320C10, TMS320C10-25
DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 19
RESET (RS) TIMING
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td11 Delay time, DEN↑, WE↑, and MEN↑ from RS 1/2tc(C)+50† ns
tdis(R) Data bus disable time after RS 1/4tc(C)+50†ns
†Values derived from characterization data and not tested.
timing requirements over recommended operating conditions
TMS320C10 TMS320C10-25
MIN NOM MAX MIN NOM MAX
tsu(R) Reset (RS) setup time prior to CLKOUT (see Note 10) 50 40 ns
tw(R) RS pulse duration 5tc(C) 5tc(C) ns
NOTE 10: RS can occur anytime during a clock cycle. T ime given is minimum to ensure synchronous operation.
INTERRUPT (INT) TIMING
timing requirements over recommended operating conditions
TMS320C10 TMS320C10-25
MIN NOM MAX MIN NOM MAX
tf(INT) Fall time, INT 15 15 ns
tw(INT) Pulse duration, INT tc(C) tc(C) ns
tsu(INT) Setup time, INT↓ before CLKOUT↓50 40 ns
IO (BIO) TIMING
timing requirements over recommended operating conditions
TMS320C10 TMS320C10-25
MIN NOM MAX MIN NOM MAX
tf(IO) Fall time, BIO 15 15 ns
tw(IO) Pulse duration, BIO tc(C) tc(C) ns
tsu(IO) Setup time, BIO↓ before CLKOUT↓50 40 ns
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
TMS320C10-14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
20
electrical characteristics over specified temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
ICC‡ Supply current f = 14.4, MHz, VCC = 5.5 V, TA = 0°C to 70°C 28 65 mA
†All typical values are at TA = 70°C and are used for thermal resistance calculations.
‡ICC characteristics are inversely proportional to temperature; i.e., ICC decreases approximately linearly with temperature.
CLOCK CHARACTERISTICS AND TIMING
The TMS320C10-14 can use either its internal oscillator or an external frequency source for a clock.
internal clock option
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency
of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and
parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW , and be specified
at a load capacitance of 20 pF.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
Crystal frequency, fxTA = 0°C to 70°C 6.7 14.4 MHz
C1, C2 TA = 0°C to 70°C 10 pF
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the table below.
switching characteristics over recommended operating conditions
TEST CONDITIONS MIN NOM MAX UNIT
tc(C) CLKOUT cycle time§277.78 ns
tr(C) CLKOUT rise time 10 ns
tf(C) CLKOUT fall time 8 ns
tw(CL) Pulse duration, CLKOUT low 131 ns
tw(CH) Pulse duration, CLKOUT high 129 ns
td(MCC) Delay time, CLKIN↑ to CLKOUT↓2560ns
§tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used).
Values derived from characterization data and not tested.
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tc(MC) Master clock cycle time 69.5 150 ns
tr(MC) Rise time, master clock input 510ns
tf(MC) Fall time, master clock input 510ns
tw(MCP) Pulse duration, master clock 0.4tc(MC)0.6tc(MC)ns
tw(MCL) Pulse duration, master clock low, tc(MC) = 50 ns 20ns
tw(MCH) Pulse duration, master clock high, tc(MC) = 50 ns 20ns
Values derived from characterization data and not tested.
RL = 825 Ω,
CL = 100 pF
(see Figure 2)
RL = 825 Ω,
CL = 100 pF
(see Figure 2)
TMS320C10-14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 21
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
td1 Delay time, CLKOUT↓ to address bus valid 10†50 ns
td2 Delay time, CLKOUT↓ to MEN↓1/4tc(C) – 5†1/4tc(C)+15 ns
td3 Delay time, CLKOUT↓ to MEN↑–10†15 ns
td4 Delay time, CLKOUT↓ to DEN↓1/4tc(C) – 5†1
/4tc(C)+15 ns
td5 Delay time, CLKOUT↓ to DEN↑–10†15 ns
td6 Delay time, CLKOUT↓ to WE↓1/2tc(C) – 5†1/2tc(C)+15 ns
td7 Delay time, CLKOUT↓ to WE↑–10†15 ns
td8 Delay time, CLKOUT↓ to data bus OUT valid 1/4tc(C)+ 65 ns
td9 T ime after CLKOUT↓ that data bus starts to be driven 1/4tc(C) – 5†ns
td10 T ime after CLKOUT↓that data bus stops being driven 1/4tc(C)+ 40†ns
tvData bus OUT valid after CLKOUT↓1/4tc(C) – 10 ns
th(A-WMD) Address hold time after WE↑, MEN↑, or DEN↑
(see Note 8) –10†ns
tsu(A-MD) Address bus setup time prior to MEN↓ or DEN↓1/4tc(C) – 45 ns
†Values derived from characterization data and not tested.
NOTE 8: For interfacing I/O devices, see Figure 3.
timing requirements over recommended operating conditions
TEST CONDITIONS MIN NOM MAX UNIT
tsu(D) Setup time, data bus valid prior to CLKOUT↓50 ns
th(D) Hold time, data bus held valid after CLKOUT↓(see Note 9) 0 ns
NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓.
RL = 825 Ω,
CL = 100 pF
(see Figure 2)
TMS320C10-14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
22
RESET (RS) TIMING
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td11 Delay time, DEN↑, WE↑, and MEN↑ from RS 1/2tc(C)+ 50†ns
tdis(R) Data bus disable time after RS 1/4tc(C)+ 50†ns
†Values were derived from characterization data and not tested.
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tsu(R) Reset (RS) setup time prior to CLKOUT (see Note 10) 50 ns
tw(R) RS pulse duration 5tc(C) ns
NOTE 10: RS can occur anytime during a clock cycle. T ime given is minimum to ensure synchronous operation.
INTERRUPT (INT) TIMING
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tf(INT) Fall time, INT 15 ns
tw(INT) Pulse duration, INT tc(C) ns
tsu(INT) Setup time, INT↓ before CLKOUT↓50 ns
IO (BIO) TIMING
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tf(IO) Fall time, BIO 15 ns
tw(IO) Pulse duration, BIO tc(C) ns
tsu(IO) Setup time, BIO↓ before CLKOUT↓50 ns
TMS320C10, TMS320C10-14, TMS320C10-25
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 23
TIMING DIAGRAMS
Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2 volts, unless
otherwise noted.
clock timing
tr(MC)
tc(MC)
tw(MCH) tw(MCP)†
tf(MC)
tw(MCL)
td(MCC)†tw(CH)
tw(CL)
tr(C)
tc(C)
tf(C)
X2/CLKIN
CLKOUT
†td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform.
memory read timing
tc(C)
td3 td2
td1 th(A-WMD)
tsu(D) th(D)
Address Bus Valid
tsu(A-MD)
Instruction Valid
CLKOUT
MEN
A11-A0
D15-D0
TMS320C10, TMS320C10-14, TMS320C10-25
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
24
TBLR instruction timing
CLKOUT
MEN
A11-A0
D15-D0
12 3 4
5678
td2
td3 td3
tsu(D) th(D)
td1
9101112
Legend:
1. TBLR Instruction Prefetch 7. Address Bus Valid
2. Dummy Prefetch 8. Address Bus Valid
3. Data Fetch 9. Instruction Valid
4. Next Instruction Prefetch 10. Instruction Valid
5. Address Bus Valid 11. Data Input Valid
6. Address Bus Valid 12. Instruction Valid
TBLW instruction timing
MEN
A11-A0
WE
D15-D0
12 3
4567
891011
td6
td10
td8
td7
td9 tv
CLKOUT
Legend:
1. TBLW Instruction Prefetch 7. Address Bus Valid
2. Dummy Prefetch 8. Instruction Valid
3. Next Instruction Prefetch 9. Instruction Valid
4. Address Bus Valid 10. Data Output Valid
5. Address Bus Valid 11. Instruction Valid
6. Address Bus Valid
TMS320C10, TMS320C10-14, TMS320C10-25
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 25
IN instruction timing
CLKOUT
MEN
A11-A0
DEN
D15-D0
tsu(D)
th(D)
tsu(A-MD)
td5
td4
12
345
678
Legend:
1. IN Instruction Prefetch 5. Address Bus Valid
2. Next Instruction Prefetch 6. Instruction Valid
3. Address Bus Valid 7. Data Input Valid
4. Peripheral Address Valid 8. Instruction Valid
OUT instruction timing
CLKOUT
MEN
A11-A0
WE
D15-D0
12
34 5
678
td6 td7
tv
td9 td10
td8
Legend:
1. OUT Instruction Prefetch 5. Address Bus Valid
2. Next Instruction Prefetch 6. Instruction Valid
3. Address Bus Valid 7. Data Output Valid
4. Peripheral Address Valid 8. Instruction Valid
TMS320C10, TMS320C10-14, TMS320C10-25
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
26
reset timing
tsu(R) tsu(R)
tw(R)
tdis(R) td11
CLKOUT
RS
DEN
WE
MEN
D15-D0
MEN
Address
Bus
(see
Note E)
Data Shown Relative to WE
Data In From
PC ADDR 0 Data In From
PC ADDR PC+1
AB = Address Bus
AB = PC AB = PC+1 AB = PC = 0
AB = PC+1
Data
Out
NOTES: A. RS forces DEN, WE, and MEN high and places data bus D0 through D15 in a high-impedance state. AB outputs (and program count-
er) are synchronously cleared to zero after the next complete CLK cycle from RS↓.
B. RS must be maintained for a minimum of five clock cycles.
C. Resumption of normal program will commence after one complete CLK cycle from RS↑.
D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK
cycle.
E. Diagram shown is for definition purpose only. DEN, WE, and MEN are mutually exclusive.
F. During a write cycle, RS may produce an invalid write address.
interrupt timing
CLKOUT
tsu(INT)
tw(INT)
tf(INT)
INT
BIO timing
CLKOUT
BIO
tsu(IO)
tw(IO)
tf(IO)
TMS320C10, TMS320C10-14, TMS320C10-25
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 27
TYPICAL POWER VS. FREQUENCY GRAPHS
1.2 4 8 12 16 20 24 28
10
16
22
28
34
40
46
52
VCC = 5.5 V
VCC = 5.0 V
VCC = 4.5 V
fx - Crystal Frequency - MHz
(a) – 40°C to 85°C Temperature Range
1.2 4 8 12 16 20 24 28
0
6
12
18
24
30
36
42
fx - Crystal Frequency - MHz
(b) Voltage = 5 V ; Temperature = 25°C
Without Load
With Load
TA = – 40°C
TA = 85°C
TA = – 40°C
TA = 85°C
TA = – 40°C
TA = 85°C
ICC - Supply Current - mAICC - Supply Current - mA
Figure 4. Typical CMOS ICC vs Frequency
32-Bit ALU/ACC
Multiplier
Shifters
Interrupt Data (16)
Address (12)
+5 V GND
256-W ord RAM
8K-Word ROM/
EPROM
D4
D5
D6
D7
IOP0
IOP1
IOP2
IOP3
IOP4
IOP5
D8
A9
CMP0
CMP1
A10
A11
CMP2
AMP4/CAP2/FSR
D0
D1
D9
RXD/DATA
TXD/CLK
D10
IOP6
IOP7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
2627 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
9876543216867666564636261
TCLK/CLKR
TCLK2/CLKX
A8
A7
A6
WE
REN
RS
INT
CLKOUT
A5
A4
NMI/MC/MP
WDT
CLKIN
A3
A2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
A0
IOP15
IOP14
IOP13
IOP12
D14
IOP11
IOP10
D13
D12
IOP9
IOP8
D11
A1
D15
D3
D2
TMS320C14, TMS320E14/P14
FN/FZ Packages
(Top View)
VCC1
VSS1
VCC2
VSS2
CMP3
CAP0
CAP1
CMP5/CAP3/FSX
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
28
Key Features: TMS320C14/E14/P14
•160-ns Instruction Cycle
•256 Words of On-Chip Data RAM
•4K Words of On-Chip Program ROM
(TMS320C14)
•4K Words of On-Chip Program EPROM
(TMS320E14/P14)
•One-Time Programmable (OTP) W indowless
EPROM Version Available (′320P14)
•EPROM Code Protection for Copyright Security
•External Memory Expansion up to 4K-Words
at Full Speed (Microprocessor Mode)
•16 ×16-Bit Multipler With 32-Bit Product
•0 to 16-Bit Barrel Shifter
•Seven Input and Seven Output External Ports
•Bit Selectable I/O Port (16 Pins)
•16-Bit Bidirectional Data Bus With Greater than
50-Mbps Transfer Rate
•Asynchronous Serial Port
•15 Internal/External Interrupts
•Event Manager With Capture Inputs and
Compare Outputs
•Four Independent Timers [Watchdog,
General Purpose (2), Serial Port]
•Four-Level Hardware Stack
•Packaging: 68-Pin PLCC (FN Suffix)
or CLCC (FZ Suffix)
•Single 5-V Supply
•Operating Free-Air Temperature
...0°C to 70°C
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 29
introduction
The ′C14/E14/P14 are 16/32-bit single-chip digital signal processing (DSP) microcontrollers that combine the
high performance of a DSP with on-chip peripherals. With a 160-ns instruction cycle, these devices are capable
of executing up to 6.4 million instructions per second (MIPS). The ′C14/E14/P14 DSPs are ideal for applications
such as automotive control systems, computer peripherals, industrial controls, and military command/control
system applications.
Control-specific on-chip peripherals include: An event manager with 6 channel PWM D/A/, 6-bit I/O pins, an
asynchronous serial port, four 16-bit timers, and internal/external interrupts.
With 4K-words of on-chip ROM, the ′C14 is a mask programmable device. Code is provided by the customer,
and TI incorporates the customer’s code into the photomask. It is offered in a 68-pin plastic chip carrier package
(FN suffix), rated for operation from 0°C to 70°C.
The ′E14 is provided with a 4K-word on-chip EPROM. This EPROM version is excellent for prototyping and for
customized applications. It is programmable with standard EPROM programmers. It is offered in a 68-pin
(windowed) cerquad package (FZ suffix), rated for operation from 0°C to 70°C.
The ′P14 features a one-time programmable 4K-word on-chip EPROM. The ′P14 is provided in an
unprogrammed state and is programmed as if it were a blank ′E14. It is offered in a low-cost,
volume-production-oriented, 68-pin plastic leaded chip carrier (PLCC) package (FN suffix), rated for operation
from 0°C to 70°C.
I/O/Z†
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
30
Each device can execute programs form either internal (MC/MP=0) or external program memory (MC/MP=1).
For proprietary code security, the ′E14 and ′P14 incorporate an EPROM protect bit (RBIT). If this bit is
programmed, the device’s internal program memory cannot be accessed by any external means.
TERMINAL FUNCTIONS
PIN DESCRIPTION
NAME NO. ADDRESS/DATA BUSES
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2/PA2
A1/PA1
A0/PA0
5
6
9
12
13
14
20
21
25
26
27
28
O/Z Program memory address bus A1 1 (MSB) through A0 (LSB) and port addresses PA2 (MSB) through
PA0 (LSB). Addresses A11 through A0 are always active and never go to high impedance except
during reset. During execution of the IN and OUT instructions, pins 26, 27, and 28 carry the port
addresses. Pins A3 through A11 are held high when port accesses are made on pins PA0 through
PA2.
D15 MSB
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 LSB
35
36
39
40
43
46
49
50
57
58
59
60
61
62
63
64
I/O/Z Parallel data bus D15 (MSB) through D0 (LSB). The data bus is always in the high-impedance state
except when WE is active (low). The data bus is also active when internal peripherals are written to.
INTERRUPT AND MISCELLANEOUS SIGNALS
INT 18 IExternal interrupt input. The interrupt signal is generated by a high-to-low transition on this pin.
NMI/MC/MP 22 INon-maskable interrupt. When this pin is brought low, the device is interrupted irrespective of the
state of the INTM bit in status register ST.
Microcomputer/microprocessor select. This pin is also sampled when RS is low . If high during reset,
internal program memory is selected. If low during reset, external memory will be selected.
WE 15 OWrite enable. When active low, WE indicates that device will output data on the bus.
REN 16 ORead enable. When active low, REN indicates that device will accept data from the bus.
RS 17 IReset. When this pin is low, the device is reset and PC is set to zero.
Continued next page.
†Input/Output/High-impedance state.
I/O/Z†
TMS320C10-14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 31
TERMINAL FUNCTIONS (concluded)
PIN DESCRIPTION
NAME NO. SUPPLY/OSCILLATOR SIGNALS
CLKOUT 19 OSystem clock output (one fourth CLKIN frequency).
VCC 4,33 I 5-V supply pins.
VSS 3,34 I Ground pins.
CLKIN 24 IMaster clock input from external clock source.
SERIAL PORT AND TIMER SIGNALS
RXD 48 IAsynchronous mode receive input.
TXD 47 O/Z Asynchronous mode transmit output.
TCLK1 10 ITimer 1 clock. If external clock is selected, it serves as clock input to Timer 1.
TCLK2 11 ITimer 2 clock. If external clock is selected, it serves as clock input to Timer 2.
WDT 23 OW atchdog timer output. An active low is generated on this pin when the watchdog timer times out.
BIT I/O PINS
IOP15 MSB
IOP14
IOP13
IOP12
IOP11
IOP10
IOP9
IOP8
IOP7
IOP6
IOP5
IOP4
IOP3
IOP2
IOP1
IOP0 LSB
29
30
31
32
37
38
41
42
44
45
51
52
53
54
55
56
I/O 16 bit I/O lines that can be individually configured as inputs or outputs and also individually set or
reset
when configured as outputs.
COMPARE AND CAPTURE SIGNALS
CMP0
CMP1
CMP2
CMP3
8
7
2
1
OCompare outputs. The states of these pins are determined by the combination of compare and action
registers.
CAP0
CAP1 68
67 ICapture inputs. A transition on these pins causes the timer register to be captured in FIFO stack.
CMP4/CAP2 66 I/O This pin can be configured as compare output or capture input.
CMP5/CAP3 65 I/O This pin can be configured as compare output or capture input.
†Input/Output/High-impedance state.
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
32
functional block diagram
WE
REN
RS
IOP0-IOP15
RXD
TXD
CAP0,1
CMP4, 5 /
CAP2, 3
CMP0-CMP3
IOP
9
9
Serial
Port
Timer
Serial
Port
Controller
CAP
Detect
(4)
4
16 4 × 16
FIFO
Stack
(4)
16
6
16
16
ACT
(6)
CMPR
(6)
32
WDT
D15-D0
TCLK1.2
16
Watchdog Timer
12 12
32
16
16 16
32
Shifter (0,1,4)
32
ACC (32)
32
Data
(256 Words)
Address
Data
32
32
16
P(32)
T(16)
Multiplier
Shifter
(0–16)
16
8
DP
7
8
8
AR1 (16)
AR0 (16)
ARP
16 16
16
16
16
A0-A11
PA0-PA2
16
Instruction
Program
ROM/EPROM
(4K Words)
3
Stack
4 × 12
12
12
PC (12)
12
12 LSB
16
CLKOUTCLKIN
Program Bus
Controller
MUX
Timers
1.2
MUX
Address
MUX
MUX
MUX
ALU (32)
Legend: DP = Data Page Pointer
ACC= Accumulator IOP = Input/Output Port
ACT = Action Register (Bit Selectable)
ALU = Arithmetic Logic Unit PC = Program Counter
ARP = Auxiliary Register Point P = P Register
AR0 = Auxiliary Register 0 RBR = Receive Buffer Register
AR1 = Auxiliary Register 1 RSR = Receive Shift Register
BSR = Bank Select Register T = T Register
CAP = Capture TBR = Transmit Buffer Register
CMPR = Compare Register TSR = Transmit Shift Register
1
TBR
RBR TSR
RSR
16
16
Data Bus
16
BSR
16
Interrupt
Controller
NMI/
MC/MP
INT
Data Bus
16
architecture
The ′C1x family utilizes a modified Harvard architecture for speed and flexibility . In a strict Harvard architecture,
program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch and execution.
The ′C1x family’s modification of a Harvard architecture allows transfers between program and data spaces,
thereby increasing the flexibility of the device. This modification permits coefficients stored in program memory
to be read into the RAM, eliminating the need for a separate coefficient ROM. It also makes available immediate
instructions and subroutines based on computed values.
32-bit ALU/accumulator
The ′C14/E14/P14 devices contain a 32-bit ALU and accumulator for support of double-precision,
twos-complement arithmetic. The ALU is a general-purpose arithmetic unit that operates on 16-bit words taken
from the data RAM or derived from immediate instructions. In addition to the usual arithmetic instructions, the
ALU can perform Boolean operations, providing the bit manipulation ability required of a high-speed controller .
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 33
The accumulator stores the output from the ALU and is often an input to the ALU. It operates with a 32-bit
wordlength. The accumulator is divided into a high-order word (bits 31 through 16) and a low-order word (bits
15 through 0). Instructions are provided for storing the high- and low- order accumulator words in memory.
shifters
T wo shifters are available for manipulating data. The ALU barrel shifter performs a left-shift of 0 to16 places on
data memory words loaded into the ALU. This shifter extends the high-order bit of the data word and zero-fills
the low-order bits for twos-complement arithmetic. The accumulator parallel shifter performs a left-shift of 0, 1,
or 4 places on the entire accumulator and places the resulting high-order accumulator bits into data RAM. Both
shifters are useful for scaling and bit extraction
16 × 16-bit parallel multiplier
The multiplier performs a 16 × 16-bit twos-complement multiplication with a 32-bit result in a single instruction
cycle. The multiplier consists of three units: the T Register, P Register, and the multiplier array. The 16-bit T
Register temporarily stores the multiplicand; the P Register stores the 32-bit product. Multiplier values either
come from the data memory or are derived immediately from the MPYK (multiply immediate) instruction word.
The fast on-chip multiplier allows the device to perform fundamental operations such as convolution, correlation,
and filtering.
data and program memory
Since the ′C14/E14/P14 devices use a Harvard architecture, data and program memory reside in two separate
spaces. These devices have 256 words of on-chip data RAM and 4K words of on-chip program ROM (′C14)
or EPROM (′E14 and the OTP ′P14). The EPROM cell utilizes standard PROM programmers and is
programmed identically to a 64K-bit CMOS EPROM (TMS27C64).
program memory expansion
The ′C1x devices are capable of executing up to 4K words of external memory at full speed for those applications
requiring external program memory space. This allows for external RAM-based systems to provide multiple
functionality.
microcomputer/microprocessor operating modes
The ′C14/E14/P14 devices offer two modes of operation defined by the state of the NMI/MC/MP pin during reset:
the microcomputer mode (NMI/MC/MP is high) or the microprocessor mode (NMI/MC/MP is low). In the
microcomputer mode, the on-chip ROM is mapped into the program memory space. In the microprocessor
mode, all 4K words of memory are external.
interrupts and subroutines
The ′C14/E14/P14 devices contain a four-level hardware stack for saving the contents of the program counter
during interrupts and subroutine calls. Instructions are available for saving the complete context of the device.
PUSH and POP instructions permit a level of nesting restricted only by the amount of available RAM. The
′C14/E14/P14 have a total of 15 internal/external interrupts. Fourteen of these are maskable; NMI is the
fifteenth.
input/output
The 16-bit parallel data bus can be utilized to access external peripherals. However, only the lower three address
lines are active. The upper nine address lines are driven high.
bit I/O
The ′C14/E14/P14 has 16 pins of bit I/O that can be individually configured as inputs or outputs. Each of the
pins can be set or cleared without affecting the others. The input pins can also detect and match patterns and
generate a maskable interrupt signal to the CPU.
serial port
The ′C14/E14/P14 includes an I/O-mapped asynchronous serial port.
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
34
event manager
An event manager is included that provides up to four capture inputs and up to six compare outputs. This
peripheral operates with the timers to provide a form of programmable event logging/detection. The six compare
outputs can also be configured to produce six channels of high precision PWM.
timers 1 and 2
Two identical 16-bit timers are provided for general purpose applications. Both timers include a 16-bit period
register and buffer latch, and can generate a maskable interrupt.
serial port timer
The serial port timer is a 16-bit timer primarily intended for baud rate generation for the serial port. Its architecture
is the same as timers 1 and 2, therefore it can serve as a general purpose timer if not needed for serial
communication.
watchdog timer
The ′C14/E14/P14 contain a 16-bit watchdog timer that can produce a timeout (WDT) signal for various
applications such as software development and event monitoring. The watchdog timer also generates, at the
point of the timeout, a maskable interrupt signal to the CPU.
instruction set
A comprehensive instruction set supports both numeric-intensive operations, such as signal processing, and
general-purpose operations, such as high-speed control. All of the first-generation devices are object-code
compatible and use the same 60 instructions. The instruction set consists primarily of single-cycle single-word
instructions, permitting execution rates of more than six million instructions per second. Only infrequently used
branch and I/O instructions are multicycle. Instructions that shift data as part of an arithmetic operation execute
in a single cycle and are useful for scaling data in parallel with other operations.
NOTE
The BIO pin on other ′C1x devices is not available for use in the ′C14/E14/P14 devices. An attempt to
execute the BIOZ (Branch on BIO low) instruction will result in a two cycle NOP action.
Three main addressing modes are available with the instruction set: direct, indirect, and immediate addressing.
direct addressing
In direct addressing, seven bits of the instruction word concatenated with the 1-bit data page pointer from the
data memory address. This implements a paging scheme in which each page contains 128 words.
indirect addressing
Indirect addressing forms the data memory address from the least-significant eight bits of one of the two
auxiliary registers, AR0 and AR1. The Auxiliary Register Pointer (ARP) selects the current auxiliary register. The
auxiliary registers can be automatically incremented or decremented and the ARP changed in parallel with the
execution of any indirect instruction to permit single-cycle manipulation of data tables. Indirect addressing can
be used with all instructions requiring data operands, except for the immediate operand instructions.
immediate addressing
Immediate instructions derive data from part of the instruction word rather than from part of the data RAM. Some
useful immediate instructions are multiply immediate (MPYK), load accumulator immediate (LACK), and load
auxiliary register immediate (LARK).
VIH High-level input voltage V
VCC Supply voltage
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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electrical specifications
This section contains all the electrical specifications for the ′C14/E14/P14 devices, including test parameter
measurement information. Parameters with PP subscripts apply only to the ′E14 and ′P14 in the EPROM
programming mode.
absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 6) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, VPP (see Note 6) –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range –0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation 0.5 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Air temperature range above operating device: L version 0 °C to 70 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature –55 °C + 150 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only , and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 6: All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
Operating voltage 4.75 5 5.25 V
Fast programming 5.75 6 6.25 V
SNAP! Pulse programming 6.25 6.5 6.75 V
VPP Supply voltage for Fast programming (see Note 11) 12.25 12.5 12.75 V
VPP Supply voltage for SNAP! Pulse programming (see Note 11) 12.75 13 13.25 V
VSS Supply voltage 0 V
CLKIN, CAP0, CAP1, CMP4/CAP2, CMP5/CAP3, RS 3
All remaining inputs 2
VIL Low-level input voltage, all inputs 0.8 V
IOH High-level output current, all outputs –300 µA
IOL Low-level output current, all outputs 2 mA
TAOperating free-air temperature 0 70 °C
NOTE 11: VPP can be applied only to programming pins designed to accept VPP as an input. During programming the total supply current
is IPP + ICC.
VOH High-level output voltage
IOZ Off-state output voltage
IIInput current
VCC = MAX µA
VI = VSS to VCC µA
CIInput capacitance pF
COOutput
capacitance pF
f = 1 MHz, All other pins 0 V
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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36
electrical characteristics over specified temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
IOH = MAX 2.4 3 V
IOH = 20 µA (see Note 7) VCC – 0.4†V
VOL Low-level output voltage IOL = MAX 0.3 0.5 V
VO = 2.4 V 20
VO = 0.4 V –20
All other inputs except CLKIN ±20
CLKIN ±50
ICC§Supply current f = 25.6 MHz, VCC = 5.25 V, TA = 0°C to 70°C 70 90 mA
IPP1 VPP supply current VPP = VCC = 5.5 V 100 µA
IPP2 VPP supply current
(during program pulse) VPP = 13 V 30 50 mA
Data bus 25‡
All others 15‡
Data bus 25‡
All others 10‡
†All typical values are at VCC = 5 V, TA = 25°C, except ICC at 70°C.
‡Values derived from characterization data and not tested.
§ICC characteristics are inversely proportional to temperature.
NOTE 7: This voltage specification is included for interface to HC logic. However , note that all of the other timing parameters defined in this data
sheet are specified for TTL logic levels and will differ for HC logic levels.
PARAMETER MEASUREMENT INFORMATION
2.15 V
From Output
Under Test
RL = 825 Ω
Test
Point
CL = 100 pF
Figure 5. Test Load Circuit
EXTERNAL CLOCK REQUIREMENTS
The TMS320C14/E14/P14 use an external frequency source for a clock. This source is applied to the CLKIN
pin, and must conform to the specifications in the table below.
PARAMETERS TEST CONDITIONS MIN NOM MAX UNIT
CLKIN Input clock frequency TA = 0°C to 70°C 6.7 25.6 MHz
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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CLOCK TIMING
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tc(C) CLKOUT cycle time‡156.25 600 ns
tr(C) CLKOUT rise time 10†ns
tf(C) CLKOUT fall time 8†ns
tw(CL) Pulse duration, CLKOUT low 72†ns
tw(CH) Pulse duration, CLKOUT high 70†ns
td(MCC) Delay time CLKIN↑ to CLKOUT↓45†ns
†Values were derived from characterization data and not tested.
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tc(MC) Master clock cycle time‡39.06 40 150 ns
tr(MC) Rise time, master clock input 5†10†ns
tf(MC) Fall time, master clock input 5†10†ns
tw(MCP) Pulse duration, master clock 0.45 tc(MC)†0.55 tc(MC)†ns
tw(MCL) Pulse duration, master clock low 15†130 ns
tw(MCH) Pulse duration, master clock high 15†130 ns
†Values were derived from characterization data and not tested.
‡tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used).
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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38
MEMORY READ AND INSTRUCTION TIMING
switching characteristics over recommended operating conditions
PARAMETER TEST
CONDITIONS MIN NOM MAX UNIT
tsu(A)R Address bus valid before REN↓0.25 tc(C)–39 ns
tsu(A)W Address bus valid before WE↓0.50 tc(C)–45 ns
th(A) Address bus valid after REN↑ or WE↑5†ns
ten(D)W Data starts being driven before WE↓0.25 tc(C)†ns
tsu(D)W Data valid prior to WE↓0.25 tc(C)–45 ns
th(D)W Data valid after WE↑0.25 tc(C)–10 ns
tdis(D)W Data in high impedance after WE↑0.25 tc(C) + 25†ns
tw(WEL) WE-low duration 0.50 tc(C)–15 ns
tw(RENL) REN-low duration 0.75 tc(C)–15 ns
trec(WE) Write recovery time, time between WE↑ and REN↓0.25 tc(C)–5 ns
trec(REN) Read recovery time, time between REN↑ and WE↓0.50 tc(C)–10 ns
td(WE-CLK) T ime from WE↑ to CLKOUT↑0.50 tc(C)–15 ns
†Values were derived from characterization data and not tested.
timing requirements over recommended operating conditions
TEST CONDITIONS MIN NOM MAX UNIT
tsu(D)R Data set-up prior to REN↑52 ns
th(D)R Data hold after REN↑0 ns
ta(A) Access time for read cycle data
valid after valid address tc(C)–90 ns
toe(REN) Access time for read cycle from REN↓0.75 tc(C)–60 ns
tdis(D)R Data in high impedance after REN↑0.25 tc(C)†ns
RESET (RS) TIMING
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
td(RS-RW) Delay from RS↓ to REN↑ and WE↑0.75 tc(C) + 20†ns
tdis(RS-RW) Delay from RS↓ to REN and
WE into high impedance 1.25 tc(C)†ns
tdis(RS-DB) Data bus disable after RS↓1.25 tc(C)†ns
tdis(RS-AB) Address bus disable after RS↓tc(C)†ns
ten(RS-AB) Address bus enable after RS↑tc(C)†ns
timing requirements over recommended operating conditions
TEST CONDITIONS MIN NOM MAX UNIT
tsu(RS) RS setup prior to CLKOUT↓ (see Note 10) 60 ns
tw(RS) RS pulse duration 5tc(C) ns
NOTE 10: RS can occur anytime during the clock cycle. T ime given is minimum to ensure synchronous operation.
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
TMS320C14, TMS320E14, TMS320P14
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MICROCOMPUTER/MICROPROCESSOR MODE (NMI/MC/MP)
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
th(MC/MP)‡Hold time after RS high tc(C) ns
†Values were derived from characterization data and not tested.
‡Hold time to put device in microprocessor mode.
INTERRUPT (INT)/NONMASKABLE INTERRUPT (NMI)
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tf(INT) Fall time, INT 15†ns
tf(NMI) Fall time, NMI 15†ns
tw(INT) Pulse duration, INT tc(C) ns
tw(NMI) Pulse duration, NMI tc(C) ns
tsu(INT) Setup time, INT before CLKOUT low (see Note 12) 60 ns
tsu(NMI) Setup time, NMI before CLKOUT low (see Note 12) 60 ns
NOTE 12: INT and NMI are synchronous inputs and can occur at any time during the cycle. NMI and INT are edge triggered only.
BIT I/O TIMING
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
trfo(IOP) Rise and fall time outputs 20†ns
td(IOP) CLKOUT low to data valid outputs 0.75 tc(C)+80 ns
timing requirements over recommended operating conditions
TEST CONDITIONS MIN NOM MAX UNIT
trfl(IOP) Rise and fall time inputs 20†ns
tsu(IOP) Data setup time before CLKOUT time 40 ns
tw(IOP) Input pulse duration tc(C) ns
GENERAL PURPOSE TIMERS
timing requirements over recommended operating conditions
TEST CONDITIONS MIN NOM MAX UNIT
tr(TIM) TCLK1, TCLK2 rise time 20†ns
tf(TIM) TCLK1, TCLK2 fall time 20†ns
twl(TIM) TCLK1, TCLK2 low time tc(C)+20 ns
twh(TIM) TCLK1, TCLK2 high time tc(C)+20 ns
tclk(TIM) Input pulse duration 2 tc(C)+40 ns
†Values were derived from characterization data and not tested.
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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40
WATCHDOG TIMER TIMING
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tf(WDT) Fall time, WDT 20†ns
td(WDT) CLKOUT to WDT valid 0.25 tc(C)+20 ns
tw(WDT) WDT output pulse duration 7 tc(C) ns
EVENT MANAGER TIMER
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tf(CMP) Fall time, CMP0-CMP5 20†ns
tr(CMP) Rise time, CMP0-CMP5 20†ns
timing requirements over recommended operating conditions
TEST CONDITIONS MIN NOM MAX UNIT
tw(CAP) CAP0-CAP3 input pulse duration tc(C)+20 ns
tsu(CAP) Capture input setup time before CLKOUT low 20†ns
†Values were derived from characterization data and not tested.
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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TIMING DIAGRAMS
Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2 volts, unless
otherwise noted.
clock timing
tr(MC)
tc(MC)
tw(MCH) tw(MCP)†
tf(MC)
tw(MCL)
td(MCC)†tw(CH)
tw(CL)
tr(C)
tc(C)
tf(C)
X2/CLKIN
CLKOUT
†td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform.
memory read timing
th(A)
tsu(D)R th(D)R
Address Bus Valid
tsu(A)R
Instruction Input Valid
REN
A11-A0
D15-D0
tw(RENL)
toe(REN)
ta(A)
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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TBLR instruction timing
REN
A11-A0
D15-D0
12 3 4
5678
tsu(D)R
th(D)R
910 1112
tsu(A)R
ta(A)
Legend:
1. TBLR Instruction Prefetch 7. Address Bus V alid
2. Dummy Prefetch 8. Address Bus Valid
3. Data Fetch 9. Instruction Input Valid
4. Next Instruction Prefetch 10. Instruction Input Valid
5. Address Bus Valid 11. Data Input Valid
6. Address Bus Valid 12. Instruction Input Valid
TBLW instruction timing
REN
A11-A0
WE
D15-D0
12 3
4567
891011
ten(D)W†
th(D)W
tdis(D)W
tsu(D)W†
tw(WEL)
†Data valid prior to WE↓
Legend:
1. TBLW Instruction Prefetch 7. Address Bus Valid
2. Dummy Prefetch 8. Instruction Input V alid
3. Next Instruction Prefetch 9. Instruction Input Valid
4. Address Bus Valid 10. Data Output Valid
5. Address Bus Valid 11. Instruction Input Valid
6. Address Bus Valid
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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IN instruction timing
REN
A11-A0
D15-D0
tsu(D)R
th(D)R
tsu(A)R
12
456
789
ta(A)
3
Legend:
1. IN Instruction Prefetch 6. Address Bus Valid
2. Data Fetch 7. Instruction Input Valid
3. Next Instruction Prefetch 8. Data Input Valid
4. Address Bus Valid 9. Instruction Input Valid
5. Peripheral Address Valid
OUT instruction timing
REN
A11-A0
WE
D15-D0
1
45
67
tw(WEL)
3
tdis(D)W
ten(D)W
th(D)W
tsu(D)W
2
Legend:
1. OUT Instruction Prefetch 5. Address Bus Valid
2. Next Instruction Prefetch 6. Instruction Input Valid
3. Address Bus Valid 7. Data Output Valid
4. Peripheral Address Valid
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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44
reset timing
tsu(RS) tsu(RS)
tw(RS)
tdis(RS-DB)
td(RS-RW)
CLKOUT
RS
REN
WE
D15-D0
ADDRESS
BUS
(see
Note E)
Data Shown Relative To WE
Data In From
PC ADDR 0 Data In From
PC ADDR PC+1
AB = Address Bus
AB = PC AB = PC = 0
AB = PC+1
tdis(RS-RW)
tdis(RS-AB)
ten(RS-AB)
Data Out
NOTES: A. RS forces REN, and WE high and then places data bus D0-D15, REN, WE, and address bus A0-A11 in a high-impedance state.
AB outputs (and program counter) are synchronously cleared to zero after the next complete CLK cycle from RS↑.
B. RS must be maintained for a minimum of five clock cycles.
C. Resumption of normal program will commence after one complete CLK cycle from RS↑.
D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK
cycle.
E. Diagram shown is for definition purpose only. WE and REN are mutually exclusive.
microcomputer/microprocessor mode timing
CLKOUT
RS
th(MC/MP)
NMI/MC/MP
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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interrupt timing
tsu(INT), tsu(NMI)
NMI or INT
CLKOUT
tw(INT), tw(NMI)
tf(INT), tf(NMI)
bit I/O timing
tw(IOP)
trfI(IOP)
trfo(IOP)
tsu(IOP)
CLKOUT
IOP15-IOP0
(Output)
IOP15-IOP0
(Input)
general purpose timers
twl(TIM)
TCLK1, TCLK2
tf(TIM)
tr(TIM)
twh(TIM)
tclk(TIM)
watchdog timer
tf(WDT)
td(WDT)
WDT
CLKOUT
tw(WDT)
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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46
event manager
tw(CAP)
tsu(CAP)
tf(CMP) / tr(CMP)
CLKOUT
CAP3-CAP0
CMP5-CMP0
TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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PROGRAMMING THE TMS320E14/P14 EPROM CELL
The ′E14 and ′P14 include a 4K × 16-bit industry-standard EPROM cell for prototyping and low-volume
production. The ′C14 with a 4K-word masked ROM then provides a migration path for cost-effective production.
An EPROM adapter socket (part # TMDX3270110), shown in Figure 5, is available to provide 68-pin to 28-pin
conversion for programming the ′E14 and ′P14.
Key features of the EPROM cell include the normal programming operation as well as verification. The EPROM
cell also includes a code protection feature that allows code to be protected against copyright violations.
The ′E14/P14 EPROM cells are programmed using the same family and device codes as the TMS27C64 8K
× 8-bit EPROM. The TMS27C64 EPROM series are ultraviolet-light erasable, electrically programmable,
read-only memories, fabricated using HVCMOS technology. They are pin compatible with existing 28-pin ROMs
and EPROMs. These EPROMs operate from a 5-V supply in the read mode; however, a 12.5-V supply is needed
for programming. All programming signals are TTL level. For programming outside the system, existing EPROM
programmers can be used. Locations may be programmed singly, in blocks, or at random.
Figure 5. EPROM Adapter Socket
The ′E14/P14 devices use 13 address lines to address the 4K-word memory in byte format (8K-byte memory).
In word format, the most-significant byte of each word is assigned an even address and the least-significant byte
an odd address in the byte format. Programming information should be downloaded to EPROM programmer
memory in a high-byte to low-byte order for proper programming of the devices (see Figure 6).
TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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48
1234h
5678h
9ABCh
DEFOh
.
.
.
0(0000h)
1(000Ah)
2(0002h)
3(0003h)
.
.
.
4095(0FFh)
TMS320C14 On-Chip
Program Memory
(Word Format)
0(0000h)
1(0001h)
2(0002h)
3(0003h)
4(0004h)
5(0005h)
6(0006h)
7(0007h)
.
.
.
0(0000h)
1(0001h)
2(0002h)
3(0003h)
4(0004h)
5(0005h)
6(0006h)
7(0007h)
.
.
.
8191(1FFFh)
TMS320E14 and
TMS320P14 On-
Chip
Program Memory
(Byte Format)
EPROM
Programmer
Memory
Byte Format with
Adapter Socket
34h
12h
78h
56h
BCh
9Ah
FOh
DEh
.
.
.
12h
34h
56h
78h
9Ah
BCh
DEh
FOh
.
.
.
Figure 6. Programming Data Format
Figure 7 shows the wiring conversion to program the ′E14 and ′P14 using the 28-pin pinout of the TMS27C64.
The table of pin nomenclature provides a description of the TMS27C64 pins.
CAUTION
The ′E14 and ′P14 do not support the signature mode available with some EPROM programmers.
The signature mode places high voltage (12.5 Vdc) on pin A9. The ′E14 and ′P14 EPROM cells are
not designed for this feature and will be damaged if subjected to it. A 3.9 kΩ resistor is standard
on the TI programmer socket between pin A9 and programmer. This protects the device from
unintentional use of the signature mode.
3.9 k Ω
A0
A1
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
4342414039383736353433323130292827
6162636465666768123456789
CLKIN
G
E
VPP
EPT
PGM
A12
A11
A10
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Q4
Q5
Q6
Q7
Q8
E
A10
G
A11
A9
A8
EPT
PGM
VCC
GND
Q3
Q2
Q1
A0
A1
A2
A3
A4
A5
A6
A7
A12
VPP
TMS27C64 Pinout
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TMS320E14
TMS320P14
A9
A8
V
V
A7
A6
A5
A4
A3
A2
CC
SS
Q8
Q7
Q6
Q5
CC
SS
Q4
Q3
Q2
Q1
V
V
Figure 7. TMS320E14/P14 EPROM Programming Conversion to TMS27C64 EPROM Pinout
TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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TERMINAL FUNCTIONS (TMS320E14/P14)
NAME I/O DEFINITION
A12(MSB)-A0(LSB)
CLKIN
E
EPT
G
GND
PGM
Q8(MSB)-Q1(LSB)
RS
VCC
VPP
I
I
I
I
I
I
I
I/O
I
I
I
On-chip EPROM programming address lines
Clock oscillator input
EPROM chip enable
EPROM test mode select
EPROM output enable
Ground
EPROM write/program select
Data lines for byte-wide programming of on-chip 8K bytes of EPROM
Reset for initializing the device
5-V to 6.5-V power supply
12.5-V to 13-V power supply
T able 4 shows the programming levels required for programming, verifying, reading, and protecting the EPROM
cell.
Table 4. TMS320E14/P14 Programming Mode Levels
SIGNAL
NAME†TMS320E14/P14
PIN TMS27C64
PIN PROGRAM PROGRAM
VERIFY READ EPROM
PROTECT PROTECT
VERIFY
E 19 20 VIL VIL VIL VIH VIL
G 23 22 VIH PULSE PULSE VIH VIL
PGM 16 27 PULSE VIH VIH VIH VIH
VPP 18 1 VPP VPP VCC VPP VCCP
VCC 4,33 28 VCCP VCCP VCC VCCP VCCP
VSS 3,34 14 VSS VSS VSS VSS VSS
CLKIN 24 14 VSS VSS VSS VSS VSS
EPT 17 26 VSS VSS VSS VPP VPP
Q1-Q8 42, 41, 38, 37,
32-29 11–13, 15-19, Data In Data Out Data Out Q8 = PULSE Q8 = RBIT
A12-A7 15, 11, 10, 8, 7, 2 2, 23, 21, 24,
25, 3 ADDR ADDR ADDR X X
A6 1 4 ADDR ADDR ADDR X VIL
A5 68 5 ADDR ADDR ADDR X X
A4 67 6 ADDR ADDR ADDR VIH X
A3-A0 66, 65, 56, 55 7-10 ADDR ADDR ADDR X X
†Signal names shown for ′E14/P14 EPROM programming mode only.
Legend:
VIH = TTL high level; VIL = TTL low level; ADDR = byte address bit; VPP = 12.5 V ± 0.25 V (FAST) or 13 V ± 0.25 V (SNAP! Pulse).
VCC =5 V ± 0.25 V ; X = don’t care; PULSE = low-going TTL pulse.
DIN = byte to be programmed at ADDR; QOUT = byte stored at ADDR.; RBIT = ROM protect bit
VCCP =6 V ± 0.25 V (FAST) or 6.5 V ± 0.25 V (SNAP! Pulse).
programming
Since every memory in the cell is at a logic high, the programming operation reprograms selected bits to low.
Once the ′320E14 is programmed, these bits can only be erased using ultraviolet light. The correct byte is placed
on the data bus with VPP set to the 12.5-V level. The PGM pin is then pulsed low to program in the zeros.
tw(PGM) Initial program pulse duration
TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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50
erasure
Before programming, the ′E14 must be erased by exposing it to ultraviolet light. The recommended minimum
exposure dose (UV-intensity × exposure-time) is 15 W•s/cm2. A typical 12-mW•s/cm2, filterless UV lamp will
erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After
exposure, all bits are in the high state.
verify/read
T o verify correct programming, the EPROM cell can be read using either the verify or read line definitions shown
in Table 5, assuming the inhibit bit (RBIT) has not been programmed.
program inhibit
Programming may be inhibited by maintaining a high level input on the E pin or PGM pin.
standard programming procedure
Before programming, the ′E14 must first be completely erased. The device can then be programmed with the
correct code. It is advisable to program unused sections with zeros as a further security measure. After the
programming is complete, the code programmed into the cell should be verified. If the cell passes verification,
the next step is to program the ROM protect bit (RBIT). Once the RBIT programming is verified, an opaque label
should be placed over the window to protect the EPROM cell from inadvertent erasure by ambient light. At this
point, the programming is complete, and the device is ready to be placed into its destination circuit.
Refer to other appendices of the
TMS320C1x User’s Guide
for additional information on EPROM programming.
recommended timing requirements for programming: VCC = 6 V and VPP = 12.5 V (FAST) or
VCC = 6.5 V and VPP = 13 V (SNAP! PULSE), TA = 25°C (see Note 13)
MIN NOM MAX UNIT
Fast programming algorithm 0.95 1 1.05 ms
SNAP! Pulse programming algorithm 95 100 105 µs
tw(FPGM) Final pulse duration Fast programming only 2.85 78.75 ms
tsu(A) Address setup time 2µs
tsu(E) E setup time 2µs
tsu(G) G setup time 2µs
tsu(D) Data setup time 2µs
tsu(VPP) VPP setup time 2µs
tsu(VCC) VCC setup time 2µs
th(A) Address hold time 0µs
th(D) Data hold time 2µs
NOTE 13: For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V and VPP = 12.5 V ± 0.5 V during
programming.
TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
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program cycle timing
A12-A0
Q8-Q1
VPP
VCC
E
PGM
G
Program Verify
Address N+1 VIH
VIL
VIH/VOH
VIL/VOL
VPP
VCC
VCCP
VCC
VIH
VIL
VIH
VIL
VIH
VIL
HI-ZData In Stable
Address Stable
tsu(A)
Data Out
Valid
tdis(G)†
th(A)
tsu(D)
tsu(VPP)
tsu(VCC)
tsu(E)
tw(FPGM) tsu(G)
ten(G)†
th(D)
†tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer.
Data (16)
Address (12)
256-W ord RAM
4K-Word ROM/EPROM
32-Bit ALU/ACC
Multiplier
Shifters
Interrupt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A1/PA1
A0/PA0
MC/MP
RS
INT
CLKOUT
X1
X2/CLKIN
BIO
VSS
D8
D9
D10
D11
D12
D13
D14
D15
D7
D6
A2/PA2
A3
A4
A5
A6
A7
A8
MEN
DEN
WE
VCC
A9
A10
A11
D0
D1
D2
D3
D4
D5
TMS320C15/E15/LC15/P15
N/JD Package
(Top View)
CLKOUT
X1
X2/CLKIN
BIO
NC
VSS
D8
D9
D10
D11
D12
A7
A8
MEN
DEN
WE
VCC
A9
A10
A11
D0
D1
123456
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
INT
RS
MC/MP
A0/PA0
A1/PA1
A2/PA2
A3
A4
A5
A6
D13
D14
D15
D7
D6
D5
D4
D3
D2
TMS320C15/E15/LC15/P15
FN/FZ Package
(Top View)
CC
VSS
V
CC
V
+5 V
or
+3.3 V GND
TMS320C15, TMS320E15, TMS320LC15, TMS320P15
DIGITAL SIGNAL PROCESSORS
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52
Key Features: TM320C15/E15/LC15/P15
•Instruction Cycle Timing:
— 160-ns (TMS320C15-25/E15-25)
— 200-ns (TMS320C15/E15/P15)
— 250-ns (TMS320LC15)
•256 Words of On-Chip Data RAM
•4K Words of On-Chip Program ROM
(TMS320C15/C15-25/LC15)
•4K Words of On-Chip Program EPROM
(TMS320E15/E15-25)
•One-Time Programmable (OTP) W indowless
EPROM Version Available (TMS320P15)
•EPROM Code Protection for Copyright Security
•External Memory up to 4K-Words at Full Speed
•16 × 16-Bit Multiplier With 32-Bit Product
•0 to 16-Bit Barrel Shifter
•On-Chip Clock Oscillator
•3.3-V Low-Power Version Available (TMS320LC15)
•Device Packaging:
— 40-Pin Dip (All Devices)
— 44-Lead PLCC (TMS320C15/C15-25/LC15/P15)
— 44-Lead-QUAD (TMS320E15/E15-25)
TMS320C15, TMS320E15, TMS320LC15, TMS320P15
DIGITAL SIGNAL PROCESSORS
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functional block diagram
312
D15-D0
32
16
16 16
32
Shifter (0,1,4)
32
ACC (32)
32
ALU (32)
Data RAM
(256 Words)
Address
Data
32
32
MUX
32
16
P(32)
T(16)
Multiplier
Shifter
(0–16)
16
8
DP
7
MUX
8
8
AR1 (16)
AR0 (16)
ARP
16 16
Data Bus
16
16
16
Program Bus
A11-A0/
PA2-PA0
12
Instruction
Program
ROM/EPROM
(4K Words)
3
RS
INT
MC/MP
BIO
MEN
DEN
WE
Stack
4 × 12
12
12
PC (12)
12
12 LSB
MUX
16
X2/CLKINCLKOUT X1
Controller
MUX
MUX
Address
Legend:
ACC = Accumulator
ALU = Arithmetic Logic Unit
ARP = Auxiliary Register Pointer
AR0 = Auxiliary Register 0
AR1 = Auxiliary Register 1
DP = Data Page Pointer
P = P Register
PC = Program Counter
T = T Register
Program Bus
Data Bus
TMS320C15, TMS320E15, TMS320LC15, TMS320P15
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
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54
TERMINAL FUNCTIONS (TMS320C15/E15/LC15/P15)†
NAME I/O‡DEFINITION
A11-A0/PA2-PA0
BIO
CLKOUT
D15-D0
DEN
INT
MC/MP
MEN
NC
RS
VCC
VSS
WE
X1
X2/CLKIN
O
I
O
I/O
O
I
I
O
O
I
I
I
O
O
I
External address bus. I/O port address multiplexed over PA2-PA0.
External polling input
System clock output, 1/4 crystal/CLKIN frequency
16-bit parallel data bus
Data enable for device input data on D15-D0
External interrupt input
Memory mode select pin. High selects microcomputer mode. Low selects microprocessor mode.
Memory enable indicates that D15-D0 will accept external memory instruction.
No connection
Reset for initializing the device
+ 5 V supply
Ground
Write enable for device output data on D15-D0
Crystal output for internal oscillator
Crystal input internal oscillator or external system clock input
†See EPROM programming section.
‡Input/Output/High-impedance state.
VIH High-level input voltage
VIL Low-level input voltage
TAOperating free-air temperature
VCC Supply voltage
TMS320C15, TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
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electrical specifications
This section contains the electrical specifications for the ′C15/E15/P15 digital signal processors, including test
parameter measurement information. Parameters with PP subscripts apply only to the ′E15/P15 in the EPROM
programming mode (see Note 11).
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 6) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, VPP –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range –0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation 0.5 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature: L suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A suffix – 40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature –55 °C to 150 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only , and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 6: All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
EPROM devices 4.75 5 5.25 V
All other devices 4.5 5 5.5 V
VPP Supply voltage (see Note 11) 12.25 12.5 12.75 V
VSS Supply voltage 0 V
CLKIN 3 V
All remaining inputs 2 V
MC/MP 0.6 V
All remaining inputs 0.8 V
IOH High-level output current, all outputs – 300 µA
IOL Low-level output current (All outputs except for TMS320LC15) 2 mA
L suffix 0 70 °C
A suffix – 40 85 °C
NOTE 11: VPP can be applied only to programming pins designed to accept VPP as an input. During programming the total supply current is
IPP + ICC.
VOH High-level output voltage
VCC = MAX
VI = VSS to VCC
IOZ Off-state output current
IIInput current
ICC‡Supply current
CiInput capacitance
CoOutput capacitance f = 1 MHz, all other pins 0 VpF
pF
mA
µA
µA
Crystal frequency, fxMHz
TMS320C15, TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
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56
electrical characteristics over specified temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
IOH = MAX 2.4 3 V
IOH = 20 µA (see Note 8) VCC – 0.4 V
VOL Low-level output voltage IOL = MAX 0.3 0.5 V
VO = 2.4 V 20
VO = 0.4 V –20
All inputs except CLKIN ±20
CLKIN ±50
TMS320C15 f = 20.5 MHz, VCC = 5.5 V, TA = 0°C to 70°C 45 55
TMS320C15-25 f = 25.6 MHz, VCC = 5.5 V, TA = 0°C to 70°C 50 65
TMS320E15 f = 20.5 MHz, VCC = 5.25 V, TA = – 40°C to 85°C 55 75
TMS320E15-25 f = 25.6 MHz, VCC = 5.25 V, TA = 0°C to 70°C 65 85
Data bus 25‡
All other 15‡
Data bus 25‡
All others 10‡
†All typical values are at VCC = 5 V, TA = 70°C and are used for thermal resistance calculations.
‡ICC characteristics are inversely proportional to temperature. For ICC dependence on temperature, frequency, and loading, see Figure 3.
NOTE 7: This voltage specification is included for interface to HC logic. However , note that all of the other timing parameters defined in this data
sheet are specified for TTL logic levels and will differ for HC logic levels.
CLOCK CHARACTERISTICS AND TIMING
The TMS320C15/E15/P15 can use either its internal oscillator or an external frequency source for a clock.
internal clock option
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency
of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and
parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and should be
specified at a load capacitance of 20 pF.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
TMS320C15 TA = 0°C to 70°C 6.7 20.5
TMS320E15/P15 TA = – 40°C to 85°C 6.7 20.5
TMS320C15-25/E15-25 TA = 0°C to 70°C 6.7 25.6
C1, C2 TA = 0°C to 70°C 10 pF
UNIT
PARAMETER TEST CONDITIONS
RL = 825 Ω,
CL = 100 pF
(see Figure 2)
TMS320C15, TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
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POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 57
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the table below.
switching characteristics over recommended operating conditions
TMS320C15/E15/P15 TMS320C15-25/E15-25
MIN NOM MAX MIN NOM MAX
tc(C) CLKOUT cycle time‡195.12 200 156.25 160 ns
tr(C) CLKOUT rise time 10†10†ns
tf(C) CLKOUT fall time 8†8†ns
tw(CL) Pulse duration, CLKOUT low 92†72†ns
tw(CH) Pulse duration, CLKOUT high 90 †70†ns
td(MCC) Delay time, CLKIN↑ to CLKOUT↓25†60†25†50†ns
†Values derived from characterization data and not tested.
‡tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used).
UNIT
RL = 825 Ω,
CL = 100 pF
(see Figure 2)
TEST
CONDITIONS
PARAMETER UNIT
RL = 825 Ω,
CL = 100 pF
(see Figure 2)
UNIT
TEST
CONDITIONS
TMS320C15, TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
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58
timing requirements over recommended operating conditions
TMS320C15/E15/P15 TMS320C15-25/E15-25
MIN NOM MAX MIN NOM MAX
tc(MC) Master clock cycle time 48.78 50 150 39.06 40 150 ns
tr(MC) Rise time, master clock input 5†10†5†10†ns
tf(MC) Fall time, master clock input 5†10†5†10†ns
tw(MCP)†Pulse duration, master clock 0.4tc(MC) 0.6tc(MC)†0.45tc(MC) 0.55tc(MC)†ns
tw(MCL) Pulse duration, master clock low 20†15†ns
tw(MCH) Pulse duration, master clock high 20†15†ns
†Values derived from characterization data and not tested.
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions
TMS320C15/E15/P15 TMS320C15-25/E15-25
MIN NOM MAX MIN NOM MAX
td1 Delay time, CLKOUT↓ to
address bus valid 10†50 10‡40 ns
td2 Delay time, CLKOUT↓ to MEN↓1/4tc(C) – 5†1/4tc(C)+15 1/4tc(C) –5
†1/4tc(C)+12 ns
td3 Delay time, CLKOUT↓ to MEN↑–10†15 –10†12 ns
td4 Delay time, CLKOUT↓ to DEN↓1/4tc(C) –5
†1/4tc(C)+15 1/4tc(C) –5
†1/4tc(C)+12 ns
td5 Delay time, CLKOUT↓ to DEN↑–10†15 –10†12 ns
td6 Delay time, CLKOUT↓ to WE↓1/2tc(C) –5
†1/2tc(C)+15 1/2tc(C) –5
†1/2tc(C)+12 ns
td7 Delay time, CLKOUT↓ to WE↑–10†15 –10†12 ns
td8 Delay time, CLKOUT↓ to data bus
OUT valid 1/4tc(C)+65 1/4tc(C)+52 ns
td9 T ime after CLKOUT↓ that data bus
starts to be driven 1/4tc(C) –5
†1/4tc(C) –5
†ns
td10 T ime after CLKOUT↓that
data bus stops being driven
(TMS320C15/C15-25 only) 1/4tc(C) + 40†1/4tc(C) + 40†ns
td10 T ime after CLKOUT↓that
data bus stops being driven
(TMS320E15/E15-25 only) 1/4tc(C) + 70†1/4tc(C) +70†ns
tvData bus OUT valid after CLKOUT↓1/4tc(C) –10 1/4tc(C) –10 ns
th(A-WMD) Address hold time after WE↑, MEN↑,
or DEN↑ (see Note 15) 0†2†0†2†ns
tsu(A-MD) Address bus setup time prior to
DEN↓1/4tc(C)–45 1/4tc(C)–35 ns
†Values derived from characterization data and not tested.
NOTE 14: Address bus will be valid upon WE↑, MEN↑, or DEN↑.
timing requirements over recommended operating conditions
TMS320C15/E15/P15 TMS320C15-25/E15-25
MIN NOM MAX MIN NOM MAX
tsu(D) Setup time, data bus valid prior to CLKOU-
T↓50 40 ns
th(D) Hold time, data bus held valid after
CLKOUT↓(see Note 9) 0 0 ns
NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓.
RL = 825 Ω,
CL = 100 pF
(see Figure 2)
UNIT
UNIT
UNIT
TMS320C15, TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 59
RESET (RS) TIMING
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td11 Delay time, DEN↑, WE↑, and MEN↑ from RS 1/2tc(C)+ 50†ns
tdis(R) Data bus disable time after RS 1/4tc(C)+ 50†ns
†Values derived from characterization data and not tested.
timing requirements over recommended operating conditions
TMS320C15/E15/P15 TMS320C15-25/E15-25
MIN NOM MAX MIN NOM MAX
tsu(R) Reset (RS) setup time prior to CLKOUT (see Note 10) 50 40 ns
tw(R) RS pulse duration 5tc(C) 5tc(C) ns
NOTE 10: RS can occur anytime during a clock cycle. T ime given is minimum to ensure synchronous operation.
INTERRUPT (INT) TIMING
timing requirements over recommended operating conditions
TMS320C15/E15/P15 TMS320C15-25/E15-25
MIN NOM MAX MIN NOM MAX
tf(INT) Fall time, INT 15 15 ns
tw(INT) Pulse duration, INT tc(C) tc(C) ns
tsu(INT) Setup time, INT↓ before CLKOUT↓50 40 ns
IO (BIO) TIMING
timing requirements over recommended operating conditions
TMS320C15/E15/P15 TMS320C15-25/E15-25
MIN NOM MAX MIN NOM MAX
tf(IO) Fall time, BIO 15 15 ns
tw(IO) Pulse duration, BIO tc(C) tc(C) ns
tsu(IO) Setup time, BIO↓ before CLKOUT↓50 40 ns
TMS320C15, TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
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60
TIMING DIAGRAMS
Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless
otherwise noted.
clock timing
tr(MC)
tc(MC)
tw(MCH) tw(MCP)†
tf(MC)
tw(MCL)
td(MCC)†tw(CH)
tw(CL)
tr(C)
tc(C)
tf(C)
X2/CLKIN
CLKOUT
†td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform.
memory read timing
tc(C)
td3 td2
td1 th(A-WMD)
tsu(D) th(D)
Address Bus Valid
tsu(A-MD)
Instruction Valid
CLKOUT
MEN
A11-A0
D15-D0
TMS320C15, TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 61
TBLR instruction timing
CLKOUT
MEN
A11-A0
D15-D0
12 3 4
5678
td2
td3 td3
tsu(D) th(D)
td1
9101112
Legend:
1. TBLR Instruction Prefetch 7. Address Bus Valid
2. Dummy Prefetch 8. Address Bus Valid
3. Data Fetch 9. Instruction Valid
4. Next Instruction Prefetch 10. Instruction Valid
5. Address Bus Valid 11. Data Input Valid
6. Address Bus Valid 12. Instruction Valid
TBLW instruction timing
CLKOUT
MEN
A11-A0
WE
D15-D0
12 3
4567
891011
td6 td7
td8 tv
td9 td10
Legend:
1. TBLW Instruction Prefetch 7. Address Bus Valid
2. Dummy Prefetch 8. Instruction Valid
3. Next Instruction Prefetch 9. Instruction Valid
4. Address Bus Valid 10. Data Output Valid
5. Address Bus Valid 11. Instruction Valid
6. Address Bus Valid
TMS320C15, TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
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62
IN instruction timing
CLKOUT
MEN
A11-A0
DEN
D15-D0
tsu(D)
th(D)
tsu(A-MD)
td5
td4
12
345
678
Legend:
1. IN Instruction Prefetch 5. Address Bus Valid
2. Next Instruction Prefetch 6. Instruction Valid
3. Address Bus Valid 7. Data Input Valid
4. Peripheral Address Valid 8. Instruction Valid
OUT instruction timing
CLKOUT
MEN
A11-A0
WE
D15-D0
12
34 5
678
td6 td7
tv
td9 td10
td8
Legend:
1. IN Instruction Prefetch 5. Address Bus Valid
2. Next Instruction Prefetch 6. Instruction Valid
3. Address Bus Valid 7. Data Output Valid
4. Peripheral Address Valid 8. Instruction Input Valid
TMS320C15, TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 63
reset timing
tsu(R) tsu(R)
tw(R)
tdis(R) td11
CLKOUT
RS
DEN
WE
MEN
D15-D0
MEN
Address
Bus
see
Note E
Data Shown Relative to WE
Data In From
PC ADDR 0 Data In From
PC ADDR PC+1
AB = Address Bus
AB = PC AB = PC+1 AB = PC = 0
AB = PC+1
NOTES: A. RS forces DEN, WE, and MEN high and places data bus D0 through D15 in a high-impedance state. AB outputs (and program count-
er) are synchronously cleared to zero after the next complete CLK cycle from RS↓.
B. RS must be maintained for a minimum of five clock cycles.
C. Resumption of normal program will commence after one complete CLK cycle from RS↑.
D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK
cycle.
E. Diagram shown is for definition purpose only. DEN, WE, and MEN are mutually exclusive.
F. During a write cycle, RS may produce an invalid write address.
interrupt timing
CLKOUT
tsu(INT)
tw(INT)
tf(INT)
INT
BIO timing
CLKOUT
BIO
tsu(IO)
tw(IO)
tf(IO)
TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
64
absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage range, VPP (see Note 6) –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only , and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 6: All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
VPP Supply voltage (see Note 11) 12.25 12.5 12.75 V
NOTE 11: VPP can be applied only to programming pins designed to accept VPP as an input. During programming the total supply current is
IPP + ICC.
electrical characteristics over specified temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
IPP1 VPP supply current VPP = VCC 5.5 V 100 V
IPP2 VPP supply current (during program pulse) VPP = 12.75 V 30 50 V
‡All typical values except for ICC are at VCC = 5 V, TA = 25°C.
recommended timing requirements for programming, TA = 25°C, VCC = 6, VPP = 12.5 V,
(see Note 13)
MIN NOM MAX UNIT
tw(IPGM) Initial program pulse duration 0.95 1 1.05 ms
tw(FPGM) Final pulse duration 3.8 63 ms
tsu(A) Address setup time 2µs
tsu(E) E setup time 2µs
tsu(G) G setup time 2µs
tdis(G) Output disable time from G (see Note
15) 0 130§ns
ten(G) Output enable time from G 0 150§ns
tsu(D) Data setup time 2µs
tsu(VPP) VPP setup time 2µs
tsu(VCC) VCC setup time 2µs
th(A) Address hold time 0µs
th(D) Data hold time 2µs
§Values derived from characterization data and not tested.
NOTES: 13. For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V and VPP = 12.5 V ± 0.5 V during
programming.
15. Common test conditions apply for tdis(G) except during programming.
TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 65
PROGRAMMING THE TMS320E15/P15 EPROM CELL
′E15/P15 devices include a 4K × 16-bit industry-standard EPROM cell for prototyping, early field testing, and
low-volume production. In conjunction with this EPROM, the ′E15/P15 with a 4K-word masked ROM, then,
provide more migration paths for cost-effective production.
EPROM adapter sockets are available that provide pin-to-pin conversions for programming any ′E15/P15
devices. One adapter socket (part number RTC/PGM320C-06), shown in Figure 8, converts a 40-pin DIP device
into an equivalent 28-pin device. Another socket (part number RTC/PGM320A-06), not shown, permits 44- to
28-pin conversion.
Figure 8. EPROM Adapter Socket (40-pin to 28-pin DIP Conversion)
Key features of the EPROM cell include the normal programming operation as well as verification. The EPROM
cell also includes a code protection feature that allows code to be protected against copyright violations.
The ′E15/P15 EPROM cell is programmed using the same family and device pinout codes as the TMS27C64
8K × 8-bit EPROM. The TMS27C64 EPROM series are unltraviolet-light erasable, electrically programmable,
read-only memories, fabricated using HVCMOS technology. They are pin-compatible with existing 28-pin
ROMs and EPROMs. These EPROMs operate from a single 5-V supply in the read mode; however, a 12.5-V
supply is needed for programming. All programming signals are TTL level. For programming outside the system,
existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random.
Figure 9 shows the wiring conversion to program the ′E15/P15 using the 28-pin pinout of the TMS27C64.
Table 5 on pin nomenclature provides a description of the TMS27C64 pins. The code to be programmed into
the device should be in serial mode. The ′E15/P15 devices use 13 address lines to address 4K-word memory
in byte format.
TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
66
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q1
Q2
Q3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A1
A0(LSB)
VPP
RS
EPT
CLKIN
GND
Q1(LSB)
Q2
Q3
Q4
Q5
Q6
Q7
Q8(MSB)
40
39
38
37
36
35
34
33
32
30
29
28
27
26
25
24
23
22
21
31
A2
A3
A4
A5
A6
A7
A8
VCC
A9
A10
A11
(MSB)A12
E
G
PGM
TMS320E15/P15
TMS27C64
PINOUT TMS27C64
PINOUT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
PGM
EPT
A8
A9
A11
G
A10
E
Q8
Q7
Q6
Q5
Q4
3.9 kΩ
CAUTION
Although acceptable by some EPROM programmers, the signature mode cannot be used on any ′E1x
device. The signature mode will input a high-level voltage (12.5 Vdc) onto pin A9. Since this pin is not
designed for high voltage, the cell will be damaged. To prevent an accidental application of voltage,
Texas Instruments has inserted a 3.9 kΩ resistor between pin A9 of the TI programmer socket and the
programmer itself.
Pin Nomenclature (TMS320E15/P15)
NAME I/O DEFINITION
A0-A12 IOn-chip EPROM programming address lines
CLKIN IClock oscillator input
E I EPROM chip select
EPT IEPROM test mode select
G I EPROM read/verify select
GND I Ground
PGM I EPROM write/program select
Q1-Q8 I/O Data lines for byte-wide programming of on-chip 8K bytes of EPROM
RS IReset for initializing the device
VCC I5-V power supply
VPP I12.5-V power supply
Figure 9. TMS320E15/P15 EPROM Programming Conversion to TMS27C64 EPROM Pinout
TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 67
Table 5 shows the programming levels required for programming, verifying, reading, and protecting the EPROM cell.
Table 5. TMS320E15/P15 Programming Mode Levels
SIGNAL NAME TMS320E15 PIN TMS27C64 PIN PROGRAM VERIFY READ PROTECT VERIFY EPROM PROTECT
E 25 20 VIL VIL VIL VIL VIH
G 24 22 VIH PULSE PULSE VIL VIH
PGM 23 27 PULSE VIH VIH VIH VIH
VPP 3 1 VPP VPP VCC VCC + 1 VPP
VCC 30 28 VCC VCC VCC VCC + 1 VCC + 1
VSS 10 14 VSS VSS VSS VSS VSS
CLKIN 8 14 VSS VSS VSS VSS VSS
RS 4 14 VSS VSS VSS VSS VSS
EPT 5 26 VSS VSS VSS VPP VPP
Q1-Q8 11-18 11-13, 15-19 DIN QOUT QOUT Q8=RBIT Q8=PULSE
A0-A3 2, 1, 40, 39 10-7 ADDR ADDR ADDR X X
A4 38 6 ADDR ADDR ADDR X VIH
A5 37 5 ADDR ADDR ADDR X X
A6 36 4 ADDR ADDR ADDR VIL X
A7-A9 35, 34, 29 3, 25, 24 ADDR ADDR ADDR X X
A10-A12 28-26 21, 23, 2 ADDR ADDR ADDR X X
Legend:
VIH = TTL high level; VIL = TTL low level; ADDR = byte address bit
VPP = 12.5 V ± 0.25 V; VCC = 5 V ± 0.25 V; X = don’t care
PULSE = low-going TTL level pulse; DIN = byte to be programmed at ADDR
QOUT = byte stored at ADDR; RBIT = ROM protect bit.
programming
Since every memory bit in the cell is a logic 1, the programming operation reprograms certain bits to 0. Once
programmed, these bits can only be erased using ultraviolet light. The correct byte is placed on the data bus
with VPP set to the 12.5 V level. The PGM pin is then pulsed low to program in the zeros.
erasure
Before programming, the device must be erased by exposing it to ultraviolet light. The recommended minimum
exposure dose (UV-intensity × exposure-time) is 15 W•s/cm2. A typical 12-mW/cm2, filterless UV lamp will erase
the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After
exposure, all bits are in the high state.
verify/read
T o verify correct programming, the EPROM cell can be read using either the verify or read line definitions shown
in Table 5, assuming the inhibit bit has not been programmed.
program inhibit
Programming may be inhibited by maintaining a high level input on the E pin or PGM pin.
read The EPROM contents may be read independent of the programming cycle, provided the RBIT (ROM protect
bit) has not been programmed. The read is accomplished by setting E to zero and pulsing G low . The contents
of the EPROM location selected by the value on the address inputs appear on Q8-Q1.
TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
68
output disable
During the EPROM programming process, the EPROM data outputs may be disabled, if desired, by establishing
the output disable state. This state is selected by setting G and E pins high. While output disable is selected,
Q8-Q1are placed in the high-impedance state.
EPROM protection
To protect the proprietary algorithms existing in the code programmed on-chip, the ability to read or verify code
from external accesses can be completely disabled. Programming the RBIT disables external access of the
EPROM cell and disables the microprocessor mode, making it impossible to access the code resident in the
EPROM cell. The only way to remove this protection is to erase the entire EPROM cell, thus removing the
proprietary information. The signal requirements for programming this bit are shown in Table 5. The cell can be
determined as protected by verifying the programming of the RBIT shown in the table.
standard programming procedure
Before programming, the device must first be completely erased. Then the device can be programmed with the
correct code. It is advisable to program unused sections with zeroes as a further security measure. After the
programming is complete, the code programmed into the cell should be verified. If the cell passes verification,
the next step is to program the ROM protect bit (RBIT). Once the RBIT programming is verified, an opaque label
should be placed over the window to protect the EPROM cell from inadvertent erasure by ambient light. At this
point, the programming is complete, and the device is ready to be placed into its destination circuit.
program cycle timing
A12-A0
Q8-Q1
VPP
VCC
E
PGM
G
Program Verify
Address Stable Address N+1
Data In Stable Data Out
Valid
tsu(A) th(A)
tsu(D)
tsu(VPP)
tdis(G)
tsu(VCC)
tsu(E) th(D)
tw(IPGM)
tw(FPGM)
tsu(G) ten(G)
VIH
VIL
VIH/VOH
VIL/VOL
VPP
VCC
VCC+1
VCC
VIH
VIL
VIH
VIL
VIH
VIL
HI-Z
High-level input voltageVIH
Operating free-air temperatureTA
VOH High-level output voltage
IOZ Of f-state ouput current
II Input current
CiInput capacitance
CoOutput capacitance
f = 1 MHz, All other pins 0 V
µA
µA
pF
pF
TMS320LC15
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 69
absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 6) –0.3 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range –0.3 V to VCC + 0.5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range –0.3 V to VCC + 0.5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation 75 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Air temperature range above operating devices: L version 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A version –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –55°C to +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only , and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 6: All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 3.0 3.3 3.6 V
VSS Supply voltage 0 V
All inputs except CLKIN 2.0 V
CLKIN 2.5 V
VIL Low-level input voltage All inputs 0.55 V
IOH High-level output current (all outputs) –300 µA
IOL Low-level output current (all outputs) 1.5 mA
L version 070°C
A version –40 85 °C
electrical characteristics over specified temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
IOH = MAX 2.0 V
IOH = 20 µA (see Note 7) VCC – 0.4‡V
VOL Low-level output voltage IOL = MAX 0.5 V
VCC = MAX, V
O = VCC 20
VO = VSS –20
VI = VSS to VCC All inputs except CLKIN ±20
VI = VSS to VCC CLKIN ±50
Data bus 25‡
All others 15‡
Data bus 25‡
All others 10‡
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡Values derived from characterization data and not tested.
NOTE 7: This voltage specification is included for interface to HC logic. However , note that all of the other timing parameters defined in this data
sheet are specified for TTL logic levels and will differ for HC logic levels.
TMS320LC15
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
70
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A1/PA1
A0/PA0
MC/MP
RS
INT
CLKOUT
X1
X2/CLKIN
BIO
VSS
D8
D9
D10
D11
D12
D13
D14
D15
D7
D6
A2/PA2
A3
A4
A5
A6
A7
A8
MEN
DEN
WE
VCC
A9
A10
A11
D0
D1
D2
D3
D4
D5
N Package
(Top View)
CLKOUT
X1
X2/CLKIN
BIO
NC
VSS
D8
D9
D10
D11
D12
A7
A8
MEN
DEN
WE
VCC
A9
A10
A11
D0
D1
123456
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
INT
RS
MC/MP
A0/PA0
A1/PA1
A2/PA2
A3
A4
A5
A6
D13
D14
D15
D7
D6
D5
D4
D3
D2
FN Package
(Top View)
SS
VSS
V
SS
V
INTERNAL CLOCK OPTION
C1 C2
Crystal
X1 X2/CLKIN
′320LC15
PARAMETER MEASUREMENT INFORMATION
1.75 V
From Output
Under Test
RL = 825 Ω
Test
Point
CL = 100 pF
Figure 10. Test Load Circuit
TA = – 40°C to 85°C
TMS320LC15
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 71
CLOCK CHARACTERISTICS AND TIMING
The ′LC15 can use either its internal oscillator or an external frequency source for a clock.
internal clock option
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency
of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and
parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW , and be specified
at a load capacitance of 20 pF.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
Crystal frequency fx4.0 16 MHz
C1, C2 10 pF
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the table below.
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tc(C) CLKOUT cycle time†250 1000 ns
tr(C) CLKOUT rise time RL = 825 Ω, 10‡ns
tf(C) CLKOUT fall time CL = 100 pF, 8‡ns
tw(CL) Pulse duration, CLKOUT low (see Figure 2) 117‡ns
tw(CH) Pulse duration, CLKOUT high 115‡ns
td(MCC) Delay time, CLKIN↑ to CLKOUT↓20 70 ns
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tc(MC) Master clock cycle time 62.5 150 ns
tr(MC) Rise time, master clock input 5‡10†ns
tf(MC) Fall time, master clock input 5‡10†ns
tw(MCP) Pulse duration, master clock 0.4tc(MC)‡0.6tc(MC)‡ns
tw(MCL) Pulse duration, master clock low at tc(MC) min 26 ns
tw(MCH) Pulse duration, master clock high at tc(MC) min 26 ns
†tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used)
‡Values derived from characterization data and not tested.
TMS320LC15
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
72
electrical characteristics over specified temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
ICC‡f = 16.0 MHz, VCC = 3.6 V, TA = 0°C to 70°C 15 20 mA
†All typical values are at TA = 70°C and are used for thermal resistance calculations.
‡ICC characteristics are inversely proportional to temperature. For ICC dependence on frequency, see figure below .
typical power vs. frequency graph (outputs unloaded)§
20.0
15.0
10.0
5.0
0.0
(mA)ICC
CLKIN Frequency, MHz
–40°C to 85°C Temperature Range
2468
10 12 14
VCC = 3.5 V
VCC = 3 V
016
§Device operation is not guaranteed below 4 MHz CLKIN.
Graph is for device in RESET; i.e., only clock-out is driven.
RL = 825Ω,
CL = 100 pF,
(see Figure 2)
RL = 825Ω,
CL = 100 pF,
(see Figure 2)
TMS320LC15
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 73
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN MAX UNIT
td1 Delay time CLKOUT↓ to address bus valid 10†75 n
s
td2 Delay time CLKOUT↓ to MEN↓1/4 tc(C)–5†1/4 tc(C)+25 ns
td3
Delay time CLKOUT↓ to MEN↑–10†30 ns
td4
Delay time CLKOUT↓ to DEN↓1/4 tc(C)–5†1/4 tc(C)+25 ns
td5
Delay time CLKOUT↓ to DEN↑–10† 30 ns
td6 Delay time CLKOUT↓ to WE↓1/2 tc(C)–5†1/2 tc(C)+25 ns
td7 Delay time CLKOUT↓ to WE↑–10†30 ns
td8 Delay time CLKOUT↓ to data bus OUT valid 1/4 tc(C)+75 ns
td9 T ime after CLKOUT↓that data bus starts to be driven 1/4 tc(C)–5†ns
td10 T ime after CLKOUT↓that data bus stops being driven 1/4 tc(C)+60 ns
tvData bus OUT valid after CLKOUT↓1/4 tc(C)–10 ns
th(A-WMD) Address hold time after WE↑, MEN↑, or DEN↑ (see Note 14) 0†ns
tsu(A-MD) Address bus setup time to DEN↓– 4†ns
†Values derived from characterization data and not tested.
NOTE 14: Address bus will be valid upon WE↑, MEN↑, or DEN↑.
timing requirements over recommended operating conditions
TEST CONDITIONS MIN NOM MAX UNIT
tsu(D) Setup time data bus valid prior to CLKOUT↓56 ns
th(D) Hold time, data bus held valid after CLKOUT↓ (see Note 9) 0 ns
NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓.
RL = 825Ω,
CL = 100 pF,
(see Figure 2)
TMS320LC15
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
74
RESET (RS) TIMING
switching characteristics over recommended operating conditions
TEST CONDITIONS MIN NOM MAX UNIT
td11 Delay time, DEN↑, WE↑, and MEN↑ from RS 1/2tc(C)+75 ns
tdis(R) Data bus disable time after RS 1/4t c(C)+75 ns
†These parameters do not apply to this device.
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tsu(R) Reset (RS) setup time prior to CLKOUT (see Note 10) 85 ns
tw(R) RS pulse duration 5tc(C) ns
NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.
INTERRUPT (INT) TIMING
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tF(INT) Fall time, INT 15 ns
tw(INT) Pulse duration, INT tc(C) ns
tsu(INT) Setup time, INT↓ before CLKOUT↓85 ns
I/O (BIO) TIMING
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tf(IO) Fall time BIO 15 ns
tw(IO) Pulse duration BIO tc(C) ns
tsu(IO) Setup time BIO↓ before CLKOUT↓85 ns
TMS320LC15
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 75
clock timing
tr(MC)
tc(MC)
tw(MCH) tw(MCP)†
tf(MC)
tw(MCL)
td(MCC)†tw(CH)
tw(CL)
tr(C)
tc(C)
tf(C)
X2/CLKIN
CLKOUT
†td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform.
IN instruction timing
CLKOUT
MEN
PA2-PA0
DEN
D15-D0
tsu(D)
th(D)
tsu(A-MD)
td5
td4
12
345
678
Legend:
1. IN Instruction Prefetch 5. Address Bus Valid
2. Next Instruction Prefetch 6. Instruction Valid
3. Address Bus Valid 7. Data Input Valid
4. Peripheral Address Valid 8. Instruction Valid
TMS320LC15
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
76
OUT instruction timing
CLKOUT
MEN
PA2-PA0
WE
D15-D0
12
34 5
678
td6 td7
td8 tv
td9 td10
Legend:
1. OUT Instruction Prefetch 5. Address Bus Valid
2. Next Instruction Prefetch 6. Instruction Valid
3. Address Bus Valid 7. Data Output Valid
4. Peripheral Address Valid 8. Instruction Valid
external memory read timing
tc(C)
td3 td2
td1 th(A-WMD)
tsu(D) th(D)
Address Bus Valid
tsu(A-MD)
Instruction Valid
CLKOUT
MEN
A11-A0
D15-D0
TMS320LC15
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 77
TBLR instruction timing
CLKOUT
MEN
A11-A0
D15-D0
12 3 4
5678
td2
td3 td3
tsu(D) th(D)
td1
9101112
Legend:
1. TBLR Instruction Prefetch 7. Address Bus V alid
2. Dummy Prefetch 8. Address Bus Valid
3. Data Fetch 9. Instruction Valid
4. Next Instruction Prefetch 10. Instruction V alid
5. Address Bus Valid 11. Data Input Valid
6. Address Bus Valid 12. Instruction Valid
TBLW instruction timing
CLKOUT
MEN
A11-A0
WE
D15-D0
12 3
4567
891011
td6 td7
td8 tv
td10
td9
Legend:
1. TBLW Instruction Prefetch 7. Address Bus Valid
2. Dummy Prefetch 8. Instruction V alid
3. Next Instruction Prefetch 9. Instruction Valid
4. Address Bus Valid 10. Data Output Valid
5. Address Bus Valid 11. Instruction Valid
6. Address Bus Valid
TMS320LC15
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
78
reset timing
tsu(R) tsu(R)
tw(R)
tdis(R) td11
CLKOUT
RS
DEN
WE
MEN
D15-D0
MEN
ADDRESS
BUS
(see
Note E)
Data Shown Relative To WE
Data In From
PC ADDR 0 Data In From
PC ADDR PC+1
AB = Address Bus
AB = PC AB = PC+1 AB = PC = 0
AB = PC+1
NOTES: A. RS forces DEN, WE, and MEN high and places data bus D0 through D15 in a high-impedance state. AB outputs (and program count-
er) are synchronously cleared to zero after the next complete CLK cycle from RS↓.
B. RS must be maintained for a minimum of five clock cycles.
C. Resumption of normal program will commence after one complete CLK cycle from RS↑.
D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK
cycle.
E. Diagram shown is for definition purpose only. DEN, WE, and MEN are mutually exclusive.
F. During a write cycle, RS may produce an invalid write address.
interrupt timing
CLKOUT
tsu(INT)
tw(INT)
tf(INT)
INT
BIO timing
CLKOUT
BIO
tsu(IO)
tw(IO)
tf(IO)
Data (16)
Address (12)
256-W ord RAM
8K-Word ROM
32-Bit ALU/ACC
Multiplier
Shifters
Interrupt
+5 V GND
8-Level Stack
NC
NC
A0/PA0
A1/PA1
A2/PA2
A3
A4
A5
A6
VSS
A7
A8
A9
A10
A11
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A13
A14
NC
NC
RS
X1
X2/CLKIN
VSS
VSS
VSS
VSS
CLKOUT
D15
D14
NC
D13
D12
D11
D10
D9
NC
NC 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52
D8
D7
D6
D5
D4
D3
D2
NC
D1
D0
A15
NC
BIO
INT
MC/MP
V
V
V
MEN
NC
IOEN
MWE
IOWE
VDD
DD
DD
DD
VDD
VSS
PG Package
(Top View)
TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 79
Key Features: TMS320C16
•114-ns Instruction Cycle Time
•256 Words of On-Chip Data RAM
•8K Words of On-Chip Program ROM
•64K Words Total External Memory at
Full Speed
•8 Level Stack
•32-Bit ALU/Accumulator
•16 × 16-Bit Multiplier With 32-Bit Product
•16-Bit Barrel Shifter
•Eight Input and Eight Output Channels
•Simple Memory and I/O Interface:
— Memory Write Enable Signal MWE
— I/O Write Enable Signal IOWE
•Single 5-V Supply
•64-Pin Quad Flatpack (PG Suffix)
•Operating Free-Air Temperature Range
...0°C to 70°C
I/O/Z†
TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
80
TERMINAL FUNCTIONS
PIN DESCRIPTION
NAME NO. ADDRESS/DATA BUSES
A15 MSB
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2/PA2
A1/PA1
A0/PA0
32
34
35
36
37
38
39
40
41
43
44
45
46
47
48
49
I/O/Z Program memory address bus A15 (MSB) through A0 (LSB) and port addresses P A2 (MSB) through
PA0 (LSB). Addresses A15 through A0 are always active and never go to high impedance. During
execution of the IN and OUT instructions, pins A2 through A0 carry the port addresses. (Address pins
A15 through A3 are always driven low on IN and OUT instruction.
D15 MSB
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 LSB
10
11
13
14
15
16
17
20
21
22
23
25
27
28
30
31
I/O/Z Parallel data bus D15 (MSB) through D0 (LSB). The data bus is always in the high-impedance state
except when IOWE or MWE are active (low).
†Input/Output/High-impedance state.
I/O/Z†DESCRIPTION
I/O/Z†
TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 81
TERMINAL FUNCTIONS (concluded)
PIN DESCRIPTION
NAME NO. INTERRUPT AND MISCELLANEOUS SIGNALS
BIO 64 IExternal polling input. Polled by BIOZ instruction. If low , the device branches to the address
specified by the instruction.
IOEN 54 OData enable for device input data. When active (low), IOEN indicates that the device will
accept data from the data bus. IOEN is active only during the IN instruction. When IOEN is
active, MEN, IOWE, and MWE will always be inactive (high).
IOWE 52 OWrite enable for device output data. When active (low), IOWE indicates that data will be
output from the device on the data bus. IOWE is active only during the OUT instruction. When
IOWE is active, MEN, IOEN, and MWE will always be inactive (high).
INT 63 IExternal interrupt input. The interrupt signal is generated by applying a negative-going edge
to the INT pin. The edge is used to latch the interrupt flag register (INTF) until an interrupt
is granted by the device. An active low level will also be sensed.
MC/MP 62 IMemory mode select pin. High selects the microcomputer mode, in which 8K words of
on-chip program memory are available. A low on MC/MP pin enables the microprocessor
mode. In this mode, the entire memory space is external; i.e., addresses 0 through 65535.
MEN 56 O
Memory enable. MEN is an active (low) control signal generated by the device to enable
instruction fetches from program memory. MEN will be active on instructions fetched from
both internal and external memory. When MEN is active, MWE, IOWE, and IOEN will be
inactive (high).
MWE 53 OWrite enable for device output data. When active (low), MWE indicates that data will be
output from the device on the data bus. MWE is active only during the TBLW instruction.
When MWE is active, MEN, IOEN, and IOWE will always be inactive (high).
NC 1, 12, 18, 19,
24, 29, 33,
50, 51, 55 —No connection.
RS 2 I
Schmitt-triggered input for initializing the device. When held active for a minimum of five
clock cycles. IOEN, IOWE, MWE, and MEN are forced high; and, the data bus (D15 through
D0) is not driven. The program counter (PC) and the address bus (A15 through A0) are then
synchronously cleared after the next complete clock cycle from the falling edge of RS. Reset
also disables the interrupt, clears the interrupt flag register, and leaves the overflow mode
register unchanged. The device can be held in the reset state indefinitely.
SUPPLY/OSCILLATOR SIGNALS
PIN
NAME NO.
CLKOUT 9 O System clock output (one-fourth crystal/CLKIN frequency).
VDD 26, 57, 58,
59, 60 I5-V suppy pins.
VSS 5, 6, 7, 8,
42, 61 IGround pins.
X1 3 O Crystal output pin for internal oscillator. If the internal oscillator is not used, this pin should
be left unconnected.
X2/CLKIN 4 I Input pin to the internal oscillator (X2) from the crystal. Alternatively, an input pin for an
external oscillator (CLKIN).
†Input/Output/High-impedance state.
TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
82
functional block diagram
16
D15-D0
32
1616 16
32
Shifter (0,1,4)
32
ACC (32)
32
ALU (32)
Data RAM
(256 Words)
Address
DATA
32
32
MUX
32
16
P(32)
T(16)
Multiplier
Shifter
(0–16)
16
8
DP
7
MUX
8
8
AR1 (16)
AR0 (16)
ARP
16 16
Data Bus
Data Bus
16
16
16
Program Bus
A15-A0/
PA2-PA0
16
Instruction
Program
ROM
(8K Words)
3
INT
MC/MP
BIO
MEN
IOWE
MWE
IOEN
Stack
8 × 16
16
PC (16)
16 LSB
MUX
16 Program Bus
X2/CLKINCLKOUT X1
Controller
MUX
Address
Legend:
ACC= Accumulator
ARP= Auxiliary Register Pointer
AR0 = Auxiliary Register 0
AR1 = Auxiliary Register 1
DP = Data Page Pointer
P = P Register
PC = Program Counter
T = T Register
MUX
RS
16
VIH High-level input voltage
VIL Low-level input voltage
V
µA
µA
pF
pF
VOH High-level output voltage
IOZ Off-state output current
CiInput capacitance
II Input current
CoOutput capacitance
f = 1 MHz, all other pins 0 V
VCC = VSS to VCC
VCC = MAX
TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 83
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 6) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation 0.5 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature: 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature –55 °C to 150 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only , and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 6: All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VSS Supply voltage 0 V
All inputs except CLKIN 2 V
CLKIN 3 V
All inputs except MC/MP 0.8 V
MC/MP 0.6 V
IOH High-level output current, all outputs –300 µA
IOL Low-level output current 2 mA
TAOperating free-air temperature 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IOH = MAX 2.4 3
IOH = 20 µA VCC – 0.4
VOL Low-level output voltage IOL = MAX 0.3 0.5 V
VO = 2.4 V 20
VO = 0.4 V –20
All inputs except CLKIN ±20
CLKIN ±50
ICC Supply current f = 35 MHz, VCC = 5.25 V 60 75 mA
Data bus 25
All others 15
Data bus 25
All others 10
TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
84
internal clock option
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
Crystal frequency, fxTA = 0°C to 70°C 6.7 35.1 MHz
C1, C2 TA = 0°C to 70°C 10 pF
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tc(MC) Master clock cycle time 28.49 28.57 150 ns
tr(MC) Rise time, master clock input 5 10 ns
tf(MC) Fall time, master clock input 5 10 ns
tw(MCP) Pulse duration, master clock 0.45tc(C) 0.55tc(C) ns
tw(MCL) Pulse duration, master clock low 10 ns
tw(MCH) Pulse duration, master clock high 10 ns
switching characteristics over recommended operating conditions
PARAMETER MIN NOM MAX UNIT
tc(C) CLKOUT cycle time 113.96 114.3 600 ns
tr(C) CLKOUT rise time 10 ns
tf(C) CLKOUT fall time 8 ns
tw(CL) Pulse duration, CLKOUT low 49 ns
tw(CH) Pulse duration, CLKOUT high 47 ns
td(MCC) Delay time, CLKIN↑ to CLKOUT↓5 50 ns
TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 85
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions
PARAMETER MIN NOM MAX UNIT
td1 Delay time, MEN↑, MWE↑, IOEN↑, IOWE↑, to next address bus valid 0 35 ns
td2 Delay time, CLKOUT↓to MEN↓1/4tc(C) –5 1/4tc(C)+12 ns
td3 Delay time, CLKOUT↓to MEN↑–3 6 ns
td4 Delay time, CLKOUT↓to IOEN↓1/4tc(C) –5 1/4tc(C)+12 ns
td5 Delay time, CLKOUT↓to IOEN↑–3 6 ns
td6 Delay time, CLKOUT↓to MWE↓, IOWE↓1/2tc(C) –5 1/2tc(C)+12 ns
td7 Delay time, CLKOUT↓to MWE↑, IOWE↑–3 6 ns
td8 Delay time, MWE↓, IOwE↓, data bus out valid 0 ns
td9(CLK) Delay time, CLKOUT↓ to data bus starts to be driven 1/4tc(C) –5 ns
td9(MEN) Delay time, MEN↑, to data bus starts to be driven 1/4tc(C) ns
td10(CLK) Delay time, CLKOUT↓to data bus stops being driven 15 ns
td10(WE) Delay time, MWE↑, IOWE↑, data bus stops being driven 20 ns
tvData bus OUT valid after MWE↑, IOWE↑5 10 ns
th(A-WMD) Address bus hold time after MWE↑, MEN↑, IOWE↑, or IOEN↑0 2 ns
tsu(A-MD) Address bus setup time prior to MEN↓, IOEN↓5 ns
timing requirements over recommended operating conditions
MIN MAX UNIT
tsu(D) Setup time, data bus valid prior to MEN↑, IOEN↑35 ns
th(D) Hold time, data bus held valid after MEN↑, IOEN↑0 ns
RESET (RS) TIMING
switching characteristics over recommended operating conditions
PARAMETER MIN MAX UNIT
td11 Delay time, IOEN↑, IOWE↑, MWE↑, and MEN↑ from RS 1/2tc(C)+50 ns
tdis(R) Data bus disable time after RS 1/4tc(C)+50 ns
timing requirements over recommended operating conditions
MIN MAX UNIT
tsu(R) Reset (RS) setup time prior to CLKOUT 30 ns
tw(R) RS pulse duration 5tc(C) ns
TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
86
INTERRUPT (INT) TIMING
timing requirements over recommended operating conditions
MIN MAX UNIT
tf(INT) Fall time, INT 15 ns
tw(INT) Pulse duration, INT tc(C) ns
tsu(INT) Setup time, INT↓ before CLKOUT↓30 ns
IO (BIO) TIMING
timing requirements over recommended operating conditions
MIN MAX UNIT
tf(IO) Fall time, BIO 15 ns
tw(IO) Pulse duration, BIO tc(C) ns
tsu(IO) Setup time, BIO↓ before CLKOUT↓30 ns
TIMING DIAGRAMS
Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless
otherwise noted.
clock timing
tr(MC)
tc(MC)
tw(MCH) tw(MCP)†
tf(MC)
tw(MCL)
td(MCC)†tw(CH)
tw(CL)
tr(C)
tc(C)
tf(C)
X2/CLKIN
CLKOUT
†td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform.
TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 87
memory read timing
tc(C)
td3 td2
td1 th(A-WMD)
tsu(D) th(D)
tsu(A-MD)
Instruction Input Valid
CLKOUT
MEN
A15-A0
D15-D0
Address Bus Valid
IN instruction timing
CLKOUT
MEN
A15-A0
IOEN
D15-D0
tsu(D)
th(D)
tsu(A-MD)
td5
12
345
678
td4
Legend:
1. IN instruction prefetch 5. Address bus valid
2. Next instruction prefetch 6. Instruction input valid
3. Address bus valid 7. Data input valid
4. Peripheral address valid 8. Instruction input valid
TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
88
OUT instruction timing
CLKOUT
MEN
A15-A0
IOWE
D15-D0 6 7 8
td7
td9(MEN) tv
td9(CLK)
td6
td8
td10(WE)
td10(CLK)
12
345
Legend:
1. OUT instruction prefetch 5. Address bus valid
2. Next instruction prefetch 6. Instruction valid
3. Address bus valid 7. Data output valid
4. Peripheral address valid 8. Instruction valid
TBLR instruction timing
CLKOUT
MEN
A15-A0
D15-D0
td2 td3
tsu(D) th(D)
td1
TBLW instruction timing
CLKOUT
MEN
A15-A0
MWE
D15-D0 6 7 8
td7
td9(MEN) tv
td9(CLK)
td6
td8
td10(WE)
td10(CLK)
TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 89
reset timing
tsu(R) tsu(R)
tw(R)
tdis(R) td11
CLKOUT
RS
IOEN, IOWE
MEN, MWE
D15-D0
MEN
Address
Bus
(see
Note E)
Data Shown Relative To IOWE
Data In From
PC ADDR 0 Data In From
PC ADDR PC+1
AB = Address Bus
AB = PC AB = PC+1 AB = PC = 0
AB = PC+1
Data
Out
NOTES: A. RS forces IOEN, IOWE, MWE, and MEN high and places data bus D0 through D15 in a high-impedance state. AB outputs (and
program counter) are synchronously cleared to zero after the next complete CLK cycle from RS↓.
B. RS must be maintained for a minimum of five clock cycles.
C. Resumption of normal program will commence after one complete CLK cycle from RS↑.
D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK
cycle.
E. Diagram shown is for definition purpose only. IOEN, IOWE, MWE, and MEN are mutually exclusive.
F. During a write cycle, RS may produce an invalid write address.
interrupt timing
CLKOUT
tsu(INT)
tw(INT)
tf(INT)
INT
BIO timing
CLKOUT
BIO
tsu(IO)
tw(IO)
tf(IO)
TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
90
design considerations for interfacing to SRAM, EPROM and peripherals
The ′C16 differs somewhat from the other members of the ′C1x family of digital signal processors (DSPs).
Additional control signals are available for easier interface to external memory or peripherals, and the memory
write cycle timings have been changed.
The discussion here will center around changes in tv and its impact upon SRAM, EPROM and
peripherals/latches interfaces.
Access time requirements for interface may be defined relative to :
1. Valid address (ta);
2. MEN/IOEN, [(ta(MEN)];
Figure 11 and the following examples summarize these timings at 35 MHz CLKIN.
tc(C)
tw(CH)
td2 ta(MEN)
td1 ta
tsu(D)
CLKOUT
MEN
A15-A0
D15-D0
ta(CLKOUT)
tf(C)
Figure 11.
where:
ta: (access time from address valid) = tc(C) – td1 – tsu(D) = 44.3 ns
ta(MEN) : (access time from MEN valid) = tc(C) – td2 – tsu(D) + td3 = 35.73 ns
and where (for 35 MHz CLKIN):
tc(C) = 114.3 ns
td1 = 35 ns
td2 = [1/4 × (114.3) + 12] ns
tsu(D) = 35 ns
tw(CH) = 47 ns nominal
tf(C) = 8 ns nominal
TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 91
In addition to the above timings, tv must be taken into account. tv is the time that the data bus is
guaranteed to be held after the rising edge of MWE or IOWE. In other ′C1x devices, the value of tv was
referenced to CLKOUT↓ and not WE↑ (see Figure 12). For the ′C16, tv is a minimum of 5 ns. This implies
that MWE and IOWE must be tied directly to the external device. If required, decode logic must be added
to an input other than the read/write input — for example, the chip select on SRAMs. If the external device
does not have two inputs, then transparent latches must be added to extend the time data is held on the
data bus. These latches must be off the bus prior to the next instruction (see Figure 12).
CLKOUT
MWE or IOWE
D15-D0
tv
td10
Figure 12.
where:
tv = 5 ns (min)
td10 = 15 ns (max)
There is a potential for bus conflict on the prefetch and execution of a TBLW or an OUT instruction. Figure 13
details the timings to be considered. In addition to the timings for the ′C16, timing definitions for interface are
also included.
tdmemh
CLKOUT
MEN
CE
D15-D0
Memory Driven Data
D15-D0
DSP Driven Data
tddeco
td9(MEN) tconf
TBLW or OUT ExecutionDummy Prefetch Cycle
Figure 13.
where:
TMS320C16
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
92
tconf (data bus conflict time) = tddeco + tdmemh – td9(MEN)
with:
tddeco : decode delay time to make the CE or OE signal
tdmemh : memory data hold time from CE or OE
td9 : delay time, MEN to data bus starts being driven
td9 : (at 35 MHz CLKIN) = [1/4tc(C)] = [1/4(114.3)] = 28.58 ns
If tconf is less than or equal to zero, data bus conflict does not occur.
If tconf is greater than zero, data conflict occurs.
Note that the following discussion is for CLKIN of 35 MHz.
static memory with output enable and write enable/chip select
The following SRAMs are able to interface directly to the ′C16, needing only to directly connect the ′C16 memory
control signals MEN and MWE to the memory . Device select decode is accomplished with address decode and
then input to the device chip select.
PRODUCT tddeco tdmemh tdconf UNITS
TC55645-35 0 15 –13.58 ns
TC55328-35 0 15 –13.58 ns
TMS6789-35 0 8 –20.58 ns
TC5588-35 0 10 –18.58 ns
TMS6716-35 0 10 –18.58 ns
ALS138
(Decoder)
WE
OE
CS
ADDR
DATA
MWE
MEN
A15-AXX
D15-D0
TMS320C16 SRAM With OE
Figure 14.
TMS320C16
DIGITAL SIGNAL PROCESSOR
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POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 93
static memory with chip enable and write enable
Without a separate output enable, a faster SRAM is required. Logic is added to decode address and memory
control to perform a read/write cycle. The MWE signal is directly connected to the WE input of the SRAM to meet
the tv specification (see Figure 15).
Product tddeco tdmemh tdconf Units
CY7C164-25 7.5 10 – 11.08 ns
Programmable
Logic WE
CE
ADDR
DATA
MWE
MEN
A15-AXX
D15-D0
TMS320C16 SRAM With CE
7.5 ns
Figure 15.
EPROM interface
The following high-speed EPROMs can be used directly:
Product tddeco tdmemh tdconf Units
CY7C291-35 0 25 – 3.58 ns
TMS27C291-35 0 25 – 3.58 ns
Decoder
7.5 ns
CS1
CS2
CS3
DATA
MEN
A15-AXX
D15-D0
TMS320C16 Fast EPROM
TMS27C291-35
ADDR
VCC
Figure 16.
TMS320C16
DIGITAL SIGNAL PROCESSOR
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POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
94
interfacing latches to the TMS320C16
As with the previous devices, the memory control signal must be directly connected to the latch and the latch
needs to have a separate chip select. There are several devices with this feature, including the SN74ALS996.
The SN74ALS996 is an 8-bit D-type edge-triggered read-back latch with three-state outputs, connected to the
′C16 as illustrated in Figure 17.
EN
IOEN
TMS320C16 ALS996A x 2
ALS 138
RD
CLK
D15-D0
IOWE
D15-D0
A2
A1
A0
Decoder
Figure 17.
Data (16)
Address (3)
Dua-Channel
Serial Port
Coprocessor
Interface
µ-Law/A-Law
Hardware
Timer
Interrupt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PA1/RBLE
PA0/HI/LO
MC
RS
EXINT
CLKOUT
X1
X2/CLKIN
BIO
VSS
D8/LD8
D9/LD9
D10/LD10
D11/LD11
D12/LD12
D13/LD13
D14/LD14
D15/LD15
D7/LD7
D6/LD6
PA2/TBLF
FSR
FSX
FR
DX1
DX0
SCLK
DRI
DEN/RD
WE/RD
VCC
DR0
XF
MC/PM
D0/LD0
D1/LD1
D2/LD2
D3/LD3
D4/LD4
D5/LD5
TMS320C17/E17/LC17/P17
N/JD Package
CLKOUT
X1
X2/CLKIN
BIO
NC
VSS
D8
D9
D10
D11
D12
DX0
SCLK
DR1
DEN/RD
WE/WR
VCC
DR0
XF
MC/PM
D0/LD0
VSS
123456
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
44 43 42 41 40 39
38
37
36
35
34
33
32
31
30
29
EXINT
RS
MC
PAO/HI/LO
PA1/RBLE
PA2/TBLF
FSR
FSX
FR
DX1
D13/LD13
D14/LD14
D15/LD15
D7/LD7
D6/LD6
D5/LD5
D4LD4
D3/LD3
D2/LD2
TMS320C17, TMS320E17
FN/FZ Packages
SS
VSS
V
D1/LD1
′320C17
or
′320E17
Serial Interface
•Device Packaging:
— 40-Pin DIP (All Devices)
— 44-Lead PLCC (TMS320C17/LC17/P17
— 44-Lead CER-QUAD (TMS320E17)
•3.3 -V Low-Power Version Available
(TMS320LC17)
•Operating Free-Air Temperature Range
...0°C to 70°C
•16-Bit Coprocessor Interface for Common
4/8/16/32-Bit Microcomputers/Microprocessors
(Top View) (Top View)
TMS320C17, TMS320E17, TMS320LC17, TMS320P17
DIGITAL SIGNAL PROCESSORS
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POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 95
Key Features: TMS320C17/E17/LC17/P17
•200-ns Instruction Cycle Timing
(TMS320C17/E17/P17)
•278-ns Instruction Cycle Timing
(TMS320LC17)
•256 Words of On-Chip Data RAM
•4K Words of On-Chip Program ROM
(TMS320C17/LC17)
•4K Words of On-Chip Program EPROM
(TMS320E17/P17)
•One-Time Programmable (OTP) W indowless
EPROM Version Available (TMS320P17)
•EPROM Code Protection for Copyright Security
•Dual-Channel Serial Port for Full-Duplex Serial
Communication
•Serial Port Timer for Standalone Serial
Communication
•On-Chip Companding Hardware for µ-law/A-law
PCM Conversions
TMS320C17, TMS320E17, TMS320LC17, TMS320P17
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
96
architecture
The ′C17/E17/LC17/P17 consists of five major functional units: the ′C15 microcomputer, a system control
register, a full-duplex dual-channel serial port, companding hardware, and a coprocessor port.
Three of the I/O ports are used by the serial port, companding hardware, and the coprocessor port. Their
operation is determined by the 32 bits of the system control register (see Table 6 for the control register bit
definitions). Port 0 accesses control register 0 and consists of the lower 16 register bits (CR15-CR0), and is used
to control the interrupts, serial port connections, and companding hardware operation. Port 1 accesses control
register 1, consisting of the upper 16 control bits (CR31-CR16), as well as both serial port channels, the
companding hardware, and the coprocessor port channels. Communication with the control register is via IN
and OUT instructions to ports 0 and 1.
Interrupts fully support the serial port interface. Four maskable interrupts (EXINT, FR, FSX, and FSR) are
mapped into I/O port 0 via control register 0. When disabled, these interrupts may be used as single-bit logic
inputs polled by software.
serial port
The dual-channel serial port is capable of full-duplex serial communication and offers direct interface to two
combo-codecs. T wo receive and two transmit registers are mapped into I/O port 1, and operate with 8-bit data
samples. Internal and external framing signals for serial port transfers (MSB first) are selected via the system
control register. The serial port clock, SCLK, provides the bit timing for transfers with the serial port, and may
be either an input or output. As an input, an external clock provides the timing for data transfers and framing
pulse synchronization. As an output, SCLK provides the timing for standalone serial communication and is
derived from the ′C17/E17/P17 system clock, X2/CLKIN, and system control register bits CR27-CR24
(see Table 7 for the available divide ratios). The internal framing (FR) pulse frequency is derived from the serial
port clock (SCLK) and system control register bits CR23-CR16. This framing pulse signal provides framing
pulses for combo-codecs, for a sample clock for voice-band systems, or for a timer used in control applications.
µ-law/A-law companding hardware
The ′C17/E17/LC17/P17 features hardware companding logic and can operate in either µ-law or A-law format
with either sign-magnitude or twos-complement numbers. Data may be companded in either a serial mode for
operation on serial port data or a parallel mode for computation inside the device. The companding logic
operation is selected through CR14. No bias is required when operating in twos-complement. A bias of 33 is
required for sign-magnitude in µ-law companding. Upon reset, the device is programmed to operate in
sign-magnitude mode. This mode can be changed by modifying control bit 29 (CR29) in control register 1. For
further information on companding, see the
TCM29C13/TCM29C14/TCM29C16/TCM29C17 Combined
Single-Chip PCM Codec and Filter Data Sheet
, and the application report, “
Companding Routines for the
TMS32010/TMS32020,”
in the book
Digital Signal Processing Applications with the TMS320 Family
(SPRA012A), both documents published by Texas Instruments.
In the serial mode, sign-magnitude linear PCM (13 magnitude bits plus 1 sign bit for µ-law format or 12
magnitude bits plus 1 sign bit for A-law format) is compressed to 8-bit sign-magnitude logarithmic PCM by the
encoder and sent to the transmit register for transmission on an active framing pulse. The decoder converts 8-bit
sign-magnitude log PCM from the serial port receive registers to sign-magnitude linear PCM.
In the parallel mode, the serial port registers are disabled to allow parallel data from internal memory to be
encoded or decoded for computation inside the device. In the parallel encode mode, the encoder is enabled
and a 14-bit sign-magnitude value written to port 1. The encoded value is returned with an IN instruction from
port 1. In the parallel decode mode, the decoder is enabled and an 8-bit sign-magnitude log PCM value is written
to port 1. On the successive IN instruction from port 1, the decoded value is returned. At least one instruction
should be inserted between an OUT and the successive IN when companding is performed with
twos-complement values.
313029282726252423222120191817161514131211109876543210
Interrupt Mask BitsFrame Counter Modulus
FR
Pulse
Widt
h
Port 1 Port 0
Reserved
I/O
Control Serial Clock
Prescale Control Serial-Port Configuration
Companding Hardware Control Interrupt Flags
Port 1 configuration control:
External framing enable:
Serial-port enable:
µ-law/A-law encoder enable:
µ-law/A-law decoder enable:
µ-law/A-law decoder encode/decoded select:
Serial clock control:
FR pulse-width control:
Two’ s-complement µ-law/A-law conversion enable:
8/16-bit length coprocessor mode select:
TMS320C17, TMS320E17, TMS320LC17, TMS320P17
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 97
Table 6. Control Register Configuration
BIT DESCRIPTION AND CONFIGURATION
0 EXINT Interrupt flag†
1 FSR interrupt flag†
2 FSX interrupt flag†
3FR interrupt flag†
4 EXINT interrupt enable mask. When set to logic 1, an interrupt on EXINT activates device interrupt circuitry.
5 FSR interrupt enable mask. Same as EXINT control.
6 FSX interrupt enable mask. Same as EXINT control.
7FR interrupt enable mask. Same as EXINT control.
80 = port 1 connects to either serial-port registers or companding hardware.
1 = port 1 accesses CR31-CR16.
90 = serial-port data transfers controlled by active FR.
1 = serial-port data transfers controlled by active FSX/FSR.
10 XF external logic output flag latch
11 0 = Parallel companding mode; serial port disabled.
1 = serial companding mode; serial port registers enabled.
12 0 = disabled.
1 = data written to port 1 is µ-law or A-law encoded.
13 0 = disabled.
1 = data written to port 1 is µ-law or A-law decoded.
14 0 = companding hardware performs µ-law conversion.
1 = companding hardware performs A-law conversion.
15 0 = SCLK is an output, derived from the prescaler in timing logic.
1 = SCLK is an input that provides the clock for serial port and frame counter in timing logic.
23-16 Frame counter modulus. Controls FR frequency = SCLK/(CNT + 2) where CNT is binary value fo CR23-CR16‡
27-24 SCLK prescale cotnrol bits. (See Table 7 for divide ratios.)
28 0 = fixed-data rate; FR is 1 SCLK cycle wide.
1 = variable-data rate; FR is 8 SCLK cycles wide.
29 0 = sign-magnitude companding
1 = twos-complement companding
30 0 = 8-bit byte length
1 = 16-bit word length
31 Reserved for future expansion: Should be set to zero.
†Interrupt flag is cleared by writing a logic 1 to the bit with an OUT instruction to port 0.
‡All ones in CR23-CR16 indicate a degenerative state and should be avoided. Bits are operational whether SCLK is an input or an output.
CNT must be greater than 7.
TMS320C17, TMS320E17, TMS320LC17, TMS320P17
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
98
Table 7. Serial Clock (SCLK) Divide Ratios (X2/CLKIN = 20.48 MHz)
CR27 CR26 CR25 CR24 DIVIDE RATIO SCLK FREQUENCY UNIT
0 0 0 0 32 0.640 MHz
0 0 0 1 28 0.731 MHz
0 0 1 0 24 0.853 MHz
0 1 0 0 20 1.024 MHz
1 0 0 0 16 1.280 MHz
1 0 0 1 14 1.463 MHz
1 0 1 0 12 1.706 MHz
1 1 0 0 10 2.048 MHz
The specification for µ-law and A-law log PCM coding is part of the CCITT G.711 recommendation. The
following diagram shows a ′C17/E17/P17 interface to two codecs as used for µ-law or A-law companding format.
DX0
DR0
SCLK
FR
DX1
DR1
VSS
VCC
MC
MC/PM
X2
X1
+5 V
PCM In
PCM Out
CLKR/X
FSX
FSR
TCM29C13
PCM In
PCM Out
CLKR/X
FSX
FSR
TCM29C13
Analog Out
Analog In
Analog Out
Analog In
TMS320C17/E17/P17
coprocessor port
The coprocessor port, accessed through I/O port 5 using IN and OUT instructions, provides a direct connection
to most 4/8-bit microcomputers and 16/32-bit micorprocessors. The coprocessor interface allows the
′C17/E17/P17 to act as a peripheral (slave) microcomputer to a microprocessor, or a master to a peripheral
microcomputer such as TMS7042. The coprocessor port is enabled by setting MC/PM and MC low. The
microcomputer mode is enabled by setting these two pins high. (Note that MC/PM ≠ MC is undefined.)
In the microcomputer mode, the 16 data lines are used for the 6 parallel 16-bit I/O ports.
In the coprocessor mode, the 16-bit coprocessor port is reconfigured to operate as a 16-bit latched bus interface.
Control bit 30 (CR30) in control register 1 is used to configure the coprocessor port to either an 8-bit or a 16-bit
length. When CR30 is high, the coprocessor port is 16 bits wide thereby making all 16 bits of the data port
available for 16-bit transfers to 16 and 32-bit microprocessors. When CR30 is low, the port is 8-bits wide and
mapped to the low byte of the data port for interfacing to 8-bit microcomputers. When operating in the 8-bit mode,
both halves of the 16-bit latch can be addressed using the HI/LO pin, thus allowing 16-bit transfers over 8 data
lines. When not in the coprocessor mode, port 5 can be used as a generic I/O port.
TMS320C17, TMS320E17
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 99
coprocessor port (continued)
The external processor recognizes the coprocessor interface in which both processors run asynchronously as
a memory-mapped I/O operation. The external processor lowers the WR line and places data on the bus. It next
raises the WR line to clock the data into the on-chip latch. The rising edge of WR automatically creates an
interrupt to the ′C17/E17/P17, and the falling edge of WR clears the RBLE (receive buffer latch empty) flag.
When the ′C17/E17/P17 reads the coprocessor port, it causes the RBLE signal to transition to a logic low state
that clears the data in the latch, and allows the interrupt condition to be cleared internally . Likewise, the external
processor reads form the latch by driving the RD line active low, thus enabling the output latch to drive the latched
data. When the data has been read, the external device will again bring the RD line high. This activates the BIO
line to signal that the transfer is complete and the latch is available for the next transfer . The falling edge of RD
resets the TBLF (transmit buffer latch full) flag. Note that the EXINT and BIO lines are reserved for coprocessor
interface and cannot be driven externally when in the coprocessor mode.
An example of the use of a coprocessor interface is shown in Figure 18, in which the ′C17/E17/P17 are DSPs
interfaced to the TMS70C42, an 8-bit microcontroller.
MC
MC/PM
HI/LO
CLKOUT
RD
TBLF
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0
TMS320C17/E17/P17 TMS70C42
XTAL2
A3
A2
D7
D6
D5
D4
D3
D2
D1
D0
WR
RBLE
A1
A0
17
9
8
19
20
21
22
23
24
26
27
7
6
6
32
40
19
20
21
22
23
24
25
26
31
1
3
27
2
Figure 18. Coprocessor Interface
TMS320C17, TMS320E17, TMS320LC17, TMS320P17
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
100
TERMINAL FUNCTIONS†
NAME I/O‡DEFINITION
BIO
CLKOUT
D15/LD15-D0/LD0
DEN/RD
DR1, DR0
DX1, DX0
EXINT
FR
FSR
FSX
MC
MC/PM
PA0/HI/LO
PA1/RBLE
PA2/TBLF
RS
SCLK
VCC
VSS
WE/WR
X1
X2/CLKIN
XF
I
O
I/O
I/O
I
O
I
O
I
I
I
I
I/O
O
O
I
I/O
I
I
O
O
I
O
External polling input
System clock output, 1/4 crystal/CLKIN frequency
16-bit parallel data bus/data lines for coprocessor latch
Data enable for device input data/external read for output latch
Serial-port receive-channel inputs
Serial-port transmit-channel outputs
External interrupt input
Internal serial-port framing output
External serial-port receive framing input
External serial-port transmit framing input
Microcomputer select (must be same state as MC/PM)
Microcomputer/peripheral coprocessor select (must be same state as MC)
I/O port address output/latch byte select pin
I/O port address output/receive buffer latch empty flag
I/O port address output/transmit buffer latch full flag
Reset for initializing the device
Serial-port clock
+ 5 V Supply
Ground
Write enable for device output data/external write for input latch
Crystal output for internal oscillator
Crystal input for internal oscillator or external oscillator system clock input
External-flag output pin
†See EPROM programming section.
‡Input/Output/High-impedance state.
TMS320C17, TMS320E17, TMS320LC17, TMS320P17
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 101
functional block diagram
DR1
DR0
DX1
DX0
RR1/RS1
RR0/RS0
8
16
14
XF
8
8
TR1/TS1
TR0/TS0
8
MUX
µ-Law/A-Law
Decoder
8
MUX
8
8
16
16
µ-Law/A-Law
Encoder
16
16
Register
MUX
System Control
16
16
Data Latch
FRFSXFSR
INT/EXINT
Interrupt Latch and
Multiplexer
Serial-port Timing and
Framing Control
MC
MC/PM
312
32
16
16 16
32
Shifter (0,1, 4)
32
ACC (32)
32
ALU (32)
Data RAM
(256 Words)
Address
Data
32
32
MUX
32
16
P(32)
T(16)
Multiplier
Shifter (0–16)
16
8
DP
7
MUX
8
8
AR1 (16)
AR0 (16)
ARP
16 16
Data Bus
Data Bus
1616
16
Program Bus
PA2–PA0
12
Instruction
Program
ROM/EPROM
(4K Words)
3
HI/LO
RS
BIO
RD/DEN
WR/WE
TBLF
RBLE
Stack
4 × 12
12
12
PC (12)
12
12 LSB
MUX
16
Program Bus
X2/CLKINCLKOUT
X1
Controller
MUX
MUX
MUX
Address
Data Latch
SCLK
Legend:
ACC = Accumulator
PC = Program Counter
ARP = Auxiliary Register Pointer
P = P Register
AR0 = Auxiliary Register 0
T = T Register
AR1 = Auxiliary Register 1
TR = Transmit Register
DP = Data Page Pointer
RR = Receive Register
D15-D0
VIL Low-level input voltage
VIH High-level input voltage
TAOperating free-air temperature
VCC Supply voltage
TMS320C17, TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
102
electrical specifications
This section contains the electrical specifications for all versions of the ′C17/E17/P17 digital signal processors,
including test parameter measurement information. Parameters with PP subscripts apply only to the ′E17/P17
in the EPROM programming mode (see Note 11).
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC, except for the ′320LC17 (see Note 6) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, VPP –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range –0.3 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation 1.5 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature: L suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A suffix – 40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature –55 °C to 150 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only , and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 6: All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
EPROM devices 4.75 5 5.25 V
All other devices 4.5 5 5.5 V
VPP Supply voltage (see Note 11) 12.25 12.5 12.75 V
VSS Supply voltage 0 V
All inputs except CLKIN 2 V
CLKIN 3 V
All inputs except MC/MP 0.8 V
MC/MP 0.6 V
IOH High-level output current, all outputs –300 µA
IOL Low-level output current (All outputs) 2 mA
L suffix 0 70 °C
A suffix – 40 85 °C
NOTE 11: VPP can be applied only to programming pins designed to accept VPP as an input. During programming the total supply current
is IPP + ICC.
mAICC‡Supply current
Crystal frequency, fxMHz
RL = 825 Ω,
CL = 100 pF
(see Figure 2)
TMS320C17, TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 103
electrical characteristics over specified temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
TMS320C17 f = 20.5 MHz, VCC = 5.5 V, TA = 0°C to 70°C 50 65
TMS320E17/P1
7f = 25.6 MHz, VCC = 5.5 V, TA = – 40°C to 85°C 55 75
†All typical values are at TA = 70°C and are used for thermal resistance calculations.
‡ICC characteristics are inversely proportional to temperature. For ICC dependance on temperature, frequency, and loading, see Figure 3.
CLOCK CHARACTERISTICS AND TIMING
The ′C17/E17/P17 can use either its internal oscillator or an external frequency source for a clock.
internal clock option
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency
of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and
parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and should be
specified at a load capacitance of 20 pF.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
TMS320C17 TA = 0°C to 70°C 6.7 20.5
TMS320E17/P1
7TA = – 40°C to 85°C 6.7 20.5
C1, C2 TA = 0°C to 70°C 10 pF
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the table below.
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tc(C) CLKOUT cycle time§195.12 200 ns
tr(C) CLKOUT rise time 10ns
tf(C) CLKOUT fall time 8ns
tw(CL) Pulse duration, CLKOUT low 92ns
tw(CH) Pulse duration, CLKOUT high 90ns
td(MCC) Delay time, CLKIN↑ to CLKOUT↓2560ns
§tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used).
Values derived from characterization data and not tested.
RL = 825 Ω
CL = 100 pF,
(see Figure 2)
RL = 825 Ω,
CL = 100 pF
(see Figure 2)
TMS320C17, TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
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104
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tc(MC) Master clock cycle time 48.78 50 150 ns
tr(MC) Rise time, master clock input 5†10†ns
tf(MC) Fall time, master clock input 5†10†ns
tw(MCP) Pulse duration, master clock 0.45tc(MC)†0.6tc(MC)†ns
tw(MCL) Pulse duration, master clock low 20†ns
tw(MCH) Pulse duration, master clock high 20†ns
†Values derived from characterization data and not tested.
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td1 Delay time, CLKOUT↓ to address bus valid 10†50 ns
td4 Delay time, CLKOUT↓ to DEN↓1/4tc(C) –5
†1/4tc(C) +15 ns
td5 Delay time, CLKOUT↓ to DEN↑–10†15 ns
td6 Delay time, CLKOUT↓ to WE↓1/2tc(C) –5
†1/2tc(C) +15 ns
td7 Delay time, CLKOUT↓ to WE↑–10†15 ns
td8 Delay time, CLKOUT↓ to data bus OUT valid 1/4tc(C) + 65 ns
td9 T ime after CLKOUT↓ that data bus starts to be driven 1/4tc(C) –5
†ns
td10 T ime after CLKOUT↓that data bus stops bieng driven 1/4tc(C)+70†ns
tvData bus OUT valid after CLKOUT↓1/4tc(C)–10 ns
th(A-WMD) Address hold time after WE↑, or DEN↑
(see Note 14) 0†2†ns
tsu(A-MD) Address bus setup time prior to DEN↓1/4tc(C)–45 ns
†Values derived from characterization data and not tested.
NOTE 14: Address bus will be valid upon WE↑, MEN↑, or DEN↑.
timing requirements over recommended operating conditions
TEST CONDITIONS MIN NOM MAX UNIT
tsu(D) Setup time, data bus valid prior to CLKOUT↓50 ns
th(D) Hold time, data bus held valid after CLKOUT↓
(see Note 16) 0 ns
NOTE 16: Data may be removed from the data bus upon DEN↑ preceding CLKOUT↓.
RL 825 Ω,
CL = 100 pF,
(see Figure 2)
TMS320C17, TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
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POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 105
RESET (RS) TIMING
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td11 Delay time, DEN↑, and WE↑ from RS 1/2tc(C)+50† ns
tdis(R) Data bus disable time after RS 1/4tc(C)+50†ns
td12 Delay time from RS↓ to high-impedance SCLK 200†ns
td13 Delay time from RS↓ to high-impedance DX1, DX0 200†ns
†Values derived form characterization data and not tested.
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tsu(R) Reset (RS) setup time prior to CLKOUT (see Note 10) 50 ns
tw(R) RS pulse duration 5tc(C) ns
NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.
INTERRUPT (EXINT) TIMING
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tf(INT) Fall time, EXINT 15 ns
tw(INT) Pulse duration, EXINT tc(C) ns
tsu(INT) Setup time, EXINT↓ before CLKOUT↓50 ns
IO (BIO) TIMING
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tf(IO) Fall time, BIO 15 ns
tw(IO) Pulse duration, BIO tc(C) ns
tsu(IO) Setup time, BIO↓ before CLKOUT↓50 ns
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(XF) Delay time CLOCKOUT↑ to valid XF RL 825 Ω, CL = 100 pF,
(see Figure 2) 5†115 ns
†Values derived form characterization data and not tested.
TMS320C17, TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
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106
SERIAL PORT TIMING
switching characteristics over recommended operating conditions
PARAMETER MIN NOM MAX UNIT
td(CH-FR) Internal framing (FR) delay from SCLK rising edge 70 ns
td(DX1-XL) DX bit 1 valid before SCLK falling edge 20 ns
td(DX2-XL) DX bit 2 valid before SCLK falling edge 20 ns
th(DX) DX hold time after SCLK falling edge tc(SCLK)/2 ns
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tc(SCLK) Serial port clock (SCLK) cycle time (see Note 17) 390 4770 ns
tf(SCLK) Serial port clock (SCLK) fall time 30†ns
tr(SCLK) Serial port clock (SCLK) rise time 30†ns
tw(SCLKL) Serial port clock (SCLK) low-pulse duration (see Note 17) 185 2500 ns
tw(SCLKH) Serial port clock (SCLK) high-pulse duration (see Note 17) 185 2500 ns
tsu(FS) FSX/FSR setup time before SCLK falling edge 100 ns
tsu(DR) DR setup time before SCLK falling edge 20 ns
th(DR) DR hold time after SCLK falling edge 20 ns
†Values derived from characterization data and not tested.
NOTES:17. Minimum cycle time is 2tc(C) where tc(C) is CLKOUT cycle time.
18. The duty cycle of the serial port clock must be within 45 to 55 percent.
COPROCESSOR INTERFACE TIMING
switching characteristics over recommended operating conditions
PARAMETER MIN NOM MAX UNIT
td(R-A) RD low to TBLF high 75 ns
td(W-A) WR low to RBLE high 75 ns
ta(RD) RD low to data valid 80 ns
th(RD) Data hold time after RD high 25 ns
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
th(HL) HI/LO hold time after WR or RD high 25 ns
tsu(HL) HI/LO setup time after WR or RD low 40 ns
tsu(WR) Data setup time prior to WR high 30 ns
th(WR) Data hold time after WR high 25 ns
tw(RDL) RD low-pulse duration 80 ns
tw(WRL) WR low-pulse duration 60 ns
TMS320C17, TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
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POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 107
TIMING DIAGRAMS
Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2 volts, unless
otherwise noted.
clock timing
tr(MC)
tc(MC)
tw(MCH) tw(MCP)†
tf(MC)
tw(MCL)
td(MCC)†tw(CH)
tw(CL)
tr(C)
tc(C)
tf(C)
X2/CLKIN
CLKOUT
†td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform.
memory read timing
th(A–WMD)
tsu(D) th(D)
Address Bus Valid
tsu(A-MD)
Instruction Input Valid
CKKOUT
A11-A0
D15-D0
tc(C)
td1
td2
td3
MEN
TMS320C17, TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
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108
IN instruction timing
CLKOUT
MEN
A11-A0
DEN
D15-D0
tsu(D)
th(D)
tsu(A-MD)
td5
td4
12
345
678
Legend:
1. IN Instruction Prefetch 5. Address Bus Valid
2. Next Instruction Prefetch 6. Instruction Input Valid
3. Address Bus Valid 7. Data Input Valid
4. Peripheral Address Valid 8. Instruction Valid
OUT instruction timing
CLKOUT
MEN
A11-A0
WE
D15-D0
12
34 5
678
td6 td7
tv
td9 td10
td8
Legend:
1. OUT Instruction Prefetch 5. Address Bus Valid
2. Next Instruction Prefetch 6. Instruction Input Valid
3. Address Bus Valid 7. Data Output Valid
4. Peripheral Address Valid 8. Instruction Valid
TMS320C17, TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
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POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 109
reset timing
tsu(R) tsu(R)
tw(R)
tdis(R) td11
CLKOUT
RS
DEN
WE
D15-D0
PA2-PA0
PA = Port Address
Valid Valid
PC = 0 PC = 1
Data
Out
SCLK
DX1, DX0
PA = PC3 + 1 = 1
PC3 = 3 LSB of PC
td13
td12
PA = PC3 = 0
interrupt timing
CLKOUT
tsu(INT)
tw(INT)
tf(INT)
INT
BIO timing
CLKOUT
BIO
tsu(IO)
tw(IO)
tf(IO)
TMS320C17, TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
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110
XF timing
42
1
XF
D15-D0
WE
PA2-PA0
CLKOUT
XF Valid
td(XF)
tv
td9
td7
3
td10
td8
td6
Legend:
1. Port Address Valid 3. Port Data Valid
2. Out Opcode Valid 4. Next Instruction Opcode Valid
external framing: transmit timing
83
21
8321
td(DX1-CL) td(DX2-CL)
th(DX)
tsu(FS)
tw(SCLKL)
tr(SCLK)
tw(SCLKH)
tf(SCLK)
tsu(FS)
DX1, DX0
FSX
SCLK
NOTES: A. Data valid on transmit output until SCLK rises.
B. The most significant bit is shifted first.
TMS320C17, TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
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POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 111
external framing: receive timing
832
tsu(DR)
1
8321
tsu(FS)
tsu(FS)
DR1, DR0
FSR
SCLK
th(DR)
NOTE: The most significant bit is shifted first.
internal framing: variable-data rate
td(CH-FR)
tsu(DR)
td(DX2-CL)
td(DX1-CL)
DX1, DX0
FR
83
2
8321
DR1, DR0
SCLK
td(CH-FR)
1
th(DR)
NOTE: The most significant bit is shifted first.
TMS320C17, TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
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112
internal framing: fixed-data rate
td(DX2-CL)
th(DR)
td(DX1-CL)
td(CH-FR)
td(CH-FR)
0
R
832
8321
0
K
1
tsu
(
DR
)
NOTE: The most significant bit is shifted first.
coprocessor timing: external write to coprocessor port
th(WR)
Valid
RBLE
DATA IN
WR
HI/LO
th(WR)
td(W-A)
tsu(HL) th(HL)
th(HL)
tsu(HL)
Valid
tw(WRL)
tw(WRL)
Only necessary for operation of 8-bit mode
constructing 16-bit data
tsu(WR)
tsu(WR)
TMS320C17, TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 113
coprocessor timing: external read to coprocessor port
ValidValid
ta(RD)
TBLF
DATA
OUT
RD
HI/LO
td(R-A)
th(RD)
ta(RD)
th(RD)
tsu(HL) th(HL)
th(HL)
tsu(HL) tw(RDL)
tw(RDL)
Only necessary for operation of 8-bit mode
constructing 16-bit data
TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
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EPROM PROGRAMMING
absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage range, VPP (see Note 6) –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only , and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 6: All voltage values are with respect to GND.
recommended operating conditions
MIN NOM MAX UNIT
VPP Supply voltage (see Note 11) 12.5 12.75 V
NOTE 11: VPP can be applied only to programming pins designed to accept VPP as an input. During programming the total supply current
is IPP + ICC.
electrical characteristics over specified temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
IPP1 VPP supply current VPP = VCC = 5.5 V 100 µA
IPP2 VPP supply current (during program pulse) VPP = 12.75 V, VCC = 5.5 V 30 50 mA
recommended timing requirements for programming, TA = 25°C, VCC = 6 V, VPP = 12.5 V,
(see Note 13)
MIN NOM MAX UNIT
tw(IPGM) Initial program pulse duration 0.95 1 1.05 ms
tw(FPGM) Final pulse duration 3.8 63 ms
tsu(A) Address setup time 2µs
tsu(E) E setup time 2µs
tsu(G) G setup time 2µs
tdis(G) Output disable time from G (see Note 15) 0 130‡ns
ten(G) Output enable time from G 150‡ns
tsu(D) Data setup time 2µs
tsu(VPP) VPP setup time 2µs
tsu(VCC) VCC setup time 2µs
th(A) Address hold time 0µs
th(D) Data hold time 2µs
†Values derived from characterization data and not tested.
NOTES: 13. For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V and VPP = 12.5 V ± 0.25 V during
programming.
15. Common test conditions apply for tdis(G) except during programming.
TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 115
PROGRAMMING THE TMS320E17/P17 EPROM CELL
Each ′E17/P17 devices include a 4K × 16-bit industry-standard EPROM cell for prototyping, early field testing,
and low-volume production. In conjunction with this EPROM, the TMS320C17 with a 4K-word masked ROM,
then, provides more migration paths for cost-effective production.
Note: The TMS320P17 is a one-time programmable (OTP) EPROM device.
EPROM adapter sockets are available that provide pin-to-pin conversions for programming any ′E17/P17
devices. One adapter socket (part number RTC/PGM320C-06), shown in Figure 19, converts a 40-pin DIP into
an equivalent 28-pin device. Another socket (part number RTC/PGM320C-06), not shown, permits 44- to 28-pin
conversion.
Figure 19. EPROM Adapter Socket (40-Pin to 28-Pin DIP Conversion)
Key features of the EPROM cell include the normal programming operation as well as verification. The EPROM
cell also includes a code protection feature that allows code to be protected against copyright violations.
The ′E17/P17 EPROM cell is programmed using the same family and device pinout codes as the TMS27C64
8K × 8-bit EPROM. The TMS27C64 EPROM series are unltraviolet-light erasable, electrically programmable,
read-only memories, fabricated using HVCMOS technology. They are pin-compatible with existing 28-pin
ROMs and EPROMs. These EPROMs operate from a single 5-V supply in the read mode; however, a 12.5-V
supply is needed for programming. All programming signals are TTL level. For programming outside the system,
existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random.
Figure 20 shows the wiring conversion to program the ′E17/P17 using the 28-pin pinout of the TMS27C64.
Table 8 on pin nomenclature provides a description of the TMS27C64 pins. The code to be programmed into
the device should be in serial mode. The ′E17/P17 devices use 13 address lines to address 4K-word memory
in byte format.
TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
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116
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q1
Q2
Q3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A1
A0(LSB)
VPP
RS
EPT
CLKIN
GND
Q1(LSB)
Q2
Q3
Q4
Q5
Q6
Q7
Q8(MSB)
40
39
38
37
36
35
34
33
32
30
29
28
27
26
25
24
23
22
21
31
A2
A3
A4
A5
A6
A7
A8
VCC
A9
A10
A11
(MSB)A12
E
G
PGM
TMS320E17/P17
TMS27C64
PINOUT TMS27C64
PINOUT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
PGM
EPT
A8
A9
A11
G
A10
E
Q8
Q7
Q6
Q5
Q4
3.9 kΩ
CAUTION
Although acceptable by some EPROM programmers, the signature mode cannot be used on any
TMS320E1x device. The signature mode will input a high-level voltage (12.5 Vdc) onto pin A9. Since this
pin is not designed for high voltage, the cell will be damaged. To prevent an accidental application of
voltage, Texas Instruments has inserted a 3.9 kΩ resistor between pin A9 of the TI programmer socket
and the programmer itself.
Pin Nomenclature (TMS320E17/P17)
NAME I/O DEFINITION
A0-A12 IOn-chip EPROM programming address lines
CLKIN IClock oscillator input
E I EPROM chip select
EPT IEPROM test mode select
G I EPROM read/verify select
GND I Ground
PGM I EPROM write/program select
Q1-Q8 I/O Data lines for byte-wide programming of on-chip 8K bytes of EPROM
RS IReset for initializing the device
VCC I5-V power supply
VPP I12.5-V power supply
Figure 20. TMS320E17/P17 EPROM Programming Conversion to TMS27C64 EPROM Pinout
TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 117
Table 8 shows the programming levels required for programming, verifying, reading, and protecting the EPROM cell.
Table 8. TMS320E17/P17 Programming Mode Levels
SIGNAL NAME TMS320E17 PIN TMS27C64 PIN PROGRAM VERIFY READ PROTECT VERIFY EPROM PROTECT
E 25 20 VIL VIL VIL VIL VIH
G 24 22 VIH PULSE PULSE VIL VIH
PGM 23 27 PULSE VIH VIH VIH VIH
VPP 3 1 VPP VPP VCC VCC + 1 VPP
VCC 30 28 VCC VCC VCC VCC + 1 VCC + 1
VSS 10 14 VSS VSS VSS VSS VSS
CLKIN 8 14 VSS VSS VSS VSS VSS
RS 4 14 VSS VSS VSS VSS VSS
EPT 5 26 VSS VSS VSS VPP VPP
Q1-Q8 11-18 11-13, 15-19 DIN QOUT QOUT Q8=RBIT Q8=PULSE
A0-A3 2, 1, 40, 39 10-7 ADDR ADDR ADDR X X
A4 38 6 ADDR ADDR ADDR X VIH
A5 37 5 ADDR ADDR ADDR X X
A6 36 4 ADDR ADDR ADDR VIL X
A7-A9 35, 34, 29 3, 25, 24 ADDR ADDR ADDR X X
A10-A12 28-26 21, 23, 2 ADDR ADDR ADDR X X
Legend:
VIH = TTL high level; VIL = TTL low level; ADDR = byte address bit
VPP = 12.5 V ± 0.25 V; VCC = 5 V ± 0.25 V; X = don’t care
PULSE = low-going TTL level pulse; DIN = byte to be programmed at ADDR
QOUT = byte stored at ADDR; RBIT = ROM protect bit.
programming
Since every memory bit in the cell is a logic 1, the programming operation reprograms certain bits to 0. Once
programmed, these bits can be erased only by using ultraviolet light. The correct byte is placed on the data bus
with VPP set to the 12.5 V level. The PGM pin is then pulsed low to program in the zeroes.
erasure
Before programming, the device must be erased by exposing it to ultraviolet light. The recommended minimum
exposure dose (UV-intensity × exposure-time) is 15 W•s/cm2. A typical 12-mW/cm2, filterless UV lamp will erase
the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After
exposure, all bits are in the high state.
verify/read
T o verify correct programming, the EPROM cell can be read using either the verify or read line definitions shown
in Table 8 assuming the inhibit bit has not been programmed.
program inhibit
Programming may be inhibited by maintaining a high level input on the E pin or PGM pin.
read The EPROM contents may be read independent of the programming cycle, provided the RBIT (ROM protect
bit) has not been programmed. The read is accomplished by setting E to zero and pulsing G low . The contents
of the EPROM location selected by the value on the address inputs appear on Q8-Q1.
TMS320E17, TMS320P17
DIGITAL SIGNAL PROCESSORS
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POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
118
output disable
During the EPROM programming process, the EPROM data outputs may be disabled, if desired, by establishing
the output disable state. This state is selected by setting G and E pins high. While output disable is selected,
Q8-Q1are placed in the high-impedance state.
EPROM protection
To protect the proprietary algorithms existing in the code programmed on-chip, the ability to read or verify code
from external accesses can be completely disabled. Programming the RBIT disables external access of the
EPROM cell, making it impossible to access the code resident in the EPROM cell. The only way to remove this
protection is to erase the entire EPROM cell, thus removing the proprietary information. The signal requirements
for programming this bit are shown in Table 8. The cell can be determined as protected by verifying the
programming of the RBIT shown in the table.
standard programming procedure
Before programming, the device must first be completely erased. The device can then be programmed with the
correct code. It is advisable to program unused sections with zeroes as a further security measure. After the
programming is complete, the code programmed into the cell should be verified. If the cell passes verification,
the next step is to program the ROM protect bit (RBIT). Once the RBIT programming is verified, an opaque label
should be placed over the window to protect the EPROM cell from inadvertent erasure by ambient light. At this
point, the programming is complete, and the device is ready to be placed into its destination circuit.
program cycle timing
A12-A0
Q8-Q1
VPP
VCC
E
PGM
G
Program Verify
Address Stable Address N+1
Data In Stable Data Out
Valid
tsu(A) th(A)
tsu(D)
tsu(VPP)
tdis(G)
tsu(VCC)
tsu(E) th(D)
tw(IPGM)
tw(FPGM)
tsu(G)
ten(G)
VIH
VIL
VIH/VOH
VIL/VOL
VPP
VCC
VCC+1
VCC
VIH
VIL
VIH
VIL
VIH
VIL
HI-Z
High-level input voltageVIH
Operating free-air temperatureTA
VOH High-level output voltage
IOZ Of f-state ouput current
II Input current
CiInput capacitance
CoOutput capacitance f = 1 MHz, All other pins 0 V
µA
µA
pF
pF
TMS320LC17
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 119
absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 6) –0.3 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range –0.3 V to VCC to 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range –0.3 V to VCC to 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation 75 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Air temperature range above operating devices: L version 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A version –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –55°C to +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only , and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 6: All voltage values are with respect to VSS.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 3.0 3.3 3.6 V
VSS Supply voltage 0 V
All inputs except CLKIN 2.0 V
CLKIN 2.5 V
VIL Low-level input voltage All inputs 0.55 V
IOH High-level output current (all outputs) –300 µA
IOL Low-level output current (all outputs) 1.5 mA
L version 070°C
A version –40 85 °C
electrical characteristics over specified temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP§MAX UNIT
IOH = MAX 2.0 V
IOH = 20 µA (see Note 19) VCC–0.4V
VOL Low-level output voltage IOL = MAX 0.5 V
VCC = MAX, V
O = VCC 20
VO = VSS –20
VI = VSS to VCC, All inputs except CLKIN ±20
VI = VSS to VCC, CLKIN ±50
Data bus 25
All others 15
Data bus 25
All others 10
§All typical values are at VCC = 3.3 V, TA = 25°C.
Values derived from characterization data and not tested.
NOTE 19: This voltage specification is included for interface to HC logic. All other timing parameters defined in this data sheet are specified for
the test load circuit shown in Figure 2.
TA = – 40°C to 85°C
TMS320LC17
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
120
123456
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
EXINT
RS
MC
PA0/HI/LO
PA1/RBLE
PA2/TBLF
FSR
FSX
FR
DX1
D13/LD13
D14/LD14
D15/LD15
D7/LD7
D6/LD6
D5/LD5
D4/LD4
D3/LD3
D2/LD2
SS
VSS
V
D1/LD1
CLKOUT
X1
X2/CLKIN
BIO
NC
VSS
D8/LD8
D9/LD9
D10/LD10
D11/LD11
D12/LD12
DX0
SLCK
DR1
DEN/RD
WE/WR
VCC
DR0
XF
MC/PM
D0/LD0
VSS
TMS320LC17
FN PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PA1/RBLE
PA0/HI/LO
MC
RS
EXINT
CLKOUT
X1
X2/CLKIN
BIO
VSS
D8/LD8
D9/LD9
D10/LD10
D11/LD11
D12/LD12
D13/LD13
D14/LD14
D15/LD15
D7/LD7
D6/LD6
PA2/TBLF
FSR
FSX
FR
DX1
DX0
SCLK
DR1
DEN/RD
WE/WR
VCC
DR0
XF
MC/PM
D0/LD0
D1/LD1
D2/LD2
D3/LD3
D4/LD4
D5/LD5
TMS320LC17
N PACKAGE
(TOP VIEW)
electrical characteristics over specified ranges (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
ICC‡ Supply current f = 14.4 MHz, VCC = 3.6 V, TA = 0°C to 70°C 15 20 mA
†All typical values are at TA = 70°C and are used for thermal resistance calculations.
‡ICC characteristics are inversely proportional to temperature. For ICC dependence on frequency, see Figure 3.
clock characteristics and timing
The TMS320LC17 can use either its internal oscillator or an external frequency source for a clock.
internal clock option
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency
of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and
parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW , and be specified
at a load capacitance of 20 pF.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
Crystal frequency fx4.0 14.4 MHz
C1, C2 10 pF
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
TMS320LC17
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 121
external clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. The external frequency injected must conform to the specifications listed in the table below.
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
tc(C) CLKOUT cycle time§277.78 1000 ns
tr(C) CLKOUT rise time 10ns
tf(C) CLKOUT fall time 8ns
tw(CL) Pulse duration, CLKOUT low 131 ns
tw(CH) Pulse duration, CLKOUT high 129 ns
td(MCC) Delay time CLKIN↑ to CLKOUT↓25 75 ns
§tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used).
Values derived from characterization data and not tested
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tc(MC) Master clock cycle time 69.5 150 ns
tr(MC) Rise time, master clock input 5† 10†ns
tf(MC) Fall time, master clock input 5† 10†ns
tw(MCP) Pulse duration, master clock 0.4tc(MC)†0.6tc(MC)†ns
tw(MCL) Pulse duration, master clock low at tc(MC) min 30 ns
tw(MCH) Pulse duration, master clock high at tc(MC) min 30 ns
†Values derived from characterization data and not tested.
MEMORY AND PERIPHERAL INTERFACE TIMING
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN MAX UNIT
td1 Delay time CLKOUT↓ to address bus valid 10†100 n
s
td4 Delay time CLKOUT↓ to DEN↓1/4 tc(C)–5†1/4 tc(C)+25 ns
td5 Delay time CLKOUT↓ to DEN↑–10†30 ns
td6 Delay time CLKOUT↓ to WE↓1/2 tc(C)–5†1/2 tc(C)+25 ns
td7 Delay time CLKOUT↓ to WE↑–10†30 ns
td8 Delay time CLKOUT↓ to data bus OUT valid 1/4 tc(C)+130 ns
td9 T ime after CLKOUT↓that data bus starts to be driven 1/4 tc(C)–5†ns
td10 T ime after CLKOUT↓that data bus stops being driven 1/4 tc(C)+90 ns
tvData bus OUT valid after CLKOUT↓1/4 tc(C)–10 ns
th(A-WMD) Address hold time after WE↑, MEN↑, or DEN↑ (see Note 14) 0†ns
tsu(A-MD) Address bus setup time or DEN↓0 ns
†Values derived from characterization data and not tested.
NOTE 14: Address bus will be valid upon WE↑, MEN↑, or DEN↑.
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
TMS320LC17
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
122
timing requirements over recommended operating conditions
TEST CONDITIONS MIN NOM MAX UNIT
tsu(D) Setup time data bus valid prior to CLKOUT↓80 ns
th(D) Hold time data bus held valid after CLKOUT↓ (see Note 9) 0 ns
NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓.
RESET (RS) TIMING
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
td11 Delay time DEN↑, WE↑, and MEN↑ from RS 1/2tc(C)+75 ns
tdis(R) Data bus disable time after RS 1/4t c(C)+75 ns
td12 Delay time from RS↓to high-impedance SCLK 200†ns
td13 Delay time from RS↓to high-impedance DX1, DX0 200†ns
†These values were derived from characterization data and not tested.
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tsu(R) Reset (RS) setup time prior to CLKOUT (see Note 10) 85 ns
tw(R) RS pulse duration 5tc(C) ns
NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.
INTERRUPT (EXINT) TIMING
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tf(INT) Fall time EXINT 15 ns
tw(INT) Pulse duration EXINT tc(C) ns
tsu(INT) Setup time EXINT↓ before CLKOUT↓85 ns
I/O (BIO) TIMING
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tf(IO) Fall time BIO 15 ns
tw(IO) Pulse duration BIO tc(C) ns
tsu(IO) Setup time BIO↓ before CLKOUT↓85 ns
RL = 825 Ω,
CL = 100 pF,
(see Figure 2)
TMS320LC17
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 123
I/O (BIO) TIMING
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
td(XF) Delay time CLKOUT↓ to valid XF 5†115 ns
†Values derived from characterization data and not tested.
SERIAL PORT TIMING
switching characteristics over recommended operating conditions
MIN NOM MAX UNIT
td(CH-FR) Internal framing (FR) delay from SCLK rising edge 120 ns
td(DX1-CL) DX bit 1 valid before SCLK falling edge 20 ns
td(DX2-CL) DX bit 2 valid before SCLK falling edge 20 ns
th(DX) DX hold time after SCLK falling edge tc(SCLK)/2 ns
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
tc(SCLK) Serial port clock (SCLK) cycle time‡555 8000 ns
tf(SCLK) Serial port clock (SCLK) fall time 30†ns
tr(SCLK) Serial port clock (SCLK) rise time 30†ns
tw(SCLK) Serial port clock (SCLK) low, pulse duration§250 4400 ns
tw(SCLKH) Serial port clock (SCLK) high, pulse duration§250 4400 ns
tsu(FS) FSX/FSR setup time before SCLK falling edge 130 ns
tsu(DR) DR setup time before SCLK falling edge 20 ns
th(DR) DR hold time after SCLK falling edge 20 ns
†Values derived from characterization data and not tested.
‡Minimum cycle time is 2tc(C) where tc(C) is CLKOUT cycle time.
§The duty cycle of the serial port clock must be within 45 to 55%.
TMS320LC17
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
124
COPROCESSOR INTERFACE TIMING
switching characteristics over recommended operating conditions
MIN NOM MAX UNIT
td(R-A) RD low to TBLF high 150 ns
td(W-A) WR low to RBLF high 150 ns
ta(RD) RD low to data valid 150 ns
th(RD) Data hold time after RD high 25
timing requirements over recommended operating conditions
MIN NOM MAX UNIT
th(HL) HI/RD hold time after WR or RD high 25 ns
tsu(HL) HI/RD setup time prior to WR or RD low 40 ns
tsu(WR) Data setup time prior to WR high 50 ns
th(WR) Data hold time after WR high 35 ns
tw(RDL) Pulse duration, RD low 150 ns
tw(WRL) Pulse duration, WR low 150 ns
TMS320LC17
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 125
clock timing
tr(MC)
tc(MC)
tw(MCH) tw(MCP)†
tf(MC)
tw(MCL)
td(MCC)†tw(CH)
tw(CL)
tr(C)
tc(C)
tf(C)
X2/CLKIN
CLKOUT
†td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform.
IN instruction timing
CLKOUT
MEN
PA2-PA0
DEN
D15-D0
tsu(D)
th(D)
tsu(A-MD)
td5
td4
12
345
678
Legend:
1. IN Instruction Prefetch 5. Address Bus Valid
2. Next Instruction Prefetch 6. Instruction Valid
3. Address Bus Valid 7. Data Input Valid
4. Peripheral Address Valid 8. Instruction Valid
TMS320LC17
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
126
OUT instruction timing
CLKOUT
MEN
PA2-PA0
WE
D15-D0
12
34 5
678
td6 td7
td8 tv
td9 td10
Legend:
1. OUT Instruction Prefetch 5. Address Bus Valid
2. Next Instruction Prefetch 6. Instruction Valid
3. Address Bus Valid 7. Data Output Valid
4. Peripheral Address Valid 8. Instruction Valid
reset timing
tsu(R) tsu(R)
tw(R)
tdis(R) td11
CLKOUT
RS
DEN
WE
D15-D0
PA2-PA0
PA = Port Address
Valid Valid
PC = 0 PC = 1
Data
Out
SCLK
DX1, DX0
PA = PC3 + 1 = 1
PC3 = 3 LSB of PC
td13
td12
PA = PC3 = 0
TMS320LC17
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 127
interrupt timing
CLKOUT
tsu(INT)
tw(INT)
tf(INT)
INT
BIO timing
CLKOUT
BIO
tsu(IO)
tw(IO)
tf(IO)
XF timing
42
1
XF
D15-D0
WE
PA2-PA0
CLKOUT
XF Valid
td(XF)
tv
td9
td7
3
td10
td8
td6
Legend:
1. Port Address Valid 3. Port Data Valid
2. Out Opcode Valid 4. Next Instruction Opcode Valid
TMS320LC17
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
128
external framing: transmit timing
83
21
8321
td(DX1-CL) td(DX2-CL)
th(DX)
tsu(FS)
tw(SCLKL)
tr(SCLK)
tw(SCLKH)
tf(SCLK)
tsu(FS)
DX1, DX0
FSX
SCLK
NOTES: A. Data valid on transmit output until SCLK rises.
B. The most significant bit is shifted first.
external framing: receive timing
832
tsu(DR)
1
8321
tsu(FS)
tsu(FS)
DR1, DR0
FSR
SCLK
th(DR)
NOTE B: The most significant bit is shifted first.
TMS320LC17
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 129
internal framing: variable-data rate
td(CH-FR)
tsu(DR)
td(DX2-CL)
td(DX1-CL)
DX1, DX0
FR
83
2
8321
DR1, DR0
SCLK
td(CH-FR)
1
th(DX)
th(DR)
NOTE: The most significant bit is shifted first.
internal framing: fixed-data rate
td(DX2-CL)
th(DR)
td(DX1-CL)
td(CH-FR)
td(CH-FR)
DX1, DX0
FR
83
2
8321
DR1, DR0
SCLK
1
th(DX)
tsu(DR)
NOTE: The most significant bit is shifted first.
TMS320LC17
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
130
coprocessor timing: external write to coprocessor port
th(WR)
ValidDATA IN
WR
HI/LO
th(WR)
tsu(HL) th(HL)
th(HL)
tsu(HL)
Valid
tw(WRL)
tw(WRL)
tsu(WR)
tsu(WR)
RBLE
td(W-A)
Only necessary for operation of 8-bit mode
constructing 16-bit data
coprocessor timing: external read to coprocessor port
ValidValid
ta(RD)
TBLF
DATA
OUT
RD
HI/LO
td(R-A)
th(RD)
ta(RD)
th(RD)
tsu(HL) th(HL)
th(HL)
tsu(HL) tw(RDL)
tw(RDL)
Only necessary for operation of 8-bit mode
constructing 16-bit data
DEVICE
TMS320C1x
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 131
THERMAL RESISTANCE CHARACTERISTICS
Commercial Devices
Device/Package Thermal Resistance
Junction To Case
RθJC (°C/W)
PDIP (N) CDIP (JD) PLCC (FN) CLCC (FZ) QFP (PG)
TMS320C10 26 17
TMS320C10-14 26 17
TMS320C10-25 26 17
TMS320C14 11
TMS320E14 8
TMS320P14 11
TMS320C15 26 17
TMS320C15-25 26 17
TMS320E15 8 8
TMS320E15-25 8 8
TMS320LC15 26 17
TMS320P15 13 13
TMS320C16 25
TMS320C17 26 17
TMS320E17 8 8
TMS320LC17 26 17
TMS320P17 13 13
DEVICE
TMS320C1x
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
132
THERMAL RESISTANCE CHARACTERISTICS
Commercial Devices
Device/Package Thermal Resistance
Junction To Ambient
RθJA (°C/W)
PDIP (N) CDIP (JD) PLCC (FN) CLCC (FZ) QFP (PG)
TMS320C10 84 60
TMS320C10-14 84 60
TMS320C10-25 84 60
TMS320C14 46
TMS320E14 49
TMS320P14 46
TMS320C15 84 60
TMS320C15-25 84 60
TMS320E15 40 64
TMS320E15-25 40 64
TMS320LC15 84 60
TMS320P15 40 55
TMS320C16 120
TMS320C17 84 60
TMS320E17 40 64
TMS320LC17 84 60
TMS320P17 40 55
TMS320C1x
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 133
MECHANICAL DATA
40-pin plastic dual-in-line package
Either or Both
Index Marks
53,1 (2.090) Max
5,08
(0.200)
Max
2,92 (0.115)
Min
1,52
(0.060)
Nom
2,54 (0.100) T.P.
Pin Spacing
(See Note A)
0,84
(0.033)
Min
0,457 ± 0,076
(0.018 ± 0.003)
Seating Plane
40 21
211
0,51
(0.020)
Min
2,41 (0.095)
1,40 (0.055)
15,24
"
0,25
(0.600
"
0.010)
C
L
C
L
105°
90°
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
0,28 ± 0,08
(0.011 ± 0.003)
NOTE A: Each pin centerline is located within 0,254 (0.010) of its true longitudinal position.
40-pin windowed ceramic dual-in-line package
123456789
10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
C
L
C
L
51,31 (2.020) Max
Index Dot
Seating
Plane
4,70 (0.185)
Max
105°
90°2,54 (0.100) T.P.
Pin Spacing
(see Note A)
0,508 (0.020)
Min
1,27
"
0,508
(0.050
"
0.020)
0,457
"
0,076
(0.018
"
0.003)
1,27
"
0,254
(0.050
"
0.010) 3,81
"
0,762
(0.150
"
0.030)
15,24
"
0,25
(0.600
"
0.010)
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
15,0 (0.590)
Nom
0,25(0.010)
Nom
NOTE A: Each pin centerline is located within 0,254 (0.010) of its true longitudinal position.
TMS320C1x
DIGITAL SIGNAL PROCESSORS
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POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
134
44-lead plastic chip carrier (FN suffix)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
16,66 (0.656)
16,51 (0.650) 17,65 (0.695)
17,40 (0.685)
16,66 (0.656)
16,51 (0.650)
17,65 (0.695)
17,40 (0.685)
Index
Dot
1,14 (0.045) × 45° Typ
4,57 (0.180)
4,19 (0.165)
3,05 (0.120)
2,29 (0.090)
0,51
(0.020)
Min
0,533 (0.021)
0,330 (0.013)
16,00 (0.630)
14,99 (0.590)
1,27
(0.050)
Typ
TMS320C1x
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 135
64-pin quad flat pack (PG suffix) (TMS320C16)
0,1 (0.004) Min
0°-10°
0,35 (0.0014) Typ
1,0 (0.039) Typ
64 20
3252
51 33
191
3,10 (0.122) Max
20,0 (0.787) Nom
14,0
(0.552)
Nom
18,0 (0.709)
17,2 (0.677)
24,0 (0.945)
23,2 (0.913)
0,20 (0.008)
0,10 (0.004)
1,0 (0.040)
0,6 (0.024)
C
LC
L
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
Lead Detail
0,64
(0.025)
Min
1,52 (0.060) Min
Seating Plane
0,25 (0.010) R Max
in 3 places
ÏÏ
ÏÏ
24,33 (0.956)
24,13 (0.950)
(see Note A)
24,33 (0.956)
24,13 (0.950)
(see Note A)
25,27 (0.995)
25,02 (0.985)
0,81 (0.032)
0,66 (0.026)
23,62 (0.930)
23,11 (0.910)
(At Seating Plane)
4,50 (0.177)
4,24 (0.167)
2,79 (0.110)
2,41 (0.095)
1,35 (0.053)
1,19 (0.047)
45
0,94 (0.037)
0,69 (0.027) R
1,27 (0.050) T.P.
(see Note B)
25,27 (0.995)
25,02 (0.985)
0,51 (0.020)
0,36 (0.014)
°
1,22 (0.048)
1,07 (0.042)
45°
NOTES: A. Centerline of center pin, each side, is within 0,10 (0.004) of package centerline as determined by this deminsion.
B. Location of each pin is within 0,27 (0.005) of true position with respect to center pin on each side.
TMS320C1x
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
136
MECHANICAL DATA
68-lead plastic chip carrier package (FN suffix)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
0,51 (0.020)
0,36 (0.014)
0,81 (0.032)
0,66 (0.026)
0,64 (0.025) R Max
Typ, 3 Places
3,55 (0.140)
3,05 (0.120)
4,57 (0.180)
3,94 (0.155)
B
A
A
B
C
(at Seating
Plane)
1.02 (0.040) × 45°1,27 (0.05) Typ
(see Note B)
1.016 (0.040) Min
(see Note A)
3,05 (0.120)
2,29 (0.090)
Seating Plane
(see Note C)
Optional
EPROM Window
TMS320C1x
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001 137
MECHANICAL DATA
68-lead ceramic chip carrier package (FZ suffix)
A B C
MIN MAX MIN MAX MIN MAX
M0-087AA 28 12,32
(0.485) 12,57
(0.495) 10,92
(0.430) 11,56
(0.455) 10,41
(0.410) 10.92
(0.430)
M0-087AB 44 17,40
(0.685) 17,65
(0.695) 16,00
(0.630) 16,64
(0.655) 15,49
0.610) 16,00
(0.630)
M0-087AD 68 25,02
(0.985) 25,27
(0.995) 23,62
(0.930) 24,26
(0.955) 23.11
(0.910) 23,62
(0.930)
NOTES: A. Centerline of center pin each side is within 0,10 (0.004) of package centerline as determined by dimension B.
B. Location of each pin is within 0,27 (0.005) of true position with respect to center pin on each side.
C. The lead contact points are planar within 0,15 (0.006)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TMS320C1x
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JUL Y 1991
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77001
138
INDEX
accumulator/ALU 5. . . . . . . . . . . . . . . . . . . . . .
architecture (TMS320C1x family) 5, 6. . . . . .
TMS320C14 32. . . . . . . . . . . . . . . . . . . . . . .
TMS320C17 96. . . . . . . . . . . . . . . . . . . . . . .
functional block diagram
TMS320C10 13. . . . . . . . . . . . . . . . . . . . . . .
TMS320C14 32. . . . . . . . . . . . . . . . . . . . . . .
TMS320C15 53. . . . . . . . . . . . . . . . . . . . . . .
TMS320C16 82. . . . . . . . . . . . . . . . . . . . . . .
TMS320C17 95. . . . . . . . . . . . . . . . . . . . . . .
codec interface
TMS320C17 3, 6, 96 – 98. . . . . . . . . . . . . .
companding hardware
TMS320C17 3, 96, 97. . . . . . . . . . . . . . . . . .
control register
TMS320C17 97. . . . . . . . . . . . . . . . . . . . . . .
coprocessor interface 98. . . . . . . . . . . . . . . . .
data memory 2, 3, 5, 33. . . . . . . . . . . . . . . . . .
description
TMS320C10 2, 3, 11. . . . . . . . . . . . . . . . . . .
TMS320C14 2, 3, 28, 29. . . . . . . . . . . . . . .
TMS320C15 2, 3, 52. . . . . . . . . . . . . . . . . . .
TMS320LC15 2, 3, 70. . . . . . . . . . . . . . . . . .
TMS320C16 2, 3, 79. . . . . . . . . . . . . . . . . . .
TMS320C17 2, 3, 95. . . . . . . . . . . . . . . . . . .
TMS320LC17 2, 3, 120. . . . . . . . . . . . . . . . .
electrical specifications
TMS320C10 14. . . . . . . . . . . . . . . . . . . . . . .
TMS320C14 35. . . . . . . . . . . . . . . . . . . . . . .
TMS320C15 55. . . . . . . . . . . . . . . . . . . . . . .
TMS320LC15 69. . . . . . . . . . . . . . . . . . . . . .
TMS320C16 83. . . . . . . . . . . . . . . . . . . . . . .
TMS320C17 102. . . . . . . . . . . . . . . . . . . . . .
TMS320LC17 120. . . . . . . . . . . . . . . . . . . . .
EPROM programming
TMS320E14/P14 47. . . . . . . . . . . . . . . . . . .
TMS320E15/P15 65. . . . . . . . . . . . . . . . . . .
TMS320E17/P17 114. . . . . . . . . . . . . . . . . .
framing pulses
TMS320C17/LC17/E17/P17 97. . . . . . . . .
instruction set 7. . . . . . . . . . . . . . . . . . . . . . . . .
interrupts 6, 33. . . . . . . . . . . . . . . . . . . . . . . . . .
interfacing to SRAM/EPROM/peripherals
TMS320C16 90. . . . . . . . . . . . . . . . . . . . . . .
I/O channels 2, 3, 6, 28, 79, 95. . . . . . . . . . . .
key features (TMS320C1x) 1. . . . . . . . . . . . . .
TMS320C10 11. . . . . . . . . . . . . . . . . . . . . . .
TMS320C14 28. . . . . . . . . . . . . . . . . . . . . . .
TMS320C15 52. . . . . . . . . . . . . . . . . . . . . . .
TMS320C16 79. . . . . . . . . . . . . . . . . . . . . . .
TMS320C17 95. . . . . . . . . . . . . . . . . . . . . . .
mechanical data 133 – 137. . . . . . . . . . . . . . .
memory (TMS320C1x) 2, 3, 5. . . . . . . . . . . . .
TMS320C10 11. . . . . . . . . . . . . . . . . . . . . . .
TMS320C14 28. . . . . . . . . . . . . . . . . . . . . . .
TMS320C15 52. . . . . . . . . . . . . . . . . . . . . . .
TMS320C16 79. . . . . . . . . . . . . . . . . . . . . . .
TMS320C17 95. . . . . . . . . . . . . . . . . . . . . . .
microcomputer/microprocessor mode 5, 33. .
microcomputer/coprocessor 7, 98. . . . . . . . . .
multiplier 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
package types (TMS320C1x) 4. . . . . . . . . . . .
pinout/nomenclature
TMS320C10 4, 11. . . . . . . . . . . . . . . . . . . . .
TMS320C14 4, 28. . . . . . . . . . . . . . . . . . . . .
TMS320C15 4, 52. . . . . . . . . . . . . . . . . . . . .
TMS320LC15 4, 70. . . . . . . . . . . . . . . . . . . .
TMS320C16 4, 79. . . . . . . . . . . . . . . . . . . . .
TMS320C17 4, 95. . . . . . . . . . . . . . . . . . . . .
TMS320LC17 4, 120. . . . . . . . . . . . . . . . . . .
serial port
TMS320C17/E17 6, 96. . . . . . . . . . . . . . . . .
shifters 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
subroutines 6. . . . . . . . . . . . . . . . . . . . . . . . . . .
terminal functions
TMS320C10 12. . . . . . . . . . . . . . . . . . . . . . .
TMS320C14 30. . . . . . . . . . . . . . . . . . . . . . .
TMS320C15 54. . . . . . . . . . . . . . . . . . . . . . .
TMS320C16 80. . . . . . . . . . . . . . . . . . . . . . .
TMS320C17 100. . . . . . . . . . . . . . . . . . . . . .
thermal data 27, 131, 132. . . . . . . . . . . . . . . . .
timing diagrams
TMS320C10 23 – 26. . . . . . . . . . . . . . . . . . .
TMS320C14 41 – 46, 51. . . . . . . . . . . . . . .
TMS320C15 60 – 63, 68. . . . . . . . . . . . . . .
TMS320LC15 75 – 78. . . . . . . . . . . . . . . . . .
TMS320C16 86 – 91. . . . . . . . . . . . . . . . . . .
TMS320C17 107 – 113, 118. . . . . . . . . . . .
TMS320LC17 125 – 130. . . . . . . . . . . . . . .
PACKAGE OPTION ADDENDUM
www.ti.com 2-Apr-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-8763308QA OBSOLETE CDIP SB JD 40 TBD Call TI N / A for Pkg Type
5962-8763308YA OBSOLETE JLCC FJ 44 TBD Call TI Call TI
SMJ320C15-25FJM OBSOLETE JLCC FJ 44 TBD Call TI Call TI
SMJ320C15-25JDM OBSOLETE CDIP SB JD 40 TBD Call TI N / A for Pkg Type
TMS320C10FNA OBSOLETE 44 TBD Call TI Call TI
TMS320C10FNL OBSOLETE PLCC FN 44 TBD Call TI Call TI
TMS320C10FNL25 NRND PLCC FN 44 26 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TMS320C10FNLR25 OBSOLETE PLCC FN 44 TBD Call TI Call TI
TMS320C10NA OBSOLETE PDIP N 40 TBD Call TI Call TI
TMS320C10NL NRND PDIP N 40 TBD Call TI Call TI
TMS320C10NL-25 NRND PDIP N 40 TBD Call TI Call TI
TMS320C10NL25 OBSOLETE 0 TBD Call TI Call TI
TMS320C14FNL OBSOLETE PLCC FN 68 TBD Call TI Call TI
TMS320C14FNLR OBSOLETE PLCC FN 68 TBD Call TI Call TI
TMS320C15FNA OBSOLETE PLCC FN 44 TBD Call TI Call TI
TMS320C15FNL OBSOLETE PLCC FN 44 TBD Call TI Call TI
TMS320C15FNL25 OBSOLETE PLCC FN 44 TBD Call TI Call TI
TMS320C15NA OBSOLETE PDIP N 40 TBD Call TI Call TI
TMS320C15NL OBSOLETE PDIP N 40 TBD Call TI Call TI
TMS320C15NL-25 OBSOLETE PDIP N 40 TBD Call TI Call TI
TMS320C15NL25 OBSOLETE PLCC NL 40 TBD Call TI Call TI
TMS320C15PEL OBSOLETE QFP PE 44 TBD Call TI Call TI
TMS320C16PGL OBSOLETE QFP PG 64 TBD Call TI Call TI
TMS320C17FNL OBSOLETE PLCC FN 44 TBD Call TI Call TI
TMS320C17NL OBSOLETE PDIP N 40 TBD Call TI Call TI
TMS320LC15FNL OBSOLETE PLCC FN 44 TBD Call TI Call TI
TMS320LC15NL OBSOLETE PDIP N 40 TBD Call TI Call TI
TMS320P14FNL OBSOLETE PLCC FN 68 TBD Call TI Call TI
TMS320P14FNLG4 OBSOLETE PLCC FN 68 TBD Call TI Call TI
PACKAGE OPTION ADDENDUM
www.ti.com 2-Apr-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TMS320P15FNL OBSOLETE PLCC FN 44 TBD Call TI Call TI
TMS320P15FNL25 OBSOLETE PLCC FN 44 TBD Call TI Call TI
TMS320P15NA OBSOLETE PDIP N 40 TBD Call TI Call TI
TMS320P15NL OBSOLETE PDIP N 40 TBD Call TI Call TI
TMS320P15NL25 OBSOLETE PDIP N 40 TBD Call TI Call TI
TMS320P17FNA OBSOLETE PLCC FN 44 TBD Call TI Call TI
TMS320P17FNL OBSOLETE PLCC FN 44 TBD Call TI Call TI
TMS320P17FNLR OBSOLETE PLCC FN 44 TBD Call TI Call TI
TMS320P17NL OBSOLETE PDIP N 40 TBD Call TI Call TI
TMS320SS16NL OBSOLETE PDIP N 40 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 2-Apr-2012
Addendum-Page 3
OTHER QUALIFIED VERSIONS OF SMJ320C15, TMS320C15 :
•Catalog: TMS320C15
•Military: SMJ320C15
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
MECHANICAL DATA
MCDI005 – JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JD (R-CDIP-T**) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
24 PINS SHOWN
0.590 (14,99)
0.620 (15,75)
TYP
0.590 (15,00)
52
0.012 (0,30)
0.008 (0,20)
48
2.435
40
2.050
0.020 (0,51) MIN
0.125 (3,18) MIN
(61,85)(52,07) (67,31)
2.650
4040087/B 04/95
Seating Plane
A
13
12
0.045 (1,14)
0.065 (1,65)
24
1
0.075 (1,91) MAX (4 Places)
2824
PINS **
0.021 (0,53)
0.015 (0,38)
1.250
(31,75)
DIM
A MAX
0.175 (4,45)
0.140 (3,56)
(36,83)
1.450
0.100 (2,54) 0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package is hermetically sealed with a metal lid.
D. The terminals are gold-plated.
MECHANICAL DATA
MJLC003A – FEBRUARY 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FZ (S-CQCC-J**) J-LEADED CERAMIC CHIP CARRIER
4040219/B 03/95
0.180 (4,57)
0.140 (3,55)
C
0.020 (0,51)
0.032 (0,81)
A B
A
B
0.025 (0,64) R TYP
0.026 (0,66)
0.120 (3,05)
0.155 (3,94)
0.014 (0,36)
0.120 (3,05)
0.040 (1,02) MIN
0.090 (2,29)
0.040 (1,02)
45°
A
MIN MAX
0.485
(12,32) (12,57)
0.495 0.455
(11,56)(10,92)
0.430
MAXMIN
BC
MIN MAX
0.410
(10,41) (10,92)
0.430
0.6300.6100.630 0.6550.6950.685 (16,00)(15,49)(16,00) (16,64)(17,65)(17,40)
0.7400.6800.730 0.7650.7950.785 (18,79)(17,28)(18,54) (19,43)(20,19)(19,94)
PINS**
28
44
52
NO. OFJEDEC
MO-087AC
MO-087AB
MO-087AA
OUTLINE
28 LEAD SHOWN
Seating Plane
(at Seating
Plane)
1426
25
19
18
12
11
50.050 (1,27)
0.9300.9100.930 0.9550.9950.985 (23,62)(23,11)(23,62) (24,26)(25,27)(25,02)
68MO-087AD
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
MECHANICAL DATA
MPDI008 – OCTOBER 1994
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE
24 PIN SHOWN
12
Seating Plane
0.560 (14,22)
0.520 (13,21)
13
0.610 (15,49)
0.590 (14,99)
524840
0.125 (3,18) MIN
2.390
(60,71)
(62,23)(53,09)
(51,82)
2.040
2.090 2.450 2.650
(67,31)
(65,79)
2.590
0.010 (0,25) NOM
4040053/B 04/95
A
0.060 (1,52) TYP
1
24
322824
1.230
(31,24)
(32,26) (36,83)
(35,81)
1.410
1.450
1.270
PINS **
DIM
0.015 (0,38)
0.021 (0,53)
A MIN
A MAX 1.650
(41,91)
(40,89)
1.610
0.020 (0,51) MIN
0.200 (5,08) MAX
0.100 (2,54)
M
0.010 (0,25) 0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-011
D. Falls within JEDEC MS-015 (32 pin only)
MECHANICAL DATA
MPLC004A – OCTOBER 1994
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
4040005/B 03/95
20 PIN SHOWN
0.026 (0,66)
0.032 (0,81)
D2/E2
0.020 (0,51) MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D2/E2
0.013 (0,33)
0.021 (0,53)
Seating Plane
MAX
D2/E2
0.219 (5,56)
0.169 (4,29)
0.319 (8,10)
0.469 (11,91)
0.569 (14,45)
0.369 (9,37)
MAX
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.008 (0,20) NOM
1.158 (29,41)
0.958 (24,33)
0.756 (19,20)
0.191 (4,85)
0.141 (3,58)
MIN
0.441 (11,20)
0.541 (13,74)
0.291 (7,39)
0.341 (8,66)
18
19
14
13
D
D1
13
9
E1E
4
8
MINMAXMIN
PINS
**
20
28
44
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
52
68
84 1.185 (30,10)
0.985 (25,02)
0.785 (19,94)
D/E
0.395 (10,03)
0.495 (12,57)
1.195 (30,35)
0.995 (25,27)
0.695 (17,65)
0.795 (20,19)
NO. OF D1/E1
0.350 (8,89)
0.450 (11,43)
1.150 (29,21)
0.950 (24,13)
0.650 (16,51)
0.750 (19,05)
0.004 (0,10)
M
0.007 (0,18)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
MECHANICAL DATA
MQFP004 – OCTOBER 1994
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PE (S-PQFP-G44) PLASTIC QUAD FLATPACK
4040099 /B 03/95
22
12
0,15 NOM
1,10
0,25
0,70
0,10 MIN
Gage Plane
0,25
0,45
23
11
33
1
10,00 TYP
34
44
SQ
SQ
13,80
14,20
17,20
18,00
3,10 MAX
2,70 TYP
Seating Plane
0,15
0°–10°
M
0,20
1,00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Contact field sales office to determine if a tighter coplanarity requirement is available for this package.
MECHANICAL DATA
MQFP008 – JULY 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PG (R-PQFP-G64) PLASTIC QUAD FLATPACK
4040101/B 03/95
0,15 NOM
18,0014,20
13,80 17,20
32
33
20
19
12,00 TYP
0,25
1,10
0,70
0,10 MIN
Gage Plane
51
1
18,00 TYP
52
64
23,20
24,00
19,80
20,20
3,10 MAX
2,70 TYP
0,25
0,45
0°–10°
Seating Plane
0,10
1,00 M
0,20
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Contact field sales office to determine if a tighter coplanarity requirement is available for this package.
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