MT8967AS - Mitel Semiconductor - Datasheet.Directory

6-19



Features

•ST-BUS compatible

• Transm it/Rec eive f ilters & PCM Codec in on e

I.C

• Meets AT&T D3 /D4 an d CC ITT G7 11 and G 712

•µ-Law: MT8960/62/64/67

• A-Law: MT8961/63/65/67

• Low power c onsu mpt ion:

Op .: 30 mW typ .

Stby.: 2.5 mW typ.

• Digita l Codi ng Opt ions :

MT8964/65/66/67 CCITT Code

MT8960/61/62/63 A lternative Code

• Digita lly c ontroll ed gai n adju st of both f ilters

• Ana log and digi tal loop ba ck

• Filte rs and c odec in depen de ntly us er

accessible fo r testing

• Powe rdown m ode av ai la bl e

• 2.04 8 MHz master clock input

• Up to six un committed contr ol o utpu ts

•±5V ±5% power su pp ly

Description

Manufac tured in ISO2-CMOS, these integrated filter/

codecs are designed to meet the demanding

performance needs of t he digital telecommunications

industry, e.g., PABX, Central Office, Digital

telephones.

Ordering Information

MT8964/65AC 18 Pin Ceramic DIP

MT8960/61/64/65AE 18 Pin Plastic DIP

MT8962/63AE 20 Pin Plastic DIP

MT8962/63/66/67AS 20 Pin SOIC

0°C to+70 ° C

Figure 1 - Functional Block Diagram

ANUL

VX

SD0

SD1

SD2

SD3

SD4

SD5

VR

VRef GNDA GNDD VDD VEE

DSTo

CSTi

CA

F1i

C2i

DSTi

Transmit

Filter

Output

Register

Receive

Filter

Analog to

Digital PCM

Encoder

PCM Digi ta l

to Analog

Decoder

Output

Register

Input

Register

A Register

8-Bits

B-Register

8-Bits

Control

Logic

ISSUE 10 May 1995

MT8960/61/62/63/64/65/66/67

Integrated PCM Filter Codec

ISO2-CMOS

MT8960/61/62/63/64/65/66/67 ISO2-CMOS

6-20

Figure 2 - Pin Connections

Pin Descript ion

Pin Name Description

CSTi Co ntro l ST-BUS In is a TT L -compa tib le digit al inpu t used to control the functi on of the f ilter/cod ec.

Three mod es of operat ion may be effect ed by applying to t his input a logic high (VDD), logic low

(GN DD), or an 8-bit serial word, dependin g on t he logic stat es of CA and F1i.

Functi ons controll ed are: powerdown, filter gain adjust , loopback, chip testing, SD outputs.

DSTi Data S T-B US In accepts the in comin g 8-bit PCM word. I nput is TTL-compati ble.

C2i C lo ck Inpu t is a TTL-com pati ble 2.048 MHz clock.

DSTo Data ST-BUS Ou t is a three-state digit al out put driving the PCM bus with t he outg oing 8-bit P CM

word.

VDD Pos iti ve pow er S upp ly (+5V).

F1i Synchronization Input is an active low digital input enabling (in conjunction with CA) the PCM input,

PCM outpu t and digital cont rol input. It is internall y sampled on every posi tive edge of t he clock, C2i,

an d provides frame and chan nel synchronization.

CA Co ntrol Address is a three-le ve l digit al input which enable s PCM input and output and dete rmine s

into which control re gister (A or B) the serial data , presented t o CS Ti , is stored.

SD3 System Dri ve Ou tp ut is an open dra in output of an N-channel t ransist or which ha s its source tied to

G NDA. Ina ctive stat e is open circui t.

SD4-5 System Drive Ou tputs are o pen dra in outputs of N-channel t ransistors whi ch have their sou rce t ied

to GNDD. I nactive stat e is open circuit.

SD0-2 System Drive Ou tputs are “Totempole“ CMOS outputs switching between GNDD and VDD. Inactive

state is logic low.

VEE Negative power supply (-5V).

VXVoice Transmit is the analog input to the transmit filter.

ANUL Auto Nul l is used to int egrate an inte rnal aut o-null signal . A 0.1µF capacitor must be connected

be tween t his pin and GNDA .

VRVoice Re ceive is the a na log out put of the receive filter.

GNDA Analo g gr oun d (0V) .

VRef Voltag e Referen ce input to D t o A converter.

GNDD Digi tal g rou nd (0V).

1

2

3

4

5

6

7

8

9

10 11

12

20

19

18

17

16

15

14

13

20 PIN PDIP/SOIC

CSTi

DSTi

C2i

DSTo

VDD

SD5

SD4

F1i

CA

SD3

GNDD

VRef

GNDA

VR

ANUL

VX

VEE

SD0

SD1

SD2

1

2

3

4

5

6

7

8

910

18

17

16

15

14

13

12

11

18 PIN CERDIP/PDIP

CSTi

DSTi

C2i

DSTo

VDD

F1i

CA

SD3

SD2

GNDD

VRef

GNDA

VR

ANUL

VX

VEE

SD0

SD1

MT8960/61/64/65 MT8962/63/66/67

ISO2-CMOS MT8960/61/62/63/64/65/66/67

6-21

Figure 3 - µ -Law Encoder Transfer Characteristic

Fi gure 4 - A-L aw E nco der Tr ansfe r Char acter istic

11111111

11110000

11100000

11010000

11000000

10110000

10100000

10010000

10000000

00000000

00010000

00100000

00110000

01000000

01010000

01100000

01110000

01111111

10000000

10001111

10011111

10101111

10111111

11001111

11011111

11101111

11111111

01111111

01101111

01011111

01001111

00111111

00101111

00011111

00001111

00000000

-2.415V -1.207V 0V +1.207V +2.415V

Bit 7... 0

MSB LSB

Analog Input Voltage (VIN)

MT8960/62

Digital Output

MT8964/66

Dig ital Outp ut

11111111

11110000

11100000

11010000

11000000

10110000

10100000

10010000

10000000

00000000

00010000

00100000

00110000

01000000

01010000

01100000

01110000

01111111

10101010

10100101

10110101

10000101

10010101

11100101

11110101

11000101

11010101

01010101

01000101

01110101

01100101

00010101

00000101

00110101

00100101

00101010

-2.5V -1.25V 0V +1.25V +2.5V

Bit 7... 0

MSB LSB

Analog Input Voltage (VIN)

MT8961/63

Digital Output

MT8965/67

Dig ital Outp ut

MT8960/61/62/63/64/65/66/67 ISO2-CMOS

6-22

Functional Descri ption

Figure 1 shows the functional block diagram of the

MT8960-67. These devices provide the conversion

interface between the voiceband analog signals of a

telephone subscriber loop and the digital signals

required in a digital PCM (pulse code modulation)

switching system. Analog (voiceband) signals in the

transmit path enter the chip at VX, are sampled at

8kHz, and the samples quantized and assigned 8-bit

digital values defined by logarithmic PCM encoding

laws. Analog signals in the receive path leave the

chip at VR after reconstruction from digital 8-bit

words.

Separate switched capacitor filter sections are used

for bandlimiting prior to digital encoding in the

transmit path and after digital decoding in the receive

path. All filter clocks are derived from the 2.048 MHz

master clock input, C2i. Chip size is minimized by

the use of common circuitry performing the A to D

and D to A conversion. A successive approximation

technique is used with capacitor arrays to define the

16 steps and 8 chords in the signal conversion

process. Eight-bit PCM encoded digital data enters

and leaves the chip serially on DSTi and DSTo pins,

respectively.

Transm it Path

Analog signals at the input (Vx) are firstly

bandlimited to 508 kHz by an RC lowpass filter

section. This performs the necessary anti-aliasing

for the following first-order sampled data lowpass

pre-filter which is clocked at 512 kHz. This further

bandlimits the signal to 124 kHz before a fifth-order

elliptic lowpass filter, clocked at 128 kHz, provides

the 3.4 kHz bandwidth required by the encoder

section. A 50/60 Hz third-order highpass notch filter

clocked at 8 kHz completes the transmit filter path.

Accumulated DC offset is cancelled in this last

sect ion by a switched-capacitor auto-zero loop which

integ r at es th e sign b it o f th e encode d PCM wo r d, fe d

back from the codec and injects this voltage level

into the non-inverting input of the comparator. An

int egrat ing capacitor (of value between 0.1 and 1 µF)

must be ext ernally connected f rom this point (ANUL)

to the Analog Ground (GNDA).

The absolute gain of the transmit filter (nominally 0

dB at 1 kHz) can be adjusted from 0 dB to 7 dB in 1

dB steps by means of three binary controlled gain

pads.

The resulting bandpass characteristics with the limits

shown in Figure 10 meet the CCITT and AT&T

recommended specifications. Typical atttenuations

are 30 dB for 0-60 Hz and 35 dB for 4.6 kHz and

above.

The filter output signal is an 8 kHz staircase

waveform which is fed into t he codec capacitor array,

or alternatively, into an external capacitive load of

250 pF when the chip is in the test mode. The digital

encoder generates an eight-bit digital word

representation of the 8 kHz sampled analog signal.

The first bit of serial data stream is bit 7 (MSB) and

represents the sign of the analog signal. Bits 4-6

represent the chord which contains the analog

sample value. Bits 0-3 represent the step value of

the analog sample within the selected chord. The

MT8960-63 provide a sign plus magnitude PCM

output code format. The MT8964/66 PCM output

code conforms to the AT &T D3 specification, i.e.,

true sign bit and inverted magnitude bits. The

MT8965/67 P CM output code conforms to the CCITT

specifications with alternate digit inversion (even bits

inverted). See Figs. 3 and 4 for the digital output

code corresponding to the analog voltage, VIN, at VX

input.

The eight-bit digital word is output at DSTo at a

nominal rate of 2.048 MHz, via the output buffer as

the first 8-bits of the 125 µs sampling frame.

Rece ive Path

An eight-bit PCM encoded digital word is received on

DSTi input once during the 125 µs period and is

loaded into the input register. A charge proportional

to the received PCM word appears on the capacitor

array and an 8 kHz sample and hold circuit

integrates this charge and holds it for the rest of the

sampling period.

The receive (D/A) filter provides interpolation filtering

on the 8 kHz sample and hold signal from the codec.

The filter consists of a 3.4 kHz lowpass fifth-order

elliptic section clocked at 128 kHz and performs

bandlimiting and smoothing of the 8 kHz "staircase"

waveform. In addition, sinx/x gain correction is

applied to the signal to compensate for the

attenuation of higher frequencies caused by the

capacitive sample and hold circuit. The absolute

gain of the receive filter can be adjusted from 0 dB to

-7 dB in 1 dB steps by means of three binary

controlled gain pads. The resulting lowpass

characteristics, with the limits shown in Figure 11,

meet the CCITT and AT & T recommended

specifications.

Typical attenuation at 4.6 kHz and above is 30 dB.

The filter is followed by a buffer amplif ier which

will drive 5V peak/peak into a 10k ohm load, suitable

for driving electronic 2-4 wire circuits.

ISO2-CMOS MT8960/61/62/63/64/65/66/67

6-23

VRef

An external voltage must be supplied to the VRef pin

which provides the reference voltage for the digital

encoding and decoding of the analog signal. For

VRef = 2.5V, the digital encode decision value for

overload (maximum analog signal detect level) is

equal to an analog input VIN = 2.415V (µ-Law

version) or 2. 5V (A-Law version) and is equivalent to

a signal level of 3.17 dBm0 or 3.14 dBm0

res pec tive ly, a t th e co d ec.

The analog output voltage from the decoder at VR is

defined as:

µ-Law: -0.5 2

C

16 .5 + S

VRef X[( 128 )+( 128 )( 33 )]±VOFFSET

A-Law:

2

C+1

0 .5 + S

VRef X[( 128 )( 32 )] ±VOFFSETC=0

2

C

1 6 .5 + S

VRef X[( 128 )( 32 )] ±VOFFSETC≠0

where C = c hord num ber (0-7)

S = step number (0-15)

VRef is a high impedance input with a varying

capacitive load of up to 40 pF.

The recommended referen ce volt age for the MT8960

series of codecs is 2.5V ±0.5%. The output voltage

from the reference source should have a maximum

temperat ure coefficient of 100 ppm/C°. This voltage

should have a total regulation tolerance of ±0.5%

both for changes in the input voltage and output

loading of the voltage reference source. A voltage

reference circuit capable of meeting these

specifications is shown in Figure 5. Analog Devices

’AD1403A voltage reference circuit is capable of

driving a large number of codecs due to the high

input impedance of the VRef input. Normal

precautions should be taken in PCB layout design to

minimize noise coupling to this pin. A 0.1 µF

capacitor connected from VRef to ground and located

as close as possible t o the codec is recom mended to

minimize noise entering through VRef. This capacitor

should have good high frequency characteristics.

Timing

The codec operates in a synchronous manner (see

Figure 9a). The codec is activated on the first

positive edge of C2i after F1i has gone low. The

digital output at DSTo (which is a three-state output

driver) will then change from a high impedance s tate

to the sign bit of the encoded PCM word to be

output. This will remain valid until the next positive

edge, when the next most significant bit will be

output.

On the first negative clock edge (af ter F1i signal has

been internally synchronized and CA is at GNDD or

VEE) the logic signal present at DSTi will be clocked

into the input shift register as the sign bit of the

incoming PCM word.

The eight-bit word is thus input at DSTi on negative

edges of C2i and output at DSTo on positive edges

of C2i .

F1i must return to a high level after the eighth

clock pulse causing DSTo to enter high impedance

and pr e v en ti ng f urth e r input da ta to DSTi. F1i will

continue to be sampled on every positive edge of

C2i. (Note: F1i may subsequently be taken low

during the same sampling frame to enable entry of

serial data into CSTi. This occurs usually m id-frame,

in conjunction with CA=VDD, in order to enter an 8-bit

contro l wo r d into Re gis ter B. In th is case , PC M i np ut

and output are inhibited by CA at VDD.)

Fig ure 5 - Ty pical Volt age Re ference Circ uit

NC

1234

5678

AD1403A

+5V

2.5V

0.1 µF

VRef

MT8960-67

FILTER/CODEC

NC NC NC

NC

MT8960/61/62/63/64/65/66/67 ISO2-CMOS

6-24

Internally the codec will then perform a decode cycle

on the newly input PCM word. The sampled and

held analog signal thus decoded will be updated 25

µs from the start of the cycle. After this the analog

input from t he filter is samp led for 18 µs, after w hich

digital conversion takes place during the remaining

82 µs of the sampling cycle.

Since a single clock frequency of 2.048 MHz is

required, all digital data is input and output at this

rate. DSTo, therefore, assumes a high impedance

state for all but 3.9 µs of the 125 µs frame. S imilarly,

DSTi input data is valid for only 3. 9 µs.

Digital Control Functi ons

CSTi is a digital in put (leve ls GN DD to VDD) which is

used to control the function of the filter/codec. It

operates in three different modes depending on the

logic levels applied to the Control Address input

(CA) and chip enable input (F1i) (see Table 1).

Mode 1

CA = -5 V (V EE); CSTi=0V (GNDD)

The filter/codec is in normal operation with nominal

transmit and receive gain of 0dB. The SD outputs

are in their active states and the test modes cannot

be entered.

CA = -5V (VEE); CSTi = +5V (VDD)

A state of powerdown is forced upon the chip

whereby DSTo becomes high impedance, VR is

connected to GNDA and all analog sections have

pow e r re m ov ed .

Mode 2

CA= -5V (VEE); CSTi receives an eight-bit control

word

CSTi accepts a serial data stream synchronously

wi th D STi (i.e ., i t a c ce pt s an e ig h t-b i t se ria l w o rd in a

3.9 µs timeslot, updated every 125 µs, and is

specified identically to DSTi for timing

considerations). This eight-bit control word is

entered into Control Register A and enables

programming of the following functions: t ransmit and

receive gain, powerdown, loopback. Register B is

reset to zero and the SD outputs assume their

inactive state. Test modes cannot be entered.

Mode 3

CA=0V (GNDD); CSTi receives an eight-bit control

word

As in Mode 2, the control word enters Register A and

the aforementioned functions are controlled. In this

mode, however, Register B is not reset, thus not

affec ting the states of the SD outputs.

CA=+5V (VDD); CSTi receives an 8-bit control word

In this case the control word is transferred into

Register B. Register A is unaff ected. The input and

output of PCM data is inhibited.

The contents of Register B controls the six

uncommitted outputs SD0-SD5 (four outputs, SD0-

SD3, on MT8960/61/ 64/65 versions of chip) and also

provide entry into one of the three test modes of the

chip.

Ta ble 1. D igit a l Con tr ol M ode s

MODE CA CSTi FUNCTION

1

(Note 1) VEE GN DD Normal chip operation.

VDD Powerdown.

2V

EE Serial Eight -bit control word int o Regist er A. Register B is reset.

Data

3

(Note 2) GNDD Serial Eight -bit control word into re giste r A. Regi ster B is unaffected.

Data

VDD Serial Eight -bit control word into re giste r A. Regi ster B is unaffected.

Data

Note 1: When operating in Mode 1, there should be only one frame pulse (F1i) per 1 25 µs fra me

Note 2: When operating in Mode 3, PCM input and output is inhibited by CA=VDD.

ISO2-CMOS MT8960/61/62/63/64/65/66/67

6-25

Note: For Modes 1 and 2, F1i must be at logic low

for one period of 3.9 µs, in each 125 µs cycle, when

PCM data is being input and output, and the control

word at CSTi enters Register A. For Mode 3, F1i

must be at a logic low for two periods of 3.9 µs, in

each 125 µs cycle. In the first period, CA m ust be at

GNDD or VEE, and in the second period CA must be

high (VDD).

Control Regi sters A, B

The contents of these registers control the filter/

codec functions as described in Tables 2 and 3.

Bit 7 of the registers is the MSB and is defined as the

first bit of the serial data stream input (corresponding

to the sign bit of the PCM word).

On initial power-up these registers are set to the

powerdown condition for a maximum of 25 clock

cycles. During this time it is impossible to change

the data in these registers.

Chip Test ing

By enabling Register B with valid data (eight-bit

cont rol word in pu t to CS Ti when F1i=GN DD and CA=

VCC) the chip testing mode can be entered. Bits 6

and 7 (most sign bits) define states for testing the

transmit filter, receive filter and the codec function.

The input in each case is VX input and the output in

each case is VR output . (See Table 3 for details.)

Loopback

Loopback of the filter/codec is controlled by the

control word entered into Register A. Bits 6 and 7

(most sign bits) provide either a digital or analog

loopback condition. Digital loopback is defined as

follows:

• PCM in put data at DS Ti is la t c he d in to the P CM

input re gi ster an d the out put of th is re giste r is

connected to the input of the 3-state PC M

outp ut reg ister.

• Th e digital input to the PC M dig ital-to-analog

dec oder is d isco nnect ed, for ced to ze ro (0 ).

• The o ut pu t of the P CM encoder i s di sable d and

thus t he enc od ed data i s l ost . T he P C M ou t put

at DSTo is determined by the P CM inp ut da ta.

Analog loopback is defined as follows:

• PCM input data is latched, decoded and filtered

as no rmal but not outp ut at V R.

Table 2 . Con trol St ates - R egis ter A

• Anal og out put b uffer at V R has its inpu t shorted

to GN DA an d discon nec ted from the receive

filter output.

• Anal og inp ut at V X i s disc onnec ted f rom the

transmi t filter inp ut.

• The rece ive filte r outp ut is connected to the

transm it fi lter i nput. T hus the dec ode s ign al is

fed b ack through t h e rec ei ve pat h and encoded

in the no rmal way. The a nalog ou tp ut bu ffe r at

VR is not tested by this configuration.

In both cases of loopback, DSTi is the input

and DSTo is t he output.

BIT 2 BIT 1 BIT 0 TRANSMIT (A/D)

FILTER GAIN (dB)

000 0

001 + 1

010 + 2

011 + 3

100 + 4

101 + 5

110 + 6

111 + 7

BIT 5 BIT 4 BIT 3 RECEI VE (D/A)

FILTER GAIN (dB)

000 0

001 - 1

010 - 2

011 - 3

100 - 4

101 - 5

110 - 6

111 - 7

BIT 7 BIT 6 FUNCTI ON CO NTRO L

0 0 Normal operat ion

0 1 Digital Loop back

1 0 Analog Loopback

1 1 Powerdown

MT8960/61/62/63/64/65/66/67 ISO2-CMOS

6-26

Logic Control O utputs SD0 -5

These outputs are directly controlled by the logic

states of bits 0-5 in Register B. A logic low (GNDD)

in Register B causes the SD outputs to assume an

inactive state. A logic high (VDD) in Register B

causes the SD outputs to assume an active state

(see Table 3). SD0-2 switch between GNDD and VDD

and may be used to control external logic or

trans istor circuitry, for example, that employed on the

line card for performing s uch functions as relay drive

for application of ringing to line, message waiting

indication, etc.

SD3-5 are used primarily to drive external analog

circuitry. Examples may include the switching in or

out of gain sections or filter sections (eg., ring trip

filter) (Figure 7).

MT8962/63/66/67 provides all six SD outputs.

MT8960/61/64/65 each packaged in an 18-pin DIP

provide only four control output s, SD0-3. Figure 6 - Typical Line Te rmination

AA

A

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

AA

A

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

AA

A

AA

Telephone Set

2 Wire

Analog

Supervision

Protection

Battery

Feed

Ringing

PCM Highway

2W/4W

Converter

MT8960/61

MT8962/63

MT8964/65

MT8966/67

Table 3. Cont rol St ates - Re gist er B

BITS 0-2 LOGIC CO N TROL OUTP UT S SD0-SD2

0 Inactive stat e - logic low (GNDD).

1 Active stat e - logic high (VDD).

BIT 3 LOGIC CONTROL OUTPUT SD3

0 Inactive stat e - High I mpedance.

1 Active stat e - GNDA.

BITS 4, 5 LOGIC CONTR OL OUTPUTS SD4, SD 5

0 Inactive stat e - High Imped ance.

1 Active stat e - GNDD.

BIT 7 BIT 6 CHIP T E STING CONTROLS

0 0 Normal operation.

0 1 T ransmit filter testing, i.e.:

Tr an smit filter input connecte d to VX inp ut

Receive filter and Buffer disconnected from VR

1 0 Receive filter te sting , i. e.:

Receive filter input connected to VX input

Receive filter input disconne cted from codec

1 1 Codec test ing i.e.:

Codec analog input connected to VX

Codec analog input di sconnected from transmit filter out put

Codec analog output connecte d to VR

VR disconnected from re ce ive filt er output

ISO2-CMOS MT8960/61/62/63/64/65/66/67

6-27

Powerdown

Powerdown of the chip is achieved in several ways:

Inte rna l Con tr o l:

1) Initial Power-up. Initial application of VDD and

VEE causes powerdown for a period of 25 clock

cycles and during this period the chip will

accept input only from C2i. The B-register is

reset to zero fo rc in g SD 0 -5 to be ina ct ive . Bits

0-5 of Register A (gain adjust bits) are forced

to zero and bits 6 and 7 of Regist er A become

logic high thus reinforcing the powerdown.

2) Loss of C2i. Powerdown is entered 10 to 40

µs after C2i has assumed a continuous logic

high (VDD). In this condition the chip will be in

the same state a s in (1) a b ove.

Note: If C2i stops at a continuous logic low

(GNDD), the digital data and status is

indeterminate.

Exter nal Contro l:

1) Register A. Powerdown is controlled by bits 6

and 7 ( when both at logic high) of Register A

which in tur n r eceives its control word input

via CSTi, when F1i is low and CA input is

either at VEE or GNDD. Power is removed

from the filters and analog sections of the c hip.

The analog ouput buffer at VR will be

connected to GNDA. DSTo becomes high

impedance and the clocks to the majority of the

logic are stopped. SD outputs are unaffected

and may be updated as normal.

2) CSTi Input. With CA at VEE and CSTi held at

continuous logic high the chip assumes the

same state as described in External Control

(1) above.

Figure 7 - Typical Use of the Special Drive Outputs

From ST-BUS

Master C lock

to ST-BUS

5V

Alignment

Register Select

CSTi

DSTi

C2i

DSTo

VDD

F1i

CA

SD3

SD2

GNDD

VRef

GNDA

VR

ANUL

VX

VEE

SD0

SD1

2.5V

0.1µF

-5V

MT8960/61/64/65

Gain

Section

2/4 Wire

Converter

Message

Waiting

(With Relay

Drive)

Ring Feed

(With Relay

Drive)

-100V DC

Telephone

Line

-4 8V DC

-48V DC

90VRMS

Ring Trip

Filter

(With Relay

Drive)

MT8960/61/62/63/64/65/66/67 ISO2-CMOS

6-28

Figure 8 - Example Architecture of a Simple Digital Switching System Using the MT8960-67

DSTi

DSTo

CDTi

VX

VR

SD0

SDn

.

•

Repeated for Lines

2 to 255

Line 1

Line 256

8

Speech

Switch

-

8980

Controlling

Micro-

Processor

Co ntro l &

Signalling

-

8980

DSTi

DSTo

CDTi

VX

VR

SD0

SDn

.

.•

•

Repeated for Lines

2 to 255

Line

Interface

&

Monitoring

Circuitry

Line

Interface

&

Monitoring

Circuitry

•

MT8960-67

ISO2-CMOS MT8960/61/62/63/64/65/66/67

6-29

* Excee ding th ese values ma y cause perm anen t d am a ge. Functi onal o pe rati on under the se cond ition s is no t impl ied.

Note 1: Temperature coeff icient of VRef should be better than 100 ppm/°C.

* Ty p ical fi gu res are at 25°C with nom inal ±5V suppl ies. Fo r desig n ai d o nly: n ot gu ar an teed and not subje ct to productio n testing .

Ab solu te Maximum Ratings*

Parameter Symbol Min Max Units

1 DC Supply Voltage s VDD-GNDD -0.3 +6.0 V

VEE-GNDD -6.0 +0.3 V

2 Re ference Vol tage VRef GNDA VDD V

3 Anal og Inpu t VXVEE VDD V

4 Digital Inp uts Except CA GNDD-0.3 VDD+0.3 V

CA VEE-0.3 VDD+0.3 V

5 O utp ut Volt age SD0-2 GNDD-0.3 VDD+0.3 V

SD3VEE-0.3 VDD+0.3 V

SD4-5 VEE-0.3 VDD+0.3 V

6 Current On Any Pin II20 mA

7 Storage Temperat ure TS-55 +125 °C

8 Power Dissipation at 25°C (Derate 16 mW/°C above 75°C) PDiss 500 mW

Recommended Operating Con ditions - Voltages are with respect to GNDD unless otherwise stated

Characteristics Sym Min Typ* Max Units Comments

1 Supply Voltage VDD 4.75 5.0 5.25 V

VEE -5.25 -5.0 -4.75 V

VRef 2.5 V See Note 1

2 Voltage On Digit al Ground VGNDD -0.1 0.0 +0.1 Vdc Ref. to GNDA

-0.4 0.0 +0.4 V ac Ref. to GNDA 400ns max.

duration in 125µs cycle

3 Operating Tem peratu re TO0+70°C

4 Operating Current VDD

VEE

IDD

IEE

3.0

3.0 4.0

4.0 mA

mA All digita l input s at VDD

or GNDD (or VEE for CA )

VRef IRef 2.0 µA Mean current

5 St andby Current VDD

VEE

IDDO

IEEO

0.25

0.25 1.0

1.0 mA

mA All digita l input s at VDD

or GNDD (or VEE for CA )

DC Electr i cal Characteristics - Voltages are with respect to GNDD unless otherwise stated.

TA=0 to 70°C, VDD=5V±5%, VEE= -5V ±5 %, VRef=2.5V±0.5%, GNDA=GNDD=0V,Clock Frequency =2.048MHz. Outputs unloaded unless

otherwise specif ie d.

Characteristics Sym Min Typ* Max Units Test Conditions

1

D

I

G

I

T

A

L

Input Current Except CA II10.0 µAV

IN = GNDD to VDD

CA IIC 10.0 µAV

IN = VEE to VDD

2 Input Low Except CA VIL 0.0 0.8 V

Voltage CA VILC VEE VEE+1.2 V

3 Input High Volt age All Inputs VIH 2.4 5.0 V

4 Input Interm ediat e CA

Voltage VIIC 0.0 0.8 V

5 Output Leakage DSTo

Current (Tristate ) SD3-5 I0Z ±0.1 10.0 µA

µAOutput High Impedance

MT8960/61/62/63/64/65/66/67 ISO2-CMOS

6-30

Note 2: VOS IN s pe ci fies th e D C c om po nent of the di gitally en c oded P CM w o r d.

* Ty p ical fi gu res are at 25°C with nom inal ±5V suppl ies. For desig n ai d o nly: n ot gu ar an teed and not subje ct to productio n testing .

DC Electr i cal Characteristics (cont’d)

Characteri stic s Sym Mi n Ty p* Max Units Test Condition s

6D

I

G

I

T

A

L

Ou tpu t Low DSTo VOL 0.4 V IOUT =1.6 mA

Voltage SD0-2 VOL 1.0 V IOUT =1 mA

7 Outpu t High DSTo VOH 4.0 V IOUT =-100µA

Voltage SD0-2 VOH 4.0 V IOUT =-1mA

8 Outpu t Resistanc e SD 3-5 ROUT 1.0 2.0 KΩVOUT =+1V

9 Outpu t Capacitance DSTo COUT 4. 0 pF Output High Impe dance

10 A

N

A

L

O

G

Input Current VXIIN 10.0 µAV

EE ≤ VIN ≤ VCC

11 Input Resistance VXRIN 10.0 MΩ

12 Input Capacitance VXCIN 30.0 pF fIN

= 0 - 4 kHz

13 Input Offset Voltage VXVOSIN +1.0 mV See Note 2

14 Output Resistanc e VRROUT 100 Ω

15 Outpu t Offset Volt age VRVOSOUT 100 mV Digital Input= +0

AC Electr i cal Characteristics - Voltages are with respect to GNDD unless otherwise stated.

TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V ±0.5%, GNDA=GNDD=0V, Clock Frequency=2.048 MHz. Output s u n loaded un less

otherwise specif ie d.

Characteri sti cs Sym Mi n Typ * Max U ni ts Test Condition s

1

D

I

G

I

T

A

L

Clock Frequency C2i fC2.046 2.048 2.05 MHz See Note 3

2 Clock Rise Tim e C2i tCR 50 ns

3 Clock Fall Time C2i tCF 50 ns

4 Clock Duty C ycle C 2i 40 50 60 %

5 Chip E nabl e Rise Time F1i tER 100 ns

6 Chip Enabl e Fall Time F1i tEF 100 ns

7 Chip E nabl e Setup Ti me F1i tES 50 ns See Note 4

8 Chip E nabl e Hold Time F1i tEH 25 ns See Note 4

9 Output Rise Time DSTo tOR 100 ns

10 Output Fall Time DSTo tOF 100 ns

11 P ropagat ion Dela y ClockDSTo

to Output Enable tPZL

tPZH

122

122 ns

ns RL=10KΩ to V CC

12 Propagat ion Dela y DS To

Clock to Output tPLH

tPHL

100

100 ns

ns CL=100 pF

13 Input Rise Time CSTi

DSTi tIR 100

100 ns

ns

14 In put Fa ll Ti me CSTi

DSTi tIF 100

100 ns

ns

15 In put Set up Tim e CSTi

DSTi tISH

tISL

25

0ns

ns

16 Input Hold Tim e CSTi

DSTi tIH 60

60 ns

ns

ISO2-CMOS MT8960/61/62/63/64/65/66/67

6-31

(S ee Figures 9a, 9b, 9c)

Note 3: The filter characteristics are totally dependent upon the accuracy of the clock frequency providing F1i is s yn c hronize d to

C2i. The A/D and D/A functions are unaffected by changes in clock frequency.

Note 4: This gives a 75 ns period, 50 ns before and 25 ns after the 50% point of C2i rising edge, when change in F1i wi ll giv e an

undetermined state to to the internally synchr onized enable signal.

* Ty p ical fi gu res are at 25°C with nom inal ±5V suppl ies. Fo r desig n ai d o nly: n ot gu ar an teed and not subje ct to productio n testing .

AC Electr i cal Characteristics (cont’d)

Charac te ristics Sym Min Typ * Max Units Test Conditio ns

17 D

I

G

I

T

A

L

Propaga tion Delay SD

Clock to SD Output tPCS 400 ns CL = 100 pF

18 SD Out put Fall Time SD tSF 200 ns CL = 20 pF

19 SD Output Rise Time SD tSR 400 ns

20 Digital Loopback

Time DSTi to DSTo tDL 122 ns

AC Electrical Characte ristics - Trans mit (A/D) Path - V o ltages are with respect to GNDD unless otherwise stated.

TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0 .5%, GNDA=GNDD=0V, Clo ck Frequency = 2 .0 48MH z,

Filter Gain Setting = 0 dB . Outputs unloade d u nless otherwise specified.

Characteristics Sym Min Typ* Max Units Test Co nditions

1

A

N

A

L

O

G

Analog Input at VX equivalent to

the overload decisi on level at

the codec

VIN 4.829

5.000 VPP

VPP

Level at codec:

µ-Law: 3.17 dBm 0

A-Law: 3.14 dBm0

See Not e 6

2 Absolu te Gain (0dB setting) G AX -0. 25 +0.25 dB 0 dB m 0 @ 1004 Hz

3 Absolu te Gain (+1dB to + 7dB

settings) -0.35 +0.35 dB from nominal,

@ 1004 Hz

4 G ain Variation Wit h Temp GAXT 0.01 dB TA=0 °C to 70°C

With Supplies GAXS 0.04 dB/V

5 G ain Tra ckin g

(See Fi gure 12) CCIT T G712

(Method 1)

GTX1 -0.25

-0.25

-0.50

+0.25

+0.50

dB

Sinu soidal Level :

+3 to -20 dBm0

Noise Signal Level:

-10 to -55 dB m 0

-55 to -60 dB m 0

CCITT G712

(Method 2)

AT&T

GTX2 -0.25

-0.50

-1.50

+0.25

+0.50

+1.50

dB

Sinu soidal Level :

+3 to -40 dBm0

-40 to -50 dB m 0

-50 to -55 dB m 0

6 Quantization

Distortion

(See Fi gure 13) CCIT T G712

(Method 1)

DQX1 28.00

35.60

33.90

29.30

14.20

dB

Noise Signal Level:

-3 dBm 0

-6 to -27 dBm 0

-34 dBm 0

-40 dBm 0

-55 dBm 0

MT8960/61/62/63/64/65/66/67 ISO2-CMOS

6-32

* Ty p ical fi gu res are at 25°C with nom inal ±5V suppl ies. For desig n ai d o nly: n ot gu ar an teed and not subje ct to productio n testing .

Note 6: 0dB m 0= 1.1 8 5 VRMS for the µ -Law codec.

0dB m 0= 1.2 3 1 VRMS for the A-Law codec.

Transmit (A/D) Path (con t’d)

Characteristics Sym Min Typ* Ma x Units Test Conditions

A

N

A

L

O

G

Quantization CCITT G712

Distortion (Method 2)

(cont’d) AT&T

(See Figure 13)

DQX2 35.30

29.30

24.30

dB

Sinusoi dal Inp ut Level:

0 to -30 dBm0

-40 dBm0

-45 dBm0

7 Idle Channel C-me ssage NCX 18 dBrnC0 µ-Law Only

Noise Psophometric NPX -67 dBm0p CCITT G712

8 Single Frequency Noise NSFX -56 dBm0 CCITT G712

9 Harmonic Distort ion

(2nd or 3rd Harmonic) -46 dB Input Signal:

0 dBm0 @ 1.02 kHz

10 Envelope Delay DAX 270 µs @ 1004 Hz

11 Envelope Del ay 1000-2600 Hz

Variation With 600-3000 Hz

Frequency 400 -3200 Hz

DDX 60

150

250

µs

Input Signal:

400-3200 H z Sinewave

at 0 dBm0

12 Intermodulation CCITT G712

Distortio n 50/60 H z IMDX1 -55 dB 50/ 60 Hz @ -23 dBm 0

and any signal within

300-3 400 H z at -9 dBm0

CCITT G712

2 to ne IMDX2 - 41 dB 740 Hz and 1255 Hz

@ -4 to -21 dBm0.

Equal Input Levels

AT&T IMDX3 -47 dB 2nd order products

4 to ne IM D X4 -49 dB 3rd order products

13 Gain Relat ive to ≤50 Hz

Gain @ 1004 Hz 60 H z

(See Figure 10) 200 Hz

300-3 000 Hz

3200 Hz

3300 Hz

3400 Hz

4000 Hz

≥4600 Hz

GRX

-1.8

-0.125

-0.275

-0.350

-0.80

-25

-30

0.00

0.125

0.030

-0.100

-14

-32

dB

0 dBm0 Input Sig nal

Transmit

Filter

Response

14 Crosstalk D/ A to A/D CTRT -70 dB 0 dBm0 @ 1.02 kHz

in D/A

15 Power Supply VDD

Rejection VEE

PSSR1

PSSR2

33

35 dB

dB Input 50 mVRMS at

1.02 kHz

16 Overload Distort ion (See Fig.15) Input frequency=1.02kHz

ISO2-CMOS MT8960/61/62/63/64/65/66/67

6-33

* Ty p ical fi gu res are at 25°C with nom inal ±5V suppl ies. Fo r desig n ai d o nly: n ot gu ar an teed and not subje ct to productio n testing .

AC Electrical Charac teristi cs - Receive (D/A) Path - Voltages are with respect to GNDD unless otherwise stated.

TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0 .5%, GNDA=GNDD=0V, Clo ck Frequency = 2 .0 48MH z,

Filter Gain Setting = 0 dB . Outputs unloade d u nless otherwise specified.

Ch aracter istics Sy m Mi n Ty p* M ax Uni ts Test Conditio ns

1

A

N

A

L

O

G

An a log out put at VR

equivale nt to t he overload

d ecision level at codec

VOUT 4.829

5.000 Vpp

Vpp

Level at codec:

µ-Law: 3.17 dB m0

A-L aw: 3. 14 dB m0

RL=10 KΩ

See Note 7

2 Absolute Gain (0dB setting) GAR -0.25 +0 .25 dB 0 dBm 0 @ 1004Hz

3 Absolute Attenuation (-1dB

to -7dB setting s) -0.35 +0.35 dB From nominal,

@ 1004Hz

4 G ain Variation Wi th Tem p. GART 0.01 dB TA=0° C to 70° C

With Suppl ies GARS 0.04 dB/V

5 G ain Tracking CCITT G712

(See Fi gure 12 ) (Method 1) GTR1 -0.25

-0.25

-0.50

+0.25

+0.50

dB

Sinusoid al Level:

+3 to -10 dBm 0

Noise Signal Level:

-10 to -55 dBm0

-55 to -60 dBm0

CCITT G712

(Method 2)

AT & T

GTR2 -0.25

-0.50

-1.50

+0.25

+0.50

+1.50

dB

Sinusoid al Level:

+3 to -40 dBm 0

-40 to -50 dBm0

-50 to -55 dBm0

6 Quantization CCITT G712

Distortion (Method 1)

(See Fi g. 13)

DQR1 28.00

35.60

33.90

29.30

14.30

dB

Noise Signal Level:

-3 dBm0

-6 to -27 dBm0

-34 dBm0

-40 dBm0

-55 dBm0

CCITT G712

(Method 2)

AT & T

DQR2 36.40

30.40

25.40

dB

Sinusoid al Input Level:

0 to -30 dBm0

-40 dBm0

-45 dBm0

7 Idle Channel C-message NCR 12 dBrnC0 µ-Law Only

Noise Psophometric NPR -75 dBm0p CCITT G712

8 Si ngle Frequ ency Noise NSFR -56 dBm0 CCI TT G712

9 Harmonic Distortion

(2nd or 3rd Harmonic) -46 d B Input S igna l 0 dB m 0

at 1.02 kHz

10 Intermodulation CCITT G712

D istort ion 2 tone IMDR2 -41 dB

AT & T I M D R3 -47 d B 2nd order products

4 to ne IM D R4 -49 d B 3rd order p roducts

MT8960/61/62/63/64/65/66/67 ISO2-CMOS

6-34

* Ty p ical fi gu res are at 25°C with nom inal ±5V suppl ies. For desig n ai d o nly: n ot gu ar an teed and not subje ct to productio n testing .

Note 7: 0dBm0=1.185 VRMS fo r µ-Law codec and 0dBm0=1.231 VRMS for A-Law codec.

Fi gure 9a - Timi ng D ia gra m - 1 25 µs Frame Period

Receive (D/A) Path (cont’d)

Ch aracteristics Sym Min Typ* Ma x Units Test Conditions

11

A

N

A

L

O

G

Enve lope Delay DAR 210 µs @ 1004 Hz

12 Envelope Delay 1000-2600 Hz

Variat ion wit h 600-30 00 Hz

Frequency 400-3200 Hz

DDR 90

170

265

µs

Input Signal:

400 - 3200 Hz di gital

sinewave at 0 dBm0

13 Gain Relative to <200 Hz

Gain @ 1004 Hz 200 Hz

(See Figure 11) 300-3000 Hz

3300 Hz

3400 Hz

4000 Hz

≥4600 Hz

GRR -0.5

-0.125

-0.350

-0.80

0.125

0.030

-0.100

-14.0

-28.0

dB

0 dBm0 Input Sig nal

Receive

F ilt e r

Response

14 Crosst alk A/D to D/A CTTR -70 dB 0 dBm0 @ 1.02 kHz

in A/D

15 Power Supply VDD

Rejection VEE

PSRR3

PSRR4

33

35 dB

dB Input 50 mVRMS at

1.02 k Hz

16 Overload Distortion

(See Fig. 15) Input frequency=1.02 kHz

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C2i

INPUT

F1i

INTERNAL

ENABLE

DSTo

OUTPUT

DSTi

INPUT

CA

CSTi

INPUT

LOAD

A-REGISTER

LOAD

B-REGISTER

125 µs

76543210 76543210

76543210 HIGH IMPEDANCE 7

7

76

6

76543210

5V

0V

(Mode 3)

ISO2-CMOS MT8960/61/62/63/64/65/66/67

6-35

Fig ur e 9 b - Tim ing Dia gr am - Out pu t E nab le

Note: In ty p ic al ap plic ation s , F1i will remain low for 8 cycles of C2i. However, the device will function normally as long as tES and

tEH are met at each positive edge of C2i.

Fig ur e 9c - Tim ing Diag r am - I npu t/ Outp u t

C2i

Input

F1i

Input

DSTo

Output high

impedance

8 CLOCK CYCLES

(See Note)

90%

50%

10%

90%

10%

tEF

tES tEH

tPZL

tPZH

tCR tCF tER

tES tEH

tPZL

tPZH

tES tEH

high-Z

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90%

50%

10%

90%

50%

10%

90%

50%

10%

C2i

Input

DSTo

Output

DSTi, CSTi

Input

tCR tCF

tOR tOF

tPLH

tIF

tIR tIH

tISH tISL

tPLH

MT8960/61/62/63/64/65/66/67 ISO2-CMOS

6-36

Figure 10 - Attenuation vs Frequency for Transmit (A/D) Filter

Figure 11 - Attenuation vs Frequency for Receive (D/A) Filter

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Attenuation

Relative To

Attenuation

At 1 kHz (dB)

SCALE B SCALE A PASSBAND ATTENUATION SCALE BSCALE A

0

10

20

25

30

40

-0.125

0.35

1

2

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4

0 5060100 200 300 3000 3200 3300 3400 4000 4600 5000 10000

0.125

0.35

1

2

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4

10

14

20

30

32

40

STOPBAND ATTENUATION

-0.125

-14

-18

SIN

∏(4000-F)

1200

∏(4000-F)

1200

- 1

-7/9

Note: Above function

crossover occurs

at 4000Hz.

FREQUENCY (Hz)

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Attenuation

Relative To

Attenuation

At 1 kHz (dB)

0

1

2

3

4

SCALE A PASSBAND ATTENUATION SCALE BSCALE A

0.125

0.35

1

2

3

4

-0.125

0 100 200 300 3000 3200 3300 3400 4000 4600 5000 10000

-14 SIN ∏(4000-F)

1200 - 1

STOPBAND ATTENUATION

FREQUENCY (Hz)

10

14

20

28

30

40

ISO2-CMOS MT8960/61/62/63/64/65/66/67

6-37

Figure 12 - Variation of Gain With Input Level

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+1.0

+0.5

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-60 -55 -50 -40 -30 -20 -10

5a. CCITT Metho d 1

CCITT End-To-End Spec

Bandlim ited White Noise Test Signa l

+1.0

+0.5

+0.25

0

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-0.5

-1.0

-10 0 -3

Sinusiodal Test Signal

1

2Channel Spec

In p ut Le ve l

(dBm0)

+1.5

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+0.25

-60 -50 -40 -30 -20 -10 0 +3

CCI TT End-To -En d Spe c

1

2Channel Spec

Input Level

(dBm0)

Sinusoidal Test Signal

5b. CCITT Metho d 2

Gain Variat ion (dB)

Gain Variation (dB)

MT8960/61/62/63/64/65/66/67 ISO2-CMOS

6-38

Figure 13 - Signal to Total Distortion Ratio vs Input Level

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-40

14.3 12.6

29.3

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26.3 28.0

Input Level (dBm0)

1

2Channel Spec

CCITT End-To-End

Spec

6a. CCITT Metho d 1

40

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0-60 -50 -40 -30 -20 -10 0

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1

2Channel Spec

D/A

1

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A/D

CCITT

End-To-End

Spec

Input Level (dBm0)

6b. CCITT Method 2

Signal to Total Distorti on Ratio (dB ) Signal to Total Distortion Ratio (dB)

ISO2-CMOS MT8960/61/62/63/64/65/66/67

6-39

Figure 14 - Envelope Delay Variation Frequency

Figure 15 - Overload Distortion (End-to-End)

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(2600Hz)

CCITT

½ Channel Spec

Envelope Delay (µs)

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4.5

4

33456789

Input Level (dBm0)

*Relative to Fundamental Output power level with +3dBm0 input signal level at a frequency of 1.02kHz.

Fundamental Output Power (dBm0)*

MT8960/61/62/63/64/65/66/67 ISO2-CMOS

6-40

NOTES: