Pamphlet U15412EJ4V1PF
The V850 Series of high-performance microcontrollers answers many different
application system needs. It realizes superlatively low power consumption and low
noise while offering high performance and a wide array of functions.
The broad V850 product lineup provides optimum solutions for the next-
generation systems of customers.
High
performance
Performance range of
20 to over 300 MIPS with
single instruction set
Product
deployment
Low-end/Middle-range/
high-end/ASSP
deployment
Additional
functions
Rich middleware
lineup
System LSIs
Smooth transition to
system LSIs
Development
environment
Rich development
environment lineup
2Pamphlet U15412EJ4V1PF
Pamphlet U15412EJ4V1PF 3
V850 Series Product Roadmap
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NEC Electronics Microcontroller Deployment
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Set Application Examples
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5 Keys of V850
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Low-End Lineup
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Middle-Range Lineup
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High-End Lineup
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ASSP Lineup
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Memory Lineup
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Package Lineup
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CPU Roadmap
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CPU Core Function Comparison
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System LSI Support
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V850 Series Common Architecture
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V850E1,V850ES Architecture
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V850E2 Architecture
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Memory Access Functions
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Analog Circuits
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Timer/Counter
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Serial Interface
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Other
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V850 Series Benchmark
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Low Power Consumption
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Low Noise Countermeasures
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V850 Series Middleware List
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Speech Recognition
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JPEG
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Text to Speech
(for Japanese Text)
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Features
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Rewrite Modes
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Flash Specifications List
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Flash Memory Programmers
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Low-End Lineup
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Middle-Range Lineup
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ASSP Lineup
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High-End Lineup
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Low-Price Development Environment Lineup
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Development Flow
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Development Tools
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V850 Series Development Environment
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Software Product
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V850 Series Website
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INDEX
4
5
5
6
8
10
12
14
18
19
20
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21
22
26
27
28
29
30
34
34
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62
57
59
Roadmap/Features
Product Lineup
CPU
Variety of Peripheral Functions
Performance
Middleware
Flash
Product Specifications List
Development Environment
Information Dissemination
Pamphlet U15412EJ4V1PF
4
V850E2 core
V850E1 core
V850ES core
V850 core
High-end lineup
Middle-range lineup
Low-end lineup
ASSP lineup
High-end lineup
Middle-range lineup
Low-end lineup
ASSP lineup
• Frequency: 33 to 150 MHz
• Memory size: ROM: ROM-less to 512 KB
RAM: 4 to 128 KB
• PKG: 100 to 240 pins (QFP & FBGA)
Inverter control
DVC control
Car audio control
Power meter control
Dashboard control
• Frequency: 16 to 64 MHz
• Memory size: ROM: ROM-less to
640 KB
RAM: 4 to 48 KB
• PKG: 64 to 257 pins
(QFP & FBGA)
• Frequency: 20 to 34 MHz
• Memory size: ROM: ROM-loss to
640 KB
RAM: 4 to 48 KB
• PKG: 100 to 144 pins (QFP & FBGA)
Realization of low EMI noise
• Frequency: 20 MHz
• Memory size: ROM: 64 to 256 KB
RAM: 4 to 16 KB
• PKG: 64 to 144 pins (QFP)
High cost-performance
High performance: On-chip MEMC/DMA
V850E2 core
200 to 400 MHz
CPU core release completed
Product deployment under
planning
V850E1 core
V850ES core
V850 core
150 MHz @ 215 MIPS
33 MHz @ 38 MIPS
20 MHz @ 29 MIPS
Field-specific lineupsStandard lineups
Roadmap/Features
V850 Series Product Roadmap
Continuously evolving V850 Series through
an expanding product lineup
Pamphlet U15412EJ4V1PF 5
Automotive
Audio
Portable devices
Camera
Computer peripherals
Home appliances
Industrial equipment
Video and
recording equipment
Other
The V850 Series is suitable for various application fields
and raises the commercial value of customer systems.
Engines, dashboards, power steering, ABS
Car audio, portable audio, component stereo systems
PDA, IC recorders
DVC, DSC, SLR cameras
Laser-beam printers, inkjet printers, scanners,
fax machines
Air conditioners, refrigerators, washing machines,
microwave ovens
Industrial motors, control equipment,
vending machines, power meters
DVD players, D-VHS, industrial cameras
Electronic instruments, electric bidets, toys,
learning devices, remote controllers, etc.
V
R
5000
Series
V
R
7700
Series
Price
High performance
78K0 78K4
32-bit RISC
8/16-bit CISC
64-bit RISC
8 to 16-bit applications 32-bit applications 64-bit applications
17K 75X/XL
V850ES/Sxx, V850/Sxx
middle-range lineup
Kx1 Series
V850ES/Kxx, 78K0/Kxx
low-end lineup
V
R
4100 Series
Inverter, DVC, storage
ASSP lineup
V850E/Mxx
high-end lineup
78K0S
System control
Data processing
TM
NEC Electronics Microcontroller Deployment
Set Application Examples
Upward compatible instruction sets
Pamphlet U15412EJ4V1PF
6
Product lineup
Low-end/Middle-range/High-end/ASSP deployment
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Low-end lineup: Kx1 Series of general-purpose
microcontrollers for 16 to 32-bit market designed for high
cost-performance.
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Middle-range lineup: Low noise, low power consumption,
large-capacity memory lineup, low-voltage operation support
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High-End lineup: Designed for high performance, on-chip
memory controller and DMA
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ASSP lineup: Field-specific product lineup, on-chip
dedicated hardware
Communication
High performance
On-chip dedicated
hardware
Low noise,
low power consumption
High cost-performance
Industrial
Home
appliances
Consumer
electronics
Office
equipment
Automotive
Additional functions
Rich middleware lineup
•Realization of systems with high added value through the
addition of supplementary functions to existing systems
via middleware
•Realization of functions heretofore realized with
peripheral ICs through V850 + middleware, reducing
development time and reducing system costs
•Rich lineup of video, audio, network-related, and other
middleware tuned for V850 Series
Image processing
Networks
Amusement machines Portable devices
Electronic
dictionaries
Phones
DSC
FAX
Home
appliances
Toys Car audio
Human interface
AV equipment
JBIG
TTS
Java
TM
MH/MR/MMR
JPEG
Browser TCP/IP
Speech
recognition
Handwriting
recognition
ADPCM
Middleware
Additional functions
Product lineup
V850E1 core
V850E2 core
V850ES core
V850
core
V850E/Mxx
High-End lineup
V850E/xxx
V850ES/xxx
V850/xxx
ASSP lineup
V850ES/Sxx
V850/Sxx
Middle-range lineup
V850ES/Kxx
Low-end lineup
High performance
Performance ranging from 20 to over 300 MIPS with single instruction set
•Compared to 8-/16-bit microcontroller, offer a MIPS
performance 10 or more times higher for the same
frequency, and 2 to 3 times higher at the actual
application level (based on NEC evaluation)
•System operation at frequencies 1/2 to 1/3 those of 8-
/16-bit microcontrollers is enabled, contributing to
lowering system power consumption.
•The V850 core, V850ES core, V850E1 core, and V850E2
core are upward compatible at the object level.
Processor products
Not compatible
Compatible at
object level!
Not compatible
Data processing
System control
Compatible with up to
middle-range class
Compatible with up to high-end class
models with MIPS performance up to
10 times higher
V850ES
V850
V850E1
V850
V850E2
Other
manufacturers' 16-bit
microcontrollers
Other
manufacturers' 32-bit
microcontrollers
66 MHz
33 MHz
32 MHz
20 MHz
150 MHz
>
=200 MHz
High performance
5 Keys of V850
5 points supporting the high performance of the V850 Series
Roadmap/Features
Pamphlet U15412EJ4V1PF 7
Processes
System
IP cores Middleware
Design environment
Micro-fabrication technology
Multi-layer wiring technology
Mixed-process technology
High-pin-count packages
MPU, DSP, DRAM,
SRAM, A V, communication,
BUS, high-speed I/O
Voice recognition/synthesis
AV processing
(JPEG1, MPEG1, etc.)
Modem
Chip design environment
Synthesis/verification
Software development environment
Hardware/software coordinated design
System LSI Smooth transition to system LSIs
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The V850 Series is also being actively expanded for ASIC
CPU cores, realizing smooth transition to system LSIs
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The following elements essential for system LSIs are provided
on a timely basis:
<1> Leading-edge process technology
<2> High-performance CPU core
<3> Rich lineup of IP cores
<4> Top-down design environment
<5> Flexible application design
CPU
Analog
Logic
Memory
Flash
DSP
DRAM
IP
middleware
System LSI
Development environment
Rich development environment lineup
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IECUBE
TM
, a low-cost high-performance emulator, and
N-Wire CARD, an ultra-low cost on-chip emulator are
available
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Realization of better connectivity with target boards, addition
of GUI customization function, improved online help, etc.
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Realization of shorter development TAT through support
of quick and accurate software development via a rich
development environment lineup featuring easy
operation and sophisticated functions
PM
Project Manager
+RD (task debugger)
+AZ (Analyzer)
PM
Project Manager
Improved versatility
Improved performance
Improved usability
Debugging support
Support of high speed
V850 development
environment
78K development
environment
V850 products
CC (Compiler) CA (Compiler)
RX (Real-time OS) RX (Real-time OS)
SM (Simulator)
ID (Debugger)
SM (Simulator)
ID (Debugger)
TW
(Performance analysis tuning tool)
IE, IECUBE
(In-circuit emulator) IE, IECUBE
(In-circuit emulator)
Utilization of existing functions
Improved usability
Debugging support
Development environment
Performance (MIPS)
Generation
66
200
300
700
1000
33
100
500 0.13 µm
process
Next-generation
process
0.18 µm
process
0.35 µm
process
Nx85E2
266 MHz
Nx85E2
200 MHz
Nx85E
150 MHz
Nx85E
66 MHz
V850E2
V850E1
MA3
V850E/ME2
V850E2/xxx
MA2V850E/MA1
Nx85E2
400 MHz
Next-generation core
800 to 1000 MIPS
Under planning
Under development
In mass production
V850
0.25 µm
process
PC I/F
Realization of high-
performance powerful
development
environment making
use of
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High performance
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General-purpose
registers
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Large memory
capacity
Pamphlet U15412EJ4V1PF
8
Item
CPU core
Performance
Maximum
operating frequency
Internal flash memory
Internal mask ROM
Internal RAM
Power supply voltage
External bus
Timer/counter
Serial interface
A/D converter
D/A converter
DMA controller
Other peripheral
functions
I/O
Power consumption
(mask version, Typ.)
Package
V850ES/Kx1
V850ES
29 MIPS (@ 20 MHz)
20 MHz (main clock)
32.768 kHz (subclock)
256 KB/128 KB/96 KB/64 KB
4.5 V to 5.5 V @ 20 MHz
4.0 V to 5.5 V @ 16 MHz
2.7 V to 5.5 V @ 10 MHz
8-bit×5 ch
WDT×2 ch
Watch timer×1 ch
-
150 mW (20 MHz @5V)
KF1
12 KB/6 KB/4 KB
Address: Multiplexed
16-bit× 2 ch (256 KB: 3 ch)
CSI×2 ch, UART×2 ch
I2C×1 ch*
CSI with automatic transfer function×1 ch
10-bit×8 ch
ROM correction function,
real-time output, key return function
67
80-pin TQFP(12×12 mm)
80-pin QFP(14×14 mm)
KE1
128 KB
128 KB
4 KB
-
16-bit×2 ch
CSI×2 ch, UART×2 ch
I2C×1 ch*
51
64-pin TQFP(12×12 mm)
64-pin LQFP(10×10 mm)
KJ1
128 KB/96 KB
16 KB/6 KB
16-bit×6 ch (256 KB: 7 ch)
CSI×3 ch, UART×2 ch
UART/I2C×1 ch*, I2C×1 ch*
CSI with automatic transfer function×2 ch
10-bit×16 ch
On-chip debug function, ROM correction function,
real-time output, key-return function
128
144-pin LQFP(20×20 mm)
KG1
256 KB/128 KB
16 KB/6 KB/4 KB
Data: 8/16-bit
16-bit×4 ch (256 KB: 5 ch)
CSI×2 ch, UART×2 ch
I2C×1ch*
CSI with automatic transfer function×2 ch
84
100-pin LQFP(14×14 mm)
100-pin QFP(14×20 mm)
Address: Multiplexed/separate
8-bit×2 ch
Product Lineup
Kx1 Series of general-purpose microcontrollers for 16 to 32-bit
market designed for high cost-performance
Low-End Lineup
V850ES/KE1+ V850ES/KF1+ V850ES/KG1+ V850ES/KJ1+
NEXT Generation
64-pin version 80-pin version 100-pin version 144-pin version
V850ES/KE1
78K0/Kxx
78K0S/Kxx
V850ES/KF1 V850ES/KG1 V850ES/KJ1
64-pin version 80-pin version 100-pin version 144-pin version
8-bit microcontrollers
Single-power-supply flash
On-chip POC/LVI
On-chip debugging function
DMA function (only KG1+, KJ1+)
Kx1+ are microcontrollers featuring additional functions.
Rich memory & package lineup
Kx1+ features
Kx1 Series lineup
V850ES/Kx1 V850ES/Kx1+
Runaway detection
function
Voltage detection
circuit
Reset functions
DMA function
Oscillation stabilization
time reduction
A/D converter
LIN bus interface
Watchdog timer running
on main clock
None
None
External reset,
WDT reset
Fixed at reset release
Conversion time 14 µs (min.)
Successive approximation mode
No hardware
High-reliability watchdog timer operating
with uninterruptible Ring OSC
On-chip voltage detection circuit
(LVI: variable detection voltage)
•On-chip reset detection circuit (POC: Fixed voltage)
•
Also possible with voltage detection circuit (LVI: Variable detection voltage)
4 on-chip channels (KG1+, KJ1+)
Can be reduced with optional function
Conversion interval of 3 µs (min.)
Successive approximation, scan mode
1 hardware channel for each product
plus
plus
plus
256K
128K
96K
60/64K
48K
32K
24K
16K
8K
4K
2K
1K
pins
ROM (Bytes)
8 16 20 30 44 52 64 80 100 144
KU1+ KY1+
KA1+
KB1+
KB1 KC1 KD1 KE1
KB1+
KC1+ KD1+
KE1+
Seamless lineup
78K0S
78K0
V850ES
Development environment usable in common for all series
Wide voltage range support (2.7 to 5.5 V)
Single-power-supply flash lineup
(self programming, EEPROMTM emulation support)
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* : Only Y products have an on-chip I2C interface.
KE1 KE1+KF1
KF1+
KG1
KG1+ KJ1+
KJ1
KF1
KF1+
In mass production
In mass production
Under development
Under development
Under planning
Under planning
Rich memory and package lineup
Large array of on-chip peripheral functions
common with 78K0/Kx1 of 8-bit microcontrollers
Low EMI noise design
Product specifications
Pamphlet U15412EJ4V1PF 9
Conventional set
X2X1
POC
LVI
VDD
Clock
monitor
External IC
RESET
Note: V850ES is supported from Kx1+
WDT independent
from CPU clock
System reset
voltage detection
Port
VDD
RESET
X1 X2
RESET
External IC
Watchdog
IC
RESET IC
Port
WDT
Ring-
OSC
RESET
output
Voltage
detector
Voltage drop
detection
Peripheral functions on
single chip
Micro
Kx1 Series
Note
set
System cost reduction
Common peripheral functions
Large array of peripheral functions common with 8-bit 78K0 Series
Item
CPU core
Performance
Maximum
operating frequency
Internal flash memory
Internal mask ROM
Internal RAM
Power supply voltage
External bus
Timer/counter
Serial interface
A/D converter
D/A converter
DMA controller
Other peripheral
functions
I/O
Power consumption
(mask ROM version, Typ.)
Package
V850ES/Kx1+
V850ES
29 MIPS (@ 20 MHz)
20 MHz (main clock)
32.768 MHz (subclock)
256 KB
4.5 V to 5.5 V @ 20 MHz
4.0 V to 5.5 V @ 16 MHz
2.7 V to 5.5 V @ 10 MHz
8-bit×5 ch
WDT× 2 ch
Watch timer×1 ch
T.B.D.
KF1+
12 KB/6 KB
Address: Multiplexed
16-bit×3 ch
CS I × 2 ch, LIN compatible UART × 1 ch
UART × 1 ch, I
2
C × 1 ch
*
CSI with automatic transfer function × 1 ch
10-bit×8 ch
POC/LVI, Ring OSC, clock monitor function
ROM correction function, real-time output, key return function
67
80-pin TQFP (12×12 mm)
80-pin QFP (14×14 mm)
KE1+
128 KB
128 KB
4 KB
-
16-bit×2 ch
CS × 2 ch, LIN compatible UART × 1 ch
UART × 1 ch, I
2
C × 1 ch
*
51
64-pin TQFP (12×12 mm)
64-pin LQFP (10×10 mm)
KJ1+
-
16-bit×7 ch
CSI × 2 ch, LIN compatible UART × 1 ch, UART × 1 ch
I
2
C × 1ch
*
, UART/CSI × 1 ch, UART/I
2
C × 1 ch
CSI with automatic transfer function × 2 ch
10-bit×16 ch
On-chip debug function, POC/LVI, Ring OSC,
clock monitor function, real-time output, key-return function
127 (Y products, 128)
144-pin LQFP (20×20 mm)
KG1+
256 KB/128 KB
Data: 8/16 bits
16-bit×5 ch
CS I × 1 ch, LIN compatible UART × 1 ch
UART × 1 ch, I
2
C × 1 ch
*
, UART/CSI × 1 ch
CSI with automatic transfer function × 2 ch
84
100-pin LQFP (14×14 mm)
100-pin QFP (14×20 mm)
16KB/6KB
Address: Multiplexed/separate
8-bit×2 ch
4ch
-
-
*
: Only Y products have an on-chip I
2
C interface.
Oscillation stop
monitoring
>Set space reduction!
>Total set cost reduction!
>Lower number of used ports!
>Higher reliability!!!
11111111
1 1 2 2 2 4 4 4 6 6 6
2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2
1 1 11 1 1
11 1 1 11
YYYY
Common to 78K0S products
11 1 1 1 1 2 1 2 1 2 2
1 1 11 1 111 1 1 1 1 1 1 1 1 1 1
1 1 11 11 1 1 1 1 1 1 1 1 1 1
1 1 11 1 1 1 1 1 1 1 1 1
1 1 1
1 1 11 1 1 1 1 2 1 2 1 2 2
1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2
2 2 2
1 1 1
2 2 2 2 2 2 2 2 2 2 2
2 1 2 2 1 2 2 2 3 3 2
1 1 1 2 2 2 2 2 2
2 2 2 2 2 2 2 2 3 3 3
1 1 1 1 1 1 1 1 1 1 1
Y Y Y Y Y Y Y Y Y Y Y
Y Y YY Y Y Y Y Y Y Y Y Y Y
Y Y YY Y Y
Y*Y* Y* Y*
YY Y Y Y Y Y Y Y Y Y Y
Common to 78K0 products
Y Y Y Y Y Y
Y Y YY Y Y Y Y Y Y Y Y Y Y
Y Y YY Y Y Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y Y Y
Y Y Y Y Y Y
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y
Y Y Y Y Y Y Y Y Y
8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 16 ch 16 ch 16 ch8 ch 8 ch 8 ch4 ch 4 ch 4 ch4 ch4 ch 4 ch 4 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch 8 ch
1 1 1 1
Y* Y* Y* Y*
Y Y Y Y
Y Y Y Y
Y Y Y Y
1 1 1 1 1 1 1 1 1 1 1
1
4
11
4
1111 1 1 1
2 ch2 ch2 ch2 ch2 ch 2 ch
1
2211111 1 1 21
YYYYYY Y Y YY YYYYYYY Y Y YY
Common to V850ES products
KU1+
1K
2K
4K
1K
2K
4K
2K
4K 4K
8K 8K 16K
24K 16K
24K
KY1+
78K0S
TMP
ROM size(bytes)
TM0
TM5
TMH
TM8
WT
WDT(Powerful WDT)
WDT
DMA
CSI
Auto CSI
UART
UART(LIN)
IIC
A/D
D/A
Ring-OSC(8 MHz)
Ring-OSC(240 kHz)
Sub-OSC
REG.
Key return
ROM correction
Real-time Output
H.MUL/DIV
POC/LVI
RESET OUT
Clock Monitor
78K0 V850ES
KA1+ KB1+ KB1 8K
16K 24K
32K
48K
60K
KE1 24K
32K 48K
60K
KF1
16K 24K
32K
48K
60K
KE1+KB1+ 8K
16K
24K
32K
KC1 16K
24K
32K
KC1+ 8K
16K
24K
32K
KD1 16K
24K
32K
KD1+ 60K 128K
KF1+ KE1 KF1
128K 64K
96K
128K
256K KG1
64K
96K
128K
256K KJ1
96K
128K 256K
KE1+ 128K
256K
KF1+ 128K
256K
KG1+ 128K
256K
KJ1+
Common to all products
* : Only for WDT/TMH
Pamphlet U15412EJ4V1PF
10
In mass production
In mass production
Under development
Under development
Under planning
Under planning
V850/SB1
V850ES/SA3
5 V low-power version
100-pin version
V850/SC1
V850/SA1
µPD703229Y
5 V large-capacity
RAM version
100-pin version
5 V general-
purpose
low noise
3 V general-
purpose,
Low power
consumption,
Low noise
2.5 V general-
purpose,
super-low
power
consumption
V850ES/SA2
V850ES/SG2
V850ES/SJ2
Large-capacity
internal memory
V850ES/SGx
V850ES/SJx
V850ES/ST2
ROM-less, high-capacity RAM
120-/144-pin version
Peripheral function
memory capacity
optimization
ROM-less
V850ES/SGx
Low voltage,
super-low power consumption
5 V low-power version
144-pin version
3 V low-power version
100-pin version
3 V low-power version
144-pin version
Single-power-supply
flash
Larger capacity
memory
Enhanced peripheral
functions
Pin compatible
Same peripheral
functions
Single-power-supply
flash
Lower voltage
Enhanced
peripheral functions
3 V low-power version
* : Only Y products have an on-chip I2C interface.
Product Lineup
Large-capacity memory, 2.5 V/3 V/5 V general-purpose product lineup
Product specifications
Middle-Range Lineup
Item
CPU core
Performance
Maximum
operating frequency
Internal flash memory
Internal mask ROM
Internal RAM
Power supply voltage
External bus
Timer/counter
Serial interface
A/D converter
D/A converter
DMA controller
Other peripheral
functions
I/O
Power consumption
(mask ROM version, Typ.)
Package
V850ES/Sx2
V850ES
29MIPS (@20 MHz)
20 MHz (main clock)
32.768 kHz (subclock)
640KB/384KB
2.85 V to 3.6 V
Address: Multiplexed/separate
Data: 8/16 bits
8-bit×2 ch
4 ch
On-chip debugging function, CRC circuit, ROM correction function, Ring OSC,
low voltage detection circuit, clock monitoring function, automotive bus (IEBusTM, aFCAN)
Note
V850ES/SAx
V850ES
29 MIPS (@ 20 MHz)
20 MHz (main clock)
32.768 kHz (subclock)
256 KB
2.2 V to 2.7 V
Address: Multiplexed/separate
Data: 8/16 bits
16-bit × 2 ch
8-bit × 4 ch
WDT × 1 ch
8-bit×2 ch
4 ch
Real-time counter (watch function), ROM correction function
38 mW (20 MHz @ 2.5 V)
SA3
256 KB
16 KB
CSI × 3 ch, CSI/UART × 1 ch
UART × 1 ch, CSI/I2C × 1 ch*
10-bit × 16 ch
102
121-pin FBGA (12 × 12 mm)
SA2
256 KB/128 KB
16 KB/8 KB
CSI × 2 ch, CSI/UART × 1 ch
UART × 1 ch, CSI/I2C × 1 ch*
10-bit × 12 ch
82
100-pin TQFP (14 × 14 mm)
µPD70F3229Y
µPD703229Y
V850ES
29MIPS (@20 MHz)
20 MHz (main clock)
32.768 kHz (subclock)
384KB
384KB
32KB
3.5 V to 5.5 V (internal)
3.0 V to 5.5 V (external bus)
Address: Multiplexed
Data: 8/16 bits
16-bit × 6 ch
WDT × 1 ch
Watch timer × 1 ch
CSI×1 ch, LIN compatible UART × 3 ch
CSI/I2C × 1 ch*
10-bit × 12 ch
-
4 ch
On-chip debugging function, ROM correction function,
low voltage detection circuit, clock monitoring function
84
100 mW (20 MHz @ 5 V)
100-pin LQFP (14 × 14 mm)
SJ2
640KB/512KB/384KB
48KB/40KB/32KB
16-bit × 11 ch
WDT × 1 ch
Watch timer × 1 ch
CSI × 4 ch, CSI/LIN compatible UART × 1 ch
LIN compatible UART × 1 ch, CSI/I
2
C × 1 ch*
UART/I
2
C × 2 ch*
10-bit × 16 ch
128
66 mW (20 MHz @ 3.3 V)
144-pin LQFP (20 × 20 mm)
SG2
640KB/512KB/384KB/256KB
48KB/40KB/32KB/24KB
16-bit×8 ch
WDT×1 ch
Watch timer×1 ch
CSI
×
3 ch, CSI/LIN compatible UART
×
1 ch
CSI/I2C × 1 ch*
LIN compatible UART/I2C × 2 ch*
10-bit × 12 ch
84
59.4 mW (20 MHz @ 3.3 V)
100-pin LQFP (14 × 14 mm)
100-pin QFP (14 × 20 mm)
Note Products without automotive bus, products with on-chip IEBus, and products with on-chip aFCAN are available.
Pamphlet U15412EJ4V1PF 11
-
*
: Only Y products have an on-chip I
2
C interface.
V850/SA1
V850
23 MIPS (@ 20 MHz)
20 MHz (main clock)
32.768 kHz (subclock)
256 KB/128 KB
256 KB/128 KB/64 KB
8 KB/4 KB
2.7 V to 3.6 V (@ 17 MHz)
3.0 V to 3.6 V (@ 20 MHz)
Address: Multiplexed/separate
Data: 16-bits
16-bit×2 ch
8-bit×4 ch
WDT×1 ch
Watch timer×1 ch
CSI×1 ch, CSI/UART×1 ch
CSI/I
2
C×1 ch*, UART×1 ch
10-bit×12 ch
-
3 ch (internal RAM-on-chip peripheral I/O)
-
85
66 mW (20 MHz @ 3.3 V)
56 mW (17 MHz @ 3 V)
100-pin LQFP (14×14 mm)
121-pin FBGA (12×12 mm)
V850/SB1
V850
23 MIPS (@ 20 MHz)
20 MHz (main clock)
32.768 kHz (subclock)
512 KB/384 KB/256 KB
512 KB/384 KB/256 KB/128 KB
24 KB/16 KB/8 KB
4.0 V to 5.5 V
Address: Multiplexed/separate
Data: 16-bits
16-bit×2 ch
8-bit×6 ch
WDT×1 ch
Watch timer×1 ch
CSI×1 ch, CSI/UART×2 ch
CSI/I
2
C×2 ch*
10-bit×12 ch
-
6ch (internal RAM-on-chip peripheral I/O)
ROM correction function
83
125 mW (20 MHz @ 5 V)
100-pin LQFP (14×14 mm)
100-pin QFP (14×20 mm)
V850/SC1
V850
23 MIPS (@ 20 MHz)
20 MHz (main clock)
32.768 kHz (subclock)
512 KB
512 KB
24 KB
3.5 V to 5.5 V (mask ROM versions)
4.0 V to 5.5 V (flash memory versions)
Address: Multiplexed/separate
Data: 16-bits
16-bit×10 ch
WDT×1 ch
Watch timer×1 ch
CSI×2 ch, CSI/UART×2 ch
UART×2 ch, CSI/I
2
C×2 ch
10-bit×12 ch
-
6 ch (internal RAM-on-chip peripheral I/O)
ROM correction function
124
125 mW (20 MHz @ 5 V)
144-pin LQFP (20×20 mm)
V850ES/ST2
V850ES
-
34 MHz
ROM-less
48 KB
3.0 V to 3.6 V
Address: Separate/multiplexed (selectable only for CS1)
Data: 8/16
16-bit×7 ch
WDT×1 ch
CSI×1 ch, CSI/UART×1 ch
UART×1 ch
10-bit×8 ch
8-bit×2 ch
-
Real-time output
65
T.B.D.
120-pin TQFP (14×14 mm)
144-pin LQFP (20×20 mm)
Item
CPU core
Performance
Maximum
operating frequency
Internal flash memory
Internal mask ROM
Internal RAM
Power supply voltage
External bus
Timer/counter
Serial interface
A/D converter
D/A converter
DMA controller
Other peripheral
functions
I/O
Power consumption
(mask ROM version, Typ.)
Package
Features
V850ES/SG2, SJ2
µPD70F3229Y, 703229Y
Large-capacity memory
ROM/RAM:384 KB/32 KB
3 V/5 V mixed system support (Internal: 3.3 V/External: 5 V)
Peripheral functions and pin assignment common with V850ES/SG2
100-pin LQFP
Low EMI noise
20 MHz @ 2.85 to 3.6 V operation
5 V withstand voltage ports incorporated, and 5 V output is possible
by setting the N-ch open-drain output
On-chip large-capacity single-power-supply flash memory
ROM/RAM:640 KB/48 KB, 512 KB/40 KB, 384 KB/32 KB,
256 KB/24 KB (SG2 only)
Automotive on-chip bus support: IEBus*, aFCAN*
(*: Only products with on-chip SG2, SJ2)
On-chip debugging function
100-pin QFP (SG2)/100-pin LQFP (SG2)/144-pin LQFP (SJ2)
V850ES/SA2, SA3
Min. 2.2 V low-voltage operation (including A/D, D/A converter, flash)
Low power consumption and high-speed operation during
38 mW @ 2.5 V, 20 MHz operation
Single-power-supply flash
ROM/RAM: 256 KB/16 KB (SA2, SA3), 128 K/8 KB (SA2 mask ROM version)
Thin and compact package support: 100-pin TQFP (SA2)/121-pin FBGA (SA3)
V850/SA1
Low power consumption and high-speed operation during
66 mW @ 3.3 V, 20 MHz operation
Large memory selection
ROM/RAM:256 KB/8 KB, 128 KB/4 KB, 64 KB/4 KB
100-pin LQFP/121-pin FBGA
V850ES/ST2
ROM-less version
On-chip high-capacity RAM (48 KB)
3.3 V, 34 MHz operation
Thin-type, compact type packages supported:
120-pin TQFP/144-pin LQFP
V850/SB1
Low EMI noise
Large-capacity memory and large memory selection
ROM/RAM:512 KB/24 KB, 384 KB/24 KB, 256 KB/16 KB, 128 KB/8 KB
100-pin QFP/100-pin LQFP
V850/SC1
Low EMI noise
Large-capacity memory (ROM/RAM: 512 KB/24 KB)
Enhanced peripheral functions for SB1
144-pin LQFP
Pamphlet U15412EJ4V1PF
12
Product Lineup
High performance, on-chip MEMC/DMA
V850E2/Mxx
High-End Lineup
Item
CPU core
Performance
Maximum
operating frequency
Internal flash memory
Internal mask ROM
Internal RAM
Cache
Power supply voltage
Memory controller
External bus
Timer/counter
Serial interface
A/D converter
D/A converter
DMA controller
Other peripheral
functions
I/O
Power consumption
(mask ROM version, Typ.)
Package
V850E/MA3
V850E1
106 MIPS(@ 80 MHz)
80 MHz
512 KB
512 KB/256 KB
32 KB/16 KB
-
2.3 V to 2.7 V (internal)
3.0 V to 3.6 V (external)
SDRAM, SRAM, etc.
Address: Separate/multiplexed
Data: 8/16 bits
16-bit× 9 ch
WDT × 1 ch
CSI/UART × 3 ch, UART/I
2
C × 1 ch
*
10-bit × 8 ch
8-bit × 2 ch
4 ch
ROM correction function
On-chip debugging function
112
T.B.D.
144-pin LQFP (20 × 20 mm)
161-pin FBGA (13 × 13 mm)
V850E/MA1
V850E1
67 MIPS(@ 50 MHz)
50 MHz
256 KB
256 KB/128 KB/ROM-less
10 KB/4 KB
-
3.0 V to 3.6 V
SDRAM, EDO DRAM, SRAM, etc.
Address: Separate
Data: 8/16 bits
16-bit × 8 ch
CSI×1 ch, CSI/UART × 2 ch
UART × 1 ch
10-bit × 8 ch
-
4 ch
PWM output: 2 ch
115
528 mW (50 MHz @ 3.3 V)
144-pin LQFP (20 × 20 mm)
161-pin FBGA (13 × 13 mm)
V850E/MS1
V850E1
47 MIPS(@ 33 MHz)
33 MHz (internal ROM products)
40 MHz (ROM-less products)
128 KB
128 KB/96 KB/ROM-less
4 KB
-
3.0 V to 3.6 V (internal/external) (3 V products)
3.0 V to 3.6 V (internal) (5 V products)
/4.5 V to 5.5 V (external)
EDO DRAM, SRAM, etc.
Address: Separate
Data: 8/16 bits
16-bit × 8 ch
CSI×2 ch, CSI/UART × 2 ch
10-bit × 8 ch
-
4 ch
-
131
330 mW (40 MHz @ 3.3 V)
272 mW (33 MHz @ 3.3 V)
144-pin LQFP (20 × 20 mm)
157-pin FBGA (14 × 14 mm)
V850E/MS2
V850E1
-
33 MHz
-
ROM-less
4 KB
-
3.0 V to 3.6 V (internal)
/4.5 V to 5.5 V (external)
EDO DRAM, SRAM, etc.
Address: Separate
Data: 8/16 bits
16-bit × 6 ch
CSI/UART × 2 ch
10-bit × 4 ch
-
4 ch
-
57
218 mW (33 MHz @ 3.3 V)
100-pin LQFP (14 × 14 mm)
V850E/MA2
V850E1
-
40 MHz
-
ROM-less
4 KB
-
3.0 V to 3.6 V
SDRAM, SRAM, etc.
Address: Separate
Data: 8/16 bits
16-bit × 6 ch
CSI/UART × 2 ch
10-bit × 4 ch
-
4 ch
-
79
416 mW (40 MHz @ 3.3 V)
100-pin LQFP (14 × 14 mm)
V850E/ME2
V850E1
215 MIPS(@ 150 MHz)
150 MHz
-
-
Instruction RAM: 128 KB; Data RAM: 16 KB
Instruction
:
8 KB
1.35 V to 1.65 V (internal)
Note
3.0 V to 3.6 V (external)
SDRAM, SRAM, etc.
Address: Separate
Data: 8/16/32 bits
16-bit × 12 ch
CSI × 1 ch, CSI/UART × 1 ch
UART × 1 ch
10-bit × 8 ch
-
4 ch
USB×1 ch, on-chip debugging
function (with trace), PWM output: 2 ch
78
200 mW (150 MHz @ 1.5 V)
176-pin LQFP (24 × 24 mm)
240-pin FBGA (16 × 16 mm)
* : Only Y products have an on-chip I
2
C interface. Note : 1.35 V to 1.65 V : @ 10 MHz to 133 MHz
1.40 V to 1.65 V : @ 10 MHz to 150 MHz
215 MIPS @150 MHz, internal 1.5 V/external 3.3 V operation ROM-less microcontroller
Large-capacity internal RAM (128 KB), real-time control
On-chip SSCG*, EMI peak reduction
USB full-speed (function), on-chip debugging function
On-chip SDRAM interface
176-pin LQFP/240-pin FBGA
67 MIPS @50 MHz
Internal 3.3 V/external 5 V tolerant operation single-chip microcontroller (MA1)
ROM-less product lineup also available
40 MHz @3.3 V ROM-less microcontroller (MA2)
ROM/RAM: 256 KB/10 KB (MA1), ROM-less/4 KB (MA1, MA2)
On-chip SDRAM interface, DMA
144-pin LQFP/161-pin FBGA (MA1), 100-pin LQFP (MA2)
106 MIPS @80 MHz, internal 2.5 V/external 3.3 V operation single-chip microcontroller
Large-capacity internal ROM/RAM (512 KB/32 KB)
Internal single power supply flash
SDRAM interface, motor control function, on-chip debugging function
144-pin LQFP/161-pin FBGA
47 MIPS @33 MHz, 3.3 V & 5 V single-chip microcontroller (MS1)
ROM-less product (Max. 40 MHz) lineup available
33 MHz @ internal 3.3 V/external 5 V ROM-less microcontroller (MS2)
ROM/RAM: 128 KB/4 KB (MS1), ROM-less/4 KB (MS1, MS2)
144-pin LQFP (MS1)/157-pin FBGA (MS1)/100-pin LQFP (MS2)
Product specifications
Features
V850E/ME2 V850E/MA1,MA2
V850E/MA3 V850E/MS1,MS2
*
Spread Spectrum Frequency Synthesizer Clock Generator
In mass production
In mass production
Under planning
Under planning
Higher performance
Large-capacity internal memory
Enhanced peripheral functions
Superscalar
On-chip instruction cache
& RAM
On-chip SDRAM controller
V850E/MS2
V850E/MA1
V850E/ME2
V850E/MA2
V850E2/Mxx
V850Ex/Mxx
33 MHz, ROM-less
100-pin
50 MHz @ 67 MIPS
144-pin/161-pin
150 MHz @ 215 MIPS
176-pin/240-pin
40 MHz, ROM-less
100-pin
V850E/MS1
33 MHz @ 47 MIPS
144-pin/157-pin
V850E/MA3
80 MHz @ 106 MIPS
144-pin/161-pin
Higher performance
On-chip instruction
cache
On-chip USB
Higher
performance
Parallel
execution
Higher performance
Large-capacity internal memory
Pamphlet U15412EJ4V1PF 13
Application examples
CPU
ROM, Flash
SDRAM
For storing image data
Printer
engine
CCD
A/D
Document
Memory
RPU
PORT
INTC
DMA
SIO
Control panel
USB
SRAM
IEEE1394
LAN
ASIC
NCU
PC
Telephone network
Communication
system
Printing paper
Motor
Browser
function
ASIC
RTC
S/H V850E/ME2
Image processing
Shooting
correction/
binarization
Instruction
RAM
128 KB
Data RAM
16 KB
Engine
controller
JPEG
MH/MR/MMR
Interface
control circuit
Image
processing
Modem
V850E/ME2
Multi Function Printer
;;;
;;;
Sensor
ADC TMQ SIO
;
Driver
TMP
MEMC
Port Uart
DMAC ASIC
Distributed control
CPU
IEEE1284 interface
controller
USB interface
controller
Address/Data/Control
DMARQ/DMAAK/TC
RS-232C
driver/receiver
serial interface
USB I/F IEEE1284 I/F
Thermal head
Stepping
motor
SRAM/
SDRAM CG-ROM
V850E/MA3
Internal ROM
(512 KB)
Internal RAM
(32 KB)
TxD/RxD
V850E/MA3
Thermal Printer
Display driver
Disk servo
control
Motor
driver
Optical pickup
unit
Preceding stage
processing
processor
Preceding stage
processing block Latter stage
processing block
Sub-CPU
MPEG2
decoder
SDRAM
DAC
ADC
Audio DAC
Video amp
V850E/MA2,
V850ES/ST2
Flash
memory
Stream
control
Remote
control
Key input
Optical disk
control
V850E/MA2
DVD Player
Image
processing Printer
engine
Printing system
Communication
system
Telephone network
NCU
Paper
Real-time
clock
Watch
Memory
Optical system
Document
CCD S/H
Image processing
Shading correction/
binarization
A/D
System bus
ROM
AFE
Motor
driver
Operation panel
Motor
SIO
INTC
PORT
RPU
RAM
4 KB
MH/MR/MMR
JBIG
CPU
SRAM
DMA
RAM
for storing image data
ROM:
128 KB
V850E/MS1
V850E/MS1
FAX Machine
MFP (Multifunction printer)
Thermal printer
Thermistor
Applied STB
Data latch
Data Clock
4-phase PWM
DVD player
Fax machine
Pamphlet U15412EJ4V1PF
14
Inverter control
DVC control
Power meter
instrument
measuring
control
V850ES/IK1
V850ES/PM1
V850E/SV2
V850/SV1
V850E/IA2
V850E/MA3
V850E/IA1
On-chip VCR servo
timer
On-chip inverter and timer
50 MHz, 144-pin
Compact version
40 MHz, 100-pin
On-chip inverter and timer, 80 MHz, 144-/161-pin
V850E/IA4
V850E/IA3
On-chip inverter and
timer, 32 MHz, 64-pin
On-chip inverter
and timer
On-chip 16-bit
∆ΣADC
Under development
Under development
3 V low-power version
176/180-pin, on-chip VCR servo timer
Enhanced peripheral functions
257-pin version, on-chip VCR servo timer
On-chip inverter and timer
64 MHz, 100-pin
Compact version
64 MHz, 80-pin
On-chip 16-bit ∆ΣADC
In mass production
In mass production
Features
Product Lineup
■
For inverter control
■
41 MIPS @ 32 MHz, 4.5 V to 5.5 V (on-chip regulator)
■
On-chip 6-phase sinusoidal PWM timer, POC/LVI, and clock
monitor functions
■
ROM/RAM: 128 KB/6 KB, 64 KB/4 KB
■
64-pin LQFP
Field-specific lineups
ASSP Lineup (1)
V850E/IA3, IA4
■
For inverter control
■
82 MIPS @ 64 MHz, internal 2.5 V/external 5 V operation
■
On-chip 6-phase sinusoidal PWM timer, on-chip operational
amplifier/comparator, on-chip high-speed A/D
■
On-chip debugging function (IA4 only)
■
ROM/RAM: 256 KB/12 KB, 128 KB/6 KB (mask ROM version only)
■
80-pin QFP (IA3), 100-pin LQFP/100-pin QFP (IA4)
V850E/SV2
■
For camcorders (incl. DVC)
■
32-bit servo timer ideal for camcorder control, boundary scan
function, on-chip debugging function, and many other on-chip
peripheral functions
■
55 MIPS @ 40.5 MHz, 2.5 V low-voltage/high-speed operation
■
Large-capacity memory (ROM/RAM: 512 KB/24 KB)
■
Internal single-power-supply flash
■
Compact high-pin-count 257-pin FBGA (14×14 mm, 0.65 mm pitch)
V850ES/PM1
■For power meter control
■On-chip high-resolution, high-accuracy 16-bit ∆ΣA/D converter
■ROM/RAM: 128 KB/10 KB, ROM-less/10 KB
■29 MIPS @ 20 MHz, 3.0 V to 3.6 V operation
■100-pin LQFP
Item
CPU core
Performance
Maximum operating frequency
Internal flash memory
Internal mask ROM
Internal RAM
Power supply voltage
External bus
Timer/counter
Serial interface
A/D converter
D/A converter
DMA controller
Other peripheral
functions
I/O
Power consumption
(mask ROM version, Typ.)
Package
V850E/IA1
V850E1
67 MIPS (@ 50 MHz)
50 MHz
256 KB
256 KB
10 KB
3.0 V to 3.6 V (internal)
4.5 V to 5.5 V (external)
Address: Multiplexed
Data: 8/16 bits
16-bit × 8 ch
CSI × 2ch, UART × 3ch
10-bit × (8 ch + 8 ch)
-
4 ch
FCAN × 1 ch
83
630 mW
(50 MHz @ 3.3 V)
144-pin LQFP (20 × 20 mm)
V850E/IA2
V850E1
54 MIPS (@ 40 MHz)
40 MHz
128 KB
128 KB
6 KB
4.5 V to 5.5 V
Address: Multiplexed
Data: 8/16 bits
16-bit × 7 ch
CSI × 1 ch, CSI/UART × 1 ch
UART × 1 ch
10-bit × (6 ch + 8 ch)
-
4 ch
-
53
440 mW
(40 MHz @ 5 V)
100-pin LQFP (14 × 14 mm)
100-pin QFP (14 × 20 mm)
V850E/IA3
V850E1
82 MIPS (@ 64 MHz)
64 MHz
256 KB
128 KB
12 KB/6 KB
2.3 V to 2.7 V (internal)
4.5 V to 5.5 V (external)
-
16-bi t × 8 ch
WDT × 1 ch
CSI × 1 ch, CSI/UART × 1 ch
UART × 1 ch
10-bit×(4 ch + 2 ch), 8/10-bit×6 ch
-
4 ch
ROM correction function
operational amplifier, comparator, pull-up function
50
175 mW
(64 MHz @ 2.5 V)
80-pin QFP (14 × 14 mm)
V850E/IA4
V850E1
82 MIPS (@ 64 MHz)
64 MHz
256 KB
256 KB/128 KB
12 KB/6 KB
2.3 V to 2.7 V (internal)
4.5 V to 5.5 V (external)
-
16-bit × 9 ch
WDT × 1 ch
CSI × 1 ch, CSI/UART × 1 ch
UART × 1 ch
10-bit× (4 ch + 4 ch), 8/10-bi t× 8 ch
-
4 ch
On-chip debugging and ROM correction functions
Operational amplifier, comparator, pull-up function
64
175 mW
(64 MHz @ 2.5 V)
100-pin QFP (14 × 20 mm)
100-pin LQFP (14 × 14 mm)
V850ES/IK1
V850ES
41 MIPS (@ 32 MHz)
32 MHz
128 KB
128 KB/64 KB
6 KB/4 KB
3.5 V to 5.5 V
-
16-bit × 7 ch
WDT × 1 ch
CSI × 1 ch, UART × 2 ch
10-bit × (4 ch+4 ch)
-
-
ROM correction function
,
pull-up function,
POC/LVI, clock monitor function
39
T.B.D.
64-pin LQFP (14 × 14 mm)
Product specifications
V850ES/IK1
Pamphlet U15412EJ4V1PF 15
Application examples
V850E/IA4
Air Conditioner
V850E/SV2
Digital Video Camera
V850ES/PM1
Power Meter
■
Air conditioner
■
DVC
■
Power meter
;;;
MM
EEPROM
WDT
µPC2925
EV
DD
V
DD
PWM output PWM output
A/D converter
A/D converter
INT INT
CSI UART
V850E/IA4
V850E1 64M Hz
ROM256K RAM12K
Timer 10ch SIO3ch
A/D16ch N-Wire
Fan motor
Indoor unit
Power module Photocoupler Power modulePhotocoupler
Compressor
motor
CCD
driver Camera DSP
processing
Audio & video
I/O interface
USB
SD memory, etc.
JPEG
SDRAM
CCD
M
M
M
Moving picture
processing
DV processing
IEEE1394
DV processing
SDRAM
IEEE1394
JPEG field
memory
;;
USB2.0
;;
JPEG
;;
Card
Interface
;;
MPEG4
LCD panel
LCD
controller
OSD
Head amplifier
Video head
Loading
Drum
Capstan
Motor driver
(motor control)
Mike
Mike
V850E/SV2
System controller &
servo control microcontroller
S1 video input
A/D, CDS, SGC
(camera pre-processing)
Camera DSP
SDRAM
Lens
driver
System control/servo control block
Camera control block Still picture and moving picture processing block
;;
;;
;;
;;
ROM
;;
;;
;;
Timers
;;
PMWs
;
RAM
;;
WDT
;;
CSI
;;
CSI
;;
UART
;;
;;
RTC
V850ES/PM1
LCD display
EEPROM
Communication function
block
Main clock
20 MHz Subclock
32 kHz
On-chip LCD C/D
8-bit microcontroller
32bit
RISC CPU
16-bit ∆Σ A/D
3-phase 3-wire
Item
CPU core
Performance
Maximum operating frequency
Internal flash memory
Internal mask ROM
Internal RAM
Power supply voltage
External bus
Timer/counter
Serial interface
A/D converter
D/A converter
DMA controller
Other peripheral
functions
I/O
Power consumption
(mask ROM version, Typ.)
Package
*
: Only Y products have an on-chip I2C interface.
V850/SV1
V850
23 MIPS (@ 20 MHz)
20 MHz
384 KB/256 KB
384 KB/256 KB/192 KB
16 KB/8 KB
3.1 V to 3.6 V @ 20 MHz
2.7 V to 3.6 V @ 16 MHz
Address: Multiplexed
Data: 16 bits
24-bit × 2 ch, 16-bit × 2 ch
8-bit×8ch, WDT × 1 ch, watch timer × 1 ch
CSI × 1 ch, CSI/UART × 2 ch
CSI/I2C × 2 ch*
10-bit × 16 ch
-
6 ch (internal RAM-on-chip peripheral I/O)
ROM correction function, dedicated PWM output × 4,
Hsync/Vsync separation circuit
151
82 mW
(20 MHz @3.3 V)
176-pin LQFP (24 × 24 mm)
180-pin FBGA (13 × 13 mm)
V850E/SV2
V850E1
55 MIPS (@ 40.5 MHz)
40.5 MHz
512 KB
512 KB
24 KB
2.3 V to 2.7 V (internal)
2.7 V to 3.6 V (external)
Address: Multiplexed/separate
Data: 8/16 bits
32-bit × 1 ch, 16-bit × 12 ch
8-bit × 12 ch, WDT × 1 ch
CSI × 5 ch, CSI/UART × 1 ch, UART×1 ch, I2C × 1 ch*
10-bit × 24 ch
-
4 ch
On-chip debugging function, boundary scan function
ROM correction function, dedicated PWM output: 5 ch
195
134 mW
(40.5 MHz @ 2.5 V)
257-pin FBGA
(14 × 14 mm)
V850ES/PM1
V850ES
29 MIPS (@20 MHz)
20 MHz
-
128 KB/ROM-less
10 KB
3.0 V to 3.6 V @ 20 MHz, 2.7 V to 3.6 V @ 10 MHz,
2.2 to 3.6 V @ 32.768 kHz
Address : Separate
Data : 8/16 bits
16-bit × 6 ch, 8-bit × 2 ch
WDT × 1 ch
CSI × 2 ch, UART × 2 ch
16-bit ∆Σ × 6 ch
-
-
ROM correction function, dedicated PWM output: 4 ch
Real-time counter (watch function)
80
81 mW
(20 MHz @3.3 V)
100-pin LQFP
(14 × 14 mm)
Pamphlet U15412EJ4V1PF
16
Product Lineup
ASSP Lineup (2)
Features
V850/DB1
■
For automotive electronics (body control applications)
■
ROM/RAM : 128 KB/6 KB
■
On-chip DCAN controller (2 ch max.)
■
18 MIPS @ 16 MHz, 4.0 to 5.5 V operation
■
128-pin QFP
V850ES/FE2, FF2, FG2, FJ2
■
For automotive electronics (body control applications)
■
On-chip large-capacity single-power-supply flash memory
■
ROM/RAM: 512 KB/20 KB, 384 KB/16 KB, 256 KB/12 KB,
128 KB/6 KB
■
On-chip aFCAN controller (4 ch max.), LIN function
compatible UART, POC/LVI
■
29 MIPS @ 20 MHz, 4.0 to 5.5 V operation
■
64-pin TQFP (FE2)/80-pin TQFP (FF2)/100-pin LQFP
(FG2)/144-pin LQFP (FJ2)
V850/SF1
■
For car audio
■
Low EMI noise
■
On-chip FCAN controller (2 ch max.)
■
ROM/RAM: 256 KB/16 KB, 128 KB/12 KB
■
100-pin LQFP/100-pin QFP
V850ES/SG2, SJ2
■
For car audio
■
On-chip large-capacity single-power-supply flash memory
■
ROM/RAM : 640 KB/48 KB, 512 KB/40 KB, 384 KB/32 KB, 256 KB/24 KB (SG2 only)
■
On-chip IEBus controller (1 ch), on-chip aFCAN controller (2 ch max.)
■
29 MIPS @ 20 MHz, 2.85 to 3.6 V operation
■
5 V withstand voltage ports incorporated, and 5 V output is possible
by setting the N-ch open-drain output
■
On-chip debugging function
■
100-pin LQFP/100-pin QFP (SG2), 144-pin LQFP (SJ2)
Under development
Under development
Under planning
Under planning
In mass production
In mass production
Field-specific lineups
Product specifications
Item
CPU core
Performance
Maximum operating frequency
Internal flash memory
Internal mask ROM
Internal RAM
Power supply voltage
External bus
Timer/counter
Serial interface
A/D converter
D/A converter
DMA controller
Other peripheral
functions
I/O
Power consumption
(mask ROM version, Typ.)
Package
FF2
256 KB/128 KB
256 KB/128 KB
12 KB/6 KB
10-bit × 12 ch
67
155 mW (20 MHz @ 5 V)
80-pin TQFP (12×12 mm)
384 KB/256 KB
-
16 KB/12 KB
CSI × 3 ch, LIN-compatible UART × 3 ch
4 ch
200 mW (20 MHz @ 5 V)
512 KB
-
20 KB
Address: Multiplexed bus
Data: 8/16 bits
CSI × 3 ch, LIN-compatible UART × 4 ch
aFCAN × 4 ch
-
FG2
V850ES
29 MIPS (@ 20 MHz)
20 MHz
384 KB/256 KB/128 KB
256 KB/128 KB
16 KB/12 KB/6 KB
4.0 V to 5.5 V
16-bit × 7 ch
WDT × 1 ch, watch timer × 1 ch
CSI × 2 ch, LIN-compatible UART × 3 ch
10-bit × 16 ch
-
POC/LVI function, clock monitor function, RAM hold flag
84
100-pin LQFP (14 ×14 mm)
FJ2
16-bit × 8 ch
WDT × 1 ch, watch timer × 1 ch
10 bit × 24 ch
128
144-pin LQFP (20 × 20 mm)
FE2
128 KB/64 KB
128 KB/64 KB
6 KB/4 KB
10-bit × 10 ch
51
64-pin TQFP (10 × 10 mm)
-
V850ES/Fx2
16-bit × 6 ch
WDT × 1 ch, watch timer × 1 ch
CSI × 2 ch, LIN-compatible UART × 2 ch
-
aFCAN
×
1 ch
aFCAN × 2 ch
Dashboard
control
Body control
Car audio
control
On-chip CAN/
On-chip IEBus
Low noise
On-chip meter driver
On-chip LCD driver
On-chip CAN
V850/SB2
5 V low-power version
19 MHz, 100-pin, IEBus
V850/SC2
5 V low-power version
19 MHz, 144-pin, IEBus
V850/SC3
5 V low-power version
16 MHz, 144-pin, FCAN
V850ES/SJ2
3 V low-power version
20 MHz, 144-pin,
On-chip aFCAN/On-chip IEBus
V850ES/SG2
3 V low-power version
20 MHz, 100-pin,
On-chip aFCAN/On-chip IEBus
V850/SF1
5 V low-power version
16 MHz, 100-pin, FCAN
V850/DB1
On-chip meter driver, On-chip DCAN,
On-chip LCD driver,
FJ2
FG2
FF2
V850ES/FE2
64-pin 80-pin 100-pin 144-pin
Large-capacity internal flash, on-chip aFCAN, on-chip LIN, POC/LVI
V850ES/SJx
V850ES/SGx
V850ES/SGx
Peripheral function/
memory capacity
Optimization
Larger capacity
Larger capacity
Pamphlet U15412EJ4V1PF
Application examples
V850ES/Fx2
Dashboard
V850/SF1
Car Audio
Dashboard
Car audio
Battery voltage
(12 V)
Switch inputs
• Mirror fold-in switch
• Left-right switching
switch
• Ignition switch
• Light control switch
•
Courtesy lamp switch
• Door lock switch
Analog input
•
Sensor inputs
• Headlamp control
• Tail lamp control
• Warning indicator
• Power window
(passenger seat)
control
• Power window (rear
right seat) control
• Power window (rear
left seat) control
• Lighting equipment
control
CPU
Serial I/O
LIN controller
CAN controller
General-purpose
I/O
General-purpose
I/O
10-bit A/D
converter
Interrupt
controller
Timer unit
Internal memory
ROM/RAM
V850ES/Fx2
Integrated body control unit
Input interface
Output interface
External I/O interface
Power supply unit
4/8 stage
LCD
Power supply system signal
speaker
Audio system signal
KEY
CD unit
Antenna
ASSP for CD
µPD63761
PLL
Tuner unit
MPX Audio DSP
(or electronic volume)
Microcontroller
(CD control)
RF
DAC
servo DSP
MD unit CAN, IEBus
driver
Power supply detection IC
Automotive communication (CAN, IEBus, etc.)
CD (MD) changer unit
MP3,WMA
µPD703229
V850ES/Kx1
Driver
Microcontroller
(CD control)
V850/SBx,
SF1,SCx
V850ES/Sx2
Microcontroller
(Display/key control)
V850E/
MA1,MA3
Power
amplifier
Battery
(continuous power supply)
ACC
(power supply when engine on)
Regulator
Driver
Power supply block
Display unit
• Dashboard control
module
• Driver seat door
module
• Passenger seat door
V850/SB2
Low EMI noise
Large-capacity memory and large memory selection
ROM/RAM:512K/24KB, 384KB/24KB, 256KB/16KB, 128KB/8KB
On-chip IEBus controller (1 ch)
100-pin QFP/100-pin LQFP
V850/SC2,SC3
Low EMI noise
Large-capacity memory (ROM/RAM: 512 KB/24 KB)
Enhanced peripheral functions for SB1
On-chip IEBus controller (V850/SC2 : 1 ch) ,
On-chip FCAN controller (V850/SC3 : 2 ch max.)
144-pin LQFP
Item
CPU core
Performance
Maximum operating frequency
Internal flash memory
Internal mask ROM
Internal RAM
Power supply voltage
External bus
Timer/counter
Serial interface
A/D converter
D/A converter
DMA controller
Other peripheral
functions
I/O
Power consumption
(mask ROM version, Typ.)
Package
V850/SCx
V850
512 KB
512 KB
24 KB
3.5 V to 5.5 V (mask version)
4.0 V to 5.5 V (flash version)
16-bit × 10ch
WDT × 1 ch, watch timer × 1 ch
CSI × 2 ch, CSI/UART × 2 ch
UART × 2 ch, CSI/I2C × 2 ch
10-bit × 12 ch
-
6 ch (internal RAM-on-chip peripheral I/O)
124
144-pin LQFP (20 × 20 mm)
V850/SB2
V850
22 MIPS (@ 19 MHz)
19 MHz/13 MHz (main clock)
32.768 kHz (subclock)
512 KB/384 KB/256 KB
512 KB/384 KB/256 KB/128 KB
24 KB/16 KB/8 KB
4.0 V to 5.5 V
Address: Multiplexed/separate
Data: 16-bits
16-bit × 2 ch, 8-bit × 6 ch
WDT × 1 ch, watch timer × 1 ch
CSI × 1 ch, CSI/UART × 2 ch
CSI/I2C × 2 ch
10-bit × 12 ch
-
6 ch (internal RAM-on-chip peripheral I/O)
IEBus × 1 ch
ROM correction function
83
125 mW (19 MHz @ 5 V)
100-pin LQFP (14 × 14 mm)
100-pin QFP (14 × 20 mm)
V850/SF1
V850
18 MIPS (@ 16 MHz)
16 MHz
256 KB
256 KB/128 KB
16 KB/12 KB
3.5 V to 5.5 V (mask version), 4.0 V to 5.5 V (flash version)
3.5 V to 5.5 V @ 32.768 kHz
Address: Multiplexed
Data: 16-bit
16-bit × 8ch
WDT × 1ch, watch timer × 1 ch
CSI × 1 ch, CSI/UART × 2 ch
CSI/I2C × 1 ch
10-bit × 12 ch
-
6 ch (internal RAM-on-chip peripheral I/O)
FCAN × 2 ch, ROM correction function
84
75 mW (16 MHz @ 5 V)
100-pin LQFP (14 × 14 mm)
100-pin QFP (14 × 20 mm)
V850/DB1
V850
18 MIPS (@ 16MHz)
16 MHz
128 KB
128 KB
6 KB
4.0 V to 5.5 V
-
16-bit × 3 ch, 8-bit × 2 ch
WDT × 1 ch, watch timer × 1 ch
CSI × 3 ch, UART × 2 ch
10-bit × 8 ch
-
-
meter controlPWM (8-bit) × 24 ch
DCAN × 2 ch
(flash version)
/1 ch (
mask version
)
107
120mW (16 MHz @ 5V)
128-pin QFP (20 × 20 mm)
SC2
21 MIPS (@ 19 MHz)
19 MHz (main clock)
32.768 kHz (subclock)
Address: Multiplexed/separate
Data: 16-bits
IEBus × 1 ch
ROM correction function
120 mW (19 MHz @ 5V)
SC3
18MIPS (@ 16 MHz)
16 MHz (main clock)
32.768 kHz (subclock)
Address: Multiplexed
Data: 16-bit
FCAN × 2 ch
ROM correction function
110 mW (16 MHz @ 5 V)
17
Pamphlet U15412EJ4V1PF
Product Lineup
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Memory Lineup
ROM Size
(bytes)
640K
512K
384K
256K
192K
128K
96K
64K
ROM
less
4K 6K 8K 10K 12K 16K 20K 24K 32K 40K 48K
* : Under development
RAM size (
bytes)
Instruction RAM :
128KB
Flash memory version Mask ROM version
MA2
FE2*
MS1 IK1*
SA1
V853
MA1
IA1 IA4
SV1
SV2 MA3*MA3
SG2
3229Y
SJ2*SJ2
Mask ROM/flash memory version
SJ2*SJ2
SG2*SG2
SC3
SC2
SC1
SB2
SB1
SB2
SB1
SA3
SA2
KG1+*
KG1*
SV1
SF1
SB2
SB1
KF1+*
KF1*
FG2*
FF2*
KJ1
KG1
KF1
DB1
FE2*
FF2*
FG2*
IA2
KE1+*
KE1
SA1
V853
MA1
MS2
MS1 PM1 ME2 ST2*
SA1
KG1
IK1*
KF1
V853
KF1
MS1 KJ1
KG1
MA1
SV1
KG1+*
KJ1+*
IA3
IA4 SA2
SB2
SB1 MA1 SF1
PM1
KJ1*
KJ1+*
MA3*SG2*MA3*
FJ2*
IA3
SV1
SG2*
SJ2*
MA3*FJ2*
FJ2*
FG2*
KF1+*
18
Pamphlet U15412EJ4V1PF
Package Lineup
No. of pins
Type
Size
Pitch
Thickness
Mounted products
121 pins
FBGA (F1)
12×12 mm
0.8 mm
1.13 mm
SA1, SA3
No. of pins
Type
Size
Pitch
Thickness
Mounted products
64 pins
LQFP (GB)
10×10 mm
0.5 mm
1.4 mm
KE1, KE1+
No. of pins
Type
Size
Pitch
Thickness
Mounted products
161 pins
FBGA (F1)
13×13 mm
0.8 mm
1.13 mm
MA1, MA3
No. of pins
Type
Size
Pitch
Thickness
Mounted products
64 pins
TQFP (GB)
10×10 mm
0.5 mm
1.0 mm
FE2
No. of pins
Type
Size
Pitch
Thickness
Mounted
products
100 pins
LQFP (GC)
14×14 mm
0.5 mm
1.4 mm
KG1, KG1+, SA1, SB1, SB2,
SF1, SG2, PM1, FG2, MS2,
MA2, IA2, IA4, V853,
µPD70F3229Y, 703229Y
No. of pins
Type
Size
Pitch
Thickness
Mounted products
180 pins
FBGA (F1)
13×13 mm
0.8 mm
1.13 mm
SV1
No. of pins
Type
Size
Pitch
Thickness
Mounted products
120 pins
TQFP (GC)
14×14 mm
0.4 mm
1.0 mm
ST2
No. of pins
Type
Size
Pitch
Thickness
Mounted products
64 pins
TQFP (GK)
12×12 mm
0.65 mm
1.0 mm
KE1, KE1+
No. of pins
Type
Size
Pitch
Thickness
Mounted products
157 pins
FBGA (F1)
14×14 mm
0.8 mm
0.96 mm
MS1
No. of pins
Type
Size
Pitch
Thickness
Mounted products
100 pins
QFP (GF)
14×20 mm
0.65 mm
1.4 mm
KG1, KG1+, SB1, SB2,
SF1, SG2, IA2, IA4
No. of pins
Type
Size
Pitch
Thickness
Mounted products
80 pins
TQFP (GK)
12×12 mm
0.5 mm
1.0 mm
KF1, KF1+, FF2
No. of pins
Type
Size
Pitch
Thickness
Mounted products
257 pins
FBGA (F1)
14×14 mm
0.65 mm
1.13 mm
SV2
No. of pins
Type
Size
Pitch
Thickness
Mounted products
128 pins
QFP (GJ)
20×20 mm
0.5 mm
1.4 mm
DB1
No. of pins
Type
Size
Pitch
Thickness
Mounted products
64 pins
LQFP (GC)
14×14 mm
0.8 mm
1.4 mm
IK1
No. of pins
Type
Size
Pitch
Thickness
Mounted products
240 pins
FBGA (F1)
16×16 mm
0.8 mm
1.13 mm
ME2
No. of pins
Type
Size
Pitch
Thickness
Mounted products
144 pins
LQFP (GJ)
20×20 mm
0.5 mm
1.4 mm
KJ1, KJ1+, SC1, SC2, SC3,
SJ2, ST2, FJ2, MS1, MA1,
MA3, IA1
No. of pins
Type
Size
Pitch
Thickness
Mounted products
80 pins
QFP (GC)
14×14 mm
0.65 mm
1.4 mm
KF1, KF1+, IA3
No. of pins
Type
Size
Pitch
Thickness
Mounted products
176 pins
LQFP (GM)
24×24 mm
0.5 mm
1.4 mm
SV1, ME2
No. of pins
Type
Size
Pitch
Thickness
Mounted products
100 pins
TQFP (GC)
14×14 mm
0.5 mm
1.0 mm
SA2
19
Pamphlet U15412EJ4V1PF
20
38 MIPS @ 33 MHz
29 MIPS @ 20 MHz
23 MIPS @ 20 MHz
96 MIPS @ 66 MHz
143 MIPS @ 100 MHz
V850E2 CPU cores
200 MHz
V850E2 CPU cores
266 MHz
V850 CPU cores V850ES CPU cores
V850E1 CPU cores
V850E2 CPU cores
215 MIPS @ 150 MHz
43 MIPS @ 32 MHz
V850E2 CPU cores
400 MHz
Under
development
In mass
production
Under
planning
800 to 1000
MIPS
Performance range of
20 to over 300 MIPS
with single instruction set
• Utilization of existing software resources
• Maintenance of real-time performance
• Pursuit of low power consumption
V850 V850E2
Function
CPU Core
Higher performance
High code efficiency
Multiplier
Interrupt responsiveness
5-stage pipeline
Harvard
architecture
2-byte instructions
CISC instructions
Improved pipeline
• Non-blocking load/store instructions
-
Parallel instruction execution (instruction execution in internal ROM)
• Addition of branching/load pipe
• Shift to 3-operand manipulations in 1 slot
Addition of C language compatible instructions
(Switch instruction, Callt instruction,
data conversion instruction,
Prepare/Dispose instruction)
32-bit relative branch instruction
3-operand instruction
Sum-of-products instruction
Bit search instruction
16×16 bits⇒32 bit
multiplication
16×16 bits ⇒32-bit operation
32×32 bits⇒64-bit operation
(32-bit multiply instruction support)
16×16 bits⇒32-bit operation
32×32 bits⇒64-bit operation
Maximum operating frequency
Instructions 47
20/33 MHz
16 MB
V850ES
20/32 MHz
80
16 MB
V850E1
66
⇒
100
⇒
150 MHz
80
64 MB
Maximum program memory space
200
⇒
266
⇒
400 MHz
89
512 MB (internal 128 MB)
4 to 10 clocks
11 to 18 clocks
• 7-stage pipeline
Simultaneous execution
of 2 instructions with 3
pipelines that can
operate independently
from each other
Maximum data memory space
16 MB 16 MB 256 MB 4 GB
CPU Roadmap
CPU Core Function Comparison
Pamphlet U15412EJ4V1PF 21
;;;;
;;;;
;;;;
;;;;
;;;;
;;;;
;;;;
;;;;
;;;
;;;
0.35µm
CB-9VX/VM
0.25µm
CB-10VX 0.18µm
CB-12L 0.18µm
CB-12M
0.13µm
CB-130L
NPB: Peripheral I/O bus
VSB: System bus
iLB: Internal instruction bus
dLB: Internal data bus
V850E2 system
TIMER
UART
PWM
PORT
CSI
etc ...
User circuit (UDL)
UDL1
UDL2
IP
RAM
External bus
Flash
memory SDRAM SRAM I/O
DMAC
NBA85E300
MEMC
NBT85E535
NPB
INTC
QL85E70x Arbiter
VSB
NBA85E2S
CPU
core
VSB
I/F
NPB
I/F
INTC
I/F
Instruction
cache
Data
cache
RCU
JTAG
IE
dLB
iLB
Instruction
memory
Data
memory
JTAG
DCU
V850E2 system configuration example
System LSI Support
V850E1 system configuration example
V850E1 system
NPB: Peripheral I/O bus
VSB: System bus
VFB: Internal instruction bus
VDB: Internal data bus
User circuit (UDL)
UDL1
UDL2
IP
RAM
MEMC
NBT85E500
NPB
VSB
VSB
I/F
NPB
I/F
DMAC
INTC
CPU
Core
DCU
Flash
memory SRAM I/O
JTAG IE
JTAG
VDB
Cache
interface
VFB
Instruction
cache
Data
memory
Instruction
memory
External bus
NBU85ET TIMER
UART
PWM
PORT
CSI
etc ...
Use of same development methods for standard V850 Series products, ASIC microcontrollers
Quick market introduction of standard products
System optimization through shift to system LSIs
CPU core development considering system LSIs
Release of cores that support on-chip debugging
2-stage structure consisting of 32-bit sync system bus & 16-bit async peripheral function bus
Large choice of peripheral function macros
Many supported processes and large range of required performance, and power consumption
Pamphlet U15412EJ4V1PF
22
The V850 Series, which consists of single-chip RISC microcontrollers that use an architecture optimized for embedding, has the following
features.
5-stage pipeline processing
Harvard architecture
32 general-purpose registers
Simple addressing
2-byte basic instruction set
32-bit barrel shifter
Support of CISC-like instructions
Multi-status flags DSP function
Harvard architecture
The V850 Series uses the Harvard architecture, which is designed so that the instruction bus and data bus can operate completely
independently from each other, thereby preventing pipeline operation problems and ensuring efficient instruction execution.
WB
In the case of an architecture other than the Harvard architecture, the MEM stage of
instruction 1 and the IF stage of instruction 4, and the MEM stage of instruction 2
and the IF stage of instruction 5 conflict, causing bus waits. This in turn causes the
pipeline operation to become disordered and lowers the instruction execution speed.
IF ID EX MEM
Instruction1
Instruction2
Instruction3
Instruction4
Instruction5
---:
Idles inserted due to bus wait
WBMEM
MEM
EX
WB
WB
EX
ID
---
---
MEM
ID
IF
WB
EX
---
MEM
---
IF
IDIF
IF ID EX
Pipeline Operation of Non-Harvard Architecture
CPU
Instruction bus
Data bus
Instruction
fetch
External
memory
On-chip
peripheral
I/O
Operand
data access
Internal
RAM
Internal
ROM
BCU
5-stage pipeline processing
ID EX WB
ID EX
MEM
MEM WB
ID EX MEM WB
ID EX MEM WB
ID EX MEM WB
IF ID EX MEM WB
Instruction1
Instruction2
Instruction3
Instruction4
Instruction5
Instruction6
IF : Instruction fetch
ID : Instruction decode
EX : Instruction execution
MEM : Memory access to target address
WB : Write execution result to re
g
ister
Instruction1
completion Instruction2
completion Instruction3
completion
An instruction is executed each clock
Instruction4
completion Instruction5
completion Instruction6
completion
Internal system clock
IF
IF
IF
IF
IF
V850 Series Common Architecture
The V850 Series uses a 5-stage pipeline structure (5 stages from instruction fetch to writeback) that supports simultaneous
processing of 5 instructions, thus enabling the execution of almost all instructions in just one clock.
Pamphlet U15412EJ4V1PF 23
General-purpose register configuration System register configuration
The number of registers can be selected from among 22, 26, and 32 as a compiler option to efficiently execute application programs.
Unused registers can be used as a software register bank for which save and restore processing is not required during interrupt
servicing or task switching, which increases the processing speed.
Software register bank
32 general-purpose registers
The V850 Series provides 32 general-purpose registers. Along with a hardware environment that is ideal for program execution, the
development environment, including compilers, exploits these 32 registers to achieve program generation with superior code efficiency
and execution performance.
0
1000
2000
3000
4000
0
3
6
9
12
Comparison of Performance/Object Efficiency According to Number of Registers
Byte count (bytes) Execution time (s)
Number of registersUsed C program: Servo control module
16 18 20 22 24 26 28 30 32
Byte count Execution time
For example, looking at the program execution time and
code size changes when the number of registers used
by the compiler is changed using the servo control
module, we can see that the larger the number of
registers, the better the program execution speed and
the smaller the code size. However, from about 26
registers, the improvement in terms of execution speed
and code size becomes smaller, and in the
neighborhood of 32 registers, there are no more
changes. This is why the V850 Series has been provided
with 32 registers as the strict minimum requirement.
Address/data variable register
(If real-time OS being used does not use r2)
r0
31
31
Zero Register
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
r20
PC
Name
r0
r1
r2
r3
r4
r5
r6-r29
r30
r31
PC
Application Operation
Zero register
Assembler
reservation
Always holds "0"
Stack pointer
Global pointer
Text pointer
Element pointer
Link pointer
Program counter
Used as working register for
address generation
Used for stack frame
generation during function call
Used when accessing global
variables in the data area
Used as register
for specifying
the beginning of the text area
(program code allocation)
Address/data variable register
Used as base pointer
for address
generation during memory
access
Used during function
call by compiler
Holds instruction addresses
during program execution
Reserved for Address Generation
Stack Pointer(SP)
Global Pointer(GP)
Text Pointer(TP)
Link Pointer(LP)
Element Pointer(EP)
Program Counter
0
0
No.
0
1
2
3
4
5
16
17
18
19
20
6-15, 21-31
EIPC
EIPSW
FEPC
FEPSW
ECR
PSW
CTPC
CTPSW
DBPC
DBPSW
CTBP
Reserved
Application
Supported by
other than
V850 CPU
core products
Register for saving status
during interrupt
Register for saving status
during NMI
Interrupt source register
Program status word
Register for saving status
during CALLT execution
Register for saving status
during exception/debug trap
CALLT base pointer
LDSR
×
×
STSR
×
×: Access prohibited
: Access enabled
LDSR: Instruction to load general-purpose register
contents to system register
STSR: Instruction to store system register contents to
general-purpose register
Operand
Specification
System
Register Name
Register bank
interrupt Program
execution Program
execution
Interrupt servicing
instruction execution
Actual interrupt
servicing time
Normal
interrupt Program
execution Interrupt servicing
instruction execution Program
execution
Actual interrupt
servicing time
User interrupt servicing routine execution time
Total interrupt servicing time
Save the program counter, etc., to a save register.
Execute the interrupt restore instruction. Restore
the program counter value, etc., from the save
register.
Save general-purpose registers to stacks.
Restore general-purpose registers from stacks.
Pamphlet U15412EJ4V1PF
24
The increased amount of address calculations in the CPU in the case of complex addressing causes disturbances in the pipeline
operation. As a result, address calculation becomes a bottleneck for pipeline processing and raising the frequency to increase the
performance becomes difficult. The V850 Series avoids this problem by supporting only simple addressing.
Simple addressing
The V850 Series employs a 2-byte instruction code to perform basic processing to enable compact program development equivalent
to 16-bit CISC microcontrollers.
2-byte basic instruction set
Instruction addresses
Addressing mode
Processin
g
time Processin
g
time
All processing is standardized and efficient
Pipeline processing sequence
Pipeline Processing Time and CPU Operating Frequency
Operating frequency
held back by slow
processing
In case of excessive addressing
In case of simple addressing
Address calculation
Execution
Memory access
Writeback
Instruction fetch
PC
26 2531 0
022 2131 Signed extension disp22
PC 026 2531 0
Memory subject to
manipulation
0
reg1
PC 026 2531
026 2531
0
Memory subject to
manipulation
•Register addressing (register indirect)
Transfer the contents of the general-purpose register specified by the instruction (reg1) to the program counter (PC).
•Relative addressing (PC dependent)
Add 9 signed bits or 22 signed bits of data of the instruction code to the program counter.
reg1 031
disp16 016 1531 Signed extension
Memory subject to
manipulation
reg1 031
disp16 0
16 15
31 Signed extension
Memory subject to
manipulation
•Based addressing
Addressing that accesses
memory, with the sum of the
contents of the general-
purpose register (reg1) and
16-bit displacement (disp16)
as the operand address.
•Bit addressing
Addressing that accesses 1
bit of 1 byte of the memory
space, with the sum of the
contents of the general-
purpose register (reg1) and
16-bit displacement (disp16)
that has been sign extended
to word length as the
operand address.
Operand addresses
•Register addressing
Addressing that accesses the general-purpose register specified by the general-purpose specification
field or a system register as an operand.
•Immediate addressing
Addressing of 5-bit data or 16-bit data for manipulation in the instruction code.
1.03
1.02
1.48
1.00
Object Code Size Comparison
(Dhrystone 1.1/Large model)
16-bitV(CISC)
78K4(CISC)
V850(RISC)
V
R
/MIPS
TM
32(RISC)
•Improved object efficiency through ROMization programming
Application of 2-byte instructions to all basic processing, consisting of load, store, arithmetic/
logic operations, and branching.
•To realize ease of use, restrictions on 16-bit fixed-length instructions are partially
removed through incorporation of 32-bit instructions.
•Bit manipulation instructions, etc.
Pamphlet U15412EJ4V1PF 25
32-bit barrel shifter
V850 Series can realize bit manipulations frequently used during signed data and image data processing in 1 instruction per clock.
Object size
Execution time
Coding example
Item
4 bytes
4 clocks 4 clocks 8 clocks
When Used When Not Used
set1 6, ASIM00[r0] ld.b ASIM00[r0], r20
ori 0x0040, r20, r20
st.b r20, ASIM00[r0] Save r20
Restore r20
add -4, sp
st.w r20, 0[sp]
ld.b ASIM00[r0], r20
ori 0x0040, r20, r20
st.b r20, ASIM00[r0]
ld.w 0[sp], r20
add 4, sp
12 bytes 24 bytes
Bit Manipulation
Instruction
CISC Microcontroller V850
Other Manufacturer's RISC Microcontroller
cmp/eq #0, r10
bt ZERO
cmp/pl r10
bt PLUS
bra MINUS
nop ;
For delay branching
cmp 0, r10
bz ZERO
bgt PLUS
br MINUS
cmp ax, 0
jz ZERO
jgt PLUS
jmp MINUS
• Easy recording with assembler
• Improved object efficiency and execution speed
Example: Program that branches to positive/negative/zero according to register contents
V850
General-purpose register CPU
DSP
Memory
MUL
INT
CPU
ALU
CPU+DSP
MUL
SAT
flag
ALU
Number of instructions41
V850
Number of execution clocks41
Example: 27-bit logical right shift
SHR 27, Rn
Other manufacturer's
RISC microcontroller
SHR16 Rn
SHR8 Rn
SHR2 Rn
SHR Rn
Processing sequence
Example: Setting (1) bit 6 of ASIM00 register
CISC-like instructions for embedding (bit manipulation instructions)
The V850 Series supports bit manipulation instructions suitable for flag manipulation on I/O registers, which play a large role in
embedding control.
• Improvement of operability of memory mapped I/
Os for control purposes
• Manipulation of any 1 bit of byte data in the
memory space
• Provision of test (tst1)/set (set1)/clear (clr1)/invert
(not1)
• Effective for reducing object size and execution
time since flags can be manipulated in 1-bit units
with 1 instruction
ZERO : Zero processing
PLUS : Positive processing
MINUS : Negative processing
Multi-status flags
In the V850 Series, calculation results are reflected in registers as status flags. As a result, delay branching such as can be seen in
the RISC microcontrollers of other manufacturers does not occur and programs can be coded with the same feel as CISC
microcontrollers.
DSP function
The V850 Series provides a DSP function for executing high-speed calculations and product-sum operations indispensable for digital
signal processing such as image and speech processing.
• Direct data handling via general-purpose registers
• Realization of digital signal processing through general-
purpose CPU
• High-speed 16-bit (V850, V850ES CPU), 32-bit (V850E1
CPU) multiply/sum-of-products
(Multiply: 1 to 2 clocks, sum-of-products: 3 clocks)
• Effective for filter operations and matrix operations for
feedback calculations in speed, position, and other servo
control.
• Shifting of any number of bits (0 to 31) executable in 1 instruction per clock
Improved execution speed/object efficiency
Effective for extracting arbitrary bit lengths of image data and signed data
(extracting code during MH/MR/MMR encoding, etc.)
Pamphlet U15412EJ4V1PF
26
IF
WB
br/sld
Pipeline
ID WB
Master Pipeline
(V850 CPU compatible)
Async WB Pipeline
Address
calculation stage Load, store buffer
(1 stage each)
ID DF
MEM
EX
IF (Instruction fetch) : Fetches instructions and increments the fetch pointer.
ID (Instruction decode) : Decodes instructions, creates immediate data,
and reads registers.
EX (ALU, multiplier, barrel shifter execution) : Executes decoded instructions.
MEM (Memory access) : Accesses memory of corresponding addresses.
WB (Writeback) : Writes execution results to registers.
DF (data fetch) : Transfers execution data to WB stage.
WB
Load
instruction
EX
V850E1 CPU
Next
instruction
ADD
instruction
Load
instruction
Next
instruction
ADD
instruction
MEM (external memory)
T1 T2 T3
Pipeline is stopped until MEM stage complete
Effective pipeline processing that uses the Async WB Pipeline when
appropriate, according to the instruction.
IF ID EX
Conventional (V850 CPU)
WBMEMIF ID
WB(MEM)EXIDIF
WB
WB
DF
MEM
EXIF ID T1 T2
MEM (external memory)
WB
IF EXID
IF ID EX
Conventional (V850 CPU)
EX
Branch
instruction
Branch
instruction
Branch destination determined in EX stage
MEM WB
V850E1 CPU
Branch destination
instruction
Branch destination
instruction
MEM
IF ID
IF ID EX WB
MEM
MEM WBIF ID
IF ID EX WB
Branch destination determined in ID stage
1-clock reduction
ADD instruction
(16-bit length)
V850E1 CPU
Next instruction
Branch instruction
(16-bit length)
ADD instruction
Next instruction
Branch instruction WBMEM
WBMEM
WBMEM
IF ID EX WB(MEM)
ID EX
Conventional (V850 CPU)
IF ID EX MEM
IF ID EX WBDF
ID
IF ID EX
2-clock reduction
Conventional
(V850 CPU)
V850E1 CPU
add r22(src2), r20(src1), r21(dst)
mov r20(src2), r21(dst)
add r22(src2), r21(dst)
• Sequence from mov to arithmetic
instruction is detected in the ID
stage, and if dst is the same, the
next manipulation is performed.
src1 : Replace with src2 of mov
src2 : src2 of arithmetic instruction
dst : As is
• mov + add instructions executable in
1 clock
• Improved bus use efficiency
• Shorter interrupt insensitivity period • 2-clock branching
• Parallel execution of instructions • Improved absolute performance
• Example: Synchronous processing
of mov + add
• Improved code efficiency
•
10 to 15% improvement in object
efficienc
y
mainl
y
when C com
p
iler used
Non-blocking load/store
Addition of branch/load pipes
Shift to 3-operand manipulations in 1 slot
Addition of high-level language-compatible instructions
* The next branch instruction code is also fetched due to the internal 32-bit bus.
The V850E1 and V850ES cores achieve high performance and higher code efficiency through the implementation of the following
improvements to the V850 CPU core.
Pipeline configuration
Addition of branch/load pipes
•Pipeline operation with branch instruction
Shift to 3-operand manipulations in 1 slot
Non-blocking load/store
•Parallel instruction execution (when executed by internal ROM)
The V850E1 and V850ES cores have enhanced the instruction
set of the V850 core as follows.
switch (2 bytes)
• C language switch statement processing
converted into instruction
callt (2 bytes)/ctret (4 bytes)
• Table-reference branching
• Reducing size of call code that frequently
appears
Data conversion instructions (2 bytes)
• char, short type cast executed with 1
instruction
• sxh, sxb, zxb, and zxh instructions
prepare/dispose (4 bytes)
• Function start/end processing executed
in 1 instruction
unsigned Load
• Reduction of unsigned manipulation code
mov imm32, reg (6 bytes/2 clocks)
• Reduction of address setting code
mul/mulu (4 bytes)
• Reduction of array address calculation
• Improvement of sum-of-products
performance
Other
• Bit manipulation (register indirect bit
specification)
• cmov (Conditional Move), divide (div/divu/
divhu)
• sasf, endian conversion
Addition of high-level language compatible instructions
V850E1, V850ES Architecture
Pamphlet U15412EJ4V1PF 27
......................................
............................
......
.................
.................................................
............................................................
......
.................
............................
......................................
.................................................
............................................................
Instruction 2
completion Instruction 4
completion Instruction 1
Instruction 6
completion
Instruction 3
Instruction 8
completion
Instruction 5
Instruction 10
completion
Instruction 7
Instruction 12
completion
Instruction 9
completion
Instruction 11
completion
Instructions executed at each clock
Instruction1
Instruction2
Instruction3
Instruction4
Instruction5
Instruction6
Instruction7
Instruction8
Instruction9
Instruction10
Instruction11
Instruction12
Time flow
Internal system clock
Processing simultaneously
performed by CPU
<1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> <12>
IF DP ID
EX WB
EX AT WB
DF
ID
IF DP ID
EX WB
EX AT WB
DF
ID
IF DP ID
EX WB
EX AT WB
DF
ID
IF DP ID
EX WB
EX AT WB
DF
ID
IF DP ID
EX WB
EX AT WB
DF
ID
IF DP ID
EX WB
EX AT WB
DF
ID
V850E2 core features V850E2 core Main added functions
Execution of up to 2 instructions/clock possible (dependent on instruction set)
V850E2 Architecture
V850E2 core CPU pipeline operation
Register file
Instruction memory, instruction cache
Instruction execution
pipeline left (Lpipe)
BSFT
unit
ALU
unit
ALU
unit
MEM
unit
MUL
unit
Data memory, data cache
Instruction fetch pipeline (Fpipe)
Instruction fetch unit (Bpipe)
Instruction buffer
Dispatch unit
Instruction execution
pipeline right (Rpipe)
Instruction
decode unit R
Instruction
decode unit L
Write back unit
2 instructions simultaneously executable using 2 instruction execution units
V850E2 core CPU pipeline configuration
Real-time performance of 250 MIPS
- Operation at over 200 MHz
Inheritance of V850E1 performance and features
- Upward instruction compatibility with V850E1 and V850ES
cores at object level
- Use of 7-stage pipeline
- Parallel pipeline configuration (2 parallel superscalar)
- 128-bit instruction fetch bus
Support of expanding application software sizes
- Address space (program/data) expansion
- Strengthened cache memory support
32-bit relative branch instruction
- Support of program space expansion
-
Long-distance branching performance, elimination of code efficiency losses
3-operand instructions (addition of target operations)
- Higher speed processing of operations such as multiplex
add/subtract (64-bit operation, saturate operation) and bit
shift, contributing to higher code efficiency
Sum-of-products instruction
-
Higher speed 32-bit sum-of-products operation (32 × 32 + 6464 bits)
Bit search instruction
- Bit row change point search for run length measurement,
contributing to increased speed of conversion from
integers to floating decimals, etc.
IF : Instruction fetch
DP : Dispatch
ID : Instruction decode
EX : Instruction execution
AT : Address transfer
DF : Data fetch
WB: Writing execution result to register
Pamphlet U15412EJ4V1PF
28
Products: V850E/MA1, MA2, MA3, ME2
SDRAM connectable without external circuit
CAS latency: 2, 3 supported
CBR (automatic) refresh: Self refresh supported
Products: V850/SA1, SB1, SB2, SV1, SF1, SC1, SC2, SC3
Transfer targets: Internal RAM-on-chip peripheral I/O
Transfer mode: Single
Transfer units: 8/16 bits
Transfer clock: 4 clocks Min.
Number of transfers: 256 Max.
CPU core
On-chip
peripheral I/O
Internal
RAM
On-chip peripheral bus
Internal bus
DMA
Transfer source address
8/16bit-data
Transfer destination address
Number of transfers
Products: V850ES/SA2, SA3, SG2, SJ2, KG1+, KJ1+, FG2, FJ2
µPD703229Y, 70F3229Y
T ransfer targets: Memory-peripheral I/O, memory-memory
Transfer mode: Single
Transfer units: 8/16 bits
Transfer type: 2-cycle transfer
Number of transfers: 65536 Max.
CPU core
DMA
Data control
Address control
Count control
Channel control
Bus interface
External I/O
External RAM
Internal RAM
On-chip peripheral I/O
External ROM
8/16 bit
bus
DMA controller (provided in V850ES products)
A0-A11
A12, A13
DQ0-DQ15
CLK
CKE
CS
RAS
CAS
LDQM
UDQM
WE
64 Mb SDRAM
(1 Mword × 16 bits × 4 banks)
A1-A12
A21, A22
Note
D0-D15
SDCLK
SDCKE
CSn
SDRAS
SDCAS
LDQM
UDQM
WE
V850E/MA1
Note The address signal used differs depending on the SDRAM product.
CPU core
DMA
Data control
Address control
Count control
Channel control
Bus interface
External I/O
External RAM
Internal RAM
On-chip peripheral I/O
External ROM
8/16 bit
bus
SDRAM controller
DMA controller (provided in V850E products)
DMA controller (provided in V850/Sxx products)
Memory Access Functions
Products: V850E/MA1, MA2, MA3, MS1, MS2, IA1, IA2, IA3, IA4,
ME2, SV2
Transfer targets: Memory-peripheral I/O, memory-
memory
Transfer mode: Single, single step, block transfer
Transfer units: 8/16 bits
Transfer type: 1-cycle transfer, 2-cycle transfer
Number of transfers: 65536 Max.
Pamphlet U15412EJ4V1PF 29
Products: V850ES/KG1, KJ1, KG1+, KJ1+, SA2, SA3, SG2,
SJ2, V850E/MA3, V853
R-2R ladder method (except for V850ES/SA2, SA3)
R string method (V850ES/SA2, SA3 only)
8-bit resolution
Operation mode: Normal mode/real-time output mode
Products: V850E/MA1, MA3, ME2, IA1, IA2, MS1, SV2,
V850/SV1, V853, etc.
Conversion startable by software or hardware
8 on-chip conversion result registers (24 for SV2)
Select/scan mode switching possible
A/D converter (multi-stage buffer type) D/A converter
ANI0
ANIn
ADTRG
AVREF
AVSS
INTAD
Successive approximation
register
Conversion control circuit
Conversion result register 0
Conversion result register 1
Conversion result register 2
Conversion result register 3
Conversion result register 4
Conversion result register 5
Conversion result register 6
Conversion result register 7
Selector
Tap selector
Resistor string
∆ΣA/D converter
Products: V850ES/PM1
High-accuracy 16-bit resolution
Sampling frequency selector (4.340 kHz/2.170 kHz)
Support of up to 3 lines and 4 phases through multiple
input channels
;;
;
;
ANI00
ANI01
;;
Reference
generator
Internal system
clock
AVREFIN
;;
VREF
buffer
;;
ANI20
ANI21
;;
;;
ANI40
ANI41
;;
ANI10
ANI11
;;
ANI30
ANI31
;;
;;
ANI50
ANI51
CPU
Analog block Digital block
;
;
INTAD
;
;
Internal reset
signal
AVDD
AVSS
Internal bus
Digital
filter
(LPF)
Digital
filter
(HPF)
Register & selector
∆Σmodulator∆Σmodulator
AVREFOUT
ANO0
AVREF1
AVSS
Conversion value
setting register 0
Conversion value
setting register 1
R-2R ladder or
R string
R-2R ladder or
R string ANO1
ANIn0
Input circuit
ADTRGn
TTRGn0
TTRGn1
AV
DD
AVSS
AMP
ANIn1
AMP
ANIn2
AMP
ANIn3
CMPREF
INTCMPn
CMP
CMP
CMP
INTADn
A/Dn conversion
result register m
(ADAnCRm/ADAnCRmH)
Array
Sample & hold
circuit Voltage
comparator
Edge detection/noise
elimination circuit
Control circuit
Selector
Selector
Successive
approximation
register (SAR)
Analog Circuits
High-speed A/D converter
Products: V850E/IA3, IA4
Simultaneous 10-bit A/D converter sampling for 2 circuits
On-chip operational amplifier (2.5 ×/5 ×) for input level
amplification
On-chip overvoltage detection comparator
Pamphlet U15412EJ4V1PF
30
Products: V850E/IA1, IA2, IA3, IA4, MA3, ME2
16-bit 2-phase encoder input possible
Compare registers: 2
Capture/compare registers: 2
Up/down counter
TCLR
TIUD
TCUD
Capture/compare
register
Selector 16-bit up/down counter timer
Compare
register
Compare
register
CLR
circuit
INTCC
0
INTCC1
INTCM
0
INTCM1
TO
Edge
detection
circuit
Output
control
Capture/compare
register
Timer/Counter
Products: V850ES/SA2, SA3, PM1
On-chip week, day, hour, minute, second counters
Counting up to 4095 periods
Support of interval interrupt generation at fixed intervals
selectable from: 0.015625 s, 0.03125 s, 0.0625 s, 0.125 s,
0.25 s, 0.5 s, 1 s, 1 mn, 1 hr, 1 day
Real-time counter
INTROV
Prescaler
3
Subcount
register
(15 bits)
INTRTC
Week
count
register
(12 bits)
1 s
0.015625 s/0.03125 s/0.0625 s/0.125 s/0.25 s/0.5 s
Count clock
= 32.768 kHz
6
1 mn 1 hr 1 day
Selector
Selector
fXT
fBRG
Count enable/
disable circuit
Internal bus
Minute
count
register
(6 bits)
Hour
count
register
(5 bits)
Day count
register
(3 bits)
Second
count
register
(6 bits)
Second count
specification
register
Minute count
specification
register
Hour count
specification
register
Day count
specification
register
Week count
specification
register
Products: V850E/SV2
32-bit timer unit for servo control
Capture registers: 12
Compare registers: 2
External input detection circuit with 1 to 256 dividers
On-chip 8-bit mask timers: 2
32-bit servo timer
Selector
Clear & count
control
TM3
(32-bit)
CP3x
(32-bit)
CP3y
(32-bit)
CP3z
(32-bit)
CM30
(32-bit)
CM31
(32-bit)
INTOV3
INTTI3
ICP3x INTCP3x
Capture
Clear
CPTTRGx
INTCP3y
Capture
INTCP3z
Capture
INTCM30
Match
INTCM31
Match
Mask
timer
EDVCMx
EDVCMy
TRGx
SLCLK
TI3
TI3
Divider
Noise elimination
Edge detection
Noise elimination
Edge detection
2ch (x=0-1)
ICP3y
TRGy Divider
Noise elimination
Edge detection
2ch (y=2-3)
ICP3z
TRGz
Noise elimination
Edge detection
8ch (z=4-11)
{
fxx-fxx/8 (4)
fxx
A/D trigger
Output
control
TMQOP
16-bit capture/compare
Interrupt signal
Interrupt signal
Clear
INTOVF
control
Interrupt signal
Interrupt signal
16-bit capture/compare
16-bit capture/compare
TMQ
TMP
16-bit capture/compare
Timer Output
A/D capture timing generation
Output duty generation
Sync start supported
TM output
control
6-phase
PWM
output
controller
A/D operation
trigger control
16-bit counter
U
U
V
V
W
W
Timer Output
Timer Output
Output period generation
Timer configuration during inverter control
Products: V850E/IA3, IA4, MA3, V850ES/IK1
0% and 100% output and 6-phase PWM output with
deadtime possible
Switchable anytime/batch overwrite for compare register
A/D converter conversion start trigger generator
Pamphlet U15412EJ4V1PF 31
Products: V850E/SV2, V850ES/KF1, KG1, KJ1, KF1+,
KG1+, KJ1+
32-byte internal buffer RAM
Automatic send/receive function
•1 to 32 bytes of transfer bytes specifiable
•Transfer interval specifiable (0 to 63 clocks)
•Single transfer/repeated transfer specifiable
SIAn
DIRn
Internal bus
SOAn
INTCSIAn
f
xx
/6-f
xx
/256
MASTERn
Automatic data transfer
address count register
Automatic data transfer address
point specification register
Serial clock
counter Interrupt
generator
Selector
Buffer RAM
(32 bytes)
Serial I/O
shift register
SCKAn Serial transfer
control circuit
6-bit counter
Automatic data
transfer interval
s
p
ecification re
g
ister
Port configuration for LIN reception
LIN reception pin
External interrupt pin
Timer input pin
Timer
SBF automatic detection
Reception
circuit
Edge detection
interrupt
Flag
Selector
Wakeup detection
Capture input
Flag
Selector
Baud rate error detection through capture timer
Timer output selectable as source clockAny baud rate selectable
LIN transmission circuit
LIN
transmission pin
Timer output selectable as source clock
Any baud rate selectable!!
SBF automatic transmission
Selector
Flag
Timer
Transmission
circuit
Able to invert output
Internally connectable by software,
so external connection not required!
LINBus
Serial interface with automatic send/receive function
Serial Interface
Interrupt
request
CRXD
CTXD MAC
(Message
Access
Controller)
Control
circuit
CAN module
CAN RAM
(message buffer)
CAN protocol
transfer block
Products: V850ES/SG2, SJ2, FE2, FF2, FG2, FJ2,
V850E/IA1, V850/SF1, SC3, DB1
CAN protocol ver. 2.0 Part B (send/receive of standard and
extended frames)
Max. transfer rate: 500 kbps (V850/DB1 only) 1 Mbps
32 message buffer
CAN
Products: V850ES/SG2, SJ2, V850/SB2, SC2
Communication mode 1 supported
Max. transfer bytes: 32 bytes/frame
Max. transfer speed: Approx. 17 kbps
IETX
IERX
Interrupt
request
Register block
Control block
Bit
controller Field
controller
Transmission
block
Reception
block
IEBus controller
Products: V850ES/KE1+, KF1+, KG1+, KJ1+, SG2, SJ2,
µPD703229Y, 70F3229Y, V850ES/FE2, FF2, FG2, FJ2
Low-cost 1-line network bus
Sync break field (SBF) send/receive possible through
hardware
(Send: 13 bits ≤ SBF ≤ 20 bits; Receive: SBF ≥ 11 bits)
Also generally usable as UART
Pamphlet U15412EJ4V1PF
32
Products: V850E/ME2
Compliant with Universal Serial Bus Specification
Support of 12 Mbps (full speed) transfer
Many endpoint configurations
Products:
V850 core :V850/SB1, SB2, SV1, SF1, SC1, SC2, SC3
V850E, V850ES cores :V850ES/SA2, SA3, SG2, SJ2, KE1,
KF1, KG1, KJ1, KE1+, KF1+, KG1+,
PM1, IK1, µPD703229Y, 70F3229Y,
V850E/MA3, SV2, IA3, IA4
Instructions of address to be modified inserted to replace
DBTRAP instruction (JMP r0 instruction in case of V850
core), branching to 0060H (0000H in case of V850 core)
Program modification following switch to mask ROM possible
Modified addresses: 4 points, 8 pointsNote
Note V850E/SV2
Note JMP r0 instruction in case of V850 core
Other
USB function 0 DMA
channel select
register (UF0CS)
USB function 0 buffer
control register (UF0BC)
UFDRQn
DMAAKn
TCn
USBSP2B
USBSP4B
INTUSB0B
INTUSB1B
INTUSB2B
INTRSUM
fUSB(48 MHz)
Remark n = 0 to 3
Selector
UDM
UDP
USB
I/O Buffer
Control transfer: Endpoint0R (64 bytes)/Endpoint0W (64 bytes)
Bulk transfer 1: Endpoint1 (64 bytes × 2)/Endpoint2 (64 bytes × 2)
Bulk transfer 2: Endpoint3 (64 bytes × 2)/Endpoint4 (64 bytes × 2)
Interrupt transfer1/2: Endpoint7 (8 bytes)/Endpoint8 (8 bytes)
Endpoint
SIE
RSUM_OUT
USB SSCG function
(Spread spectrum Frequency Synthesizer Clock Generator)
ROM correction function Explanation of ROM correction operation
Download
modification
program
Correction
address enable
setting information
ROM correction
request flag = 0?
Yes
No
Read modification
program to RAM
Correction address
setting
ROM correction enable
Replace DBTRAP
instruction
Note
Main routine
Normal flow
ROM correction flow
Internal ROM
External ROM,
EEPROM, etc.
Internal RAM
Return to
internal ROM
Modification
program execution
RESET
Jump to
modification program
ROM correction
request flag clear
Correction address = XXXX
ROM correction
enable flag = 1
Next processing...
Correction point
Initialization
Modification
program download
Comparator
Output trigger
control circuit
DBTRAP instruction
Note
generation block
Internal ROM
Instruction
replacement part
Instruction data bus
ROM correction
address register
Instruction address bus
Products: V850E/ME2
EMI peak noise reduction through input frequency
modulation
Large reduction in noise countermeasure time and cost
possible
Frequency modulation rate and modulation period
changeable by register setting
Modulation period
Without frequency modulation
With frequency modulation rate of -3%Modulation period: 13 to 27 kHz
Improvement of
10 dB or more
Frequency
modulation rate
Note JMP r0 instruction for the V850 core
Pamphlet U15412EJ4V1PF 33
V850 Series
Series
Flash
Target system
On-chip debug emulator
N-Wire CARD
(IE-V850E1-CD-NW)
Notebook PC
•Break function
•Execute function
•Pin mask function
•Flash programmer function
•Execution time measurement
•Non-use of user resources
Clock monitor function
On-chip debugging function Boundary scan function
Main clock Internal reset signal
Ring oscillator clock
reset
enable
Flag
Reset upon abnormal stop
Main clock oscillation monitoring
Run/stop settable by software
+
---
Reference
voltage Flag
Interrupt signal
VDD
VDD
Reset signal
Selector
Detection level selection
ResistorResistorResistor
Products:
V850ES/KE1+, KF1+, KG1+, KJ1+, SG2, SJ2,
µPD703229Y, 70F3229Y, V850ES/FE2, FF2, FG2, FJ2, IK1
Detection voltage level changeable by software
Usable instead of reset IC, contributing to lower system cost
Detection voltage not changeable after mode transition
(security protection)
Products:
V850ES/KE1+, KF1+, KG1+, KJ1+, SG2, SJ2,
µPD703229Y, 70F3229Y, V850ES/FE2, FF2, FG2, FJ2, IK1
Monitors abnormal stops of main clock with internal Ring- Oscillator
During abnormal stop, entire system can be set to reset status
Prevention of destruction due to system deadlock or runaway
Products: V850E/ME2Note, V850E/MA3, IA4, SV2,
V850ES/KJ1, KJ1+, SG2, SJ2, FE2, FF2, FG2,
FJ2, µPD70F3229Y
Realization of on-chip debugging of microcontroller with DCU
(Debug Control Unit)
Compact and low-cost PC card-type emulator
Flash programmer function
Integrated debugger (ID850) supported
Note Trace function support is possible by using the RTE-2000-TP
made by Midas Lab Co., Ltd., or PARTNER-ET II, PARTNER-J
made by Kyoto Micro Computer Co., Ltd.
Products: V850E/SV2
Use of JTAG (Joint Test Action Group) communication
specifications, IEEE1149.1 compliant
Progressive scan of device’s external I/O pins, test data input/
output possible
Connection check of devices soldered on user board possible
TCS
TDI
I/O
I/O
I/O
I/O
TMS
TRST
TDO
Bypass register
Instruction register
Decoder
Internal logic
Selector
Selector
TPA controller
Boundary scan register
: Boundary scan target pin
: JTAG interface pin
: Boundary scan cell
Low-voltage detection circuit (LVI)
Pamphlet U15412EJ4V1PF
34
V850ES-20 MHz
A 16bit 20 MHz
A 16bit 16 MHz
B 32bit 50 MHz
V850ES-20 MHz
A 16bit 20 MHz
A 16bit 16 MHz
B 32bit 50 MHz
10 2345
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
4.1
1.7
1.0
3.6
0.97
1.00
1.37
1.18
Performance comparison
Code size comparison
(Relative comparison)
(Relative comparison)
* NEC Electronics measurement results usin
g
sam
p
le
p
ro
g
ram
Cycle time 0.2 µs 0.4 µs
78K0S
78K0
78K0/Kx1
V850ES/Kxx
0.24
0.20
0.05
0.40
78K4 0.125
32-bit RISC
16-bit CISC
8-bit CISC
: 12 MHz (0.168 µs) supported for some products
: 10 MHz (0.2 µs) supported for some products
Minimum instruction execution time V850 Series performance
Clock gear function Standby mode
Consumption
current
fxx/8
(2.5 MHz)
fxx
(20 MHz) fxx/32
(625 kHz) f
XT
(32.768 kHz)
Operating
frequency
Reduction to 1/400
through switch from main
clock to subclock
Reduction to 1/10th
through clock gear (1/32)
Reduction to 1/5th
through clock gear (1/8)
CPU Sub
Oscillation circuit
or
or
Consumption current
Normal
operation mode
HALT mode
IDLE mode
Sub normal
operation mode
Sub IDLE mode
STOP mode
(sub operation)
STOP mode
(sub stop)
Approx. 1/2
Approx. 1/10
Approx. 1/400
Approx. 1/4000
Approx. 1/4000
Approx. 1/15000
Operating Stopped
Peripheral
function
Watch
timer
Main
V850 Series Benchmark
The V850 Series realizes high speed, high performance, and high code efficiency.
Low Power Consumption
Thanks to thorough energy-saving design, a superior current/performance ratio of 1.1 to 0.7 mA/MIPS is realized, particularly for V850ES
and V850/Sxx products. As a result, a reduction in power consumption to 1/5 or less compared to 16-bit CISC microcontrollers of similar
performance is realized. Lower system power consumption and higher performance are simultaneously realized through this extremely
high power performance.
Power performance
;;
;;
0
5
10
Consumption current/performance
mA/MIPS
9.2 mA/MIPS
8-bit CISC
16-bit CISC
V850/SV1 V850/SB1
V850/SA1
7.3 mA/MIPS
1.1 mA/MIPS
1.1 mA/MIPS 0.9 mA/MIPS
0.7 mA/MIPS
Realization of low consumption current that is
1/5 or less compared to 16-bit CISC of similar performance
V850ES/SA2, 3
Pamphlet U15412EJ4V1PF 35
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Noise
[dBm]
70 75 80 85 90 95 100 105 110 115 120
Fre
q
uenc
y
[
MHz
]
Existing 78K0
V850ES/KJ1
Power supply voltage 5V
Operating frequency 78K0 10MHz
V850ES/KJ1 16MHz
EMS countermeasures
EMS measurement results (power supply coupling measurement)
EMS noise measurement results
Voltage control
oscillator
To CPU
peripheral
functions
Oscillation
circuit
Phase comparator
LPF VCO
Divider
Use of PLL for oscillation circuit
High-frequency noise cut
through PLL filter
2.0 kV or higher1.0 kV0 kV
V850ES/KJ1
Existing V850 products
(PLL-less products)
Existing V850 products V850ES/KJ1 (flash version)
V
DD
=5 V
Resonator: 4 MHz
Internal operation frequency: 16 MHz
(PLL = ON)
V
DD
=5 V
Resonator: 16 MHz
Internal operation frequency: 16 MHz
Noise application
voltage
Minimizing the influence of electromagnetic interference (EMI) emitted from the microcontroller and the influence of noise applied to the microcontroller
(EMS) is a high priority, particularly for AV equipment such as car audio systems, and thus superior noise performance is required of microcontrollers.
Various noise countermeasures are implemented in the V850 Series, and noise performance equivalent or superior to that of 16-bit products has been
realized.
Low Noise Countermeasures
CPU power supply separation Insertion of capacitance
between VDD and GND
Vport
Vcpu
GNDport
GNDcpu
I/O
PORT
Reg. (OFF setting possible)
CPU OSC
AMP
Port power
supply separation
Due to the relation between the power supply and GND pad positions and the lead frame, placement is done so as to lower the power supply impedance.
EMI noise countermeasures: Power supply circuit countermeasures
Pamphlet U15412EJ4V1PF
36
Next-generation processors
V850 Series RISC
Platforms
IP vendors
Standards
Original NEC
technologies
Planning
Middleware development
Solution development
System
design
Development
Mass
production
System proposal
Demo systems
Evaluation systems
Consultation
Performance
verification
Integration
Customization
Maintenance
Customers Development support system
An increasing number of processors optimized for various systems and
based on NEC Electronics' original technology and the superb
technology of third parties, as well as other technologies that have been
established as standards, are being deployed from.
Shift to middleware accelerating deployment to
optimum processors
Middleware Performance Power (MIPS) ROM RAM
JPEG QVGA×24 : Enc0.32s/Dec0.24s --- 17.5 KB 15 KB
G.726 (ADPCM) 32Kbps, 16Kbps Enc8/Dec8.2 9 KB 80 B
Speech recognition 0.4s 19 (20 words) 82 KB 3.5 KB
(small vocabulary) 63 (100 words) (15 words)
Middleware plays a major role for maximizing processor performance and realizing high-speed processing of complex data with flexibility
and ease.
NEC Electronics offers a large array of middleware that is optimized for the CPU architecture and importantly contributes to sh ortening
development time, while also facilitating additions and changes to dedicated functions whose implementation as hardware for devices,
etc., used to have high cost and time requirements, and the creation of user-friendly interfaces.
Middleware performance list
V850 Series Middleware List
Realization of latest technology
and functions
Shortening of
development time Reduction in
development cost
Easy performance enhancement
and function expansion
Easy creation of
user-friendly interface
Multimedia processing
realizable just with CPU
Realization of higher
reliability and quality
Dedicated device development
not required
Maximization of system
added value
Middleware merits:
Category
Image JPEG
MPEG-4/H.263 Video
Speech Text To Speech Japanese
Speech CODEC G.723.1 Annex A/C
G.726 (ADPCM)
G.729 Annex A/B
AMR
MPEG-4 CELP
Acoustic echo canceller (for hands-free operation)
AEC
Noise suppressor 3GPP-NS
Sound Audio decoder AAC
MP3
WMA
Sound generator for cellular phone ringer melody
Middleware V850
Series Category
Recognition Speech recognition
Japanese (large vocabulary)
Japanese (small vocabulary)
Chinese (small vocabulary)
English (small vocabulary)
Handwriting recognition
Japanese (input frame required)
Japanese (input frame not required)
Security Encryption CIPERUNICORN
Fingerprint recognition
Internet TCP/IP
Storage
PC-compatible file system
Middleware V850
Series
: Development completed
Middleware product list
Pamphlet U15412EJ4V1PF 37
LPF
Mike amp
V850/SA1
(Internal 20 MHz)
Internal ROM
A/D (1 ch)
Internal RAM
•Conforms to JPEG international standard
Conforms to DCT baseline process (non-reverse coding)
•Versatile compression and decompression processing
<Compression functions>
•User-customizable VRAM input module
•User-specified Huffman and quantization tables
•APPn marker insertion
•Compression suspend function
<Decompression processing>
•User-customizable VRAM output module
•Support of various JPEG markers (DRI, RSTn, DNL)
•Decompression suspend function
Speech recognition is realized on a single chip using the memory and peripheral I/Os in the V850 Series. Ideal for applications such as
games and home appliances that must feature speech recognition but are subject to large restrictions.
•Realization of speech recognition using only memory and
peripheral I/Os contained in V850 Series
•Expansion of number of recognized words
•Realization of speech recognition with memory and peripheral
I/Os contained in V850 Series
•Expansion of number of recognized words
Recognized number of words: 30 words (in case of V850/SA1, 20 MHz)
•Speech recognition
evaluation system
NEC Electronics provides an environment
allowing easy evaluation for the introduction of
speech recognition.
For details and the purchasing method, consult
your NEC Electronics sales representative.
Expansion of number of recognized words Memory capacity
Recognition dictionary and work vary depending on the number of recognized words.
Sub dictionary 1
Jim, Marc, Sally
Sub dictionary 2
Smith, Jones, Brown
Sub dictionary 3
ANA, JAL, ticket
Main dictionary
Friend
Company
Reservation
.
.
.
ROM/RAM
ROM
ROM/RAM mix
RAM
Program
Data
Recognition dictionary (in case of 15 words)
Work area (in case of 15 words)
Stack
26 KB
40 KB
0.5 KB
3.4 KB
0.3 KB
Description Capacity
V850 Series
Speech recognition system configuration example
Speech Recognition
CPU
4:1:1
(Quality75)
V850E/MS1
(33MHz)
Note
Processing Time
Sample Ratio VGA (640×480×24)
Compression Decompression Compression Decompression
JPEG performance
Note Programs are placed in internal ROM, and stack and (some) work areas are placed in internal RAM.
The data and other works are
p
laced in external RAM.
QVGA (320×240×24)
0.32 s 0.24 s 1.3 s 0.97 s
RAM
Compression Decompression Compression Decompression
Memory
ROM
10 KB 7.5 KB 5 KB 10 KB
ROM Program 126 KB
Data 35 KB
Dictionary data (approx. 80,000 words)
1.2 MB
Phoneme data 567 KB (8 kHz sampling)
684 KB (11 kHz sampling)
RAM Work 160 KB
Stack 508 bytes
Speech output buffer 12 KB
Description CapacityROM/RAM
JPEG
Text to Speech (for Japanese Text)
•
Speech synthesized from Japanese Kana and Kanji text (SJIS code)
•Versatile speech synthesis
Synthesis of female voices possible
Various adjustable parameters such as intonation and reading speed
•Rhythm of synthesized speech (pitch, phoneme duration) can
be designed (Speech Designer compatible)
Speech synthesis using natural rhythm possible (synthesis of more natural sounding speech)
•Support of special characters (Reading of special characters
settable in user dictionaries)
•Synthesis speed
Works also with V850/SA1 (20 MHz). (However, text is placed in internal ROM.)
Pamphlet U15412EJ4V1PF
38
Features
Rewrite Modes
Note 1. In the case of dual-power-supply flash, VPP Note 2. In the case of dual-power-supply flash, don’t connect.
To enable integrated use ranging from development to mass production and maintenance, the V850 Series supports a programmer
rewrite mode that uses serial communication supporting on-board programming, as well as a self-programming mode that rewrites flash
memory with user programs.
Handshake-compatible CSI communication method
CSI communication method UART communication method
On-board programming mode
This programming mode is used to rewrite the flash memory mounted on the target system using a dedicated flash memory programmer.
Off-board programming mode
This programming mode is used to rewrite flash memory using a dedicated flash memory programmer and dedicated program adapter (FA
SeriesNote 1).
Self-programming mode
This programming mode is used to rewrite flash memory by executing the user program written beforehand to the flash memory using on-board/
off-board programming.Note 2
Notes 1. The FA Series is a product of Naito Densei Machida Mfg. Co., Ltd.
2. Since instruction fetch and data access cannot be performed from the internal flash memory area during self-programming, a program for rewriting internal
RAM or external memory must be transferred in advance.
Dedicated flash
memory programmer
(PG-FP4, etc.)
Example: V850ES/SA2
VDD
VSS
RESET
SI0
SO0
SCK0
VDD
GND
RESET
SO
SI
SCK
FLMD1 or VSSFLMD1 FLMD0FLMD0 Note 1
Note 2
Dedicated flash
memory programmer
(PG-FP4, etc.)
Example: V850ES/SA2
VDD
VSS
RESET
SI0
SO0
SCK0
PDH0
VDD
GND
RESET
SO
SI
SCK
HS
FLMD1 or VSSFLMD1 FLMD0FLMD0 Note 1
Note 2
Dedicated flash
memory programmer
(PG-FP4, etc.)
Example: V850ES/SA2
FLMD1 or V
SS
V
DD
V
SS
RESET
RXD0
TXD0
FLMD1 FLMD0FLMD0
V
DD
GND
RESET
TxD
RxD
Note 1
Note 2
To answer the need for shorter development time
and maintenance after shipping, NEC Electronics
offers microcontrollers with on-chip flash memory
available in a large range of capacities from 64
KB to 640 KB as part of the V850 Series. NEC
Electronics’ flash memory microcontrollers offer the
following features.
Flash capacity
64 to 640 KB
Overwrite unit
Entire memory at one time, or block units
Rewrite method
Serial communication with dedicated flash
memory programmer (on-board, off-board)
Self-flash programming
Rewrite voltage
Single-power-supply flash: Operation voltage
Dual-power-supply flash: Operation voltage
7.8 V/10.3 V
Rewrite count:
100 times
Flash Memory Size
(bytes)
RAM size (bytes)
V850ES/KF1
V850ES/KE1
V850ES/KG1
V850ES/KJ1
V850ES/KE1+*
V850ES/KF1+*
V853
V850/SA1
V850E/IA3, IA4
V850E/IA2
V850/SB1
V850/SB2
V850E/MA1
V850E/MA3
V850/SC1,SC2,SC3
V850ES/KG1+*
V850ES/KJ1+*
V850ES/SG2
µPD70F3229Y
V850ES/SA2
,SA3
V850ES/SJ2
128K64K 192K 256K 384K 512K
640K
4K 4K 6K 8K 12K 16K 8K 10K 12K 16K 16K 24K 32K 20K 24K 32K 48K
V850E/MS1
V850E/IA1
V850ES/IK1*
V850ES/FF2*
V850ES/FG2*
V850ES/FJ2*
V850E/SV2
V850ES/FE2*
V850/SV1
V850/SF1
V850/DB1 *: Under development
/
/
/
: Single power supply
: Dual power supply
: Single power supply/dual power supply
/
Programmer program (on-board/off-board)
Flash microcontroller lineup
Pamphlet U15412EJ4V1PF 39
Category
Low end
Middle range
High end
ASSP
Part No. Max. Operating
Frequency Rewrite Voltage Rewrite Mode Rewrite
Count
(Times)
On-Board/Off-Board
Programming
Self-
Programming
VPP CSI UART CSI+HS
V850ES/KE1
V850ES/KF1
V850ES/KF1
V850ES/KG1
V850ES/KG1
V850ES/KJ1
V850ES/KJ1
V850ES/KE1+*
V850ES/KF1+*
V850ES/KG1+*
V850ES/KJ1+*
V850ES/SG2
V850ES/SJ2
µPD70F3229Y
V850ES/SA2
V850ES/SA3
V850/SA1
V850/SB1
V850/SC1
V850E/MA3
V850E/MA1
V850E/MS1
V850E/MS1
V853
V850E/IA4
V850E/IA3
V850E/IA2
V850E/IA1
V850ES/IK1*
V850E/SV2
V850ES/FE2*
V850ES/FF2*
V850ES/FG2*
V850ES/FJ2*
*: Under development
V850/SV1
V850/SB2
V850/SC2
V850/SC3
V850/SF1
V850/DB1
Flash Memory
Capacity
128 KB
256 KB/128 KB
128 KB
256 KB/128 KB
128 KB
256 KB/128 KB
128 KB
128 KB
256 KB/128 KB
256 KB/128 KB
256 KB/128 KB
640 KB/384 KB
640 KB/384 KB
384 KB
256 KB
256 KB
256 KB/128 KB
256 KB/128 KB
384 KB/256 KB/128 KB
512 KB/384 KB/256 KB
384 KB/256 KB
512 KB/384 KB/256 KB
512 KB/384 KB/256 KB
512 KB
512 KB
256 KB
256 KB
256 KB
128 KB
128 KB
256 KB
512 KB
512 KB
512 KB
256 KB
128 KB
128 KB/64 KB
128 KB
128 KB
256 KB/128 KB
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
80 MHZ
50 MHZ
33 MHZ
33 MHZ
33 MHZ
32 MHZ
64 MHZ
64 MHZ
40 MHZ
50 MHZ
40.5 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
20 MHZ
19 MHZ
20 MHZ
20 MHZ
16 MHZ
16 MHZ
VDD
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.5 V to 5.5 V
2.85 V to 3.6 V
2.85 V to 3.6 V
3.5 V to 5.5 V
2.2 V to 2.7 V
2.2 V to 2.7 V
3.0 V to 3.6 V
4.0 V to 5.5 V
3.5 V to 5.5 V
2.3 V to 2.7 V
(internal)
3.0 V to 3.6 V
(external)
3.0 V to 3.6 V
(internal)
4.5 V to 5.5 V
(external)
2.3 V to 2.7 V
(internal)
4.5 V to 5.5 V
(external)
2.3 V to 2.7 V
(internal)
4.5 V to 5.5 V
(external)
3.0 V to 3.6 V
(internal)
4.5 V to 5.5 V
(external)
2.3 V to 2.7 V
(internal)
2.7 V to 3.6 V
(external)
3.0 V to 3.6 V
3.0 V to 3.6 V
4.5 V to 5.5 V
4.5 V to 5.5 V
4.0 V to 5.5 V
4.5 V to 5.5 V
4.0 V to 5.5 V
4.0 V to 5.5 V
4.0 V to 5.5 V
3.1 V to 3.6 V
4.0 V to 5.5 V
3.5 V to 5.5 V
3.5 V to 5.5 V
3.5 V to 5.5 V
4.0 V to 5.5 V
4.5 V to 5.5 V -----
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10.3 V
10.3 V
10.3 V
10.3 V
7.8 V
7.8 V
7.8 V
7.8 V
7.8 V
7.8 V
7.8 V
7.8 V
7.8 V
7.8 V
7.8 V
7.8 V
7.8 V
7.8 V
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
20
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
-----
-----
-----
-----
-----
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
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√
√
√
√
√
√
√
√
Flash memory can be erased and rewritten using a self-programming library
from a program placed in an area outside the flash memory.
Self-programming mode (single-power-supply method)
Self-programming flow
All blocks completed?
YES NO
Erase processing
Flash environment initialization processing
Write processing
Internal verify processing
Flash environment end processing
Processing end
Flash information setting processing
Boot area replacement processing
Flash memory operation
• Access to flash area prohibited
• Stop instruction execution
prohibited
• Clock stop prohibited
256 KB
Flash memory
Library initialization
processing
Library end
processing
00000H
3FFFFH Block
7(60KB)
Block
6(60KB)
Block
5(60KB)
Block
4(60KB)
Block
3(4KB)
Block
2(4KB)
Block
1(4KB)
Block
0(4KB)
Flash memory
Normal operation mode Self-programming mode
00000H
3FFFFH
Self-programming
Library
(Erase/Write
routine execution)
Caution The number of blocks and block capacity differ depending on the products.
(Example: V850ES/SA2)
Flash Specifications List
Pamphlet U15412EJ4V1PF
40
Flash Memory Programmers
NEC Electronics flash memory programmer: PG-FP4
[Features]
Supports write to all NEC Electronics microcontrollers with internal flash memory.
USB support through host machine interface
Allows verification of various types of information, including programmer setting information, error
messages, and check-sum, even in stand-alone configuration, from the main unit’s LCD.
Enables downloading of two types of user code and selecting of valid code
Device-specific information required for writing automatically settable with parameter files
Supports both on-board programming and program adapter programming.
Easy-to-carry A5 size
Simple operation either on stand-alone basis and on WindowsTM 95/Windows 98/Windows Me/
Windows 2000/Windows XP, Windows NTTM 4.0 using a dedicated application (Flashpro4)
[Manufacturer/Distributor] Wave Technology Co., Ltd.
[Target Devices] V850/SV1, SB1 (µPD70F3032B, 70F3033B), SB2 (70F3035B, 70F3037H),
V850E/IA1 (70F3116), MA1
[Features]
Gang programmer enabling simultaneous programming and verification of up to 8 devices
Enables reading of master data directly from floppy disk to internal memory
Data dump display and editing functions
Master data storable on internal hard disk
Designed for simple and comfortable operation via touch panel, and superior operability
via PASS/FAIL display, check-sum display, and task count display supporting sockets.
[Additional information]
TEL : +81-3-5304-1885 FAX : +81-3-5304-1886
E-mail : sales@y1000.com
Website: http://www.y1000.com/index_e.html
•Programming system Y1000-8
PG-FP4 allows single-microcontroller programming when used with a program adapter (FA Series of Naito Densei Machida Mfg. Co., Ltd.). On-
board programming can also be performed.
A sample rewrite environment when using the program adapter is shown below.
•Flash memory programmer configuration
Rewrite environment example
Flash memory program (PG-FP4)
Target system
Power-supply unit
Host machine interface (USB)
To host machine
Cautions 1. Install the PG-FP4 control software and target device
parameter file in the host machine.
•PG-FP4 control software: Bundled with PG-FP4
•PG-FP4 parameter file: Distributed via online
delivery service
2. In addition to programming using the program adapter,
on-board programming on the target system is also
possible.
Third-party flash memory programmers (1/2)
Pamphlet U15412EJ4V1PF 41
Third-party flash memory programmers (2/2)
[Manufacturer/Distributor] Naito Densei Machida Mfg. Co.
[Target Devices] V850 Series
[Features]
Supports writing to all NEC Electronics microcontrollers with internal flash memory.
USB support through host machine interface
Allows verification of various types of information, including programmer setting information, error
messages, and check-sum, even in stand-alone configuration, from the main unit’s LCD.
Enables downloading of two types of user code and selecting of valid code
Device-specific information required for writing automatically settable with parameter files
Supports both on-board programming and program adapter programming.
Easy-to-carry A5 size
Simple operation either on stand-alone basis and on Windows 95/Windows 98/Windows Me/
Windows 2000/Windows XP, Windows NT 4.0 using a dedicated application (Flashpro4)
[Additional information]
TEL : +81-45-475-4191 FAX : +81-45-475-4091
E-mail : info@ndk-m.co.jp
Website: http://www.ndk-m.co.jp/asmis/eng/index.html
•FlashPRO IV: FL-PR4
•NET IMPRESS
[Manufacturer] Forward Electric Co., Ltd. (Hong Kong)
[Distributor] Application Co., Ltd.
[Target Devices] V850/SB1(70F3033A), V850E/MA1
[Features]
Host machine interface supports USB.
Easy operation and rich array of GUI software provided
Low cost from development to mass production
Compact and easy to carry (FL-S01)
Gang programmer enabling simultaneous programming of up to 8 devices (FL-G01)
Can be used on standalone basis using compact flash (FL-G01).
Programming adapter board (option) usable in common for FL-S01 and FL-G01.
[Additional Details]
TEL : +81-42-732-1377 FAX : +81-42-732-1378
Website:http://www.apply.co.jp/index_eng.html
•Flash Burner Forward FL-S01, Flash Gang Forward FL-G01
FL-S01 FL-G01
[Manufacturer/Distributor] Yokogawa Digital Computer Corporation
[Target Devices]
V850/SB1 (µPD70F3033B), SB2(70F3037H), SA1(70F3017A), SC3(70F3089Y),
V853(70F3003A, 70F3025A), V850E/MS1(70F3102A), MA1(70F3107), IA1,
IA2(70F3114), V850ES/KF1(70F3210), FE2, FF2, FG2, FJ2, SG2, SJ2
[Features]
Enables programming of flash memory microcontrollers of various writing specifications solder mounted on user system boards.
One control module is the key to this product’s versatility.
Microcontrollers of the same family are supported by changing parameters, and microcontrollers of
different families are supported by purchasing the required license for the descriptor part.
Can be used on standalone basis as well as via a host machine.
Rich lineup of downloadable freeware
[Additional Information]
TEL : Japan +81-42-333-6224
U.S.A +408-941-0132 (Yokogawa Corporation of America)
Europe +44-1256-811998 (Ashling Microsystems Limited)
Korea +82-2-785-3929 (KM DATA INC.)
South East Asia +65-6563-2082 (Unidux Electronics Pte Ltd.)
FAX : Japan +81-42-352-6109
U.S.A +408-941-0121 (Yokogawa Corporation of America)
Europe +44-1256-811761 (Ashling Microsystems Limited)
Korea +82-2-785-3117 (KM DATA INC.)
South East Asia +65-6569-4661 (Unidux Electronics Pte Ltd.)
Website: http://www.ydc.co.jp/micom/index_E.htm
Pamphlet U15412EJ4V1PF
42
Item V850ES/KE1
V850ES/KF1
Part No.
µPD703207/3207Y µPD703208/3208Y µPD703209/3209Y µPD703210/3210Y µPD703211/3211YµPD70F3207H/F3207HY
µPD70F3211H/F3211HYµPD70F3210/F3210Y
µPD70F3210H/F3210HY
Operating ambient temperature
CPU core V850ES V850ES
CPU performance 29 MIPS (@20 MHz: 5 MHz × 4) 29 MIPS (@20 MHz: 5 MHz × 4)
Internal ROM 128 KB (mask) 64 KB (mask) 96 KB (mask)128 KB (flash) 128 KB (mask) 256 KB (mask)
128 KB (flash) 256 KB (flash)
Internal RAM 4 KB 6 KB 12 KB4 KB
External bus interface Bus type −Multiplexed
Address bus
−16 bits
Data bus −8/16 bits
Chip select signal
−2
Memory controller −SDRAM, etc.
Interrupt sources Internal 25 (Y products: 26) 28 (Y products: 29)25 (Y products: 26)
External 8 (8)
Note 1
8(8)
Note 1
Timer/counter 16-bit timer/event counter (TM0) × 1 ch
16-bit timer/event counter (TMP) × 1 ch
8-bit timer/event counter (TMH) × 2 ch
8-bit timer/event counter (TM5) × 2 ch
8-bit interval timer (BRG) × 1 ch
16-bit timer/event counter (TM0) × 2 ch
16-bit timer/event counter (TMP) × 1 ch
Note 3
8-bit timer/event counter (TMH) × 2 ch
8-bit timer/event counter (TM5) × 2 ch
8-bit interval timer (BRG) × 1 ch
Watchdog timer 2 ch 2 ch
Serial interface CSI with automatic transfer function (32-byte buffer) × 1 chCSI × 2 ch
UART × 2 ch
I
2
C
×
1 ch
Note 2
CSI × 2 ch
UART × 2 ch
I
2
C × 1 ch
Note 2
A/D converter 10-bit
×
8 ch 10 bits × 8 ch
D/A converter − −
DMA controller − −
Ports I/O 43 59
Input 8 8
Debug control unit −
−
Other peripheral functions
Watch timer: 1 ch, ROM correction function: 4 points, real-time output
Watch timer: 1 ch, ROM correction function: 4 points, real-time output
Operating frequency When using main clock: 2 to 20 MHz
When using subclock: 32.768 kHz When using main clock: 2 to 20 MHz
When using subclock: 32.768 kHz
Power supply voltage 2.7 to 5.5 V 2.7 to 5.5 V
Power consumption (Typ.) 150 mW (128 KB mask products: 20 MHz @5 V operation)
29.7 mW (128 KB mask products: 10 MHz @3.3 V operation)
200 mW (128 KB mask products: 20 MHz @5 V operation)
39.6 mW (128 KB mask products: 10 MHz @3.3 V operation)
Package 64-pin TQFP (12 × 12 mm)
64-pin LQFP (10 × 10 mm) 80-pin TQFP (12 × 12 mm)
80-pin QFP (14 × 14 mm)
-40 to +85°C -40 to +85°C
V850ES/KG1 V850ES/KJ1
µPD703212/3212Y µPD703213/3213Y µPD703214/3214Y µPD703215/3215Y µPD703216/3216Y µPD703217/3217Y
µ
PD70F3215H/F3215HY
µPD70F3217/F3217Y
µ
PD70F3218H/F3218HY
µPD70F3214/F3214Y
µ
PD70F3214H/F3214HY
µ
PD70F3217H/F3217HY
V850ES V850ES
30 (Y products : 31) 33 (Y products : 34) 38(Y products : 40) 41(Y products : 43)
29 MIPS (@ 20 MHz: 5 MHz × 4) 29 MIPS (@ 20 MHz: 5 MHz × 4)
64 KB (mask) 96 KB (mask) 128 KB (mask) 256 KB (mask) 96 KB (mask)
128 KB (flash) 256 KB (flash) 256 KB (flash)
128 KB (mask)
128 KB (flash)
4 KB 6 KB 16 KB 16 KB6 KB
Multiplexed/separate Multiplexed/separate
22 bits 24 bits
8/16 bits 8/16 bits
2 4
SRAM, etc. SRAM, etc.
8(8)
Note 1
8(8)
Note 1
16-bit timer/event counter (TM0) × 4 ch
16-bit timer/event counter (TMP) × 1 ch
Note 2
8-bit timer/event counter (TMH) × 2 ch
8-bit timer/event counter (TM5) × 2 ch
8-bit interval timer (BRG) × 1 ch
16-bit timer/event counter (TM0) × 6 ch
16-bit timer/event counter (TMP) × 1 ch
Note 3
8-bit timer/event counter (TMH) × 2 ch
8-bit timer/event counter (TM5) × 2 ch
8-bit interval timer (BRG) × 1 ch
2ch 2 ch
CSI with automatic transfer function (32-byte buffer) × 2 ch
CSI × 2 ch
UART × 2 ch
I
2
C × 1 ch
Note 4
CSI with automatic transfer function (32-byte buffer) × 2 ch
CSI × 3 ch
UART/I
2
C × 1 ch
Note 4
UART × 2 ch
I
2
C × 1 ch
Note 4
10-bit × 8 ch 10-bit × 16 ch
8-bit × 2 ch 8-bit × 2 ch
− −
76 112
8 16
Watch timer: 1 ch, ROM correction function: 4 points, real-time output Watch timer: 1 ch, ROM correction function: 4 points, real-time output
When using main clock: 2 to 20 MHz
When using subclock: 32.768 kHz When using main clock: 2 to 20 MHz
When using subclock: 32.768 kHz
2.7 V to 5.5 V 2.7 V to 5.5 V
150 mW (128 KB mask products: 20 MHz @ 5 V operation)
29.7 mW (128 KB mask products: 10 MHz @ 3.3 V operation) 150 mW (128 KB mask products: 20 MHz @ 5 V operation)
29.7 mW (128 KB mask products: 10 MHz @ 3.3 V operation)
100-pin LQFP (14 × 14 mm)
100-pin QFP (14 × 20 mm) 144-pin LQFP (20 × 20 mm)
-40 to +85°C-40 to +85°C
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
−−Provided(RUN/break)
Notes 1. Number of external interrupts that can be used to release STOP mode
2. Only Y products have an on-chip I
2
C interface.
3. µPD703211, 703211Y, 70F3211H, 70F3211HY only
Notes 1. Number of external interrupts that can be used to release STOP mode
2. µPD703215, 703215Y, 70F3215H, 70F3215HY only
3. µPD70F3218H, 70F3218HY only
4. Onl
y
Y
p
roducts have an on-chi
p
I
2
C interface.
Low-End Lineup (1/2)
Pamphlet U15412EJ4V1PF 43
V850ES/KE1+ V850ES/KF1+
µPD703302/3302Y µPD70F3302/F3302Y µPD70F3306/F3306Y µPD703308/3308Y
µPD70F3308/F3308Y
128 KB (mask) 128 KB (flash) 128 KB (flash) 256 KB (mask)
256 KB (flash)
6 KB 12 KB
V850ES
29 MIPS (@20 MHz: 5 MHz × 4)
4 KB
−
−
−
−
−
26 (Y products: 27)
9(9)
Note 1
16-bit timer/event counter (TM0) × 1 ch
16-bit timer/event counter (TMP) × 1 ch
8-bit timer (TMH) × 2 ch, 8-bit timer/event counter (TM5) × 2 ch,
8-bit interval timer (BRG) × 1 ch
2 ch
CSI × 2ch
UART × 1ch
UART (LIN compatible) × 1 ch
I
2
C × 1 ch
Note 2
10-bit × 8 ch
−
−
43
8
−
Watch timer: 1 ch, ROM correction function: 4 points, POC/LVI/clock monitor, real-time output
Using main clock: 2 to 20 MHz
Using subclock: 32.768 kHz
Ring-OSC: 240 kHz
2.7 to 5.5V
200 mW (128 KB mask products: 20 MHz @ 5 V operation)
39.6 mW (128 KB mask products: 10 MHz @ 3.3 V operation)
64-pin TQFP (12 × 12 mm)
64-pin LQFP (10 × 10 mm)
-40°C to +85°C
V850ES
29 MIPS (@20 MHz: 5 MHz × 4)
Multiplexed
16 bits
8/16 bits
2
SRAM, etc.
29 (Y products: 30)
9(9)
Note 1
16-bit timer/event counter (TM0) × 2 ch
16-bit timer/event counter (TMP) × 1 ch
8-bit timer (TMH) × 2 ch, 8-bit timer/event counter (TM5) × 2 ch,
8-bit interval timer (BRG) × 1 ch
2 ch
CSI with automatic transfer function (32-byte buffer) × 1 ch
CSI × 2 ch
UART × 1 ch
UART (LIN compatible) × 1 ch
I
2
C × 1 ch
Note 2
10-bit × 8 ch
−
−
59
8
−
Watch timer: 1 ch, ROM correction function: 4 points, POC/LVI/clock monitor,
real-time output
Using main clock: 2 to 20 MHz
Using subclock: 32.768 kHz
Ring-OSC: 240 kHz
2.7 to 5.5V
220 mW (256 KB mask products: 20 MHz @ 5 V operation)
42.9 mW (256 KB mask products: 10 MHz @ 3.3 V operation)
80-pin TQFP (12 × 12 mm)
80-pin QFP (14 × 14 mm)
-40°C to +85°C
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
µPD70F3316/F3316Y
Serial interface
V850ES/KG1+ V850ES/KJ1+
µPD70F3311/F3311Y µPD703313/3313Y
µPD70F3313/F3313Y µPD70F3318/F3318Y
V850ES
256 KB (flash)
V850ES
Item
Part No.
CPU core 29 MIPS (@ 20 MHz : 5 MHz × 4) 29 MIPS (@ 20 MHz : 5 MHz × 4)
CPU performance 256 KB (mask)128 KB (flash) 128 KB (flash) 256 KB (flash)
Internal ROM
6 KB 16 KB 6 KB 16 KB
Internal RAM Multiplexed/separateMultiplexed/separate
External bus
interface Bus type 24 bits22 bitsAddress bus 8/16 bits8/16 bits
Data bus 42Chip select signal SRAM, etc.
SRAM, etc.Memory controller 46 (Y products: 48)41 (Y products: 42)
Interrupt sources Internal 9 (9)
Note 1
9 (9)
Note 1
External 16-bit timer/event counter (TM0) × 6 ch
16-bit timer/event counter (TMP) × 1 ch
8-bit timer (TMH) × 2 ch, 8-bit timer/event counter (TM5) × 2 ch,
8-bit interval timer (BRG) × 1 ch
16-bit timer/event counter (TM0) × 4 ch
16-bit timer/event counter (TMP) × 1 ch
8-bit timer (TMH) × 2 ch, 8-bit timer/event counter (TM5) × 2 ch,
8-bit interval timer (BRG) × 1 ch
Timer/counter
2ch2chWatchdog timer
CSI with automatic transfer function (32-byte buffer) × 2 ch
CSI × 2 ch
UART
Note3
/CSI × 1 ch
UART
Note3
/I
2
C × 1 ch
Note2
UART (LIN compatible) × 1 ch
UART× 1 ch, I
2
C × 1 ch
Note 2
CSI with automatic transfer function (32-byte buffer) × 2 ch
CSI × 1 ch
UART/CSI × 1 ch
UART × 1 ch
UART (LIN compatible) × 1 ch
I
2
C × 1 ch
Note 2
10-bit × 16 ch10-bit × 8 ch
A/D converter 8-bit × 2 ch8-bit × 2 ch
D/A converter 4 ch4 ch
DMA controller 11276
Ports I/O 168
Input
Watch timer: 1 ch, POC/LVI/clock monitor, real-time outputWatch timer: 1 ch, ROM correction function: 4 points, POC/LVI/clock monitor, real-time output
Other peripheral functions
When using main clock: 2 to 20 MHz
When using subclock: 32.768 kHz
Ring-OSC: 240 kHz
When using main clock: 2 to 20 MHz
When using subclock: 32.768 kHz
Ring-OSC: 240 kHz
Operating frequency
2.7 to 5.5 V
2.7 to 5.5 V
Power supply voltage 275 mW (256 KB flash products: 20 MHz @ 5 V operation)
59.4 mW (256 KB flash products: 10 MHz @ 3.3 V operation)
220 mW (256 KB mask products: 20 MHz @ 5 V operation)
42.9 mW (256 KB mask products: 10 MHz @ 3.3 V operation)
Power consumption (Typ.)
144-pin LQFP (20 × 20 mm)100-pin LQFP (14 × 14 mm)
100-pin QFP (14 × 20 mm)
Package
-40°C to +85°C-40°C to +85°C
Operating ambient temperature
−
Debug control unit −Provided (RUN/break)
Notes 1. Number of external interrupts that can be used to release STOP mode
2. Onl
y
Y
p
roducts have an on-chi
p
I
2
C interface.
Notes 1. Number of external interrupts that can be used to release STOP mode
2. Only Y products have an on-chip I
2
C interface.
3. These UARTs are the identical and the number of channels in KJ1+ totals 3 channels.
Low-End Lineup (2/2)
Pamphlet U15412EJ4V1PF
44
V850ES/SG2
µPD703260/3260Y
µPD703270/3270Y
µPD703280/3280Y
Without IEBus, aFCAN
On-chip IEBus
On-chip aFCAN
µPD703261/3261Y
µPD703271/3271Y
µPD703281/3281Y
µPD70F3261/F3261Y
µPD70F3271/F3271Y
µPD70F3281/F3281Y
µPD703262/3262Y
µPD703272/3272Y
µPD703282/3282Y
µPD703263/3263Y
µPD703273/3273Y
µPD703283/3283Y
µPD70F3263/F3263Y
µPD70F3273/F3273Y
µPD70F3283/F3283Y
256 KB (mask) 384 KB (mask) 384 KB (flash) 512 KB (mask) 640 KB (mask) 640 KB (flash)
24 KB 32 KB 40 KB 48 KB
−Provided (RUN/break) −Provided (RUN/break)
V850ES
29 MIPS (@ 20 MHz)
Multiplexed/separate
22 bits
8/16 bits
−
SRAM, etc.
47
Note 1
/52
Note 2
9(9)
Note 1
16-bit interval timer(TMM) × 1 ch
16-bit timer/event counter(TMP) × 6 ch
16-bit timer/event counter(TMQ) × 1 ch
1 ch
CSI × 3 ch
UART(LIN compatible)/CSI × 1 ch
CSI/I
2
C × 1 ch
Note 4
UART(LIN compatible)/I
2
C × 2 ch
Note 4
10-bit × 12 ch
8-bit × 2 ch
4 ch
84
−
Watch timer: 1 ch
IEBus controller × 1 ch
Note 5
aFCAN controller × 1 ch
Note 6
ROM correction function : 4 points
Real-time output
LVI/clock monitor
When using main clock: 2.5 to 20 MHz
When using subclock: 32.768 kHz
Ring-OSC: 200 kHz
2.85 to 3.6 V (@ 20 MHz) 59.4 mW(3.3 V,@ 20 MHz)82.5 mW(3.3 V,@ 20 MHz)59.4 mW(3.3 V,@ 20 MHz) 89.1 mW(3.3 V,@ 20 MHz)
100-pin LQFP (14 × 14 mm)
100-pin QFP (14 × 20 mm)
-40°C to +85°C
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
V850ES/SG2
µPD703260/3260Y
µPD703270/3270Y
µPD703280/3280Y
Without IEBus, aFCAN
On-chip IEBus
On-chip aFCAN
µPD703261/3261Y
µPD703271/3271Y
µPD703281/3281Y
µPD70F3261/F3261Y
µPD70F3271/F3271Y
µPD70F3281/F3281Y
µPD703262/3262Y
µPD703272/3272Y
µPD703282/3282Y
µPD703263/3263Y
µPD703273/3273Y
µPD703283/3283Y
µPD70F3263/F3263Y
µPD70F3273/F3273Y
µPD70F3283/F3283Y
256 KB (mask) 384 KB (mask) 384 KB (flash) 512 KB (mask) 640 KB (mask) 640 KB (flash)
24 KB 32 KB 40 KB 48 KB
−Provided (RUN/break) −Provided (RUN/break)
V850ES
29 MIPS (@ 20 MHz)
Multiplexed/separate
22 bits
8/16 bits
−
SRAM, etc.
47Note 1/52Note 2
9(9)Note 1
16-bit interval timer(TMM) × 1 ch
16-bit timer/event counter(TMP) × 6 ch
16-bit timer/event counter(TMQ) × 1 ch
1 ch
CSI × 3 ch
UART(LIN compatible)/CSI × 1 ch
CSI/I2C × 1 chNote 4
UART(LIN compatible)/I2C × 2 chNote 4
10-bit × 12 ch
8-bit × 2 ch
4 ch
84
−
Watch timer: 1 ch
IEBus controller × 1 chNote 5
aFCAN controller × 1 chNote 6
ROM correction function : 4 points
Real-time output
LVI/clock monitor
When using main clock: 2.5 to 20 MHz
When using subclock: 32.768 kHz
Ring-OSC: 200 kHz
2.85 to 3.6 V (@ 20 MHz) 59.4 mW(3.3 V,@ 20 MHz)82.5 mW(3.3 V,@ 20 MHz)59.4 mW(3.3 V,@ 20 MHz) 89.1 mW(3.3 V,@ 20 MHz)
100-pin LQFP (14 × 14 mm)
100-pin QFP (14 × 20 mm)
-40°C to +85°C
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
Notes1.Only products without IEBus or aFCAN
2.Only products with IEBus or aFCAN
3.Number of external interrupts that can be used to release STOP mode
Notes4.Only Y products have an on-chip I
2
C interface.
5.µPD703270 (Y)/3271 (Y)/F3271 (Y)/3272 (Y)/3273 (Y)/F3273 (Y)
6.µPD703280 (Y)/3281 (Y)/F3281 (Y)/3282 (Y)/3283 (Y)/F3283 (Y)
Notes 1. Only products without IEBus or aFCAN
2. Only products with IEBus or aFCAN
3. Only products with two aFCAN channels
4. Number of external interrupts that can be used to release STOP mode
Notes 5. Only Y products have an on-chip I2C interface.
6. µPD703274(Y)/F3274(Y)/3275(Y)/3276(Y)/F3276(Y)
7. µPD703284(Y)/F3284(Y)/3285(Y)/3286(Y)/F3286(Y)
8. µPD703287(Y)/3288(Y)/F3288(Y)
Middle-Range Lineup (1/3)
Pamphlet U15412EJ4V1PF 45
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
V850/SB1
µPD703031B/3031BY µ
PD703033B/3033BY
µ
PD70F3033B/F3033BY
µ
PD703030B/3030BY
µ
PD70F3030B/F3030BY
µ
PD703032B/3032BY
µ
PD70F3032B/F3032BY
V850
23 MIPS (@20 MHz)
128 KB (mask) 256 KB (mask) 256 KB (flash) 384 KB (mask) 384 KB (flash) 512 KB (mask) 512 KB (flash)
8 KB 16 KB 24 KB
Multiplexed/separate
22 bits
16 bits
−
SRAM, etc.
31 (Y products: 32)
8(6)
Note 1
16-bit timer/event counter × 2 ch
8-bit timer/event counter × 6 ch
8-bit timer × 2 ch
1 ch
CSI × 1 ch
CSI/I
2
C × 2 ch
Note 2
CSI/UART × 2 ch
10-bit × 12 ch
−
6 ch (dedicated internal RAMon-clip peripheral I/O)
71
12
−
ROM correction function:4 points, watch timer: 1 ch
When using main clock: 2 to 20 MHz
When using subclock: 32.768 kHz
4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V)
125 mW (5 V, @ 20 MHz) 165 mW (5 V, @ 20 MHz) 125 mW (5 V, @ 20 MHz) 185 mW (5 V, @ 20 MHz) 125 mW (5 V, @ 20 MHz) 210 mW (5 V, @ 20 MHz)
100-pin LQFP (14 × 14 mm)
100-pin QFP (14 × 20 mm) 100-pin QFP (14 × 20 mm)
-40 to +85°C
µPD703229Y V850/SC1 V850/SC2 V850/SC3
V850/SC1,V850/SC2,V850/SC3
µPD703229Y µPD70F3229Y µPD703088Y µPD703089Y µPD70F3089Y
V850
18 MIPS (@ 16 MHz) 23 MIPS (@ 20 MHz)
384 KB (mask) 384 KB (flash) 512 KB (mask) 512 KB (flash)
46 49
When using main clock:
4 to 16 MHz (@5 V) When using main clock:
4 to 20 MHz (@5 V)
When using subclock: 32.768 kHz
When using subclock: 32.768 kHz
3.5 to 5.5 V (A/D converter: 4.5 to 5.5 V) 4.0 to 5.5 V
(A/D converter: 4.5 to 5.5 V)
µPD703068Y
23 MIPS (@ 20 MHz)
42
When using main clock:
4 to 20 MHz (@5 V)
When using subclock: 32.768 kHz
125 mW (5 V, @ 20 MHz)
µPD703069Y
21 MIPS (@ 19 MHz)
44
When using main clock:
4 to 19 MHz (@5 V)
When using subclock: 32.768 kHz
120 mW (5 V, @ 19 MHz) 110 mW (5 V, @ 16 MHz) 150 mW (5 V, @ 20 MHz)
V850ES
29 MIPS (@ 20 MHz)
32 KB
Multiplexed
18 bits
8/16 bits
2
SRAM, etc.
38 sources
9 (9)Note
16-bit internal timer (TMM) × 1 ch
16-bit timer/event counter (TMP) × 4 ch
16-bit timer/event counter (TMQ) × 1 ch
1 ch
UART (LIN compatible) × 3 ch
CSI × 1 ch
CSI/I2C × 1 ch
10-bit × 12 ch
−
4 ch
84
−
−Provided (RUN, break)
ROM correction function : 4 points, watch timer: 1 ch, LVI/clock monitor
When using main clock: 2.5 to 20 MHz
When using subclock: 32.768 kHz
During Ring OSC operation: 200 kHz
3.5 to 5.5V
100 mW (5 V, @ 20MHz) 145 mW (5 V, @ 20MHz)
100-pin LQFP (14 × 14 mm)
-40°C to +85°C
24 KB
Multiplexed (can be separated only for V850/SC1, V850/SC2)
22 bits
16 bits
−
SRAM, etc.
11 (9)Note
16-bit timer/event counter × 10 ch
1ch
CSI × 2 ch
CSI/I2C × 2 ch
CSI/UART × 2 ch
UART × 2 ch
10-bit × 12 ch
−
6 ch (dedicated internal RAMon-chip peripheral I/O)
112
12
−
ROM correction function : 4 points, watch timer: 1 ch, IEBus controller : 1 ch (V850/SC2 only), FCAN controller : 2 ch (1 ch : µPD703088Y only) (V850/SC3 only)
144-pin LQFP (20 × 20 mm)
-40 to +85°C
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
Notes 1. Number of external interrupts that can be used to release STOP mode
2. Onl
y
Y
p
roducts have an on-chi
p
I
2
C interface.
Note Number of external interru
p
ts that can be used to release STOP mode
Middle-Range Lineup (2/3)
Pamphlet U15412EJ4V1PF
46
V850ES/SA2 V850ES/SA3 V850ES/ST2
µPD703200/3200Y µPD703201/3201Y µPD70F3201/F3201Y µPD703204/3204Y µPD70F3204/F3204Y µPD703220
V850ES V850ES
29 MIPS (@ 20 MHz)
128 KB (mask) 256 KB (mask) 256 KB (flash) 256 KB (mask) 256 KB (flash) ROM-less
8 KB 16 KB 48 KB
22 bits
30 (Y products: 31)
CSI × 2 ch
10-bit × 12 ch
Multiplexed/separate Separate/multiplexed
(selectable only for CS1)
8/16 bits 8/16 bits
4 4
SRAM, etc. SRAM, etc.
8 (8)
Note1
16-bit timer/event counter × 2 ch
8-bit timer/event counter × 4 ch
16-bit interval timer (TMM) × 1 ch
16-bit timer/event counter (TMP) × 6 ch
1 ch 1 ch
CSI/UART × 1 ch
CSI/I
2
C × 1 ch
Note 2
UART × 1 ch
8-bit × 2 ch8-bit × 2 ch
4 ch
68
14
24 bits 22 bits
31 (Y products: 32) 28
9
CSI × 3 ch CSI × 1 ch
CSI/UART × 1 ch
UART × 1 ch
10-bit × 16 ch 10-bit × 8 ch
84
18
57
8
−
ROM correction function : 4 points, real-time counter (watch timer): 1 ch Real-time output
When using main clock: 2 to 20 MHz
When using subclock: 32.768 kHz 20 to 34 MHz
2.2 to 2.7 V 3.0 to 3.6 V
38 mW (2.5 V, @ 20 MHz) 46 mW (2.5 V, @ 20 MHz) T.B.D.46 mW (2.5 V, @ 20 MHz) 38 mW (2.5 V, @ 20 MHz)
100-pin TQFP (14 × 14 mm) 121-pin FBGA (12 × 12 mm) 120-pin TQFP (14 × 14 mm)
144-pin LQFP (20 × 20 mm)
-40°C to +85°C-40°C to +85°C
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
−
−
−
V850/SA1
µPD703014A/3014AY
µ
PD703014B/3014BY
µ
PD703015A/3015AY
µ
PD703015B/3015BY
µ
PD70F3015B/F3015BY
µ
PD703017A/3017AY
µ
PD70F3017A/F3017AY
V850
23 MIPS (@ 20 MHz)
64 KB (mask) 128 KB (mask) 128 KB (flush) 256 KB (mask) 256 KB (flash)
4 KB 8 KB
Multiplexed/separate
22 bits
16 bits
−
SRAM, etc.
24
8 (5)Note 1
16-bit timer/event counter × 2 ch
8-bit timer/event counter × 4 ch
1ch
CSI × 1 ch,
CSI/I2C × 1 chNote 2
CSI/UART × 1 ch
UART × 1ch
10-bit × 12 ch
−
3 ch (dedicated internal RAMon-chip peripheral I/O)
72
13
−
Watch timer: 1 ch
When using main clock: 2 to 20 MHz
When using subclock: 32.768 kHz
3.0 to 3.6 V (@20 MHz)
2.7 to 3.6 V (@17 MHz)
66 mW (3.3 V, @ 20 MHz)
56 mW (3.0 V, @ 17 MHz) 105 mW (3.3 V, @ 20 MHz)
99 mW (3.0 V, @ 17 MHz) 66 mW (3.3 V, @ 20 MHz)
56 mW (3.0 V, @ 17 MHz) 105 mW (3.3 V, @ 20 MHz)
99 mW (3.0 V, @ 17 MHz)
121-pin FBGA (12 × 12 mm) 100-pin LQFP (14 × 14 mm)
121-pin FBGA (12 × 12 mm)
100-pin LQFP (14 × 14 mm) 100-pin LQFP (14 × 14 mm)
121-pin FBGA (12 × 12 mm)
-40°C to +85°C
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
Notes 1. Number of external interrupts that can be used to release STOP mode
2. Onl
y
Y
p
roducts have an on-chi
p
I
2
C interface.
Notes 1. Number of external interrupts that can be used to release STOP mode
2. Onl
y
Y
p
roducts have an on-chi
p
I
2
C interface.
Middle-Range Lineup (3/3)
Pamphlet U15412EJ4V1PF 47
V850E/IA4 V850E/IA3 V850E/IA1 V850E/IA2
µPD703185 µPD703186 µPD70F3186 µPD703183 µPD70F3184 µPD703116 µPD70F3116 µPD703114 µPD70F3114
V850E1
54 MIPS (@ 40 MHz)
128 KB (mask) 256 KB (flash) 128 KB (mask) 256 KB (flash) 256 KB (mask) 256 KB (flash) 128 KB (mask) 128 KB (flash)
6 KB 12 KB 6 KB
Multiplexed
22 bits
8/16 bits
−
SRAM, etc.
42
16(12)
Note
16-bit 3-phase sinusoidal PWM timer × 2 ch
16-bit encoder counter/timer × 1 ch
16-bit timer/counter × 2 ch
16-bit timer/event counter × 1 ch
16-bit interval timer × 1 ch
−
CSI × 1 ch
CSI/UART × 1 ch
UART × 1 ch
10-bit × 6 ch (A/D converter 0)
10-bit × 8 ch (A/D converter 1)
−
4 ch
47
6
−
−
4 to 40 MHz
5 V (3.3 V (internal), 5 V (A/D converter))
5 V (external) (on-chip regulator)
440 mW (5 V, @ 40 MHz operation)
100-pin QFP (14 × 20 mm)
100-pin LQFP (14 × 14 mm)
V850E1
82 MIPS (@ 64 MHz)
256 KB (mask)
−
−
−
−
−
53
8 (7)
Note
16-bit timer/event counter (TMQ) × 2 ch
(inverter timer support possible)
16-bit encoder counter/timer (TMENC) × 2 ch
16-bit timer/event counter (TMP) × 2 ch
16-bit timer/counter (TMP) × 2 ch
16-bit interval timer (TMM) × 1 ch
1 ch
CSI × 1 ch
UART × 1 ch
CSI/UART × 1 ch
10-bit × 4 ch, 2 units (conversion time: 2 µs)
8/10-bit × 8 ch
−
4 ch
56
8Provided (RUN/break)-
ROM correction function : 4 points, operational amplifier, comparator, software pull-up function
0.5 to 64 MHz
2.5 V (internal), 5 V (A/D converter)
5 V (external)
175 mW (internal 2.5 V, @ 64 MHz)
100-pin LQFP (14 × 14 mm)
100-pin QFP (14 × 20 mm)
-40°C to +85°C
V850E1
82 MIPS (@ 64 MHz)
6 KB 12 KB
−
−
−
−
−
49
7 (6)
Note
16-bit timer/event counter (TMQ) × 1 ch
(inverter timer support possible)
16-bit encoder counter/timer (TMENC) × 1 ch
16-bit timer/event counter (TMP) × 2 ch
16-bit timer/event counter (TMQ) × 1 ch
16-bit timer/counter (TMP) × 2 ch
16-bit interval timer (TMM) × 1 ch
1 ch
CSI × 1 ch
UART × 1 ch
CSI/UART × 1 ch
10-bit × 4 ch, 10-bit × 2 ch (conversion time: 2 µs)
8/10-bit × 6 ch
−
4 ch
44
6
−
ROM correction function : 4 points, operational amplifier, comparator, software pull-up function
0.5 to 64 MHz
2.5 V (internal), 5 V (A/D converter)
5 V (external)
175 mW (internal 2.5 V, @ 64 MHz)
80-pin QFP (14 × 14 mm)
-40°C to +85°C
V850E1
67 MIPS (@ 50 MHz)
10 KB
Multiplexed
24 bits
8/16 bits
8
SRAM, etc.
45
20(14)
Note
16-bit 3-phase sinusoidal PWM timer × 2 ch
16-bit encoder counter/timer × 2 ch
16-bit timer/counter × 2 ch
16-bit timer/event counter × 1 ch
16-bit interval timer × 1 ch
−
CSI × 2 ch
UART × 3 ch
10-bit × 8 ch, 2 units
−
4 ch
75
8
−
FCAN controller × 1 ch
4 to 50 MHz
3.3 V (internal), 5 V (A/D converter)
5 V (external)
630 mW (internal 3.3 V, external 5 V, @ 50 MHz operation)
144-pin LQFP (20 × 20 mm)
-40°C to +85°C (Provided 110°C products)-40°C to +85°C
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt
sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
V850/SB2V850ES/IK1
When using main clock: 2 to 13 MHz (@ 5 V)
When using subclock: 32.768 kHz When using main clock: 2 to 19 MHz (@ 5 V)
When using subclock: 32.768 kHz
µPD703327 µPD703329
µPD70F3329 µPD703034B/3034BY µPD703035B/3035BY
µPD70F3035B/F3035BY µPD703036H/3036HY
µPD70F3036H/F3036HY µPD703037H/3037HY
µPD70F3037H/F3037HY
V850
Multiplexed/separate
22 bits
16 bits
−
SRAM, etc.
33 (Y products : 34)
8 (6)
Note 1
16-bit timer/event counter × 2 ch
8-bit timer/event counter × 4 ch
8-bit timer × 2 ch
1 ch
CSI × 1 ch
CSI/I
2
C × 2 ch
Note 2
CSI/UART × 2 ch
10-bit × 12 ch
−
6 ch (dedicated internal RAM 0n-chip peripheral I/O)
71
12
−
ROM correction function : 4 points, watch timer × 1 ch, IEBus controller (simple version) : 1 ch
4.0 to 5.5 V (A/D converter : 4.5 to 5.5 V)
-40°C to +85°C
V850ES
41MIPS (@ 32 MHz)
−
−
−
−
−
36
7 (6)
Note 1
16-bit timer/event counter (TMQ) × 1ch (inverter timer support possible)
16-bit timer/event counter (TMP) × 1 ch
16-bit timer/event counter (TMQ) × 1 ch
16-bit timer counter (TMP) × 3 ch
16-bit interval timer (TMM) × 1 ch
1 ch
CSI × 1 ch
UART × 2 ch
10 bits × 4 ch, 2 units (conversion time 2 µs)
−
−
39
−
−
ROM correction function : 4 points, software pull-up function, POC/LVI/clock monitor
20 to 32 MHz
3.5 to 5.5 V (A/D converter : 4.5 to 5.5 V)
T.B.D.
64-pin LQFP (14 × 14 mm)
-40°C to +85°C
64 KB (mask)
4 KB
128 KB (mask)
128 KB (flash)
6 KB
15 MIPS (@ 13 MHz) 22MIPS (@ 19 MHz)
128 KB (mask) 256 KB (mask) 384 KB (mask) 512 KB (mask)
256 KB (flash) 384 KB (flash) 512 KB (flash)
8 KB 16 KB 24 KB
75 mW (mask ROM version : @ 5 V, 13 MHz)
125 mW (flash memory version : @ 5 V, 13 MHz)
125 mW (mask ROM version : @5 V, 19 MHz)
185 mW (flash memory version : @ 5 V, 19 MHz) 125 mW (mask ROM version : @ 5 V, 19 MHz)
210 mW (flash memory version : @ 5 V, 19 MHz)
100-pin QFP (14 × 20 mm)
100-pin LQFP (14 × 14mm)
100-pin QFP (14 × 20mm)
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt
sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
Note Number of external interru
p
ts that can be used to release STOP mode.
Notes 1. Number of external interrupts that can be used to release STOP mode.
2. Onl
y
Y
p
roducts have an on-chi
p
I
2
C interface.
ASSP Lineup (1/3)
Pamphlet U15412EJ4V1PF
48
V850ES/FE2 V850ES/FF2
µPD70F3231µPD703231µPD70F3230µPD703230 µPD70F3233µPD703233µPD70F3232µPD703232
128 KB (flash)128 KB (mask)64 KB (flash)64 KB (mask) 256 KB (flash)256 KB (mask)128 KB (flash)128 KB (mask)
6 KB4 KB 12 KB6 KB
−
Provided (RUN, break)
−
Provided (RUN, break)
−Provided (RUN, break)
−
Provided (RUN, break)
−
Watch timer: 1 ch, on-chip POC/LVI, RAM hold flag, aFCAN controller: 1 ch
170 mW
(@5.0 V, 20 MHz)
155 mW
(@5.0 V, 20 MHz)
170 mW
(@5.0 V, 20 MHz) 170 mW
(@5.0 V, 20 MHz)
170 mW
(@5.0 V, 20 MHz)
155 mW
(@5.0 V, 20 MHz) 155 mW
(@5.0 V, 20 MHz)
155 mW
(@5.0 V, 20 MHz)
V850ES
29 MIPS (@20 MHz)
−
−
−
−
−
44 44
9(9)
Note
16-bit timer/event counter (TMP) × 4 ch
16-bit timer/event counter (TQM) × 1 ch
16-bit interval timer (TMM) × 1 ch
1 ch
CSI × 2 ch
UART (LIN compatible) × 2 ch
10-bit × 10 ch
−
−
51
−
When using main clock: 16 to 20 MHz
4.0 to 5.5V
64-pin TQFP (10 × 10 mm)
-40°C to +85°C, -40°C to +110°C
V850ES
29 MIPS (@20 MHz)
−
−
−
−
9(9)
Note
16-bit timer/event counter (TMP) × 4 ch
16-bit timer/event counter (TMQ) × 1 ch
16-bit interval timer (TMM) × 1 ch
1 ch
CSI × 2 ch
UART (LIN compatible) × 2 ch
10-bit × 12 ch
−
−
67
−
Watch timer: 1 ch, on-chip POC/LVI, RAM hold flag, aFCAN controller: 1 ch
When using main clock: 16 to 20 MHz
4.0 to 5.5V
80-pin TQFP (12 × 12mm)
-40°C to +85°C, -40°C to +110°C
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt
sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
V850ES/FG2 V850ES/FJ2
µPD70F3236µPD70F3235µPD703235 µPD70F3239µPD70F3238
µPD70F3237
V850ES
29 MIPS (@ 20 MHz)
512 KB (flash)384 KB (flash)384 KB (flash)
16 KB
256 KB (flash)
12 KB
256 KB (mask)
20 KB16 KB
256 KB (flash)
12 KB
Multiplexed
4
−
−
−
−
−
8373
16 bits
8/16 bits
SRAM, etc.
16 (16)Note
16-bit timer/event counter (TMP) × 4 ch
16-bit timer/event counter (TMQ) × 3 ch
16-bit interval timer (TMM) × 1 ch
1ch
CSI × 3 ch
UART (LIN compatible) × 4 ch
CSI × 3 ch
UART (LIN compatible) × 3 ch
10-bit × 24 ch
−
4 ch
128
−
Provided (RUN, break)
−Provided (RUN, break)
Watch timer: 1 ch, on-chip POC/LVI, RAM hold flag
aFCAN controller: 4 chaFCAN controller: 2 ch
When using main clock: 16 to 20 MHz
4.0 to 5.5V
170 mW (@ 5.0 V, 20 MHz)155 mW
(@ 5.0 V, 20 MHz)
µPD70F3234
128 KB (flash)
Provided (RUN, break)
170 mW
(@ 5.0 V, 20 MHz)
µPD703234
128 KB (mask)
6 KB
−
155 mW
(@ 5.0 V, 20 MHz) 200 mW (@ 5.0 V, 20 MHz)
144-pin LQFP (20 × 20 mm)
V850ES
29 MIPS (@ 20 MHz)
−
−
−
−
−
62
12 (12)Note
16-bit timer/event counter (TMP) × 4 ch
16-bit timer/event counter (TMQ) × 2 ch
16-bit interval timer (TMM) × 1 ch
1 ch
CSI × 2 ch
UART (LIN compatible) × 3 ch
10-bit × 16 ch
−
4 ch
84
−
Watch timer: 1 ch, on-chip POC/LVI, RAM hold flag, aFCAN controller: 2 ch
When using main clock: 16 to 20 MHz
4.0 to 5.5V
100-pin LQFP (14 × 14 mm)
-40°C to +85°C, -40°C to +110°C-40°C to +85°C, -40°C to +110°C
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt
sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
Note Number of external interru
p
ts that can be used to release STOP mode
Note Number of external interru
p
ts that can be used to release STOP mode
ASSP Lineup (2/3)
Pamphlet U15412EJ4V1PF 49
V850E/SV2 V850/SV1
µPD703166/3166Y µ
PD70F3166/F3166Y
µ
PD703041/3041Y
µ
PD703039/3039Y
µ
PD703040/3040Y
µPD70F3040/F3040Y µPD703038/3038Y µPD70F3038/F3038Y
V850E1 V850
55 MIPS (@ 40.5 MHz) 23 MIPS (@ 20 MHz)
512 KB (mask) 512 KB (flash) 192 KB (mask) 256 KB (mask) 256 KB (flash) 384 KB (mask) 384 KB (flash)
24 KB 8 KB 16 KB
Multiplexed/separate Multiplexed
26 bits 22 bits
8/16 bits 16 bits
8−
SRAM, etc. SRAM, etc.
75 (Y products : 76) 45 (Y products: 46)
12(12)
Note 1
9(6)
Note1
32-bit timer/event counter × 1 ch
16-bit timer/event counter × 6 ch
16-bit interval timer × 6 ch
8-bit timer/event counter × 12 ch
24-bit timer/event counter × 2 ch
16-bit timer/event counter × 2 ch
8-bit timer/event counter × 8 ch
1 ch 1 ch
CSI × 1 ch
CSI/I
2
C × 2 ch
Note 2
CSI/UART × 2ch
CSI with automatic transfer function × 2 ch
CSI × 3 ch
UART/CSI × 1 ch
UART × 1 ch
I
2
C × 1 ch
Note 2
10-bit × 24 ch 10-bit × 16 ch
− −
4 ch 6 ch (dedicated internal RAMinternal peripheral I/O)
171 135
24 16
Provided (RUN, break) −
Boundary scan function, 12- to 16-bit PWM output : 5 ch,
real-time output, ROM correction function : 8 points
Watch timer: 1 ch, 12- to 16-bit PWM output : 4 ch, V
sync
/H
sync
separator, ROM correction function : 4 points
10 to 40.5 MHz When using main clock: 4 to 20 MHz
When using subclock: 32.768 kHz
2.3 to 2.7 V (internal)
2.7 to 3.6 V (external) 3.1 to 3.6 V (@ 20 MHz)
2.7 to 3.6 V (@ 16 MHz)
134 mW
(@ 2.5 V, 40.5 MHz) 159 mW
(@ 2.5 V, 40.5 MHz) 82 mW (@ 3.3 V, 20 MHz) 148 mW (@ 3.3 V, 20 MHz) 82 mW (@ 3.3 V, 20 MHz) 148 mW (@ 3.3 V, 20 MHz)
257-pin FBGA (14 × 14 mm) 180-pin FBGA (13 × 13 mm)176-pin LQFP
(24 × 24 mm) 176-pin LQFP (24 × 24 mm)
180-pin FBGA (13 × 13 mm)
-10°C to +70°C-40°C to +85°C
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt
sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt
sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
V850/SF1 V850/DB1 V850ES/PM1
µPD703075AY µPD703076AY µPD703078AY µPD703079AY
µPD70F3079AY
µPD70F3080 µPD703081 µPD703228
V850 V850
18 MIPS (@ 16 MHz) 18 MIPS (@ 16 MHz)
128 KB (mask) 256 KB (mask) 256 KB (flash) 128 KB (flash) 128 KB (mask)
12 KB 16 KB 6 KB
Multiplexed −
22 bits −
16 bits −
− −
SRAM, etc. −
35 38 35 38 44 40
8 (6)Note 7 (7)Note 1 7 (7)Note 1
16-bit timer/event counter × 8 ch 16-bit timer/event counter (TMG) × 1 ch
16-bit timer/event counter (TM0) × 2 ch
8-bit timer/event counter (TM5) × 2 ch
1 ch 1 ch
CSI × 1 ch
CSI/I2C × 1 ch
CSI/UART × 2 ch
CSI × 3 ch
UART × 2 ch
10-bit × 12 ch 10-bit × 8 ch
− −
6 ch (dedicated internal RAM internal peripheral I/O) −
72 99 (Including 16 output-only)
12 8
− −
Watch timer: 1 ch
FCAN controller : 1 ch
ROM correction
function : 4 points
Watch timer: 1 ch
FCAN controller : 2 ch
ROM correction
function : 4 points
Watch timer: 1 ch
FCAN controller : 1 ch
ROM correction
function : 4 points
Watch timer: 1 ch
FCAN controller : 2 ch
ROM correction function : 4 points
Watch timer: 1 ch,16-bit PWM output: 6 ch
8-bit PWM output: 2 ch,
meter control PWM: 24 ch
DCAN controller: 2 ch
Watch timer: 1 ch,
16-bit PWM output: 6 ch
8-bit PWM output: 2 ch,
meter control PWM: 24 ch
DCAN controller: 1 ch
When using main clock: 4 to 16 MHz
When using subclock: 32.768 kHz When using main clock: 4 to 16 MHz
3.5 to 5.5 V (A/D converter: 4.5 to 5.5 V) 4.0 to 5.5 V
75 mW (@ 5 V, 16 MHz) 125 mW
(@ 5 V, 16 MHz) 180 mW (@ 5 V, 16 MHz) 120 mW (@ 5 V, 16 MHz)
100-pin LQFP (14 × 14 mm)
100-pin QFP (14 × 20 mm) 128-pin QFP (20 × 20 mm)
-40°C to +85°C-40°C to +85°C
V850ES
29 MIPS (@ 20 MHz)
128 KB (mask)/ROM-less
10 KB
Separate
19 bits
8/16 bits
3
SRAM, etc.
28
4 (4)Note 1
16-bit timer/event counter (TM1)
× 6 ch
8-bit timer/event counter (TM2)
× 2 ch
1 ch
CSI × 2 ch
UART × 2ch
16-bit × 6 ch (12 inputs)
−
−
68
−
−
Real-time counter
(watch timer) : 1 ch
ROM correction function : 4 points
8- to 12-bit PWM output : 4 ch
When using main clock: 2 to 20 MHz
When using subclock: 32.768 kHz
3.0 to 3.6 V (@ 20 MHz)
2.7 to 3.6 V (@ 10 MHz)
2.2 to 3.6 V (@ 32.768 kHz)
81 mW (@ 3.3 V, 20 MHz)
100-pin LQFP (14 × 14 mm)
-40°C to +85°C
Notes 1. Number of external interrupts that can be used to release STOP mode
2. Only Y products have an on-chip I
2
C interface.
Note Number of external interrupts that can be used to release STOP mode
ASSP Lineup (3/3)
Pamphlet U15412EJ4V1PF
50
V850E/MA3 V850E/ME2
µPD703131A/3131AY
µPD703132A/3132AY µPD703133A/3133AY µPD703134A/3134AY µPD70F3134A/F3134AY µPD703111A
V850E1 V850E1
106 MIPS (@ 80 MHz) 215 MIPS (@ 150 MHz)
256 KB (mask) 512 KB (mask) 512 KB (flash) ROM-less (instruction cache : 8 KB)
16 KB 32 KB 16 KB 32 KB Instruction: 128 KB; Data: 16 KB
Multiplexed/separate Separate
26 bits 26 bits
8/16 bits 8/16/32 bits
8 8
SDRAM, SRAM, etc. SDRAM, SRAM, etc.
41 59
26(26)
Note 1
40(32)
Note 1
16-bit interval timer (TMD) × 4 ch
16-bit timer/event counter (TMP) × 3 ch
16-bit timer/event counter (TMQ) × 1 ch (inverter timer support possible)
16-bit encoder counter/timer (TMENC) × 1 ch
16-bit timer/event counter (TMC) × 6 ch
16-bit interval timer (TMD) × 4 ch
16-bit encoder counter/timer (TMENC) × 2 ch
1 ch −
CSI/UART × 3 ch
UART/I
2
C × 1 ch
Note 2
CSI (with FIFO) × 1 ch
CSI (with FIFO)/UART × 1 ch
UART × 1 ch
10-bit × 8 ch 10-bit × 8 ch
8-bit × 2 ch −
4 ch 4 ch
101 77
11 1
Provided (RUN, break) Provided (RUN, break, trace)
ROM correction function : 4 points USB (function) × 1 ch, SSCG
16-bit PWM output × 2 ch
5 to 80 MHz 10 to 150 MHz
2.3 to 2.7 V (internal)/3.0 to 3.6 V (external)
1.35 to 1.65 V (internal)/3.0 to 3.6 V (external) (@ 133 MHz)
1.40 to 1.65 V (internal)/3.0 to 3.6 V (external) (@ 150 MHz)
T.B.D. 575 mW (@2.5 V, 80 MHz) 200 mW (@ 1.5 V, 150 MHz)
144-pin LQFP (20 × 20 mm)
161-pin FBGA (13 × 13 mm) 176-pin LQFP (24 × 24 mm)
240-pin FBGA (16 × 16 mm)
-40°C to +85°C
-40°C to +85°C (@133MHz), -40 to°C +70°C (@150MHz)
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt
sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
V850E/MA1 V850E/MA2
µPD703103A µPD703105A µPD703106A µPD703107A µPD70F3107A µPD703108
V850E1 V850E1
−67 MIPS (@ 50 MHz) −
ROM-less 128 KB (mask) 256 KB (mask) 256 KB (flash) ROM-less
4 KB 10 KB 4 KB
Separate Separate
26 bits 25 bits
8/16 bits 8/16 bits
8 4
SDRAM, SRAM, etc. SDRAM, SRAM, etc.
33 23
25 (17)Note 8 (4)Note
16-bit timer/event counter (TMC) × 4 ch
16-bit interval timer (TMD) × 4 ch 16-bit timer/event counter (TMC) × 2 ch
16-bit interval timer (TMD) × 4 ch
− −
CSI × 1 ch
CSI/UART × 2 ch
UART × 1 ch
CSI/UART × 2 ch
10-bit × 8 ch 10-bit × 4 ch
−
−
4 ch 4 ch
106 74
9 5
− −
12-bit PWM output × 2ch
−
−
4 to 50 MHz 4 to 40 MHz
3.0 to 3.6 V 3.0 to 3.6 V
528 mW (@ 3.3 V, 50 MHz) 627 mW (@ 3.3 V, 50 MHz) 416 mW (@ 3.3 V, 40 MHz)
144-pin LQFP (20 × 20 mm) 144-pin LQFP (20 × 20 mm)
161-pin FBGA (13 × 13 mm) 100-pin LQFP (14 × 14 mm)
-40°C to +85°C-40°C to +85°C
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt
sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
Notes 1. Number of external interrupts that can be used to release STOP mode
2. Onl
y
Y
p
roducts have an on-chi
p
I
2
C interface.
Note Number of external interru
p
ts that can be used to release STOP mode
High-End Lineup (1/2)
Pamphlet U15412EJ4V1PF 51
V850E/MS1 V850E/MS2
µPD703130
µPD703100A-33/-40
µPD703100-33/-40
µPD703101A-33
µPD703101-33
µPD703102A-33
µPD703102-33
µPD70F3102A-33
µPD70F3102-33
−
ROM-less 96 KB (mask) 128 KB (mask) 128 KB (flash)
47 MIPS (@ 33 MHz)
272 mW (@ 3.3 V, 33 MHz)
430 mW (@ 5 V, 33 MHz) 294 mW (@ 3.3 V, 33 MHz)
515 mW (@ 5 V, 33 MHz)
V850E1
4 KB
Separate
24 bits
8/16 bits
8
EDO DRAM, SRAM, etc.
47
25 (1)
Note1
16-bit timer/event counter × 6 ch
16-bit interval timer × 2 ch
−
CSI × 2 ch
CSI/UART × 2 ch
10-bit × 8 ch
−
4ch
122
9
−
−
2 to 40 MHz (-40 product)
2 to 33 MHz (-33 product)
3.0 to 3.6 V (internal, external) (A products)
3.0 to 3.6 V (internal)/4.5 to 5.5 V (external) (Products without A)
144-pin LQFP (20 × 20 mm)
157-pin FBGA (14 × 14 mm)
Note2
-40°C to +85°C
Note3
V850E1
−
ROM-less
4 KB
Separate
24 bits
8/16 bits
4
EDO DRAM, SRAM, etc.
35
10 (1)
Note1
16-bit timer/event counter × 4 ch
16-bit interval timer × 2 ch
−
CSI/UART × 2ch
10-bit × 4 ch
−
4 ch
52
5
−
−
10 to 33 MHz
3.0 to 3.6 V (internal)/
4.5 to 5.5 V (external)
218 mW (@ 3.3 V, 33 MHz)
100-pin LQFP (14 × 14 mm)
-40°C to +85°C
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
External 3.3V
External 5V
Data bus
Chip select signal
Memory controller
Interrupt
sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
V853
µPD703003A µPD703004A µPD703025A µPD70F3003A µPD70F3025A
V850
38 MIPS (@ 33 MHz)
128 KB (mask) 96 KB (mask) 256 KB (mask) 128 KB (flash) 256 KB (flash)
4 KB 8 KB 4 KB 8 KB
Multiplexed
20 bits
16 bits
−
SRAM, etc.
32
17(1)Note
16-bit timer/event counter × 4 ch
16-bit interval timer × 1 ch
−
−
CSI × 2 ch
CSI/UART × 2 ch
10 bits × 8 ch
2 ch
−
67
8
12-bit PWM output × 2 ch
2 to 33 MHz
4.5 to 5.5V
365 mW (@ 5 V, 33 MHz) 450 mW (@ 5 V, 33 MHz) 425 mW (@ 5 V, 33 MHz) 480 mW (@ 5 V, 33 MHz)
100-pin LQFP (14 × 14 mm)
-40°C to +85°C
Item
Part No.
CPU core
CPU performance
Internal ROM
Internal RAM
External bus
interface Bus type
Address bus
Data bus
Chip select signal
Memory controller
Interrupt
sources Internal
External
Timer/counter
Watchdog timer
Serial interface
A/D converter
D/A converter
DMA controller
Ports I/O
Input
Debug control unit
Other peripheral functions
Operating frequency
Power supply voltage
Power consumption (Typ.)
Package
Operating ambient temperature
Notes 1. Number of external interrupts that can be used to release STOP mode
2. µPD703100A-33, 703101A-33, 703102A-33, and 70F3102A-33 only
3. µPD703100-40, 703100A-40 : -40°C to +70°C
Others : -40°C to +85°C
Note Number of external interru
p
ts that can be used to release STOP mode
High-End Lineup (2/2)
Pamphlet U15412EJ4V1PF
V850 Series Development Environment
The V850 Series development
environment consists of tools designed
to make the development of application
systems using the V850 Series of high-
performance microcontrollers made by
NEC Electronics more pleasant, faster,
and more accurate.
Each one of these development tools
features functions to fully exploit the
performance of the V850 Series.
52 Pamphlet U15412EJ4V1PF
Pamphlet U15412EJ4V1PF
Emulator and evaluation board available at low prices
Low-Priced Development Environment Lineup
Function
Price
* For details, refer to V850 Series Development Environment Pamphlet (U15763E)
53
Low-priced full-function emulator
IECUBE
Ultra-low-priced on-chip emulator
N-Wire CARD
Starter kit for simple evaluation
TK-850 Series
• Low prices 1/3 or 1/4 the price of
conventional emulators
• Connectable to PC via USB
• Enhanced real-time RAM monitor and time
measuring function
• On-chip self-diagnosis function
• Debugger and simple programmer provided
• Palm size
• Ultra low price 1/10 the price of conventional
emulators
• Connectable to PC via PCMCIA
• Writing to the microcontroller on-chip flash
memory possible
• Debugger provided
• Evaluation kit enabling easy
performance testing
• Lineup for V850ES/Kx1, V850ES/SA2,
and V850ES/SG2
• Debugger, compiler, and circuit
diagrams provided as standard
Pamphlet U15412EJ4V1PF
54
Product planning
System design
System debugging
System evaluation
Commercialization
PM plus
IE, IECUBE
Hardware tools
Software tools
RX850, RX850 Pro
CA850
DF703xxx
SM850, SM plus
ID850, ID850NW,
ID850QB
+RD850, +RD850 Pro
+AZ850, +TW850
Hardware design
Fabrication
Standalone testing
Software design
Coding
Compiling/
assembly
Debugging
Product Name
Software package SP850
C compiler CA850
Note 1
Device file DF703xxx
Note 2
Project Manager PM plus
Notes 1, 3
Integrated debugger ID850
Note 1
, ID850NW
Note 1
, ID850QB
Note 4
System simulator SM850
Note 1
, SM plus
Note 5
Real-time OS RX850, RX850 Pro
Task debugger RD850, RD850 Pro
Note 6
System performance analyzer AZ850
Note 6
Middleware AP703000-Bxxx, AP703100-Bxxx
Performance analysis tool TW850
Note 1
Notes 1. Packaged in SP850
2. Download from the NEC Electronics Website.
(URL: http://www.necel.com/micro/index_e.html)
3. Included with CA850
4. Included with IECUBE and IE-V850E1-CD-NW.
5. Instruction simulation version: Included with SP850.
Instruction + peripheral simulation version: Only the SM plus for the µPD70F3261Y is included with
SP850.
6. Included with RX850, RX850 Pro
Remark For details, refer to the V850 Series Development Environment Pamphlet (U15763E).
Development Flow
Development Tools (1/3)
Software tools
Pamphlet U15412EJ4V1PF 55
Development Tools (2/3)
Hardware tools (when using IECUBE)
Hardware tools (using other emulators)
Hardware tools (when using N-Wire CARD)
Target Device In-Circuit Emulator
V850E/IA3, V850E/IA4, V850ES/IK1
V850ES/KE1, V850ES/KE1+, V850ES/KF1, V850ES/KF1+,
V850ES/KG1, V850ES/KG1+, V850ES/KJ1, V850ES/KJ1+
V850ES/SG2, V850ES/SJ2
V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2,
µPD703229Y, 70F3229Y
QB-V850EIA4-ZZZ
QB-V850ESKX1H-ZZZ
QB-V850ESSX2-ZZZ
QB-V850ESFX2-ZZZ
Remarks 1. A separate socket is required for each above emulator.
2. A power supply, a USB interface cable, a debugger, and a simple programmer are included. A PC interface board is not required.
3. For details, refer to the V850 Series Development Environment Pamphlet (U15763E).
Target Device On-Chip Debug Emulator
V850E/ME2, V850E/MA3, V850E/IA4, V850E/SV2, V850ES/SG2,
V850ES/SJ2, V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2,
V850ES/KJ1, V850ES/KJ1+, µPD70F3229Y IE-V850E1-CD-NW
Remarks 1. A target connection cable, a connector conversion board, a target connector, and a debugger are included.
A power supply and a PC interface board are not required.
2. For details, refer to the V850 Series Development Environment Pamphlet (U15763E).
Notes 1. A separate socket and probe are required for connection to the target system.
The optional PC interface board (IE-70000-PCI-IF-A or IE-70000-CD-IF-A) are required as a common part.
2. A separate socket is required for connection to the target system.
The optional PC interface board (IE-70000-PCI-IF-A or IE-70000-CD-IF-A) are required as a common part.
3. Depending on the target device package, a separate socket and probe may be required.
The following items are required as common items.
• PC interface board: IE-70000-PCI-IF-A or IE-70000-CD-IF-A
• Power supply: IE-70000-MC-PS-B
Remark
For details, refer to the V850 Series Development Environment Pamphlet (U15763E).
Target Device In-Circuit Emulator
Main Unit
V850E/IA1
V850E/IA2
V850E/MA1, V850E/MA2
V850ES/SA2, V850ES/SA3
V850ES/KF1, V850ES/KG1, V850ES/KJ1
V850ES/SG2, V850ES/SJ2 IE-V850ES-G1
IE-V850E-MC-A
IE-V850E-MC
IE-703102-MC
IE-703002-MC
V850ES/PM1
V850ES/FE2, V850/FF2, V850ES/FG2, V850ES/FJ2, µPD703229Y, 70F3229Y
V850ES/ST2
V850E/SV2
V850E/MS1 (5V), V850E/MS2 (5V)
V850E/MS1 (3.3V)
V850/SA1
V850/SB1, V850/SB2
V850/SV1
V850/SF1
V850/SC1, V850/SC2, V850/SC3
V853
IE-703116-MC-EM1
IE-703114-MC-EM1
IE-703107-MC-EM1
Note 3
IE-703204-G1-EM1
Note 1
IE-703217-G1-EM1
Note 2
IE-703288-G1-EM1
Note 2
IE-703228-G1-EM1
Note 2
IE-703239-G1-EM1
Note 2
IE-703220-G1-EM1
Note 2
IE-703166-MC-EM1
IE-703102-MC-EM1
Note 3
IE-703102-MC-EM1-A
IE-703017-MC-EM1
Note 3
IE-703037-MC-EM1
Note 3
IE-703040-MC-EM1
Note 3
IE-703079-MC-EM1
Note 3
IE-703089-MC-EM1
IE-703003-MC-EM1
Emulation Board
Pamphlet U15412EJ4V1PF
•IE-V850ES-G1 configuration example
In-circuit emulator (main unit)
Emulation board (connected inside main unit)
Emulation probe
Conversion adapter/conversion socket
PC interface cable (provided with )
Power supply cable (provided with )
•IE-V850E-MC, IE-V850E-MC-A, IE-703102-MC, IE-703002-MC
configuration example
In-circuit emulator (main unit)
Option board
Power supply unit
Conversion adapter/conversion socket (provided with )
PC interface cable (provided with )
Development Tools (3/3)
•IECUBE configuration example
In-circuit emulator (IECUBE)
AC adapter (provided with )
USB interface cable (provided with )
Extension probe
Exchange adapter (provided with Note)
Target connector (provided with Note)
Mount adapter
•N-Wire CARD configuration example
Host machine (with PCMCIA slot)
On-chip emulator IE-V850E1-CD-NW
In-circuit emulator connection cable
Connector conversion board
In-circuit emulator connector
Note If ordering the in-circuit emulator ( ), if the part number
ends in "-ZZZ", the above exchange adapter ( ) and
target connector ( ) are not provided.
56
Pamphlet U15412EJ4V1PF 57
Integrated development
environment
Note The RD850, RD850 Pro, and AZ850 can be used with the ID850, ID850QB, MULTI, PARTNER, and WATCHPOINT.
Task debugger Analyzer
Real-time OS Compiler Debugger In-circuit emulator
N-Wire emulator
RD850
Note
RD850 Pro
Note
RX850
RX850 Pro
G-OS
Native-G
GAIO
Nucleus PLUS
ATI
NORTi
Mispo
CA850
CCV850
CCV850E
GHS
XCC-V
XASS-V
GAIO
AZ850
Note
TW850
AZ850
TW850
ID850
ZIPC850
ID850
ID850QB
ID850NW
CATS
AZ850
MULTI
GHS
KMC
AZ850
PARTNER
AZ850
WATCHPOINT
Sophia Systems
GNU
Red Hat
exeGCC
KMC
CodeWarrior
Metrowerks
micro VIEW-G
micro VIEW-PLUS
YDC
Refer to Development Tools Hardware tools
(when using N-Wire CARD) (p. 55)
Refer to Development Tools Hardware tools
(when using IECUBE) (p. 55)
IE-703002-MC
IE-703102-MC
IE-V850E-MC
IE-V850E-MC-A
IE-V850ES-G1
Nx85ET
IE-70000-MC-NW-A
Refer to Development Tools Hardware tools
(when using N-Wire CARD) (p. 55)
IE-V850E1-CD-NW
V852
V853, V853A
V850/SA1
V850/SB1, V850/SB2
V850E/MA1
V850E/ IA1
Nx85ET
Nx85ET, V850E/ME2, V850E/MA3,
NA85E2, AS85EP2
V850E/MA3
RTE-V852-IE
RTE-V853-IE
RTE-V850/SA1-IE
RTE-V850/SB1-IE
RTE-V850E/MA1-IE
RTE-V850E/IA1-IE
RTE-1000-TP
RTE-2000-TP
KIT-V850E/MA3-IE
Midas Lab
advice V853
advice V850/SA1
advice V850/SB1
advice V850E/MS1
advice V850E/MA1
advice Nx85ET
advice V850E/IA1
advice V850E/ME2
advice V850ES/KF1
advice V850ES/KG1
advice V850ES/KJ1
YDC
V853
V850/SA1
V850/SB1
V850E/MS1
V850E/MA1
Nx85ET
V850E/IA1
V850E/ME2
V850ES/KF1
V850ES/KG1
V850ES/KJ1
PARTNER-ET
II
PARTNER-J
PARTNER-Jet
KMC
Nx85ET, V850E/ME2
Nx85ET, V850E/ME2
Nx85ET, V850E/ME2
V853, V853A
V850/SV1
V850/SA1
V850/SB1, V850/SB2
V850E/MS1
V850E/MA1
Nx85ET, Nx85E
V850E/IA1
V850ES/KF1, V850ES/KG1,
V850ES/KJ1
V850E/ME2
V850ES/SG2, V850ES/SJ2,
V850ES/Fx2, V850ES/Kx1+,
V850ES/Kx1, V850ES/IK1,
V850E/IA3, V850E/IA4
UniSTAC V853
UniSTAC V850/SV1
UniSTAC V850/SA1
UniSTAC V850/SB1
UniSTAC V850E/MS1
UniSTAC V850E/MA1
UniSTAC Nx85ET
UniSTAC V850E/IA1
UniSTAC V850ES/Kx1
UniSTACII/J V850E/ME2
IECUBE
Sophia Systems
QB-V850ESSX2-ZZZ
QB-V850EIA4-ZZZ
QB-V850ESKX1H-ZZZ
QB-V850ESFX2-ZZZ
ATI :Accelerated Technology, Inc.
CATS :Communication and Technology Systems, Inc.
GAIO :Gaio Technology Co., Ltd.
GHS :Green Hills Software, Inc.
KMC :Kyoto Microcomputer Corporation
Metrowerks :Metrowerks Corporation
Midas Lab :Midas Lab Co., Ltd.
Mispo :MiSPO, Inc.
Red Hat :Red Hat Corporation
Sophia Systems :Sophia Systems Co., Ltd.
YDC :Yokogawa Digital Computer Corporation
Unmarked :NEC Electronics
Development environment using in-circuit emulator, N-Wire emulator
V850 Series Development Environment (1/2)
Pamphlet U15412EJ4V1PF
58
Development environment using ROM emulator, evaluation board
V850 Series Development Environment (2/2)
Evaluation board
Task debugger Analyzer
Real-time OS ROM emulator
Compiler Debugger
Low-cost evaluation board
(limited functions)
RD850
Note
RD850 Pro
Note
RX850
RX850 Pro
Nucleus PLUS
ATI
NORTi
Mispo
CA850
CA850
exeGCC
KMC KMC
CCV850
CCV850E
GHS
AZ850
Note
PARTNER
AZ850
MULTI
GHS
XDEB-V
SystemSimulator
GAIO
GNU
Red Hat
G-OS
Native-G
GAIO
XCC-V
XASS-V
GAIO
Code Warrior
Metrowerks
PARTNER-ET
II
KMC
MDX700
Lightwell
EMUSE
Midoriya
EMUSE-G
II
Midoriya
CEB-V850E/MS1
CEB-V850E/MA1 V850E/MS1
V850E/MA1
CEB-V850/SA1
CEB-V850/SB1 V850/SA1
V850/SB1
Cosmo
TK-850/SA2 V850ES/SA2
APPLY
TK-850/SG2 V850ES/SG2
APPLY
TK-850/KG1 V850ES/KG1
APPLY
RTE-V850E/MS1-PC
RTE-V850E/MA1-CB
RTE-V850E/ME2-CB
RTE-V850ES/SA3-CB
V850E/MS1
V850E/MA1
V850E/ME2
V850ES/SA3
RTE-V852-PC
RTE-V853-PC V852
V853
Midas Lab
Monitor version ID850
APPLY :Application Corporation
ATI :Accelerated Technology, Inc.
Cosmo :Cosmo Co., Ltd.
Red Hat :Red Hat Corporation
GAIO :Gaio Technology Co., Ltd.
GHS :Green Hills Software, Inc.
KMC :Kyoto Microcomputer Corporation
Lightwell :Lightwell Co., Ltd.
Metrowerks :Metrowerks Corporation
Midas Lab :Midas Lab, Co., Ltd.
Midoriya :Midoriya Electric Co., Ltd.
Mispo :MiSPO, Inc.
WRS :Wind River Systems, Inc.
eSOL :eSOL Co., Ltd.
Unmarked :NEC Electronics
Note RD850, RD850 Pro, and AZ850 can be used with MULTI, PARTNER.
CEB-V850E/MA3
CEB-V850E/IA1
CEB-V850ES/FJ2
CEB-V850ES/SJ2
V850E/MA3
V850E/IA1
V850ES/FJ2
V850ES/SJ2
V850E/MA1
V850E/ME2
SG-703107-1
SG-703111-1
Evaluation board
Pamphlet U15412EJ4V1PF 59
Software package (SP850) C compiler (CA850)
Product configuration
The SP850 software package consists of the following software
development tools.
•C compiler (CA850)
•Project Manager (PM plus)
•Integrated debugger (ID850, ID850NW) (to be packaged)
•System simulator (SM850, SM plus) (to be packaged)
•Performance analysis tuning tool (TW850)
•Device file (DF703xxx)
Features
•Complies with ANSI-C, a C language standard.
•Supports libraries for embedded systems
•Compact code size and faster execution speed can be realized through
powerful optimization
•Utilities useful for embedded systems (ROMization processor, etc.)
•Description of embedded systems in C language (specification of
memory allocation and I/O register access) is possible.
Project manager (PM plus)
Features
•Project management (management of target chip, source, and
environment during debugging is possible.)
•Supports wizard function during project creation
•Automation of series of operations consisting of edit, build, and debug
•Integration of Help function
System simulator (SM850, SM plus)
Features
•Same operability as debugger
•Target-less evaluation prior to target completion possible
•In addition to the operation of the CPU itself, target system operation including
on-chip peripheral unit and interrupt servicing can also be simulated.
•Pseudo-target system construction and I/O operation are possible through
external parts.
•Data generated by 0/1 logic and timing charts can be input to the program
being simulated.
•Larger number of events than in-circuit emulator
•Execution speed estimates can be done on the host machine to accurately
simulate pipeline operationNote.
•Construction by user target system users is possible through user open
interface.
•A peripheral I/O register status can be specified and when this status occurs,
the system can be made to output an interrupt at the desired timing or transfer
data to memory (peripheral I/O register event & action function).
Note The pipeline mode is supported by the V853.
Target devices
V853, V850/SA1, V850/SB1, V850/SB2, V850/SF1, V850/SC1,
V850/SC2, V850/SC3, V850E/MS1, V850E/MA1, V850E/MA2,
V850E/IA1, V850E/IA2, V850ES/SA2, V850ES/SA3, V850ES/KF1, V850ES/
KG1, V850ES/KJ1, V850ES/SG2Note, V850ES/SJ2Note, V850ES/FE2Note,
V850ES/FF2Note, V850ES/FG2Note, V850ES/FJ2Note
Note Only SM plus is supported
Software Product
Features
•Supports V850E and V850ES
•Emulator for on-chip debugging
•Enables realization of low-cost development environment
•Compact PC card type
•Function for download to internal flash ROM
•Same ease of operation as ID850
Target Devices
V850E/ME2, V850E/MA3, V850E/IA4, V850E/SV2, V850ES/SG2, V850ES/SJ2,
V850ES/FE2, V850ES/FF2, V850ES/FG2, V850ES/FJ2, V850ES/KJ1, V850ES/
KJ1+, µPD70F3229Y
N-Wire card (IE-V850E1-CD-NW)
Pamphlet U15412EJ4V1PF
60
Integrated debugger (ID850, ID850NW, ID850QB)
Real-time OSs (RX850, RX850 Pro)
Features
•Comply with global standard (µITRON 3.0 specifications).
•Support power management function.
•Enable embedding of required functions only (selection of system calls
to be used).
•Support sophisticated task development through task debugger (RD).
•Support application operation analysis through system performance
analyzer (AZ)
•Inherit attributes of real-time OS of 16-bit V Series and 78K Series
Features
•Supports object files
•Debugging at source level
•Debugging using target resources
•Real-time execution on target
•Event setting according to complex software operation
•Online help function
System performance analyzer (AZ850)
Features
•Detection of bugs through system timing errors
•Detection of bugs due to simultaneous operation of complex tasks
•Detection/analysis of real-time system execution performance
•Operation linked to various debuggers
Task debuggers (RD850, RD850 Pro)
Features
•Display detailed information on OS resources such as tasks.
•Display source of referenced tasks.
•Included with real-time OS (RX850, RX850 Pro)
TCP/IP software library (RX-NET) for V850E products
Product configuration
•TCP/IP protocol stack
•Applications
•LAN control driver
Features
•RFC-compliant
•Support of numerous socket interfaces/libraries
•Support of applications as option products
•Provided device driver
•Support of NEC Electronics real-time OS (RX850 Pro)
Target devices
V850E products
Features
•Emulator functions loaded in dedicated chip to realize high equivalence
•Connectable to variety of computers
•Large array of emulation functions
•Realization of maximum operating frequency equivalent to that of device
In-circuit emulator (IE, IECUBE)
Features
•Performance analysis changing the internal ROM size, instruction
cache size, etc., is possible.
•Display of inter-function call relationships, call count information,
function execution time information, and cache mishit information
•Functions optimally placed to reduce cache mishit count
•Functions causing bottlenecks placed into internal ROM or other
high-speed access memory
Performance analysis tuning tool (TW850)
Pamphlet U15412EJ4V1PF 61
• Kernel
Compliant with OSEK/VDX OS Ver. 2.0 specifications
Supports 4 conformance classes: BCC1, BCC2, ECC1, and ECC2.
• Configurator
Configurator (OIL850) allowing easy system information creation provided as standard.
Configuration files support formats compatible with OIL Ver. 2.0.
• Task debugger (RD-OSEK850)
Task debugger effective for application debugging using RX-OSEK850 provided as standard
Features
• General-purpose evaluation boards available as RISC microcontroller software development platform
• Target CPU: V850E/MA1, V850E/ME2
• Industry standard PC-compatible interfaces including PCI, ISA, PCMCIA, E-IDE, EthernetTM, Serial, Parallel, PS/2, and USB, provided
• CPU independent motherboards and CPU boards used combined
• Bundled real-time OS, middleware, and sample drivers
• MULTI-PARTNER remote monitor version can be used
• Reference design information provided
Time
Actually tested
Board design/
development
Software design/
development
Circuit diagrams attached This board usable for comparison purposes
Bundle OS/
middleware Various peripheral devices are
mounted, so debugging
can be started from
device-independent parts
Provide user-own coding block as
sample according to this board
I want to measure
CPU performance.
Is it possible to realize
such a function?
First time I use this device, please
provide sample circuits.
I would like to use
OS/middleware.
H/W
S/W
I want to start software
development prior to the board.
Likely to be a long time until
OS/middleware are ready
Not working properly. Is the
cause hardware or software?
Debug
At such times, RISC microcontroller reference platform
Device selection
Features
By deepening cooperation with third-party companies and forming an array of tools combining NEC Electronics-made tools and third-party-made tools,
NEC Electronics offers development environments that support the diverse needs of users.
Cooperation with third parties
OSEK/VDX specifications compliant OS (RX-OSEK850)
RISC microcontroller reference platform (SolutionGearTM)
Pamphlet U15412EJ4V1PF
62
V850 Series Website
Microcontroller Search Tool
•
Facility for searching for V850 Series microcontrollers
by function
Information about V850 microcontrollers and V850 microcontroller
development environment can be viewed at the NEC Electronics
Microcomputer website.
Product Lineup
•
Microcontroller product information
Document Download
•
Microcontroller, development environment,
and middleware documents can be downloaded
from this area.
http://www.necel.com/micro/english/document/index.html
Development Tool Download
•
V850 Series development tools can be downloaded
from this area. Customers who are registered users
receive upgrade information by email.
http://www.necel.com/micro/ods/eng/index.html
http://www.necel.com/micro/index_e.htmlhttp://www.necel.com/micro/index_e.html
Pamphlet U15412EJ4V1PF 63
Specify search
condition(s) here.
The corresponding NEC Electronics
development environment
documents can be searched from
here with a single link.
Facility for searching V850 Series microcontrollers by function.
Microcontroller Search Tool
Document Information List
Development Tool List
Pamphlet U15412EJ4V1PF
64
Product Lineup
Pamphlet U15412EJ4V1PF 65
MEMO
Pamphlet U15412EJ4V1PF
66
MEMO
Pamphlet U15412EJ4V1PF 67
EEPROM, IEBus, IECUBE, SolutionGear, and VR are trademarks of NEC Electronics Corporation.
MIPS is a trademark of MIPS Technologies, Inc. in the United States.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in
the United States and/or other countries.
JAVA and all trademarks and logos related to JAVA are either registered trademarks or trademarks of Sun
Microsystems, Inc. in the United States and/or other countries.
Ethernet is a trademark of Xerox Corporation.
TRON stands for The Real-time Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
µITRON is an abbreviation of Micro Industrial TRON.
TRON, ITRON, and µITRON do not refer to specific products or product groups.
All other marks or trademarks in this document are property of their respective holders.
The information in this document is current as of September, 2004. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
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appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
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NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
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systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
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1753, Shimonumabe, Nakahara-ku,
Kawasaki, Kanagawa 211-8668,
Japan
Tel: 044-435-5111
http://www.necel.com/
[North America]
NEC Electronics America, Inc.
2880 Scott Blvd.
Santa Clara, CA 95050-2554, U.S.A.
Tel: 408-588-6000
800-366-9782
http://www.necelam.com/
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Room 2509-2510, Bank of China Tower,
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Tel: 021-5888-5400
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Tel: 02-2719-2377
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#12-08 Novena Square,
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Tel: 6253-8311
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12/F., Cityplaza 4,
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Seoul, 135-080, Korea
Tel: 02-558-3737
For further information,
please contact:
C2002, 2004 Printed in Japan
G04.1
[Europe]
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Arcadiastrasse 10
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Document No. U15412EJ4V1PF00 (4th edition)
Date Published January 2005 N CP(K)
