LC Filter
LC Filter
Left
Right
4.5 V-26 V
PSU
Tuner AM/FM
CD/ MP3
Aux in
Left
Right
Audio Processor
And control
TPA3116D2
AM /FM Avoidance
Control
FAULTZ
SDZ
MUTE
Sync
Capable of synchronizing to other devices
GAIN/SLV
GAIN control and Master /Slave setting
AM2,1,0
PLIMIT
Power Limit
PBTL
Detect
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA3116D2
,
TPA3118D2
,
TPA3130D2
SLOS708G –APRIL 2012–REVISED DECEMBER 2017
TPA3116D2 15-W, 30-W, 50-W Filter-Free Class-D Stereo Amplifier Family With AM
Avoidance
1
1 Features
1• Supports Multiple Output Configurations
– 2 × 50 W Into a 4-ΩBTL Load at 21 V
(TPA3116D2)
– 2 × 30 W Into a 8-ΩBTL Load at 24 V
(TPA3118D2)
– 2 × 15 W Into a 8-ΩBTL Load at 15 V
(TPA3130D2)
• Wide Voltage Range: 4.5 V to 26 V
• Efficient Class-D Operation
– >90% Power Efficiency Combined With Low
Idle Loss Greatly Reduces Heat Sink Size
– Advanced Modulation Schemes
• Multiple Switching Frequencies
– AM Avoidance
– Master and Slave Synchronization
– Up to 1.2-MHz Switching Frequency
• Feedback Power-Stage Architecture With High
PSRR Reduces PSU Requirements
• Programmable Power Limit
• Differential and Single-Ended Inputs
• Stereo and Mono Mode With Single-Filter Mono
Configuration
• Single Power Supply Reduces Component Count
• Integrated Self-Protection Circuits Including
Overvoltage, Undervoltage, Overtemperature, DC-
Detect, and Short Circuit With Error Reporting
• Thermally Enhanced Packages
– DAD (32-Pin HTSSOP Pad Up)
– DAP (32-Pin HTSSOP Pad Down)
• –40°C to 85°C Ambient Temperature Range
2 Applications
• Mini-Micro Component, Speaker Bar, Docks
• After-Market Automotive
• CRT TV
• Consumer Audio Applications
3 Description
The TPA31xxD2 series are stereo efficient, digital
amplifier power stage for driving speakers up to 100
W/2Ωin mono. The high efficiency of the
TPA3130D2 allows it to do 2 × 15 W without external
heat sink on a single layer PCB. The TPA3118D2 can
even run 2 × 30 W / 8 Ωwithout heat sink on a dual
layer PCB. If even higher power is needed the
TPA3116D2 does 2 × 50 W / 4 Ωwith a small heat-
sink attached to its top side PowerPAD. All three
devices share the same footprint enabling a single
PCB to be used across different power levels.
The TPA31xxD2 advanced oscillator/PLL circuit
employs a multiple switching frequency option to
avoid AM interferences; this is achieved together with
an option of either master or slave option, making it
possible to synchronize multiple devices.
The TPA31xxD2 devices are fully protected against
faults with short-circuit protection and thermal
protection as well as overvoltage, undervoltage, and
DC protection. Faults are reported back to the
processor to prevent devices from being damaged
during overload conditions.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPA3116D2 DAD (32) 11.00 mm × 6.20 mm
TPA3118D2
TPA3130D2 DAP (32) 11.00 mm × 6.20 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Application Circuit
2
TPA3116D2
,
TPA3118D2
,
TPA3130D2
SLOS708G –APRIL 2012–REVISED DECEMBER 2017
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Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 DC Electrical Characteristics .................................... 6
6.6 AC Electrical Characteristics..................................... 7
6.7 Typical Characteristics.............................................. 8
7 Detailed Description............................................ 13
7.1 Overview................................................................. 13
7.2 Functional Block Diagram....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 24
8 Application and Implementation ........................ 25
8.1 Application Information............................................ 25
8.2 Typical Application.................................................. 25
9 Power Supply Recommendations...................... 28
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 29
10.3 Heat Sink Used on the EVM................................. 31
11 Device and Documentation Support................. 32
11.1 Related Links ........................................................ 32
11.2 Receiving Notification of Documentation Updates 32
11.3 Community Resources.......................................... 32
11.4 Trademarks........................................................... 32
11.5 Electrostatic Discharge Caution............................ 32
11.6 Glossary................................................................ 32
12 Mechanical, Packaging, and Orderable
Information........................................................... 32
4 Revision History
Changes from Revision F (February 2017) to Revision G Page
• Changed R to GND column row 1 From: "Short" To: "Open" in Table 3 ............................................................................. 16
• Changed R to GVDD column row 1 From: "Open" To: "Short" in Table 3........................................................................... 16
Changes from Revision E (September 2015) to Revision F Page
• Changed pin 20 Description From: ceramic cap to OUTPL To: ceramic cap to OUTNL in the Pin Functions table............. 4
• Changed pin 24 Description From: ceramic cap to OUTNL To: ceramic cap to OUTPL in the Pin Functions table............. 4
• Changed 2.3 Hz To 1.9 Hz for HIGH-PASS FILTER in Table 2 ......................................................................................... 14
Changes from Revision D (January 2015) to Revision E Page
• Deleted Package DAP (32) from Part Number TPA3116D2 in the Device Information table ............................................... 1
Changes from Revision C (April 2012) to Revision D Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision B (May 2012) to Revision C Page
• Changed Notes 2 and 3 of the Thermal Information Table.................................................................................................... 6
• Changed the Gain (BTL) Test Condition values for R1 and R2............................................................................................. 6
• Changed the Gain (SLV) Test Condition values for R1 and R2............................................................................................. 6
• Changed the System Block Diagram.................................................................................................................................... 13
32
31
30
29
19
13
14
15
16 17
18
20
1
2
3
4
5
6
7
8
9
10
11
12 21
22
23
24
28
27
26
25
FAULTZ
SDZ
SYNC
AM0
AM1
MUTE
LINN
LINP
PLIMIT
RINN
GVDD
RINP
AVCC
OUTPR
PVCC
BSPL
GND
OUTPL
PVCC
OUTNL
BSNL
PVCC
OUTNR
BSNR
MODSEL
BSPR
GND
GND
PVCC
GND
GAIN/SLV
AM2
Thermal
PAD
32
31
30
29
19
13
14
15
16 17
18
20
1
2
3
4
5
6
7
8
9
10
11
12 21
22
23
24
28
27
26
25
FAULTZ
SDZ
SYNC
AM0
AM1
MUTE
LINN
LINP
PLIMIT
RINN
GVDD
RINP
AVCC
OUTPR
PVCC
BSPL
GND
OUTPL
PVCC
OUTNL
BSNL
PVCC
OUTNR
BSNR
MODSEL
BSPR
GND
GND
PVCC
GND
GAIN/SLV
AM2
Thermal
PAD
3
TPA3116D2
,
TPA3118D2
,
TPA3130D2
www.ti.com
SLOS708G –APRIL 2012–REVISED DECEMBER 2017
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5 Pin Configuration and Functions
DAD Package
32-Pin HTSSOP With PowerPAD Up
TPA3116D2 Only, Top View
DAP Package
32-Pin HTSSOP With PowerPAD Down
Top View
4
TPA3116D2
,
TPA3118D2
,
TPA3130D2
SLOS708G –APRIL 2012–REVISED DECEMBER 2017
www.ti.com
Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2
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(1) TYPE: DO = Digital Output, I = Analog Input, G = General Ground, PO = Power Output, BST = Boot Strap.
Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 MODSEL I Mode selection logic input (LOW = BD mode, HIGH = 1 SPW mode). TTL logic levels with compliance to
AVCC.
2 SDZ I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with
compliance to AVCC.
3 FAULTZ DO General fault reporting including Over-temp, DC Detect. Open drain.
FAULTZ = High, normal operation
FAULTZ = Low, fault condition
4 RINP I Positive audio input for right channel. Biased at 3 V.
5 RINN I Negative audio input for right channel. Biased at 3 V.
6 PLIMIT I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly
to GVDD for no power limit.
7 GVDD PO Internally generated gate voltage supply. Not to be used as a supply or connected to any component other
than a 1 µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers.
8 GAIN/SLV I Selects Gain and selects between Master and Slave mode depending on pin voltage divider.
9 GND G Ground
10 LINP I Positive audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
11 LINN I Negative audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode.
12 MUTE I Mute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic
levels with compliance to AVCC.
13 AM2 I AM Avoidance Frequency Selection
14 AM1 I AM Avoidance Frequency Selection
15 AM0 I AM Avoidance Frequency Selection
16 SYNC DIO Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV terminal.
17 AVCC P Analog Supply
18 PVCC P Power supply
19 PVCC P Power supply
20 BSNL BST Boot strap for negative left channel output, connect to 220 nF X5R, or better ceramic cap to OUTNL
21 OUTNL PO Negative left channel output
22 GND G Ground
23 OUTPL PO Positive left channel output
24 BSPL BST Boot strap for positive left channel output, connect to 220 nF X5R, or better ceramic cap to OUTPL
25 GND G Ground
26 BSNR BST Boot strap for negative right channel output, connect to 220 nF X5R, or better ceramic cap to OUTNR
27 OUTNR PO Negative right channel output
28 GND G Ground
29 OUTPR PO Positive right channel output
30 BSPR BST Boot strap for positive right channel output, connect to 220 nF X5R or better ceramic cap to OUTPR
31 PVCC P Power supply
32 PVCC P Power supply
33 PowerPAD G Connect to GND for best system performance. If not connected to GND, leave floating.
5
TPA3116D2
,
TPA3118D2
,
TPA3130D2
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SLOS708G –APRIL 2012–REVISED DECEMBER 2017
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(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) 100 kΩseries resistor is needed if maximum slew rate is exceeded.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VCC PVCC, AVCC –0.3 30 V
Input voltage, VI
INPL, INNL, INPR, INNR –0.3 6.3 V
PLIMIT, GAIN / SLV, SYNC –0.3 GVDD+0.3 V
AM0, AM1, AM2, MUTE, SDZ, MODSEL –0.3 PVCC+0.3 V
Slew rate, maximum(2) AM0, AM1, AM2, MUTE, SDZ, MODSEL 10 V/ms
Operating free-air temperature, TA–40 85 °C
Operating junction temperature , TJ–40 150 °C
Storage temperature, Tstg –40 125 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. .
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2) ±500
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
VCC Supply voltage PVCC, AVCC 4.5 26 V
VIH High-level input
voltage AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL 2 V
VIL Low-level input
voltage AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL 0.8 V
VOL Low-level output
voltage FAULTZ, RPULL-UP = 100 kΩ, PVCC = 26 V 0.8 V
IIH High-level input
current AM0, AM1, AM2, MUTE, SDZ, MODSEL (VI= 2 V, VCC = 18 V) 50 µA
RL(BTL) Minimum load
Impedance
Output filter: L = 10 µH, C = 680 nF TPA3116D2, TPA3118D2 3.2 4
Ω
TPA3130D2 5.6 8
RL(PBTL) Output filter: L = 10 µH, C = 1 µF TPA3116D2, TPA3118D2 1.6
TPA3130D2 3.2 4
LoOutput-filter
Inductance Minimum output filter inductance under short-circuit condition 1 µH
6
TPA3116D2
,
TPA3118D2
,
TPA3130D2
SLOS708G –APRIL 2012–REVISED DECEMBER 2017
www.ti.com
Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) For the PCB layout please see the TPA3130D2EVM user guide.
(3) For the PCB layout please see the TPA3118D2EVM user guide.
(4) The heat sink drawing used for the thermal model data are shown in the application section, size: 14mm wide, 50mm long, 25mm high.
6.4 Thermal Information
THERMAL METRIC(1) TPA3130D2 TPA3118D2 TPA3116D2
UNITDAP(2) DAP(3) DAD(4)
32 PINS 32 PINS 32 PINS
RθJA Junction-to-ambient thermal resistance 36 22 14 °C/WψJT Junction-to-top characterization parameter 0.4 0.3 1.2
ψJB Junction-to-board characterization parameter 5.9 4.7 5.7
6.5 DC Electrical Characteristics
TA= 25°C, AVCC = PVCC = 12 V to 24 V, RL= 4 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
| VOS |Class-D output offset voltage (measured
differentially) VI= 0 V, Gain = 36 dB 1.5 15 mV
ICC Quiescent supply current SDZ = 2 V, No load or filter, PVCC = 12 V 20 35 mA
SDZ = 2 V, No load or filter, PVCC = 24 V 32 50
ICC(SD) Quiescent supply current in shutdown
mode SDZ = 0.8 V, No load or filter, PVCC = 12 V <50 µA
SDZ = 0.8 V, No load or filter, PVCC = 24 V 50 400
rDS(on) Drain-source on-state resistance,
measured pin to pin PVCC = 21 V, Iout = 500 mA, TJ= 25°C 120 mΩ
G Gain (BTL)
R1 = 5.6 kΩ, R2 = Open 19 20 21 dB
R1 = 20 kΩ, R2 = 100 kΩ25 26 27
R1 = 39 kΩ, R2 = 100 kΩ31 32 33 dB
R1 = 47 kΩ, R2 = 75 kΩ35 36 37
G Gain (SLV)
R1 = 51 kΩ, R2 = 51 kΩ19 20 21 dB
R1 = 75 kΩ, R2 = 47 kΩ25 26 27
R1 = 100 kΩ, R2 = 39 kΩ31 32 33 dB
R1 = 100 kΩ, R2 = 16 kΩ35 36 37
ton Turn-on time SDZ = 2 V 10 ms
tOFF Turn-off time SDZ = 0.8 V 2 µs
GVDD Gate drive supply IGVDD < 200 µA 6.4 6.9 7.4 V
VOOutput voltage maximum under PLIMIT
control V(PLIMIT) = 2 V; VI= 1 Vrms 6.75 7.90 8.75 V
7
TPA3116D2
,
TPA3118D2
,
TPA3130D2
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6.6 AC Electrical Characteristics
TA= 25°C, AVCC = PVCC = 12 V to 24 V, RL= 4 Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
KSVR Power supply ripple rejection 200 mVPP ripple at 1 kHz, Gain = 20 dB, Inputs AC-
coupled to GND –70 dB
POContinuous output power THD+N = 10%, f = 1 kHz, PVCC = 14.4 V 25 W
THD+N = 10%, f = 1 kHz, PVCC = 21 V 50
THD+N Total harmonic distortion + noise VCC = 21 V, f = 1 kHz, PO= 25 W (half-power) 0.1%
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB 65 µV
–80 dBV
Crosstalk VO= 1 Vrms, Gain = 20 dB, f = 1 kHz –100 dB
SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB,
A-weighted 102 dB
fOSC Oscillator frequency
AM2=0, AM1=0, AM0=0 376 400 424
kHz
AM2=0, AM1=0, AM0=1 470 500 530
AM2=0, AM1=1, AM0=0 564 600 636
AM2=0, AM1=1, AM0=1 940 1000 1060
AM2=1, AM1=0, AM0=0 1128 1200 1278
AM2=1, AM1=0, AM0=1 ReservedAM2=1, AM1=1, AM0=0
AM2=1, AM1=1, AM0=1
Thermal trip point 150+ °C
Thermal hysteresis 15 °C
Over current trip point TPA3130D2 4.5 A
TPA3118D2, TPA3116D2 7.5
0.001
0.01
0.1
1
10
20 100 1k 10k 20k
Frequency (Hz)
THD+N (%)
PO = 1W
PO = 5W
PO = 10W
Gain = 26dB
PVCC = 24V
TA = 25°C
RL = 8Ω
G006
0.001
0.01
0.1
1
10
0.01 0.1 1 10
Output Power (W)
THD+N (%)
f = 20Hz
f = 1kHz
f = 6kHz
Gain = 26dB
PVCC = 6V
TA = 25°C
RL = 4Ω
G008
0.001
0.01
0.1
1
10
20 100 1k 10k 20k
Frequency (Hz)
THD+N (%)
PO = 1W
PO = 5W
PO = 10W
Gain = 26dB
PVCC = 24V
TA = 25°C
RL = 4Ω
G004
0.001
0.01
0.1
1
10
20 100 1k 10k 20k
Frequency (Hz)
THD+N (%)
PO = 1W
PO = 2.5W
PO = 5W
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 8Ω
G005
0.001
0.01
0.1
1
10
20 100 1k 10k 20k
Frequency (Hz)
THD+N (%)
PO = 0.5W
PO = 1W
PO = 2.5W
Gain = 26dB
PVCC = 6V
TA = 25°C
RL = 4Ω
G002
0.001
0.01
0.1
1
10
20 100 1k 10k 20k
Frequency (Hz)
THD+N (%)
PO = 1W
PO = 2.5W
PO = 5W
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 4Ω
G003
8
TPA3116D2
,
TPA3118D2
,
TPA3130D2
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6.7 Typical Characteristics
fs= 400 kHz, BD Mode (unless otherwise noted)
Figure 1. Total Harmonic Distortion + Noise (BTL) vs
Frequency Figure 2. Total Harmonic Distortion + Noise (BTL) vs
Frequency
Figure 3. Total Harmonic Distortion + Noise (BTL) vs
Frequency Figure 4. Total Harmonic Distortion + Noise (BTL) vs
Frequency
Figure 5. Total Harmonic Distortion + Noise (BTL) vs
Frequency Figure 6. Total Harmonic Distortion + Noise (BTL) vs Output
Power
0
10
20
30
40
50
01234
PLIMIT Voltage (V)
Output Power (W)
Gain = 26dB
TA = 25°C
PVCC = 24V
RL = 4Ω
G013
20 100 1k 10k 100k
−50
−40
−30
−20
−10
0
10
20
30
−500
−400
−300
−200
−100
0
100
200
300
Frequency (Hz)
Gain (dB)
Phase (°)
Gain
Phase
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 4Ω
G014
0.001
0.01
0.1
1
10
0.01 0.1 1 10 50
Output Power (W)
THD+N (%)
f = 20Hz
f = 1kHz
f = 6kHz
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 8Ω
G011
0.001
0.01
0.1
1
10
0.01 0.1 1 10 50
Output Power (W)
THD+N (%)
f = 20Hz
f = 1kHz
f = 6kHz
Gain = 26dB
PVCC = 24V
TA = 25°C
RL = 8Ω
G012
0.001
0.01
0.1
1
10
0.01 0.1 1 10 40
Output Power (W)
THD+N (%)
f = 20Hz
f = 1kHz
f = 6kHz
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 4Ω
G009
0.001
0.01
0.1
1
10
0.01 0.1 1 10 100
Output Power (W)
THD+N (%)
f = 20Hz
f = 1kHz
f = 6kHz
Gain = 26dB
PVCC = 24V
TA = 25°C
RL = 4Ω
G010
9
TPA3116D2
,
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,
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Typical Characteristics (continued)
fs= 400 kHz, BD Mode (unless otherwise noted)
Figure 7. Total Harmonic Distortion + Noise (BTL) vs Output
Power Figure 8. Total Harmonic Distortion + Noise (BTL) vs Output
Power
Figure 9. Total Harmonic Distortion + Noise (BTL) vs Output
Power Figure 10. Total Harmonic Distortion + Noise (BTL) vs
Output Power
Figure 11. Output Power (BTL) vs Plimit Voltage Figure 12. Gain/Phase (BTL) vs Frequency
−140
−130
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
20 100 1k 10k 20k
Frequency (Hz)
Crosstalk (dB)
Right to Left
Left to Right
Gain = 26dB
PVCC = 24V
TA = 25°C
RL = 8Ω
G021
−140
−130
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
20 100 1k 10k 20k
Frequency (Hz)
Crosstalk (dB)
Right to Left
Left to Right
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 4Ω
G022
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30 35 40 45 50
Output Power (W)
Power Efficiency (%)
PVCC = 6V
PVCC =12V
PVCC = 24V
Gain = 26dB
TA = 25°C
RL = 8Ω
G017
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30 35 40 45 50
Output Power (W)
Power Efficiency (%)
PVCC = 6V
PVCC = 12V
PVCC = 24V
Gain = 26dB
TA = 25°C
RL = 4Ω
G018
0
5
10
15
20
25
30
35
40
45
50
4 6 8 10 12 14 16 18 20 22 24 26
Supply Voltage (V)
Maximum Output Power (W)
THD+N = 1%
THD+N = 10%
Gain = 26dB
TA = 25°C
RL = 8Ω
G015
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
4 6 8 10 12 14 16 18 20 22 24 26
Supply Voltage (V)
Maximum Output Power (W)
THD+N = 1%
THD+N = 10%
Gain = 26dB
TA = 25°C
RL = 4Ω
G016
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Typical Characteristics (continued)
fs= 400 kHz, BD Mode (unless otherwise noted)
Figure 13. Maximum Output Power (BTL) vs Supply Voltage Figure 14. Maximum Output Power (BTL) vs Supply Voltage
Figure 15. Power Efficiency (BTL) vs Output Power Figure 16. Power Efficiency (BTL) vs Output Power
Figure 17. Crosstalk vs Frequency Figure 18. Crosstalk vs Frequency
0
10
20
30
40
50
60
70
80
90
100
0 10 20 30 40 50 60 70 80 90 100
Output Power (W)
Power Efficiency (%)
PVCC = 6V
PVCC = 12V
PVCC =24V
Gain = 26dB
TA = 25°C
RL = 2Ω
G028
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
20 100 1k 10k 20k
Frequency (Hz)
kSVR (dB)
Gain = 26dB
PVCC = 12VDC + 200mVP-P
TA = 25°C
RL = 2Ω
G030
0.001
0.01
0.1
1
10
0.01 0.1 1 10 40
Output Power (W)
THD+N (%)
f = 20Hz
f = 1kHz
f = 6kHz
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 2Ω
G025
0
20
40
60
80
100
120
140
160
180
4 6 8 10 12 14 16 18 20 22 24 26
Supply Voltage (V)
Maximum Output Power (W)
THD+N = 1%
THD+N = 10%
Gain = 26dB
TA = 25°C
RL = 2Ω
G027
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
20 100 1k 10k 20k
Frequency (Hz)
kSVR (dB)
Left Channel
Right Channel
Gain = 26dB
PVCC = 12VDC + 200mVP-P
TA = 25°C
RL = 8Ω
G023
0.001
0.01
0.1
1
10
20 100 1k 10k 20k
Frequency (Hz)
THD+N (%)
PO = 1W
PO = 5W
PO = 10W
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 2Ω
G024
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Typical Characteristics (continued)
fs= 400 kHz, BD Mode (unless otherwise noted)
Figure 19. Supply Ripple Rejection Ratio (BTL) vs
Frequency Figure 20. Total Harmonic Distortion + Noise (PBTL) vs
Frequency
Figure 21. Total Harmonic Distortion + Noise (PBTL) vs
Output Power Figure 22. Maximum Output Power (PBTL) vs Supply
Voltage
Figure 23. Power Efficiency (PBTL) vs Output Power Figure 24. Supply Ripple Rejection Ratio (PBTL) vs
Frequency
0.001
0.01
0.1
1
10
0.01 0.1 1 10 100 200
Output Power (W)
THD+N (%)
f = 20Hz
f = 1kHz
f = 6kHz
Gain = 26dB
PVCC = 24V
TA = 25°C
RL = 3Ω
G032
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
4 6 8 10 12 14 16 18 20 22 24 26
Supply Voltage (V)
Maximum Output Power (W)
THD+N = 1%
THD+N = 10%
Gain = 26dB
TA = 25°C
RL = 3Ω
G034
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Typical Characteristics (continued)
fs= 400 kHz, BD Mode (unless otherwise noted)
Figure 25. Total Harmonic Distortion + Noise (PBTL) vs
Output Power Figure 26. Maximum Output Power (PBTL) vs Supply
Voltage
+
–
+
–
+–
+
+
SDZ
MUTE
TTL
Buffer
Gain
Control
GAIN
OUTPR_FB
RINP
RINN
Gain
Control
OUTPNR_FB
FAULTZ
SYNC
GAIN/SLV
AM<2:0>
PLIMIT
AVCC
GVDD
LDO
Regulator
LINP
LINN
GND
Input
Sense PBTL
Select
OUTPL_FB
Gain
Control
OUTNL_FB
AVDD
GVDD
PLIMIT
Reference
Ramp
Generator Biases and
References
Startup Protection
Logic
SC Detect
DC Detect
Thermal
Detect
UVLO/OVLO
PVCC
GVDD PVCC
Gate
Drive
OUTNL_
FB
PVCC
GVDD
PVCC
Gate
Drive
PWM
Logic
Modulation and
PBTL Select OUTPL_FB
GND
OUTPL
BSPL
GND
OUTNL
BSNL
GND
BSNR
OUTPR
GND
OUTNR
OUTNR_
FB
BSPR
OUTPR_FB
PVCC
GVDD
PVCC
Gate
Drive
PVCC
GVDD
PVCC
Gate
Drive
PWM
Logic
Modulation and
PBTL Select
PLIMIT
PLIMIT
+
–
+
–
+
–
+
–
+
–
+
–
–
–
Thermal
Pad
+
–
PVCCPVCC
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7 Detailed Description
7.1 Overview
The TPA31xxD2 device is a highly efficient Class D audio amplifier with integrated 120m Ohms MOSFET that
allows output currents up to 7.5 A. The high efficiency allows the amplifier to provide an excellent audio
performance without the need for a bulky heat sink.
The device can be configured for either master or slave operation by using the SYNC pin. This helps to prevent
audible beats noise.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Gain Setting and Master and Slave
The gain of the TPA31xxD2 family is set by the voltage divider connected to the GAIN/SLV control pin. Master or
Slave mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four
stages sets the GAIN in Master mode in gains of 20, 26, 32, 36 dB respectively, while the next four stages sets
the GAIN in Slave mode in gains of 20, 26, 32, 36 dB respectively. The gain setting is latched during power-up
and cannot be changed while device is powered. Table 1 lists the recommended resistor values and the state
and gain:
i i
1
f2 Z Cp
=
ƒ
5
6
7
8
9
10
INNR
PLIMIT
GVDD
GAIN/SLV
GND
21
1
2
C5 1 Fµ
2 1
51 k
R1
51 k
R2
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Feature Description (continued)
(1) Resistor tolerance should be 5% or better.
Table 1. Gain and Master/Slave
MASTER / SLAVE
MODE GAIN R1 (to GND)(1) R2 (to GVDD)(1) INPUT IMPEDANCE
Master 20 dB 5.6 kΩOPEN 60 kΩ
Master 26 dB 20 kΩ100 kΩ30 kΩ
Master 32 dB 39 kΩ100 kΩ15 kΩ
Master 36 dB 47 kΩ75 kΩ9 kΩ
Slave 20 dB 51 kΩ51 kΩ60 kΩ
Slave 26 dB 75 kΩ47 kΩ30 kΩ
Slave 32 dB 100 kΩ39 kΩ15 kΩ
Slave 36 dB 100 kΩ16 kΩ9 kΩ
Figure 27. Gain, Master/Slave
In Master mode, SYNC terminal is an output, in Slave mode, SYNC terminal is an input for a clock input. TTL
logic levels with compliance to GVDD.
7.3.2 Input Impedance
The TPA31xxD2 family input stage is a fully differential input stage and the input impedance changes with the
gain setting from 9 kΩat 36 dB gain to 60 kΩat 20 dB gain. Table 1 lists the values from min to max gain. The
tolerance of the input resistor value is ±20% so the minimum value will be higher than 7.2 kΩ. The inputs need to
be AC-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages during power-
ON and power-OFF. The input ac-coupling capacitor together with the input impedance forms a high-pass filter
with the following cut-off frequency:
(1)
If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz.
Table 2 lists the recommended ac-couplings capacitors for each gain step. If a -3 dB is accepted at 20 Hz 10
times lower capacitors can used – for example, a 1 µF can be used.
Table 2. Recommended Input AC-Coupling Capacitors
GAIN INPUT IMPEDANCE INPUT CAPACITANCE HIGH-PASS FILTER
20 dB 60 kΩ1.5 µF 1.8 Hz
26 dB 30 kΩ3.3 µF 1.6 Hz
32 dB 15 kΩ5.6 µF 1.9 Hz
36 dB 9 kΩ10 µF 1.8 Hz
Input
Signal
Ci
IN Zi
Zf
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Figure 28. Input Impedance
The input capacitors used should be a type with low leakage, like quality electrolytic, tantalum or ceramic. If a
polarized type is used the positive connection should face the input pins which are biased to 3 Vdc.
7.3.3 Startup and Shutdown Operation
The TPA31xxD2 family employs a shutdown mode of operation designed to reduce supply current (Icc) to the
absolute minimum level during periods of nonuse for power conservation. The SDZ input terminal should be held
high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SDZ low
will put the outputs to mute and the amplifier to enter a low-current state. It is not recommended to leave SDZ
unconnected, because amplifier operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power
supply. The gain setting is selected at the end of the start-up cycle. At the end of the start-up cycle, the gain is
selected and cannot be changed until the next power-up.
7.3.4 PLIMIT Operation
The TPA31xxD2 family has a built-in voltage limiter that can be used to limit the output voltage level below the
supply rail, the amplifier simply operates as if it was powered by a lower supply voltage, and thereby limits the
output power. Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external
reference may also be used if tighter tolerance is required. Add a 1 µF capacitor from pin PLIMIT to ground to
ensure stability. It is recommended to connect PLIMIT to GVDD when using 1SPW-modulation mode.
Figure 29. Power Limit Example
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to a fixed maximum value. This limit can be thought of as a "virtual" voltage rail which is lower than the supply
connected to PVCC. This "virtual" rail is approximately 4 times the voltage at the PLIMIT pin. This output voltage
can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance.
2
LP
L S
OUT
L
RV
R + 2 R
P = for unclipped power
2 R
æ ö
æ ö´
ç ÷
ç ÷
ç ÷
´
è ø
è ø
´
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(1) PLIMIT measurements taken with EVM gain set to 26 dB and input voltage set to 1 Vrms.
where
• POUT (10% THD) = 1.25 × POUT (unclipped)
• RLis the load resistance.
• RSis the total series resistance including RDS(on), and output filter resistance.
• VPis the peak amplitude
• VP= 4 × PLIMIT voltage if PLIMIT < 4 × VP(2)
Table 3. Power Limit Example
PVCC (V) PLIMIT VOLTAGE (V)(1) R to GND R to GVDD OUTPUT VOLTAGE (Vrms)
24 V GVDD Open Short 17.9
24 V 3.3 45 kΩ51 kΩ12.67
24 V 2.25 24 kΩ51 kΩ9
12 V GVDD Short Open 10.33
12 V 2.25 24 kΩ51 kΩ9
12 V 1.5 18 kΩ68 kΩ6.3
7.3.5 GVDD Supply
The GVDD Supply is used to power the gates of the output full bridge transistors. It can also be used to supply
the PLIMIT and GAIN/SLV voltage dividers. Decouple GVDD with a X5R ceramic 1 µF capacitor to GND. The
GVDD supply is not intended to be used for external supply. It is recommended to limit the current consumption
by using resistor voltage dividers for GAIN/SLV and PLIMIT of 100 kΩor more.
7.3.6 BSPx AND BSNx Capacitors
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 220 nF ceramic capacitor of quality X5R or better, rated for at
least 16 V, must be connected from each output to its corresponding bootstrap input. (See the application circuit
diagram in Figure 37.) The bootstrap capacitors connected between the BSxx pins and corresponding output
function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each
high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-
side MOSFETs turned on.
7.3.7 Differential Inputs
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA31xxD2 family with a differential source, connect the positive lead of the audio source to the RINP or
LINP input and the negative lead from the audio source to the RINN or LINN input. To use the TPA31xxD2 family
with a single-ended source, ac ground the negative input through a capacitor equal in value to the input capacitor
on positive and apply the audio source to either input. In a single-ended input application, the unused input
should be ac grounded at the audio source instead of at the device input for best noise performance. For good
transient performance, the impedance seen at each of the two differential inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to
allow the input dc blocking capacitors to become completely charged during the 10 ms power-up time. If the input
capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching
which can result in pop if the input components are not well matched.
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7.3.8 Device Protection System
The TPA31xxD2 family contains a complete set of protection circuits carefully designed to make system design
efficient as well as to protect the device against any kind of permanent failures due to short circuits, overload,
over temperature, and under-voltage. The FAULTZ pin will signal if an error is detected according to Table 4:
Table 4. Fault Reporting
FAULT TRIGGERING CONDITION
(typical value) FAULTZ ACTION LATCHED/SELF-
CLEARING
Over Current Output short or short to PVCC or GND Low Output high impedance Latched
Over Temperature Tj> 150°C Low Output high impedance Latched
Too High DC Offset DC output voltage Low Output high impedance Latched
Under Voltage on
PVCC PVCC < 4.5V – Output high impedance Self-clearing
Over Voltage on
PVCC PVCC > 27V – Output high impedance Self-clearing
7.3.9 DC Detect Protection
The TPA31xxD2 family has circuitry which will protect the speakers from DC current which might occur due to
defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be
reported on the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by
changing the state of the outputs to Hi-Z.
If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the
SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the DC Detect
protection latch.
A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 60% for more than
420 msec at the same polarity. Table x below shows some examples of the typical DC Detect Protection
threshold for several values of the supply voltage. This feature protects the speaker from large DC currents or
AC currents less than 2Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-
up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and
negative inputs to avoid nuisance DC detect faults.
Table 5 lists the minimum output offset voltages required to trigger the DC detect. The outputs must remain at or
above the voltage listed in the table for more than 420 ms to trigger the DC detect.
Table 5. DC Detect Threshold
PVCC (V) VOS - OUTPUT OFFSET VOLTAGE (V)
4.5 0.96
6 1.3
12 2.6
18 3.9
7.3.10 Short-Circuit Protection and Automatic Recovery Feature
The TPA31xxD2 family has protection from over current conditions caused by a short circuit on the output stage.
The short circuit protection fault is reported on the FAULTZ pin as a low state. The amplifier outputs are switched
to a high impedance state when the short circuit protection latch is engaged. The latch can be cleared by cycling
the SDZ pin through the low state.
If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the
SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the short-
circuit protection latch.
In systems where a possibility of a permanent short from the output to PVDD or to a high voltage battery like a
car battery can occur, pull the MUTE pin low with the FAULTZ signal with a inverting transistor to ensure a high-
Z restart, like shown in the figure below:
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> 1.4sec
mPTPA3116D2
SDZ
MUTE
FAULTZ
SDZ
MUTE
FAULTZ
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Figure 30. MUTE Driven by Inverted FAULTZ Figure 31. Timing Requirement for SDZ
7.3.11 Thermal Protection
Thermal protection on the TPA31xxD2 family prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal trip point, the device enters into the shutdown state and the outputs are disabled. This is a
latched fault.
Thermal protection faults are reported on the FAULTZ terminal as a low state.
If automatic recovery from the thermal protection latch is desired, connect the FAULTZ pin directly to the SDZ
pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the thermal
protection latch.
7.3.12 Device Modulation Scheme
The TPA31xxD2 family has the option of running in either BD modulation or 1SPW modulation; this is set by the
MODSEL pin.
7.3.12.1 MODSEL = GND: BD-Modulation
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
OUTP
OUTN
OUTP-OUTN
Speaker
Current
OUTP
OUTN
OUTP-OUTN
Speaker
Current
OUTP
OUTN
OUTP-OUTN
Speaker
Current
0V
0V
PVCC
No Output
Positive Output
Negative Output
0A
0A
0V
-PVCC
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Figure 32. BD Mode Modulation
7.3.12.2 MODSEL = HIGH: 1SPW-modulation
The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty
in THD degradation and more attention required in the output filter selection. In 1SPW mode the outputs operate
at ~15% modulation during idle conditions. When an audio signal is applied one output will decrease and one will
increase. The decreasing output signal will quickly rail to GND at which point all the audio modulation takes place
through the rising output. The result is that only one output is switching during a majority of the audio cycle.
Efficiency is improved in this mode due to the reduction of switching losses. The THD penalty in 1SPW mode is
minimized by the high performance feedback loop. The resulting audio signal at each half output has a
discontinuity each time the output rails to GND. This can cause ringing in the audio reconstruction filter unless
care is taken in the selection of the filter components and type of filter used.
OUTP
OUTN
OUTP-OUTN
Speaker
Current
OUTP
OUTN
OUTP-OUTN
Speaker
Current
OUTP
OUTN
OUTP-OUTN
Speaker
Current
0 V
0 V
PVCC
No Output
Positive Output
Negative Output
0
A
0 A
0 V
-PVCC
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Figure 33. 1SPW Mode Modulation
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7.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier-based on AD modulation needs an output filter is that the
switching waveform results in maximum current flow. This causes more loss in the load, which causes lower
efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is
proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the
time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store
the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The
speaker is both resistive and reactive, whereas an LC filter is almost purely reactive.
The TPA3116D2 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
7.3.14 Ferrite Bead Filter Considerations
Using the Advanced Emissions Suppression Technology in the TPA3116D2 amplifier it is possible to design a
high efficiency class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to
accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite
bead used in the filter. One important aspect of the ferrite bead selection is the type of material used in the ferrite
bead. Not all ferrite material is alike, so it is important to select a material that is effective in the 10 to 100 MHz
range which is key to the operation of the class-D amplifier. Many of the specifications regulating consumer
electronics have emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation
in the 30 MHz and above range from appearing on the speaker wires and the power supply lines which are good
antennas for these signals. The impedance of the ferrite bead can be used along with a small capacitor with a
value in the range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best
performance, the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz.
Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected
for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In
this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak
current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead
current handling capability by measuring the resonant frequency of the filter output at low power and at maximum
power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of
ferrite beads which have been tested and work well with the TPA3130D2 can be seen in the TPA3130D2EVM
user guide SLOU341.
A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good
temperature and voltage characteristics will work best.
Additional EMC improvements may be obtained by adding snubber networks from each of the class-D outputs to
ground. Suggested values for a simple RC series snubber network would be 18 Ωin series with a 330 pF
capacitor although design of the snubber network is specific to every application and must be designed taking
into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate
the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make
sure the layout of the snubber network is tight and returns directly to the GND pins on the IC.
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Figure 34. TPA311xD2 Radiated Emissions
7.3.15 When to Use an Output Filter for EMI Suppression
The TPA3116D2 has been tested with a simple ferrite bead filter for a variety of applications including long
speaker wires up to 125 cm and high power. The TPA3116D2 EVM passes FCC class-B specifications under
these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet
application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.
There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These
circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases a classic
second order Butterworth filter similar to those shown in the figures below can be used.
Some systems have little power supply decoupling from the AC line but are also subject to line conducted
interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these
cases, LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using
low frequency ferrite material can also be effective at preventing line conducted interference.
OUTP
OUTN
10 µH
L1
10 µH
L2
C2
C3
0.68 µF
0.68 µF
OUTP
OUTN
Ferrite
Chip Bead
1 nF
1 nF
Ferrite
Chip Bead
4 - 8W W
4 - 8W W
23
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Figure 35. TPA31xxD2 Output Filters
7.3.16 AM Avoidance EMI Reduction
To reduce interference in the AM radio band, the TPA3116D2 has the ability to change the switching frequency
via AM<2:0> pins. The recommended frequencies are listed in Table 6. The fundamental frequency and its
second harmonic straddle the AM radio band listed. This eliminates the tones that can be present due to the
switching frequency being demodulated by the AM radio.
Table 6. AM Frequencies
US EUROPEAN SWITCHING FREQUENCY (kHz) AM2 AM1 AM0
AM FREQUENCY (kHz) AM FREQUENCY (kHz)
522-540
540-917 540-914 500 0 0 1
917-1125 914-1122 600 (or 400) 010
000
1125-1375 1122-1373 500 0 0 1
1375-1547 1373-1548 600 (or 400) 010
000
1547-1700 1548-1701 600 (or 500) 010
001
TPA3116D2 4.5 V–26 V
PSU
LC Filter
OUTPR
OUTNR
OUTPL
OUTNL
Right
Left PBTL
Detect
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7.4 Device Functional Modes
7.4.1 Mono Mode (PBTL)
The TPA31xxD2 family can be connected in MONO mode enabling up to 100W output power. This is done by:
• Connect INPL and INNL directly to Ground (without capacitors) this sets the device in Mono mode during
power up.
• Connect OUTPR and OUTNR together for the positive speaker terminal and OUTNL and OUTPL together for
the negative pin.
• Analog input signal is applied to INPR and INNR.
Figure 36. Mono Mode
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
This section describes a 2.1 Master and Slave application. The Master is configured as stereo outputs and the
Slave is configured as mono PBTL output.
8.2 Typical Application
A 2.1 solution, U1 TPA3116D2 in Master mode 400 kHz, BTL, gain if 20 dB, power limit not implemented. U2 in
Slave, PBTL mode gain of 20 dB. Inputs are connected for differential inputs.
Power Pad
U1
TPA3116D2
MODSEL
1
SDZ
2
FAULTZ
3
INPR
4
INNR
5
PLIMIT
6
GVDD
7
GAIN/SLV
8
GND
9
INPL
10
INNL
11
MUTE
12
AM2
13
AM1
14
AM0
15
SYNC
16
PVCC 32
PVCC 31
BSPR 30
OUTPR 29
GND 28
OUTNR 27
BSNR 26
GND 25
BSPL 24
OUTPL 23
GND 22
OUTNL 21
BSNL 20
PVCC 19
PVCC 18
AVCC 17
PVCC DECOUPLING
C17 220nF
21
PVCC DECOUPLING
GND
C16 220nF
21
C13 1uF
2 1
C58 100nF
21
C29
680nF
21
L7 10uH
1 2
R10 3.3R
1 2
L8 10uH
1 2
C28
680nF
21
L9
10uH
1 2
C57
10nF
21
R12
20k
1
2
L10 10uH
12
C38
10nF
21
R14 100k
1 2
C25
220uF
1
2
C26
680nF
21
R18
3.3R
1
2
C40
10nF
21
R17
3.3R
1
2
GND
C41
1nF
21
C32
1nF
21
C11 1uF
2 1
C22
220uF
1
2
GND
C21
100nF
21
C20
1nF
21
C31
1nF
21
R15
3.3R
1
2
C33
1nF
21
R16
3.3R
1
2
GND
C19 220nF
21
C30
1nF
21
C27
680nF
21
C34
10nF
21
C37
10nF
21
IN_P_LEFT
IN_N_RIGHT
IN_N_LEFT
IN_P_RIGHT
GND
PVCC
GND GND
GND
GND
GND
GND GND
GND
OUT_ N_LEFT OUT_P_LEFT
-
+
OUT_N_RIGHT OUT_P_RIGHT
+
-
PVCC
C14 1uF
2 1
R11
100k
1
2
MUTE_LR
OUTPUT LC FILTER
R13
100k
1
2
C15
1uF
21
EMI C-RC SNUBBER
C24
100nF
21
GND
PVCC
C18 220nF
21
GND
/SD_LR
PVCC
C23
1nF
21
GND
C12 1uF
2 1
R73
10k
1
2
C42 220nF
21
L15 10uH
1 2
L16 10uH
1 2
R21
75k
1
2
R22
100k
12
C50
220uF
1
2
C51
1uF
21
GND
C35 1uF
2 1
GND
C47
220uF
1
2
C46
100nF
21
C45
1nF
21
C54
1nF
21
R23
3.3R
1
2
GND
R24
3.3R
1
2
C44 220nF
21
C53
1nF
21
C52
1uF
21
C55
10nF
21
C56
10nF
21
IN_P_SUB
IN_N_SUB
GND
SYNC
GND
GND
GND
-
+
OUT_P_SUB
OUT_N_SUB
PVCC
MUTE_SUB
R20
47k
1
2
OUTPUT LC FILTER
R19
100k
1
2
C39
1uF
21
C49
100nF
21
EMI C-RC SNUBBER
PVCC
C43 220nF
21
PVCC
/SD_SUB
C48
1nF
21
GND
C36 1uF
2 1
GND
Power Pad
U2
TPA3116D2
MODSEL
1
SDZ
2
FAULTZ
3
INPR
4
INNR
5
PLIMIT
6
GVDD
7
GAIN/SLV
8
GND
9
INPL
10
INNL
11
MUTE
12
AM2
13
AM1
14
AM0
15
SYNC
16
PVCC 32
PVCC 31
BSPR 30
OUTPR 29
GND 28
OUTNR 27
BSNR 26
GND 25
BSPL 24
OUTPL 23
GND 22
OUTNL 21
BSNL 20
PVCC 19
PVCC 18
AVCC 17
PVCC DECOUPLING
C43 220nF
21
PVCC DECOUPLING
GND
4R
4R
2R
Copyright © 2016, Texas Instruments Incorporated
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Typical Application (continued)
Figure 37. Schematic
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Typical Application (continued)
8.2.1 Design Requirements
DESIGN PARAMETERS EXAMPLE VALUE
Input voltage range PVCC 4.5 V to 26 V
PWM output frequencies 400 kHz, 500 kHz, 600 kHz, 1 MHz or 1.2 MHz
Maximum output power 50 W
8.2.2 Detailed Design Procedure
The TPA31xxD2 family is a very flexible and easy to use Class D amplifier; therefore the design process is
straightforward. Before beginning the design, gather the following information regarding the audio system.
• PVCC rail planned for the design
• Speaker or load impedance
• Maximum output power requirement
• Desired PWM frequency
8.2.2.1 Select the PWM Frequency
Set the PWM frequency by using AM0, AM1 and AM2 pins.
8.2.2.2 Select the Amplifier Gain and Master/Slave Mode
In order to select the amplifier gain setting, the designer must determine the maximum power target and the
speaker impedance. Once these parameters have been determined, calculate the required output voltage swing
which delivers the maximum output power.
Choose the lowest analog gain setting that corresponds to produce an output voltage swing greater than the
required output swing for maximum power. The analog gain and master/slave mode can be set by selecting the
voltage divider resistors (R1 and R2) on the Gain/SLV pin.
8.2.2.3 Select Input Capacitance
Select the bulk capacitors at the PVCC inputs for proper voltage margin and adequate capacitance to support the
power requirements. In practice, with a well-designed power supply, two 100-μF, 50-V capacitors should be
sufficient. One capacitor should be placed near the PVCC inputs at each side of the device. PVCC capacitors
should be a low ESR type because they are being used in a high-speed switching application.
8.2.2.4 Select Decoupling Capacitors
Good quality decoupling capacitors need to be added at each of the PVCC inputs to provide good reliability,
good audio performance, and to meet regulatory requirements. X5R or better ratings should be used in this
application. Consider temperature, ripple current, and voltage overshoots when selecting decoupling capacitors.
Also, these decoupling capacitors should be located near the PVCC and GND connections to the device in order
to minimize series inductances.
8.2.2.5 Select Bootstrap Capacitors
Each of the outputs require bootstrap capacitors to provide gate drive for the high-side output FETs. For this
design, use 0.22-μF, 25-V capacitors of X5R quality or better.
0.001
0.01
0.1
1
10
0.01 0.1 1 10 40
Output Power (W)
THD+N (%)
f = 20Hz
f = 1kHz
f = 6kHz
Gain = 26dB
PVCC = 12V
TA = 25°C
RL = 4Ω
G009
0.001
0.01
0.1
1
10
0.01 0.1 1 10 100
Output Power (W)
THD+N (%)
f = 20Hz
f = 1kHz
f = 6kHz
Gain = 26dB
PVCC = 24V
TA = 25°C
RL = 4Ω
G010
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8.2.3 Application Curves
Figure 38. Total Harmonic Distortion + Noise (BTL) vs
Output Power Figure 39. Total Harmonic Distortion + Noise (BTL) vs
Output Power
9 Power Supply Recommendations
The power supply requirements for the TPA3116D2 consist of one higher-voltage supply to power the output
stage of the speaker amplifier. Several on-chip regulators are included on the TPA3116D2 to generate the
voltages necessary for the internal circuitry of the audio path. It is important to note that the voltage regulators
which have been integrated are sized only to provide the current necessary to power the internal circuitry. The
external pins are provided only as a connection point for off-chip bypass capacitors to filter the supply.
Connecting external circuitry to these regulator outputs may result in reduced performance and damage to the
device. The high voltage supply, between 4.5 V and 26 V, supplies the analog circuitry (AVCC) and the power
stage (PVCC). The AVCC supply feeds internal LDO including GVDD. This LDO output are connected to
external pins for filtering purposes, but should not be connected to external circuits. GVDD LDO output have
been sized to provide current necessary for internal functions but not for external loading.
10 Layout
10.1 Layout Guidelines
The TPA3116D2 can be used with a small, inexpensive ferrite bead output filter for most applications. However,
since the class-D switching edges are fast, it is necessary to take care when planning the layout of the printed
circuit board. The following suggestions will help to meet EMC requirements.
• Decoupling capacitors — The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC terminals as possible. Large (100 μF or greater) bulk power supply decoupling capacitors should
be placed near the TPA3116D2 on the PVCC supplies. Local, high-frequency bypass capacitors should be
placed as close to the PVCC pins as possible. These caps can be connected to the IC GND pad directly for
an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between
220 pF and 1 nF and a larger mid-frequency cap of value between 100 nF and 1 µF also of good quality to
the PVCC connections at each end of the chip.
• Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna.
• Grounding — The PVCC decoupling capacitors should connect to GND. All ground should be connected at
the IC GND, which should be used as a central ground connection or star ground for the TPA3116D2.
• Output filter — The ferrite EMI filter (see Figure 35) should be placed as close to the output terminals as
possible for the best EMI performance. The LC filter should be placed close to the outputs. The capacitors
used in both the ferrite and LC filters should be grounded.
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Layout Guidelines (continued)
For an example layout, see the TPA3116D2 Evaluation Module (TPA3116D2EVM) User Guide (SLOU336). Both
the EVM user manual and the thermal pad application reports, SLMA002 and SLMA004, are available on the TI
Web site at http://www.ti.com.
10.2 Layout Example
Figure 40. Layout Example Top
MACHINE THESE
3 EDGES AFTER
ANODIZATION
0.00
–0.60
+.000
–.024
SINK HEIGHT
25.00
.984
1.00
[.118]
3.00
[.118]
0
[.000]
10.00
[.394]
19.50
[.768]
30.50
[1.201]
40.00
[1.575]
50.00±0.38
[1.969±.015]
SINK LENGTH
3.00
[.118]
6.35
[.250]
13.90±0.38
[.547±.015]
BASE WIDTH
6.95
[.274]
5.00
[.197]
40.00
[1.575] 2X 4-40 6.5x
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10.3 Heat Sink Used on the EVM
The heat sink (part number ATS-TI 10 OP-521-C1-R1) used on the EVM is an 14x25x50 mm extruded aluminum
heat sink with three fins (see drawing below). For additional information on the heat sink, go to www.qats.com.
Figure 42. EVM Heatsink
This size heat sink has shown to be sufficient for continuous output power. The crest factor of music and having
airflow will lower the requirement for the heat sink size and smaller types can be used.
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11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7. Related Links
PARTS PRODUCT FOLDER ORDER NOW TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
TPA3116D2 Click here Click here Click here Click here Click here
TPA3118D2 Click here Click here Click here Click here Click here
TPA3130D2 Click here Click here Click here Click here Click here
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates — go to the product folder for your device on ti.com. In the
upper right-hand corner, click the Alert me button to register and receive a weekly digest of product information
that has changed (if any). For change details, check the revision history of any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Nov-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPA3116D2DAD ACTIVE HTSSOP DAD 32 46 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA
3116
D2
TPA3116D2DADR ACTIVE HTSSOP DAD 32 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA
3116
D2
TPA3118D2DAP ACTIVE HTSSOP DAP 32 46 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3118
TPA3118D2DAPR ACTIVE HTSSOP DAP 32 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3118
TPA3130D2DAP ACTIVE HTSSOP DAP 32 46 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3130
TPA3130D2DAPR ACTIVE HTSSOP DAP 32 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3130
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Nov-2017
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPA3116D2, TPA3118D2 :
•Automotive: TPA3116D2-Q1, TPA3118D2-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPA3116D2DADR HTSSOP DAD 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1
TPA3118D2DAPR HTSSOP DAP 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1
TPA3130D2DAPR HTSSOP DAP 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Nov-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA3116D2DADR HTSSOP DAD 32 2000 367.0 367.0 45.0
TPA3118D2DAPR HTSSOP DAP 32 2000 367.0 367.0 45.0
TPA3130D2DAPR HTSSOP DAP 32 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Nov-2017
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
8.3
7.9
30X 0.65
32X 0.30
0.19
2X
9.75
(0.15) TYP
0 - 8 0.15
0.05
1.2
1.0
4.36
3.26
4.11
3.31
0.25
GAGE PLANE
0.75
0.50
A
NOTE 3
11.1
10.9
B6.2
6.0
PowerPAD TSSOP - 1.2 mm max heightDAD0032A
PLASTIC SMALL OUTLINE
4222646/A 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
PowerPAD is a trademark of Texas Instruments.
TM
132
0.1 C A B
17
16
PIN 1 ID AREA
EXPOSED
THERMAL PAD
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.600
www.ti.com
EXAMPLE BOARD LAYOUT
(7.5)
0.05 MAX
AROUND
0.05 MIN
AROUND
32X (1.5)
32X (0.45)
30X (0.65)
(R ) TYP0.05
PowerPAD TSSOP - 1.2 mm max heightDAD0032A
PLASTIC SMALL OUTLINE
4222646/A 12/2015
SYMM
SYMM
SEE DETAILS
LAND PATTERN EXAMPLE
SCALE:8X
1
16 17
32
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
TM
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
32X (1.5)
32X (0.45)
(7.5)
30X (0.65)
(R ) TYP0.05
PowerPAD TSSOP - 1.2 mm max heightDAD0032A
PLASTIC SMALL OUTLINE
4222646/A 12/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:8X
SYMM
SYMM
1
16 17
32
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