Product Folder Order Now Support & Community Tools & Software Technical Documents TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 TPA3116D2 15-W, 30-W, 50-W Filter-Free Class-D Stereo Amplifier Family With AM Avoidance 1 Features 3 Description * The TPA31xxD2 series are stereo efficient, digital amplifier power stage for driving speakers up to 100 W / 2 in mono. The high efficiency of the TPA3130D2 allows it to do 2 x 15 W without external heat sink on a single layer PCB. The TPA3118D2 can even run 2 x 30 W / 8 without heat sink on a dual layer PCB. If even higher power is needed the TPA3116D2 does 2 x 50 W / 4 with a small heatsink attached to its top side PowerPAD. All three devices share the same footprint enabling a single PCB to be used across different power levels. 1 * * * * * * * * * * * Supports Multiple Output Configurations - 2 x 50 W Into a 4- BTL Load at 21 V (TPA3116D2) - 2 x 30 W Into a 8- BTL Load at 24 V (TPA3118D2) - 2 x 15 W Into a 8- BTL Load at 15 V (TPA3130D2) Wide Voltage Range: 4.5 V to 26 V Efficient Class-D Operation - >90% Power Efficiency Combined With Low Idle Loss Greatly Reduces Heat Sink Size - Advanced Modulation Schemes Multiple Switching Frequencies - AM Avoidance - Master and Slave Synchronization - Up to 1.2-MHz Switching Frequency Feedback Power-Stage Architecture With High PSRR Reduces PSU Requirements Programmable Power Limit Differential and Single-Ended Inputs Stereo and Mono Mode With Single-Filter Mono Configuration Single Power Supply Reduces Component Count Integrated Self-Protection Circuits Including Overvoltage, Undervoltage, Overtemperature, DCDetect, and Short Circuit With Error Reporting Thermally Enhanced Packages - DAD (32-Pin HTSSOP Pad Up) - DAP (32-Pin HTSSOP Pad Down) -40C to 85C Ambient Temperature Range The TPA31xxD2 advanced oscillator/PLL circuit employs a multiple switching frequency option to avoid AM interferences; this is achieved together with an option of either master or slave option, making it possible to synchronize multiple devices. The TPA31xxD2 devices are fully protected against faults with short-circuit protection and thermal protection as well as overvoltage, undervoltage, and DC protection. Faults are reported back to the processor to prevent devices from being damaged during overload conditions. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPA3116D2 DAD (32) 11.00 mm x 6.20 mm TPA3118D2 TPA3130D2 DAP (32) 11.00 mm x 6.20 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Application Circuit Tuner AM/FM CD/ MP3 Audio Processor And control Right * * * * Mini-Micro Component, Speaker Bar, Docks After-Market Automotive CRT TV Consumer Audio Applications PBTL Detect Left 2 Applications 4.5 V-26 V PSU TPA3116D2 Right LC Filter Left LC Filter SDZ MUTE Aux in FAULTZ AM /FM Avoidance Control GAIN control and Master /Slave setting Power Limit Capable of synchronizing to other devices AM2,1,0 GAIN/SLV PLIMIT Sync Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 5 5 5 6 6 7 8 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. DC Electrical Characteristics .................................... AC Electrical Characteristics..................................... Typical Characteristics .............................................. Detailed Description ............................................ 13 7.1 Overview ................................................................. 13 7.2 Functional Block Diagram ....................................... 13 7.3 Feature Description................................................. 13 7.4 Device Functional Modes........................................ 24 8 Application and Implementation ........................ 25 8.1 Application Information............................................ 25 8.2 Typical Application .................................................. 25 9 Power Supply Recommendations...................... 28 10 Layout................................................................... 28 10.1 Layout Guidelines ................................................. 28 10.2 Layout Example .................................................... 29 10.3 Heat Sink Used on the EVM ................................. 31 11 Device and Documentation Support ................. 32 11.1 11.2 11.3 11.4 11.5 11.6 Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 32 32 32 32 32 32 12 Mechanical, Packaging, and Orderable Information ........................................................... 32 4 Revision History Changes from Revision F (February 2017) to Revision G Page * Changed R to GND column row 1 From: "Short" To: "Open" in Table 3 ............................................................................. 16 * Changed R to GVDD column row 1 From: "Open" To: "Short" in Table 3 ........................................................................... 16 Changes from Revision E (September 2015) to Revision F Page * Changed pin 20 Description From: ceramic cap to OUTPL To: ceramic cap to OUTNL in the Pin Functions table ............. 4 * Changed pin 24 Description From: ceramic cap to OUTNL To: ceramic cap to OUTPL in the Pin Functions table ............. 4 * Changed 2.3 Hz To 1.9 Hz for HIGH-PASS FILTER in Table 2 ......................................................................................... 14 Changes from Revision D (January 2015) to Revision E * Page Deleted Package DAP (32) from Part Number TPA3116D2 in the Device Information table ............................................... 1 Changes from Revision C (April 2012) to Revision D * Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision B (May 2012) to Revision C Page * Changed Notes 2 and 3 of the Thermal Information Table. ................................................................................................... 6 * Changed the Gain (BTL) Test Condition values for R1 and R2............................................................................................. 6 * Changed the Gain (SLV) Test Condition values for R1 and R2............................................................................................. 6 * Changed the System Block Diagram.................................................................................................................................... 13 2 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 5 Pin Configuration and Functions DAD Package 32-Pin HTSSOP With PowerPAD Up TPA3116D2 Only, Top View MODSEL 1 32 PVCC SDZ 2 31 PVCC FAULTZ 3 30 BSPR RINP 4 29 OUTPR RINN 5 28 GND PLIMIT 6 27 OUTNR GVDD 7 26 BSNR GAIN/SLV 8 25 GND GND 9 24 BSPL Thermal PAD LINP 10 23 OUTPL LINN 11 22 GND MUTE 12 21 OUTNL AM2 13 20 BSNL AM1 14 19 PVCC AM0 15 18 PVCC SYNC 16 17 AVCC DAP Package 32-Pin HTSSOP With PowerPAD Down Top View MODSEL 1 32 PVCC SDZ 2 31 PVCC FAULTZ 3 30 BSPR RINP 4 29 OUTPR RINN 5 28 GND PLIMIT 6 27 OUTNR GVDD 7 26 BSNR GAIN/SLV 8 25 GND Thermal PAD GND 9 24 BSPL LINP 10 23 OUTPL LINN 11 22 GND MUTE 12 21 OUTNL AM2 13 20 BSNL AM1 14 19 PVCC AM0 15 18 PVCC SYNC 16 17 AVCC Copyright (c) 2012-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 3 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 www.ti.com Pin Functions PIN NO. NAME TYPE (1) DESCRIPTION 1 MODSEL I Mode selection logic input (LOW = BD mode, HIGH = 1 SPW mode). TTL logic levels with compliance to AVCC. 2 SDZ I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC. 3 FAULTZ DO 4 RINP I Positive audio input for right channel. Biased at 3 V. 5 RINN I Negative audio input for right channel. Biased at 3 V. 6 PLIMIT I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit. 7 GVDD PO Internally generated gate voltage supply. Not to be used as a supply or connected to any component other than a 1 F X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers. 8 GAIN/SLV I Selects Gain and selects between Master and Slave mode depending on pin voltage divider. 9 GND G Ground 10 LINP I Positive audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode. 11 LINN I Negative audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode. 12 MUTE I Mute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC. 13 AM2 I AM Avoidance Frequency Selection 14 AM1 I AM Avoidance Frequency Selection 15 AM0 I AM Avoidance Frequency Selection 16 SYNC DIO 17 AVCC P Analog Supply 18 PVCC P Power supply 19 PVCC P Power supply 20 BSNL BST Boot strap for negative left channel output, connect to 220 nF X5R, or better ceramic cap to OUTNL 21 OUTNL PO Negative left channel output 22 GND G 23 OUTPL PO Positive left channel output 24 BSPL BST Boot strap for positive left channel output, connect to 220 nF X5R, or better ceramic cap to OUTPL 25 GND G 26 BSNR BST Boot strap for negative right channel output, connect to 220 nF X5R, or better ceramic cap to OUTNR 27 OUTNR PO Negative right channel output General fault reporting including Over-temp, DC Detect. Open drain. FAULTZ = High, normal operation FAULTZ = Low, fault condition Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV terminal. Ground Ground 28 GND G 29 OUTPR PO Positive right channel output 30 BSPR BST Boot strap for positive right channel output, connect to 220 nF X5R or better ceramic cap to OUTPR 31 PVCC P Power supply 32 PVCC P Power supply 33 PowerPAD G Connect to GND for best system performance. If not connected to GND, leave floating. (1) 4 Ground TYPE: DO = Digital Output, I = Analog Input, G = General Ground, PO = Power Output, BST = Boot Strap. Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) Supply voltage, VCC Input voltage, VI Slew rate, maximum (2) MIN MAX UNIT PVCC, AVCC -0.3 30 V INPL, INNL, INPR, INNR -0.3 6.3 V PLIMIT, GAIN / SLV, SYNC -0.3 GVDD+0.3 V AM0, AM1, AM2, MUTE, SDZ, MODSEL -0.3 PVCC+0.3 V 10 V/ms Operating free-air temperature, TA -40 85 C Operating junction temperature , TJ -40 150 C Storage temperature, Tstg -40 125 C (1) (2) AM0, AM1, AM2, MUTE, SDZ, MODSEL Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 100 k series resistor is needed if maximum slew rate is exceeded. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. . 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM Supply voltage PVCC, AVCC VIH High-level input voltage AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL VIL Low-level input voltage AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL 0.8 V VOL Low-level output voltage FAULTZ, RPULL-UP = 100 k, PVCC = 26 V 0.8 V IIH High-level input current AM0, AM1, AM2, MUTE, SDZ, MODSEL (VI = 2 V, VCC = 18 V) 50 A Output filter: L = 10 H, C = 680 nF Minimum load Impedance RL(PBTL) Lo Output filter: L = 10 H, C = 1 F Output-filter Inductance 2 3.2 4 TPA3130D2 5.6 8 TPA3116D2, TPA3118D2 1.6 TPA3130D2 3.2 4 1 Submit Documentation Feedback Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 V V TPA3116D2, TPA3118D2 Minimum output filter inductance under short-circuit condition Copyright (c) 2012-2017, Texas Instruments Incorporated 26 UNIT VCC RL(BTL) 4.5 MAX H 5 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 www.ti.com 6.4 Thermal Information THERMAL METRIC (1) TPA3130D2 TPA3118D2 TPA3116D2 DAP (2) DAP (3) DAD (4) 32 PINS 32 PINS 32 PINS RJA Junction-to-ambient thermal resistance 36 22 14 JT Junction-to-top characterization parameter 0.4 0.3 1.2 JB Junction-to-board characterization parameter 5.9 4.7 5.7 (1) (2) (3) (4) UNIT C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For the PCB layout please see the TPA3130D2EVM user guide. For the PCB layout please see the TPA3118D2EVM user guide. The heat sink drawing used for the thermal model data are shown in the application section, size: 14mm wide, 50mm long, 25mm high. 6.5 DC Electrical Characteristics TA = 25C, AVCC = PVCC = 12 V to 24 V, RL = 4 (unless otherwise noted) PARAMETER TEST CONDITIONS | VOS | Class-D output offset voltage (measured differentially) ICC Quiescent supply current ICC(SD) Quiescent supply current in shutdown mode rDS(on) Drain-source on-state resistance, measured pin to pin G G Gain (BTL) Gain (SLV) TYP MAX VI = 0 V, Gain = 36 dB 1.5 15 SDZ = 2 V, No load or filter, PVCC = 12 V 20 35 SDZ = 2 V, No load or filter, PVCC = 24 V 32 50 SDZ = 0.8 V, No load or filter, PVCC = 12 V <50 SDZ = 0.8 V, No load or filter, PVCC = 24 V 50 PVCC = 21 V, Iout = 500 mA, TJ = 25C 120 19 20 21 25 26 27 R1 = 39 k, R2 = 100 k 31 32 33 R1 = 47 k, R2 = 75 k 35 36 37 R1 = 51 k, R2 = 51 k 19 20 21 R1 = 75 k, R2 = 47 k 25 26 27 R1 = 100 k, R2 = 39 k 31 32 33 R1 = 100 k, R2 = 16 k 35 36 37 SDZ = 2 V tOFF Turn-off time SDZ = 0.8 V GVDD Gate drive supply IGVDD < 200 A VO Output voltage maximum under PLIMIT control V(PLIMIT) = 2 V; VI = 1 Vrms UNIT mV mA A m R1 = 20 k, R2 = 100 k Turn-on time Submit Documentation Feedback 400 R1 = 5.6 k, R2 = Open ton 6 MIN 10 dB dB dB dB ms 2 s 6.4 6.9 7.4 V 6.75 7.90 8.75 V Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 6.6 AC Electrical Characteristics TA = 25C, AVCC = PVCC = 12 V to 24 V, RL = 4 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN 200 mVPP ripple at 1 kHz, Gain = 20 dB, Inputs ACcoupled to GND KSVR Power supply ripple rejection PO Continuous output power THD+N Total harmonic distortion + noise VCC = 21 V, f = 1 kHz, PO = 25 W (half-power) Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB Crosstalk VO = 1 Vrms, Gain = 20 dB, f = 1 kHz Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted SNR fOSC Oscillator frequency TYP MAX -70 THD+N = 10%, f = 1 kHz, PVCC = 14.4 V 25 THD+N = 10%, f = 1 kHz, PVCC = 21 V 50 UNIT dB W 0.1% 65 V -80 dBV -100 dB 102 dB AM2=0, AM1=0, AM0=0 376 400 424 AM2=0, AM1=0, AM0=1 470 500 530 AM2=0, AM1=1, AM0=0 564 600 636 AM2=0, AM1=1, AM0=1 940 1000 1060 AM2=1, AM1=0, AM0=0 1128 1200 1278 kHz AM2=1, AM1=0, AM0=1 AM2=1, AM1=1, AM0=0 Reserved AM2=1, AM1=1, AM0=1 Thermal trip point Thermal hysteresis Over current trip point 150+ C 15 C TPA3130D2 4.5 TPA3118D2, TPA3116D2 7.5 Copyright (c) 2012-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 A 7 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 www.ti.com 6.7 Typical Characteristics fs = 400 kHz, BD Mode (unless otherwise noted) 10 10 PO = 0.5W PO = 1W PO = 2.5W Gain = 26dB PVCC = 6V TA = 25C RL = 4 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.001 PO = 1W PO = 2.5W PO = 5W Gain = 26dB PVCC = 12V TA = 25C RL = 4 0.1 0.01 20 100 1k Frequency (Hz) 10k 0.001 20k 20 100 1k Frequency (Hz) 10k 20k G002 Figure 1. Total Harmonic Distortion + Noise (BTL) vs Frequency G003 Figure 2. Total Harmonic Distortion + Noise (BTL) vs Frequency 10 10 PO = 1W PO = 5W PO = 10W Gain = 26dB PVCC = 24V TA = 25C RL = 4 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.001 PO = 1W PO = 2.5W PO = 5W Gain = 26dB PVCC = 12V TA = 25C RL = 8 0.1 0.01 20 100 1k Frequency (Hz) 10k 0.001 20k 20 100 1k Frequency (Hz) G004 Figure 3. Total Harmonic Distortion + Noise (BTL) vs Frequency 20k G005 Figure 4. Total Harmonic Distortion + Noise (BTL) vs Frequency 10 10 PO = 1W PO = 5W PO = 10W Gain = 26dB PVCC = 24V TA = 25C RL = 8 Gain = 26dB PVCC = 6V TA = 25C RL = 4 1 THD+N (%) 1 THD+N (%) 10k 0.1 0.01 0.1 0.01 f = 20Hz f = 1kHz f = 6kHz 0.001 20 100 1k Frequency (Hz) 10k 20k 0.001 0.01 0.1 1 Output Power (W) G006 Figure 5. Total Harmonic Distortion + Noise (BTL) vs Frequency 8 Submit Documentation Feedback 10 G008 Figure 6. Total Harmonic Distortion + Noise (BTL) vs Output Power Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 Typical Characteristics (continued) fs = 400 kHz, BD Mode (unless otherwise noted) 10 10 Gain = 26dB PVCC = 12V TA = 25C RL = 4 Gain = 26dB PVCC = 24V TA = 25C RL = 4 1 THD+N (%) 0.1 0.1 0.01 0.01 f = 20Hz f = 1kHz f = 6kHz 0.001 0.01 0.1 f = 20Hz f = 1kHz f = 6kHz 1 Output Power (W) 10 0.001 0.01 40 0.1 1 Output Power (W) 10 100 G009 Figure 7. Total Harmonic Distortion + Noise (BTL) vs Output Power G010 Figure 8. Total Harmonic Distortion + Noise (BTL) vs Output Power 10 10 Gain = 26dB PVCC = 12V TA = 25C RL = 8 Gain = 26dB PVCC = 24V TA = 25C RL = 8 1 THD+N (%) THD+N (%) 1 0.1 0.1 0.01 0.01 f = 20Hz f = 1kHz f = 6kHz 0.001 0.01 0.1 f = 20Hz f = 1kHz f = 6kHz 1 Output Power (W) 10 0.001 0.01 50 0.1 1 Output Power (W) 10 50 G011 Figure 9. Total Harmonic Distortion + Noise (BTL) vs Output Power G012 Figure 10. Total Harmonic Distortion + Noise (BTL) vs Output Power 50 Gain = 26dB TA = 25C PVCC = 24V RL = 4 300 20 200 10 100 0 0 30 Gain (dB) Output Power (W) 40 30 20 -10 -100 -20 -200 -300 -30 10 Gain = 26dB PVCC = 12V TA = 25C RL = 4 -40 0 0 1 2 PLIMIT Voltage (V) 3 4 -50 20 100 -400 Gain Phase 1k Frequency (Hz) 10k -500 100k G013 Figure 11. Output Power (BTL) vs Plimit Voltage Copyright (c) 2012-2017, Texas Instruments Incorporated Phase () THD+N (%) 1 G014 Figure 12. Gain/Phase (BTL) vs Frequency Submit Documentation Feedback Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 9 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 www.ti.com Typical Characteristics (continued) fs = 400 kHz, BD Mode (unless otherwise noted) 50 Gain = 26dB TA = 25C RL = 8 45 Maximum Output Power (W) Maximum Output Power (W) 40 35 30 25 20 15 10 5 0 THD+N = 1% THD+N = 10% 4 6 8 10 12 14 16 18 Supply Voltage (V) 20 22 24 26 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 Gain = 26dB TA = 25C RL = 4 THD+N = 1% THD+N = 10% 4 6 8 10 12 14 16 18 Supply Voltage (V) 20 22 24 26 G015 G016 Figure 14. Maximum Output Power (BTL) vs Supply Voltage 100 100 90 90 80 80 70 70 Power Efficiency (%) Power Efficiency (%) Figure 13. Maximum Output Power (BTL) vs Supply Voltage 60 50 40 30 50 40 30 20 20 PVCC = 6V PVCC =12V PVCC = 24V Gain = 26dB TA = 25C RL = 8 10 0 60 0 5 10 15 20 25 30 35 Output Power (W) 40 45 0 50 PVCC = 6V PVCC = 12V PVCC = 24V Gain = 26dB TA = 25C RL = 4 10 0 5 10 15 20 25 30 35 Output Power (W) 40 45 50 G017 Figure 15. Power Efficiency (BTL) vs Output Power G018 Figure 16. Power Efficiency (BTL) vs Output Power 0 0 Gain = 26dB PVCC = 24V TA = 25C RL = 8 -10 -20 -30 -30 -40 -40 -50 -50 Crosstalk (dB) Crosstalk (dB) -20 -60 -70 -80 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 Right to Left Left to Right -130 -140 Gain = 26dB PVCC = 12V TA = 25C RL = 4 -10 20 100 1k Frequency (Hz) 10k Right to Left Left to Right -130 20k -140 20 100 1k Frequency (Hz) 10k G021 Figure 17. Crosstalk vs Frequency 10 Submit Documentation Feedback 20k G022 Figure 18. Crosstalk vs Frequency Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 Typical Characteristics (continued) fs = 400 kHz, BD Mode (unless otherwise noted) 10 0 Gain = 26dB PVCC = 12VDC + 200mVP-P TA = 25C RL = 8 -10 -20 Gain = 26dB PVCC = 12V TA = 25C RL = 2 1 -40 THD+N (%) kSVR (dB) -30 -50 -60 0.1 -70 0.01 -80 -90 -100 PO = 1W PO = 5W PO = 10W Left Channel Right Channel 20 100 1k Frequency (Hz) 10k 0.001 20k 20 100 1k Frequency (Hz) 10k 20k G023 Figure 19. Supply Ripple Rejection Ratio (BTL) vs Frequency G024 Figure 20. Total Harmonic Distortion + Noise (PBTL) vs Frequency 180 10 Gain = 26dB PVCC = 12V TA = 25C RL = 2 140 Maximum Output Power (W) 1 THD+N (%) Gain = 26dB TA = 25C RL = 2 160 0.1 0.01 120 100 80 60 40 f = 20Hz f = 1kHz f = 6kHz 0.001 0.01 20 0.1 1 Output Power (W) 10 0 40 THD+N = 1% THD+N = 10% 4 6 8 10 12 14 16 18 Supply Voltage (V) 20 22 24 26 G025 G027 Figure 22. Maximum Output Power (PBTL) vs Supply Voltage 100 0 90 -10 80 -20 70 -30 60 -40 kSVR (dB) Power Efficiency (%) Figure 21. Total Harmonic Distortion + Noise (PBTL) vs Output Power 50 40 30 -50 -60 -70 20 -80 PVCC = 6V PVCC = 12V PVCC =24V Gain = 26dB TA = 25C RL = 2 10 0 Gain = 26dB PVCC = 12VDC + 200mVP-P TA = 25C RL = 2 0 10 20 30 40 50 60 70 Output Power (W) 80 90 -90 100 -100 20 100 G028 Figure 23. Power Efficiency (PBTL) vs Output Power Copyright (c) 2012-2017, Texas Instruments Incorporated 1k Frequency (Hz) 10k 20k G030 Figure 24. Supply Ripple Rejection Ratio (PBTL) vs Frequency Submit Documentation Feedback Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 11 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 www.ti.com Typical Characteristics (continued) fs = 400 kHz, BD Mode (unless otherwise noted) 10 140 Gain = 26dB PVCC = 24V TA = 25C RL = 3 Gain = 26dB TA = 25C RL = 3 130 120 110 Maximum Output Power (W) THD+N (%) 1 0.1 100 90 80 70 60 50 40 0.01 30 20 f = 20Hz f = 1kHz f = 6kHz 0.001 0.01 0.1 THD+N = 1% THD+N = 10% 10 1 10 Output Power (W) 100 200 0 4 6 8 10 G032 Figure 25. Total Harmonic Distortion + Noise (PBTL) vs Output Power 12 Submit Documentation Feedback 12 14 16 18 Supply Voltage (V) 20 22 24 26 G034 Figure 26. Maximum Output Power (PBTL) vs Supply Voltage Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 7 Detailed Description 7.1 Overview The TPA31xxD2 device is a highly efficient Class D audio amplifier with integrated 120m Ohms MOSFET that allows output currents up to 7.5 A. The high efficiency allows the amplifier to provide an excellent audio performance without the need for a bulky heat sink. The device can be configured for either master or slave operation by using the SYNC pin. This helps to prevent audible beats noise. 7.2 Functional Block Diagram GVDD SDZ MUTE PVCC BSPR PVCC TTL Buffer Modulation and PBTL Select Gain Control OUTPR_FB Gate Drive GAIN OUTPR + OUTPR_FB - RINP RINN Gain Control + - + - + PLIMIT - + - GND PWM Logic GVDD - PVCC BSNR PVCC OUTPNR_FB OUTNR_ FB + FAULTZ Gate Drive OUTNR SC Detect GND SYNC GAIN/SLV Ramp Generator AM<2:0> Biases and References PLIMIT Reference PLIMIT PVCC Startup Protection Logic DC Detect Thermal Detect UVLO/OVLO PVCC GVDD AVDD AVCC BSNL LDO Regulator GVDD Gate Drive GVDD LINP Gain Control OUTNL - OUTNL_FB LINN PVCC PVCC - + + - - + + - GND PWM Logic PLIMIT + OUTNL_ FB GVDD + PVCC BSPL PVCC OUTPL_FB - Input Sense Gate Drive OUTPL Modulation and PBTL Select PBTL Select OUTPL_FB GND GND Thermal Pad Copyright (c) 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Gain Setting and Master and Slave The gain of the TPA31xxD2 family is set by the voltage divider connected to the GAIN/SLV control pin. Master or Slave mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four stages sets the GAIN in Master mode in gains of 20, 26, 32, 36 dB respectively, while the next four stages sets the GAIN in Slave mode in gains of 20, 26, 32, 36 dB respectively. The gain setting is latched during power-up and cannot be changed while device is powered. Table 1 lists the recommended resistor values and the state and gain: Copyright (c) 2012-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 13 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 www.ti.com Feature Description (continued) Table 1. Gain and Master/Slave MASTER / SLAVE MODE GAIN R1 (to GND) (1) R2 (to GVDD) (1) INPUT IMPEDANCE Master 20 dB 5.6 k OPEN 60 k Master 26 dB 20 k 100 k 30 k Master 32 dB 39 k 100 k 15 k Master 36 dB 47 k 75 k 9 k Slave 20 dB 51 k 51 k 60 k Slave 26 dB 75 k 47 k 30 k Slave 32 dB 100 k 39 k 15 k Slave 36 dB 100 k 16 k 9 k (1) Resistor tolerance should be 5% or better. 5 2 1 C5 1 F 2 2 1 R1 INNR 6 1 R2 51 k 51 k PLIMIT 7 GVDD 8 GAIN/SLV 9 GND 10 Figure 27. Gain, Master/Slave In Master mode, SYNC terminal is an output, in Slave mode, SYNC terminal is an input for a clock input. TTL logic levels with compliance to GVDD. 7.3.2 Input Impedance The TPA31xxD2 family input stage is a fully differential input stage and the input impedance changes with the gain setting from 9 k at 36 dB gain to 60 k at 20 dB gain. Table 1 lists the values from min to max gain. The tolerance of the input resistor value is 20% so the minimum value will be higher than 7.2 k. The inputs need to be AC-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages during powerON and power-OFF. The input ac-coupling capacitor together with the input impedance forms a high-pass filter with the following cut-off frequency: 1 f = 2pZiCi (1) If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz. Table 2 lists the recommended ac-couplings capacitors for each gain step. If a -3 dB is accepted at 20 Hz 10 times lower capacitors can used - for example, a 1 F can be used. Table 2. Recommended Input AC-Coupling Capacitors 14 GAIN INPUT IMPEDANCE INPUT CAPACITANCE HIGH-PASS FILTER 20 dB 60 k 1.5 F 1.8 Hz 26 dB 30 k 3.3 F 1.6 Hz 32 dB 15 k 5.6 F 1.9 Hz 36 dB 9 k 10 F 1.8 Hz Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 Zf Ci IN Input Signal Zi Figure 28. Input Impedance The input capacitors used should be a type with low leakage, like quality electrolytic, tantalum or ceramic. If a polarized type is used the positive connection should face the input pins which are biased to 3 Vdc. 7.3.3 Startup and Shutdown Operation The TPA31xxD2 family employs a shutdown mode of operation designed to reduce supply current (Icc) to the absolute minimum level during periods of nonuse for power conservation. The SDZ input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SDZ low will put the outputs to mute and the amplifier to enter a low-current state. It is not recommended to leave SDZ unconnected, because amplifier operation would be unpredictable. For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power supply. The gain setting is selected at the end of the start-up cycle. At the end of the start-up cycle, the gain is selected and cannot be changed until the next power-up. 7.3.4 PLIMIT Operation The TPA31xxD2 family has a built-in voltage limiter that can be used to limit the output voltage level below the supply rail, the amplifier simply operates as if it was powered by a lower supply voltage, and thereby limits the output power. Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also be used if tighter tolerance is required. Add a 1 F capacitor from pin PLIMIT to ground to ensure stability. It is recommended to connect PLIMIT to GVDD when using 1SPW-modulation mode. Figure 29. Power Limit Example The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle to a fixed maximum value. This limit can be thought of as a "virtual" voltage rail which is lower than the supply connected to PVCC. This "virtual" rail is approximately 4 times the voltage at the PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance. Copyright (c) 2012-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 15 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 aeae o o RL cc c / VP // e RL + 2 RS o o = e 2 RL POUT www.ti.com 2 for unclipped power where * * * * * POUT (10% THD) = 1.25 x POUT (unclipped) RL is the load resistance. RS is the total series resistance including RDS(on), and output filter resistance. VP is the peak amplitude VP = 4 x PLIMIT voltage if PLIMIT < 4 x VP (2) Table 3. Power Limit Example PVCC (V) PLIMIT VOLTAGE (V) R to GND R to GVDD OUTPUT VOLTAGE (Vrms) GVDD Open Short 17.9 24 V 3.3 45 k 51 k 12.67 24 V 2.25 24 k 51 k 9 12 V GVDD Short Open 10.33 12 V 2.25 24 k 51 k 9 12 V 1.5 18 k 68 k 6.3 24 V (1) (1) PLIMIT measurements taken with EVM gain set to 26 dB and input voltage set to 1 Vrms. 7.3.5 GVDD Supply The GVDD Supply is used to power the gates of the output full bridge transistors. It can also be used to supply the PLIMIT and GAIN/SLV voltage dividers. Decouple GVDD with a X5R ceramic 1 F capacitor to GND. The GVDD supply is not intended to be used for external supply. It is recommended to limit the current consumption by using resistor voltage dividers for GAIN/SLV and PLIMIT of 100 k or more. 7.3.6 BSPx AND BSNx Capacitors The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 220 nF ceramic capacitor of quality X5R or better, rated for at least 16 V, must be connected from each output to its corresponding bootstrap input. (See the application circuit diagram in Figure 37.) The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the highside MOSFETs turned on. 7.3.7 Differential Inputs The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA31xxD2 family with a differential source, connect the positive lead of the audio source to the RINP or LINP input and the negative lead from the audio source to the RINN or LINN input. To use the TPA31xxD2 family with a single-ended source, ac ground the negative input through a capacitor equal in value to the input capacitor on positive and apply the audio source to either input. In a single-ended input application, the unused input should be ac grounded at the audio source instead of at the device input for best noise performance. For good transient performance, the impedance seen at each of the two differential inputs should be the same. The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to allow the input dc blocking capacitors to become completely charged during the 10 ms power-up time. If the input capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching which can result in pop if the input components are not well matched. 16 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 7.3.8 Device Protection System The TPA31xxD2 family contains a complete set of protection circuits carefully designed to make system design efficient as well as to protect the device against any kind of permanent failures due to short circuits, overload, over temperature, and under-voltage. The FAULTZ pin will signal if an error is detected according to Table 4: Table 4. Fault Reporting FAULT TRIGGERING CONDITION (typical value) FAULTZ ACTION LATCHED/SELFCLEARING Over Current Output short or short to PVCC or GND Low Output high impedance Latched Over Temperature Tj > 150C Low Output high impedance Latched Too High DC Offset DC output voltage Low Output high impedance Latched Under Voltage on PVCC PVCC < 4.5V - Output high impedance Self-clearing Over Voltage on PVCC PVCC > 27V - Output high impedance Self-clearing 7.3.9 DC Detect Protection The TPA31xxD2 family has circuitry which will protect the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be reported on the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the state of the outputs to Hi-Z. If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the DC Detect protection latch. A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 60% for more than 420 msec at the same polarity. Table x below shows some examples of the typical DC Detect Protection threshold for several values of the supply voltage. This feature protects the speaker from large DC currents or AC currents less than 2Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at powerup until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults. Table 5 lists the minimum output offset voltages required to trigger the DC detect. The outputs must remain at or above the voltage listed in the table for more than 420 ms to trigger the DC detect. Table 5. DC Detect Threshold PVCC (V) VOS - OUTPUT OFFSET VOLTAGE (V) 4.5 0.96 6 1.3 12 2.6 18 3.9 7.3.10 Short-Circuit Protection and Automatic Recovery Feature The TPA31xxD2 family has protection from over current conditions caused by a short circuit on the output stage. The short circuit protection fault is reported on the FAULTZ pin as a low state. The amplifier outputs are switched to a high impedance state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SDZ pin through the low state. If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the shortcircuit protection latch. In systems where a possibility of a permanent short from the output to PVDD or to a high voltage battery like a car battery can occur, pull the MUTE pin low with the FAULTZ signal with a inverting transistor to ensure a highZ restart, like shown in the figure below: Copyright (c) 2012-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 17 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 www.ti.com > 1.4sec SDZ mP MUTE TPA3116D2 FAULTZ SDZ MUTE FAULTZ Copyright (c) 2016, Texas Instruments Incorporated Figure 30. MUTE Driven by Inverted FAULTZ Figure 31. Timing Requirement for SDZ 7.3.11 Thermal Protection Thermal protection on the TPA31xxD2 family prevents damage to the device when the internal die temperature exceeds 150C. There is a 15C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal trip point, the device enters into the shutdown state and the outputs are disabled. This is a latched fault. Thermal protection faults are reported on the FAULTZ terminal as a low state. If automatic recovery from the thermal protection latch is desired, connect the FAULTZ pin directly to the SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the thermal protection latch. 7.3.12 Device Modulation Scheme The TPA31xxD2 family has the option of running in either BD modulation or 1SPW modulation; this is set by the MODSEL pin. 7.3.12.1 MODSEL = GND: BD-Modulation This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage. The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages. The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The voltage across the load sits at 0V throughout most of the switching period, reducing the switching current, which reduces any I2R losses in the load. 18 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 OUTP OUTN No Output OUTP- OUTN 0V Speaker Current OUTP OUTN Positive Output PVCC OUTP-OUTN 0V Speaker Current 0A OUTP Negative Output OUTN OUTP - OUTN 0V - PVCC Speaker Current 0A Figure 32. BD Mode Modulation 7.3.12.2 MODSEL = HIGH: 1SPW-modulation The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty in THD degradation and more attention required in the output filter selection. In 1SPW mode the outputs operate at ~15% modulation during idle conditions. When an audio signal is applied one output will decrease and one will increase. The decreasing output signal will quickly rail to GND at which point all the audio modulation takes place through the rising output. The result is that only one output is switching during a majority of the audio cycle. Efficiency is improved in this mode due to the reduction of switching losses. The THD penalty in 1SPW mode is minimized by the high performance feedback loop. The resulting audio signal at each half output has a discontinuity each time the output rails to GND. This can cause ringing in the audio reconstruction filter unless care is taken in the selection of the filter components and type of filter used. Copyright (c) 2012-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 19 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 www.ti.com OUTP OUTN OUTP -OUTN No Output 0V Speaker Current OUTP OUTN Positive Output PVCC OUTP -OUTN 0V Speaker Current 0A OUTP Negative Output OUTN OUTP -OUTN 0V - PVCC Speaker Current 0A Figure 33. 1SPW Mode Modulation 20 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 7.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme The main reason that the traditional class-D amplifier-based on AD modulation needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 x VCC, and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive. The TPA3116D2 modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is VCC instead of 2 x VCC. As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed. An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching frequency than the speaker, which results in less power dissipation, therefore increasing efficiency. 7.3.14 Ferrite Bead Filter Considerations Using the Advanced Emissions Suppression Technology in the TPA3116D2 amplifier it is possible to design a high efficiency class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite bead used in the filter. One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to the operation of the class-D amplifier. Many of the specifications regulating consumer electronics have emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30 MHz and above range from appearing on the speaker wires and the power supply lines which are good antennas for these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance, the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz. Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead current handling capability by measuring the resonant frequency of the filter output at low power and at maximum power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of ferrite beads which have been tested and work well with the TPA3130D2 can be seen in the TPA3130D2EVM user guide SLOU341. A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good temperature and voltage characteristics will work best. Additional EMC improvements may be obtained by adding snubber networks from each of the class-D outputs to ground. Suggested values for a simple RC series snubber network would be 18 in series with a 330 pF capacitor although design of the snubber network is specific to every application and must be designed taking into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make sure the layout of the snubber network is tight and returns directly to the GND pins on the IC. Copyright (c) 2012-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 21 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 www.ti.com Figure 34. TPA311xD2 Radiated Emissions 7.3.15 When to Use an Output Filter for EMI Suppression The TPA3116D2 has been tested with a simple ferrite bead filter for a variety of applications including long speaker wires up to 125 cm and high power. The TPA3116D2 EVM passes FCC class-B specifications under these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency. There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases a classic second order Butterworth filter similar to those shown in the figures below can be used. Some systems have little power supply decoupling from the AC line but are also subject to line conducted interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these cases, LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using low frequency ferrite material can also be effective at preventing line conducted interference. 22 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 10 H OUTP L1 C2 0.68 F 4W-8W 10 H OUTN L2 C3 0.68 F Ferrite Chip Bead OUTP 1 nF 4W-8W Ferrite Chip Bead OUTN 1 nF Figure 35. TPA31xxD2 Output Filters 7.3.16 AM Avoidance EMI Reduction To reduce interference in the AM radio band, the TPA3116D2 has the ability to change the switching frequency via AM<2:0> pins. The recommended frequencies are listed in Table 6. The fundamental frequency and its second harmonic straddle the AM radio band listed. This eliminates the tones that can be present due to the switching frequency being demodulated by the AM radio. Table 6. AM Frequencies US EUROPEAN AM FREQUENCY (kHz) AM FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) AM2 AM1 AM0 500 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 522-540 540-917 540-914 917-1125 914-1122 600 (or 400) 1125-1375 1122-1373 500 1375-1547 1373-1548 1547-1700 1548-1701 Copyright (c) 2012-2017, Texas Instruments Incorporated 600 (or 400) 600 (or 500) Submit Documentation Feedback Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 23 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 www.ti.com 7.4 Device Functional Modes 7.4.1 Mono Mode (PBTL) The TPA31xxD2 family can be connected in MONO mode enabling up to 100W output power. This is done by: * Connect INPL and INNL directly to Ground (without capacitors) this sets the device in Mono mode during power up. * Connect OUTPR and OUTNR together for the positive speaker terminal and OUTNL and OUTPL together for the negative pin. * Analog input signal is applied to INPR and INNR. TPA3116D2 4.5 V-26 V PSU OUTPR OUTNR Right LC Filter PBTL Detect Left OUTPL OUTNL Figure 36. Mono Mode 24 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information This section describes a 2.1 Master and Slave application. The Master is configured as stereo outputs and the Slave is configured as mono PBTL output. 8.2 Typical Application A 2.1 solution, U1 TPA3116D2 in Master mode 400 kHz, BTL, gain if 20 dB, power limit not implemented. U2 in Slave, PBTL mode gain of 20 dB. Inputs are connected for differential inputs. Copyright (c) 2012-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 25 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 www.ti.com Typical Application (continued) OUTPUT LC FILTER 16 BSNL AM1 PVCC AM0 PVCC SY NC AVCC 19 C19 OUT_P_RIGHT 1 1 2 1 2 OUT_N_RIGHT 1 1 2 2 2 OUT_P_LEFT 1 C32 1nF C38 10nF + GND PVCC 17 C29 680nF C25 220uF SYNC 2 C24 100nF L9 10uH GND C40 10nF C33 1nF 4R - R18 3.3R 2 1 GND PVCC DECOUPLING PVCC DECOUPLING 1 1 1 2 PVCC C47 220uF 2 2 2 C46 100nF 2 12 13 R22 100k 1 14 15 16 INNL MUTE GND OUTNL AM2 BSNL AM1 PVCC AM0 PVCC SY NC AVCC 22 1 20 C44 OUT_P_SUB 1 1 2 GND C56 10nF C54 1nF 2 1 19 2 2R GND C52 1uF 2 R24 3.3R - 220nF L16 18 10uH PVCC 17 C48 1nF C50 220uF C49 100nF 2 2 TPA3116D2 + 220nF 220nF 2 23 1 C41 1nF 2 C43 C43 1 21 1 1 2 25 C55 10nF 2 1 BSPL OUTPL 1 1 GND INPL 26 24 C53 1nF OUT_N_SUB 11 GND MUTE_SUB GND GND C51 1uF 1 2 12 2 10 GAIN/SLV BSNR 27 R23 3.3R 2 9 8 GVDD OUTNR 10uH 1 R21 75k GND PLIMIT 28 2 7 INNR L15 29 1 R20 47k OUTPR EMI C-RC SNUBBER 2 2 1 6 BSPR INPR 1 220nF 2 1 1uF FAULTZ OUTPUT LC FILTER C42 1 30 1 5 PVCC 31 2 4 1 SDZ GND 32 GND 3 PVCC GND 1uF 1 MODSEL GND 2 1 Power Pad 1 GND U2 /SD_SUB 1 R17 3.3R 220nF 1 2 2 2 2 C45 1nF R19 100k C39 1uF 10uH 18 PVCC C36 1 1 2 1 C23 1nF R73 10k 2 L10 C28 680nF 20 TPA3116D2 C35 2 10uH 1 2 21 L8 1 1 22 R16 3.3R 2 2 OUTNL 220nF 220nF 2 23 GND IN_N_SUB 1 2 AM2 GND C17 C18 1 24 1 2 MUTE OUTPL 25 2 1 R14 100k INNL BSPL 1 OUT_ N_LEFT 15 2 INPL GND 27 26 GND 2 1 GND BSNR 1 MUTE_LR GAIN/SLV OUTNR C31 1nF C27 680nF 1 2 14 GVDD 28 - C37 10nF 2 C14 1uF PLIMIT GND 1 13 GND GND 2 1 OUTPR INNR 220nF 2 29 1 11 C13 1uF 2 1 INPR C16 1 30 2 12 2 2 10 BSPR 1 9 8 FAULTZ + 2 R12 20k 12 IN_P_SUB C34 10nF 4R 1 7 2 IN_N_LEFT R15 3.3R C30 1nF 31 2 1 1 6 R11 100k PVCC 2 5 1uF PVCC SDZ 1 1 C12 MODSEL GND 3 1uF 1 2 IN_P_LEFT 10uH C26 680nF GND 32 GND 2 4 GND C22 220uF GND C11 2 C15 1uF L7 C21 100nF 2 GND /SD_LR IN_N_RIGHT C20 1nF GND U1 1 IN_P_RIGHT 2 C58 100nF EMI C-RC SNUBBER 2 2 1 1 1 GND GND PVCC 2 R10 3.3R R13 100k 2 1 2 1 2 C57 10nF Power Pad PVCC 1 1 1 2 PVCC DECOUPLING PVCC GND PVCC DECOUPLING Copyright (c) 2016, Texas Instruments Incorporated Figure 37. Schematic 26 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 Typical Application (continued) 8.2.1 Design Requirements DESIGN PARAMETERS EXAMPLE VALUE Input voltage range PVCC 4.5 V to 26 V PWM output frequencies 400 kHz, 500 kHz, 600 kHz, 1 MHz or 1.2 MHz Maximum output power 50 W 8.2.2 Detailed Design Procedure The TPA31xxD2 family is a very flexible and easy to use Class D amplifier; therefore the design process is straightforward. Before beginning the design, gather the following information regarding the audio system. * PVCC rail planned for the design * Speaker or load impedance * Maximum output power requirement * Desired PWM frequency 8.2.2.1 Select the PWM Frequency Set the PWM frequency by using AM0, AM1 and AM2 pins. 8.2.2.2 Select the Amplifier Gain and Master/Slave Mode In order to select the amplifier gain setting, the designer must determine the maximum power target and the speaker impedance. Once these parameters have been determined, calculate the required output voltage swing which delivers the maximum output power. Choose the lowest analog gain setting that corresponds to produce an output voltage swing greater than the required output swing for maximum power. The analog gain and master/slave mode can be set by selecting the voltage divider resistors (R1 and R2) on the Gain/SLV pin. 8.2.2.3 Select Input Capacitance Select the bulk capacitors at the PVCC inputs for proper voltage margin and adequate capacitance to support the power requirements. In practice, with a well-designed power supply, two 100-F, 50-V capacitors should be sufficient. One capacitor should be placed near the PVCC inputs at each side of the device. PVCC capacitors should be a low ESR type because they are being used in a high-speed switching application. 8.2.2.4 Select Decoupling Capacitors Good quality decoupling capacitors need to be added at each of the PVCC inputs to provide good reliability, good audio performance, and to meet regulatory requirements. X5R or better ratings should be used in this application. Consider temperature, ripple current, and voltage overshoots when selecting decoupling capacitors. Also, these decoupling capacitors should be located near the PVCC and GND connections to the device in order to minimize series inductances. 8.2.2.5 Select Bootstrap Capacitors Each of the outputs require bootstrap capacitors to provide gate drive for the high-side output FETs. For this design, use 0.22-F, 25-V capacitors of X5R quality or better. Copyright (c) 2012-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 27 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 www.ti.com 8.2.3 Application Curves 10 10 Gain = 26dB PVCC = 12V TA = 25C RL = 4 Gain = 26dB PVCC = 24V TA = 25C RL = 4 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.1 0.01 f = 20Hz f = 1kHz f = 6kHz 0.001 0.01 0.1 f = 20Hz f = 1kHz f = 6kHz 1 Output Power (W) 10 40 0.001 0.01 0.1 G009 Figure 38. Total Harmonic Distortion + Noise (BTL) vs Output Power 1 Output Power (W) 10 100 G010 Figure 39. Total Harmonic Distortion + Noise (BTL) vs Output Power 9 Power Supply Recommendations The power supply requirements for the TPA3116D2 consist of one higher-voltage supply to power the output stage of the speaker amplifier. Several on-chip regulators are included on the TPA3116D2 to generate the voltages necessary for the internal circuitry of the audio path. It is important to note that the voltage regulators which have been integrated are sized only to provide the current necessary to power the internal circuitry. The external pins are provided only as a connection point for off-chip bypass capacitors to filter the supply. Connecting external circuitry to these regulator outputs may result in reduced performance and damage to the device. The high voltage supply, between 4.5 V and 26 V, supplies the analog circuitry (AVCC) and the power stage (PVCC). The AVCC supply feeds internal LDO including GVDD. This LDO output are connected to external pins for filtering purposes, but should not be connected to external circuits. GVDD LDO output have been sized to provide current necessary for internal functions but not for external loading. 10 Layout 10.1 Layout Guidelines The TPA3116D2 can be used with a small, inexpensive ferrite bead output filter for most applications. However, since the class-D switching edges are fast, it is necessary to take care when planning the layout of the printed circuit board. The following suggestions will help to meet EMC requirements. * Decoupling capacitors -- The high-frequency decoupling capacitors should be placed as close to the PVCC and AVCC terminals as possible. Large (100 F or greater) bulk power supply decoupling capacitors should be placed near the TPA3116D2 on the PVCC supplies. Local, high-frequency bypass capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the IC GND pad directly for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between 220 pF and 1 nF and a larger mid-frequency cap of value between 100 nF and 1 F also of good quality to the PVCC connections at each end of the chip. * Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna. * Grounding -- The PVCC decoupling capacitors should connect to GND. All ground should be connected at the IC GND, which should be used as a central ground connection or star ground for the TPA3116D2. * Output filter -- The ferrite EMI filter (see Figure 35) should be placed as close to the output terminals as possible for the best EMI performance. The LC filter should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be grounded. 28 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 Layout Guidelines (continued) For an example layout, see the TPA3116D2 Evaluation Module (TPA3116D2EVM) User Guide (SLOU336). Both the EVM user manual and the thermal pad application reports, SLMA002 and SLMA004, are available on the TI Web site at http://www.ti.com. 10.2 Layout Example Figure 40. Layout Example Top Copyright (c) 2012-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 29 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 www.ti.com Layout Example (continued) Figure 41. Layout Example Bottom 30 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 10.3 Heat Sink Used on the EVM The heat sink (part number ATS-TI 10 OP-521-C1-R1) used on the EVM is an 14x25x50 mm extruded aluminum heat sink with three fins (see drawing below). For additional information on the heat sink, go to www.qats.com. 50.000.38 [1.969.015] SINK LENGTH MACHINE THESE 3 EDGES AFTER ANODIZATION 0.00 25.00 -0.60 +.000 .984 -.024 SINK HEIGHT 3.00 [.118] 1.00 [.118] 6.35 [.250] 3.00 [.118] 40.00 [1.575] 30.50 [1.201] 19.50 [.768] 10.00 [.394] 0 [.000] 13.900.38 [.547.015] BASE WIDTH 6.95 [.274] 5.00 [.197] 40.00 [1.575] 2X 4-40 x 6.5 Figure 42. EVM Heatsink This size heat sink has shown to be sufficient for continuous output power. The crest factor of music and having airflow will lower the requirement for the heat sink size and smaller types can be used. Copyright (c) 2012-2017, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 31 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708G - APRIL 2012 - REVISED DECEMBER 2017 www.ti.com 11 Device and Documentation Support 11.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 7. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPA3116D2 Click here Click here Click here Click here Click here TPA3118D2 Click here Click here Click here Click here Click here TPA3130D2 Click here Click here Click here Click here Click here 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates -- go to the product folder for your device on ti.com. In the upper right-hand corner, click the Alert me button to register and receive a weekly digest of product information that has changed (if any). For change details, check the revision history of any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 32 Submit Documentation Feedback Copyright (c) 2012-2017, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 PACKAGE OPTION ADDENDUM www.ti.com 15-Nov-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPA3116D2DAD ACTIVE HTSSOP DAD 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA 3116 D2 TPA3116D2DADR ACTIVE HTSSOP DAD 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA 3116 D2 TPA3118D2DAP ACTIVE HTSSOP DAP 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3118 TPA3118D2DAPR ACTIVE HTSSOP DAP 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3118 TPA3130D2DAP ACTIVE HTSSOP DAP 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3130 TPA3130D2DAPR ACTIVE HTSSOP DAP 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3130 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Nov-2017 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPA3116D2, TPA3118D2 : * Automotive: TPA3116D2-Q1, TPA3118D2-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 15-Nov-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPA3116D2DADR HTSSOP DAD 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1 TPA3118D2DAPR HTSSOP DAP 32 2000 330.0 TPA3130D2DAPR HTSSOP DAP 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1 24.4 8.6 11.5 1.6 12.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Nov-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA3116D2DADR HTSSOP DAD 32 2000 367.0 367.0 45.0 TPA3118D2DAPR HTSSOP DAP 32 2000 367.0 367.0 45.0 TPA3130D2DAPR HTSSOP DAP 32 2000 367.0 367.0 45.0 Pack Materials-Page 2 PACKAGE OUTLINE DAD0032A PowerPAD TM TSSOP - 1.2 mm max height SCALE 1.600 PLASTIC SMALL OUTLINE C 8.3 TYP 7.9 A SEATING PLANE PIN 1 ID AREA 0.1 C 30X 0.65 32 1 EXPOSED THERMAL PAD 11.1 10.9 NOTE 3 4.36 3.26 16 17 4.11 3.31 B 2X 9.75 0.30 0.19 0.1 C A 32X B 6.2 6.0 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0 -8 1.2 1.0 0.75 0.50 0.15 0.05 DETAIL A TYPICAL 4222646/A 12/2015 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. www.ti.com EXAMPLE BOARD LAYOUT DAD0032A PowerPAD TM TSSOP - 1.2 mm max height PLASTIC SMALL OUTLINE 32X (1.5) SEE DETAILS SYMM 1 32 32X (0.45) 30X (0.65) SYMM (R0.05) TYP 17 16 (7.5) LAND PATTERN EXAMPLE SCALE:8X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.05 MIN AROUND 0.05 MAX AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4222646/A 12/2015 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DAD0032A PowerPAD TM TSSOP - 1.2 mm max height PLASTIC SMALL OUTLINE 32X (1.5) SYMM 1 32 32X (0.45) 30X (0.65) SYMM (R0.05) TYP 16 17 (7.5) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X 4222646/A 12/2015 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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