MB86930 C FUJITSU SPARClite 32-BIT RISC EMBEDDED PROCESSOR e 40MHz (25ns/cycle) operating frequency e SPARC high-performance RISC architecture e 2Kbytes 2-way set associative instruction cache e 2Kbytes 2-way set associative data cache e Flexible locking mechanism for data and instruction cache entries e Harvard-style separate instruction and data buses on-chip e 8 window, 136 word register file e Fast interrupt response time e 247 address spaces, 4 Gbyte each e User and supervisor modes e Buffered writes and instruction pre-fetching e Fast page-mode DRAM support e Programmable address decoder and wait-state generator e 16-bit auto reload timer e On-chip clock generator circuit e JTAG test interface e Emulator support hardware e Single vector trapping e 0.8 micron gate, 3 level metal CMOS technology The MB86930 is a member of the SPARClite series of RISC processors which offers high performance and high integration for a wide range of embedded applications. The processor is based on the SPARC architecture and is upward code compatible with previous implementations. At 40 MHz, the processor executes with 40 MIPs peak and 37 MIPs sustained performance. On-chip data and instruction caches are included to help decouple the processor from external memory latency. Separate on-chip instruction and data paths provide a high bandwidth interface between the IU and caches. May 25, 1994 Includedto maximize the performance of the system with minimum glue logic, are chip select outputs, program- mable wait-state generation and built-in support for a high performance connection to page-mode DRAM. See MB86930 block diagram on page 5. Support for debug and diagnostic tools has been included on-chip and allows for direct connection to hardware emulators and improves debug capability when using ROM based monitors. These features combine to give the MB86930 superior speed, flexibility and efficiency to make it the ideal choice for a wide variety of low-cost, high-performance embedded systems. PIN CONFIGURATION 156 105 l l 157 =O OF 104 208-PIN QFP INDEX xO 208 =O rR 53 | l 1 52 TOP VIEW INDEX AREA (For pin assignment, see pin assignment table)MB86930 PIN ASSIGNMENT 179-PIN PGA oO FUJITSU PIN PIN PIN PIN NO. PIN NAME TYPE | NO. PIN NAME TYPE | NO. PIN NAME TYPE | NO. PIN NAME TYPE 1 VDD 46 ADR<19> oO 91 IRL<2> I 136 VSS 2 ASI<0> 0 47 ADR< 18> oO 92 ADR<31> 137. ADR<24> oO 3 -BE<2> oO 48 ADR<16> oO 93 ADR<29> oO 138 VDD _ 4 -SAME_PAGE O 49 ADR<15> 94 VDD _ 139 VSS _ 5 -CS<5> 0 50 ADR<13> oO 95 ADR<23> oO 140 VDD _ 6 -CS<2> 51 ADR<12> 96 ADR<21> 3 141. ADR<10> oO 7 -CS<1> 3 52 VSS _ 97 ADR<20> 0 142 ADR<8> O 8 -AS 3 53 ADR<7> oO 98 ADR<17> oO 143. VDD _ 9 RD/-WR oO 54 ADR<5> oO 99 ADR<14> oO 144 ASI<7> oO 10 -BGRNT 0 55 ADR<3> oO 100 ADR<11> 145 VDD _ 11. -READY I 56 ASI<5> oO 101 ADR<9> 146 VSS _ 12 -RESET I 57 ASI<4> 102 ADR<6> 147, VSS _ 13 D<O> vo 58 ASI<1> oO 103 ADR<4> oO 148 VDD - 14 VDD _ 9 -BE<1> oO 104 ASI<6> 149 VSS 15 VSS _ 60 VDD _ 105 ASI<3> oO 150 VDD - 16 VDD _ 61 VSS _ 106 ASI<2> oO 151 VSS 17. D<10> vO 62 -CS<3> oO 107. -BE<0> 152 D<1> vo 18 D<14> vo 63 -CS<0> oO 108 -BE<3> oO 163 D<4> Vo 19 D<15> vo 64 -LOCK oO 109 -CS<4> oO 154 VSS 20 D<16> vo 65 VOD _ 110 VSS _ 155 VSS - 21 D<17> vo 66 -MEXC ! 111. -ERROR oO 156 VDD - 22 D<20> vO 67 VDD 112 VSS _ 157. VSS _ 23 D<21> vo 68 D<3> vo 113. -BREQ I 158 VDD _ 24 VDD _ 69 VSS _ 114 D<2> vo 169 VSS 25 D<25> vo 70 VDD _ 15 D<6> vo 160 D<30> vo 26 D<<28> vo 71 D<9> vO 16 D<7> vo 161 EMU_D<0> vo 27 D<29> vO 72 D<12> vo 117 D<8> VO 162 VSS _ 28 VSS 73 D<13> vO 118 O<11> vO 163. VSS _- 29 VDD _ 74 VDD _ 119 ~=VSS - 164 VDD _ 30 EMU_SD<1> W/O 75 D<18> vo 120 D<19> vO 165 VSS _ 31 VDD 76 D<22> vo 121 D<23> vo 166 VDD _ 32. ~2VSS _ 77. ~+VSS _ 122 D<24> ie) 167. VSS 33 CLKOUT2 0 78 D<26> vO 123 0<27> vO 168 VDD 34 XTAL1 I 79 +\VDD _ 124 D<31> vo 169 ADR<28> oO 35 XTAL2 oO 80 VDD _ 125 EMU_D<2> vO 170 VSS _ 36 -TIMER_OVF oO 81 -EMU_ENB I 126 EMU_D<3> vo 171. VSS _ 37. TDO oO 82 EMU_SD<0> W/O 127 EMU_SD<2> W/O 172. VDD 38 4 =-TMS I 83 EMU_SD<3> W/O 128 -EMU_BRK 1 173 VSS - 39 = TDI I 84 VSS _ 129 CLKOUT1 oO 174 VDD 40 IRL<1> I 85 VDD _ 130 VDD _ 175 VSS - 41 IRL<3> { 86 VSS _- 131 VSS _ 176 ADR<2> oO 42 ADR<30> O 87 VDD _ 132. -TRST I 177 D<5> vo 43 VDD _ 88 VDD 193 IRL <0O> I 178 EMU_D<1> VO 44 ADR<25> oO 89 TCK . I 134 VSS ~ 179 ADR<27> oO 45 ADR<22> oO 90 CLK_ECB I 135 ADR<26> oO ORDERING CODE Clock Frequency (MHz) Ordering Code Package Type Marking on Part P/N on Box 20 MB86930-20PFV-G Plastic QFP 208 MB86930-20 MB86930-20PFV-G-BND 30 MB86930-30ZF-G Ceramic QFP 208 MB86930-30 MB86930-30ZF-G-BND 40 MB86930-40ZF-G Ceramic QFP 208 w/FIN MB86930-40 MB86930-40ZF-G-BND-FIN 40 MB86930-40CR-G Ceramic PGA179 MB86930-40 MB86930-40CR-G-BND Note: The ordering code is for production level product. Early shipments of this device may be marked with "ES to indicate that the part is not yet at full production status. Contact your local Fujitsu representative for additional information on "ES level products.MB86930 PIN ASSIGNMENT 208-PIN QFP co FUJITSU PIN PIN PIN PIN NO. PINNAME TYPE|NO. PINNAME TYPE|NO. PINNAME TYPE|NO. PINNAME TYPE 1 AOR<28> 0 53. EMU_D<0> W/O 105. D<4> vO 157 VDD _ 2 ADR<29> oO 54 VSS 106 VSS 158 NC. 3 ADR<30> oO 55 -EMU_ENB 107 VDD 159 ASI<4> Oo 4 ADR<31> oO 56 VSS 108 D<3> vO 160 ASI<5> Oo 5 VDD 57 VOD - 109 D<2> vO 161 ASI<6> Oo 6 VSS _ 58 D<31> vO 110 Det> V0 162 ASI<7> Oo 7 VDD 59 D<30> vo 111 Deo> Vo 163 ADR<2> Oo 8 IRL<3> 60 D<29> vo 112 VDD 164 ADR<3> Oo 9 IRL<2> 1 61 VOD 113 -RESET 165 ADR<4> Oo 10 IRL<1> 1 62 D<28> vo 114 -BREQ 166 ADR<5> Oo 11 IRL<0> 63 D<27> vo 115 VSS 167 VDD _ 12 vss 64 VSS _ 116 -MEXG 168 VSS _ 13 CLK_ECB 65 D<26> vO 117 -READY oO 169 ADR<6> Oo 14 TDI 66 D<25> vO 118 VSS _ 170 ADR<7> oO 15 -TRST 1 67 D<24> vo 119 VDD _ 171 NC. 16 TCK 68 vss 120 -BGRNT Oo 172 ADR<8> Oo 17 TMS \ 69 VDD 121 VDD 173 ADR<9> oO 18 VDD 70 VDD _ 122 -ERROR oO 174 VSS _ 19 VSS _ 71 VDD 123 -LOCK oO 175 VDD _ 20 vss _ 72 D<23> vo 124 NC. 176 ADR<10> Oo 21 VDD _ 73 D<22> vO 125 AD/-WR oO 177 NC. 22 VDD 74 VSS. 126 -AS oO 178 ADR<11> Oo 23 VSS 75 D<21> vo | 127 NC. _ 179 ADR<12> Oo 24 TDO Oo 76 D<20> vo | 128 vss _ 180 VDD 25 -TIMER_LOVF 0 77 VDD _ 129 VSS _ 181 ADR<13> 0 26 VOD 78 D<19> vo | 130 vss _ 182 VDD _ 27 ~VSS 79 VSS - 131 -CS<0> Oo 183 VSS 28 VDD 80 D<18> vo | 132 N.C. 184 ADR<14> 0 29 XTAL2 oO 81 NC, _ 133 -CS<1> Oo 185 VSS 30 XTALt \ 82 D<17> vO 134 VSS 186 ADR<15> Oo 31 vss _ 83 D<i6> vO 135 -CS<2> Oo 187. ADR< 16> oO 32 NC. 84 VDD 136 -CS<3> Oo 188 NC. 33 CLKOUT1 oO 85 VSS 137 _-CS<4> oO 189 ADR<17> Oo 34 VDD _ 86 VOD- 138 NC. _ 190 VSS 35 CLKOUT2 Oo 87 D<15> vo | 139 VDD _ 191 VDD _ 36 vss _ 88 N.C. 140 -CS <5> oO 192 ADR<18> Oo 37 NC. 89 D<14> vO | 141 -SAME_PAGE oO 193 ADR<19> Oo 38 VOD _ 90 D<13> vo | 142 VDD 194 ADR<20> Oo 39 vss _ 91 D<12> vo 143. VSS _ 195 N.C. _ 40 NC. 92 D<t1> vO 144 VDD 196 ADR<21> oO 41. -EMU_BRK 93 VSS 145 NC. 197 VDD _ 42 VSS _ 94 D<10> vo 146 -BE<3> oO 198 VSS _ 43 VDD _ 95 D<9> vO 147 VSS _ 199 ADR<22> Oo 44 EMU_SD<3> W/O 9 D<6> vo 148 -BE<2> Oo 200 ADR<23> oO 45 EMU_SD<2> W/O 97 VDD. _ 149 -BE<1> Oo 201 ADR<24> Oo 46 EMU_SD<i> 1/0 98 VSS 150 -BE<0> Oo 202 ADR<25> Oo 47 V8S 99 VSS 151 ASI<0> Oo 203 ~VSS _ 48 VDD - 100 VDD 152 VSS 204 VDD _ 49 EMU_SD<0> VO | 101 D<7> vo 153 VDD 205 VDD _ 50 EMU_D<3> VO | 102 D<6> vO 154 ASI<1> Oo 206 VSS _ 51 EMUD<2> WO | 103 NC. 155 ASI<2> 0 207 ADR<26> Oo 52 EMUD<1> VO | 104 D<5> re) 156 ASI<3> Oo 208 ADR<27> OoFUJITSU MB86930 vpD AD30|IRL3 IRL1 TDI -TMS DO -TOVF XTL2 XTL1 CLO2 VSS VDD EMUSI VDD Oo O Oo O O Oo 8 6 oO 43 42 | 41 40 39 38 37 36 35 34 33 32 32 29 AD25 AD29 AD31|IRL2 CLKECB TCK VDD VDD VSS VDD VSS EMUS3 EMSUO -EMEN VSS oO O o 6 e @ oO 44 93 92 | 91 90 89 88 87 85 84 83 82 81 28 AD22. VDD ap26| VSS IRLO TRST VSS VDD ctot -EMBRK EMUS2 EMUD3 EMUD2 vpp | D29 Oo O oO e 9 O | O 45 94 135 {134 133 132 131 130 129 4128 127 #126 125 80 | 27 AD19 AD23 VSS AD28| VDD VSS VDD VSS VDD VSS VSS EMUDO| D31 VDD p28 O e o0|/e @ceeocee @ 0;0 8 O 46 95 136 169 | 168 167 166 165 164 163 162 161 | 124 79 26 ADI8 AD21 AD24 VSS AD27 eMuD1| D30. D27 -D26 ~25 oO O e@ oOo oO OO O O 47 96 137 170 _179 178 | 160 123 78 25 ADI6 AD20 VDD vss vSS p24 VSS VDD Oo Oo 8 @ e Oo 8 6 48 97 138 171 159 122 77 24 ADIS5 AD17 VSS VDD VDD p23. D222 O e o OO O O 49 98 139 172 158 121 76 23 AD13. AD14. VDD vss vss D19 p18 p20 O o @ oOo oO O 50 99 140 173 157. 120 75~Sso22 AD12 AD11 AD10 VDD VDD VSS VDD D17 oO ) @ O 51 100 141 174 156 119 74 21 VSS AD9 AD8 VSS VSS Dll p13 D16 Oo O O O @ oOo OO O 52 101 142 175 155 118 73 20 AD? AD6 VDD AD2 | INDEX DS vsS D8 oDi2 ois Oo OO 8 O oO 0 OO O 53 102 143 176 177 154 117.=72Ssa9 aps ap4|asi7| vbD vsS vsS vpD vss vpp vss | pl D4 D7 v9 ODi4 Oo 0; 0} @ @ @;0 0 0 0 90 54 103 | 144 | 145 146 147 148 #149 150 151 | 152 153 116 71 18 ap3 [ASI6 ASI3 ASI2|-BEO -BE3 -CS4 SS -ERR VSS -BRBQ| D2 D6 VDD D10 O O O oO Oo O 86 O 55 | 104 105 106 | 107 108 109 110 111 112 4113 L414 #115 70 417 ASI5 ASI4 asi1|-BEl VDD VSS -CS3 -CSO -LOCK VDD -MEXC VDD | D3 vSS VDD OoO;O e O oO oO 8 oO o;O 8 56 57 58 | 59 60 62 64 65 67 | 68 69 16 vpD ASI0|-BE2 -SP -CS5 -es2 -CS$1 -AS RD/-WR-BGNT -RDY -RST| DO VDD vss Oo Oo 0 0 0 0 0 Oo 0;0 86 1 2 3 4 5 6 7 8 9 10 11 12 | 13 14 15 MB86930 179 PGA Pin Assignment (Top View)(oo) MB86930 FUJITSU BLOCK DIAGRAM a ee CLOCK I GENERATOR CLK_OUT ~ EMULATOR BUS DRAM deere ie CONTROL 4 ) CONTROLLER | [* PWG CHIP_SEL << |76-BIT TIMER SAME_PAGE ~+_J [appress REFRESH <|_ DECODE e SPARC INTEGER UNIT Z f cata > S BUS o INTERFACE D> ADDRESS UNIT oO 2 a iu a 2K INSTRUCTION 2K DATA CACHE CACHECc MB86930 FUJITSU SIGNAL DESCRIPTIONS SYMBOL TYPE DESCRIPTION RESET I SYSTEM RESET: Asserting reset for at least 4 processor cycles after the clock has A(L) stabilized, causes the MB86930 to be initialized. XTAL1, vo EXTERNAL OSCILLATOR: The crystal inputs determine execution rate and timing of the (CLK_IN) oO MB86930 processor. Connecting a crystal to these pins forms a complete crystal oscillator XTAL2 G(Q) | circuit. The crystal oscillator frequency is the same as the processor operating frequency. 1(Q) When driving the processor with an external clock, XTAL2 pin should be left floating. CLKOUT1 oO CLOCK OUTPUT 1: This is an output signal against which MB86930 bus transactions can G(Q) | bereferenced. The CLKOUT1 frequency is the same as the frequency applied to XTAL1 and 1(Q) is the same as the processor operating frequency. CLKOUT1 is in phase with CLK_IN. CLKOUT2 oO CLOCK OUTPUT 2: This is an output signal against which MB86930 bus transactions can G(Q) | bereferenced. The CLKOUT2 frequency is the same as the frequency applied to XTAL1 and 1(Q) is the same as the processor operating frequency. CLKOUT2 is out of phase with CLK_IN. -LOCK oO BUS LOCK: Thisis a control signal asserted by the processor to indicate to the system that S (L) the current bus transaction requires more than one transfer on the bus. The Atomic Load G (2) Store instruction for example requires contiguous bus transactions which cause the 1(1) assertionof the bus lock signal. The bus may not be granted to another bus owner as long as -LOCK is active. -LOCK is asserted with the assertion of -AS and remains active until -READY is asserted at the end of the locked transaction. -BREQ I BUS REQUEST: Asserted by another device on the bus toindicate thatitwants ownership of S$ (L) the bus. The request must be answered with a bus grant (-BGRNT) from the MB86930 beforethe device can proceed by driving the bus. Once the bus has been granted, the device has ownership of the bus until itdeasserts -BREQ. The user should ensure that devices on the bus cannot monopolize the bus to the exclusion of the CPU. Inputs to -BREQ while -RESET is active are valid and cause Bus Grant to be asserted. -BGRNT oO BUS GRANT: Asserted by the CPU in response to a request from a device wanting $ (L) ownership of the bus. The CPU grants the bus to other devices only after all transfers forthe G (0) current transaction are completed. See the "Note section at the end of this table and the 1 (Q) Type column for other signals to determine the effect due to the assertion of -BGRNT. -ERROR oO ERROR SIGNAL: Asserted by the CPU to indicate that it has halted in an error state as a A(L) resultof encountering a synchronous trap while traps are disabled. In this situation the CPU G(Q) | saves the PC and nPC registers, sets the tt value in the TBR, enters into an error state and 1(Q) asserts the -ERROR signal. The system can monitor the -ERROR pin and initiate a reset under the error condition. This pin is high on reset. -MEXC | MEMORY EXCEPTION: Asserted by the memory system to indicate a memory error on $ (L) eithera data orinstruction access. Assertion of this signal initiates either a data or instruction access exception trap in the IU. The current bus access is invalidated by asserting the -MEXC in the same cycle as the -READY signal. Assertion in any other bus cycle gives indeterminateresults. The IU ignores the contents of the data bus in cycles where -MEXCis asserted. IRL <3:0> I INTERRUPT REQUEST BUS: The value on these pins defines the external interruptlevel. S$ (L) IRL < 3:0>=1111 forces a nonmaskable interrupt. IRL value of 0000 indicates no pending interrupts. All other values indicate maskable interrupts as enabled in the PIL field of the processor status register (PSR ). Interrupts should be latched and prioritized by external logicand shouldbe held pending until acknowledged by the processor. Aninterruptcontroller is available on the MB86940. 1. In the following descriptions, signal names preceded by a minus sign (-) indicate an active low state. Dual function pins have two names separated by a slash (/).MB86930 o) FUJITSU SIGNAL DESCRIPTIONS (Continued) 1(4) SYMBOL TYPE DESCRIPTION -TIMER_OVF Oo TIMER UNDERFLOW: Asserted by the processor to indicate that the internal 16bit timer $ (L) has underflowed. This signal can be used to initiate a DRAM refresh cycle or a one cycle G (Q) periodic waveform. On reset, the timer is turned off and -TIMER_OVF is high. 1(Q) SAME_PAGE oO SAME-PAGE DETECT: The -SAME_PAGE is used to take advantage of fast consecutive $ (L) accesses within Fast Page Mode DRAM page boundaries. This signal is an output asserted G (1) by the processor when the current address is within the same page as the previous memory 1(1) access. The -SAME_PAGE signal is asserted with -AS and remains active for one processor cycle. -SAME_PAGE is never asserted in the first transaction following a transaction by another device on the bus. The page size is specified by writing the SAME-PAGE MASK register. CS0,-CS1, oO CHIP SELECTS: These outputs are asserted when the value on the address bus matches CS2,-CS3, S$ (L) theaddress rangeinone of the corresponding ADDRESS RANGE registers. The signals are -CS4,-CS5 G (1) used to decode the current address into one of six address ranges. Address ranges should 1 (1) not overlap. Each address range has a corresponding wait specifier which is used to automatically assert the -READY signal after a user defined number of processor clock cycles. This allows a variety of memory and I/O devices with different access times to be connected to the MB86930 without the need for additional logic. ADR <31:2> oO ADDRESS BUS: The 30-bit ADDRESS BUS (A31-A2) is an output which identifies the data (L) or instruction address of a 32-bit word. Reads are always one word in size while byte, G (Z) half-word, or word transaction sizes for writes is identified by separate byteenable signals 1(1) (-BEO-3). The address bus is valid for the duration of the bus transaction. ASI <7:0> O ADDRESS SPACE IDENTIFIERS: The ADDRESS SPACE IDENTIFIERS are outputs $ (L) which indicate to which of 256 available spaces the current ADDRESS BUS value G (2) corresponds. The AS] values are defined as follows: ASI <7:0> ADDRESS SPACE 0x1 Control Registers 0x2 Instruction Cache Lock 0x3 Data Cache Lock 0x4-0x7 | ApplicationDefinable 0x8 User Instruction Space Ox9 Supervisor Instruction Space OxA User Data Space OxB Supervisor Data Space OxC Instruction Cache Tag RAM OxD instruction Cache Data RAM OxE Data Cache Tag RAM OxF Data Cache Data RAM 0x10-OxFD | ApplicationDefinable OxFE OxFF | Reserved for Debug Hardware The ASI values specified as application definable can be used by supervisor mode instructions such as Load Alternate and Store Alternate. The ASI value is available in the same cycle in which the corresponding address value is asserted on the address bus. The ASI pins are valid for the duration of the bus transaction. ASI values 0x8, 0x9, OxA, and 0xB are cacheable.MB86930 FUJITSU SIGNAL DESCRIPTIONS (Continued) SYMBOL TYPE DESCRIPTION BE30 0 S (L) G (2) 1(0) BYTE ENABLES: These pins indicate whether the current store transaction is a byte, half-word or word transaction. -BE3-0 signals are available in the same cycle in which the corresponding address value is asserted on the address bus and is valid for the duration of the bus transaction. This bus should be used only to qualify store transactions. For load transactions all sub-word requests are read (and replaced in the cache) as words and then the appropriate byte or half-word is extracted by the integer unit. Possible values for -BE30 are as follows: Byte 0 Byte 2 veo 1g 7 g Byte 3 Byte 1 av 23 vi 16 7 0 11170]/1101/1011/01114 1100 0ooi11 Byte Writes Half-Word Word Writes 0000 D <31:0> Vo S (L) G (2) | (2) DATA BUS: The bus interface has 32 bidirectional data pins (D31D0) to transfer data in thirty-two bit quantities. D(31) corresponds to the most significant bit of the least significant byte of the 32-bit word. A double wordis aligned on an 8byte boundary, a wordis alignedon a4~byte boundary, and a half-word is aligned on a 2byte boundary. If aload or store of any of these quantities is not properly aligned, a Not Aligned Trap will occur in the processor. Inwrite bus cycles, the point at which data is driven onto the bus depends on the type of the preceding cycle. If the preceding cycle was a write, data is driven in the cycle immediately followingthe cycle in which-READY was asserted. If the preceding cycle was a read, datais drivenone cycle after the cycle in which -READY was asserted to minimize bus contention between the processor and the system. All bits of the data bus are driven regardless of word size. The values on the pins not corresponding to the byte or half-word being written are undefined. S (L) G (2) (1) ADDRESS STROBE: A control signal asserted by the MB86930 or other bus master to indicatethe start of anew bus transaction. Abus transaction begins with the assertion of -AS and ends with the assertion of -READY. AS remains asserted for 1 clock cycle. During cycles in which neither the processor nor another bus masteris driving the bus the busisidle, andAS remains deasserted. RD/-WR S (L) G(2) 1 (1) READ/BUS TRANSACTION: This signa! specifies whether the current bus transaction isa read or a write operation. When AS is asserted and RD/-WR is low, then the current transactionis awrite. With-AS asserted and RD/-WR high, the currenttransactionis aread. RD/-WR remains active for the duration of the bus transaction and is deasserted with the assertion of -READY. -READY | S (L) READY: This is a control signal asserted by the external memory system to indicate that the current bus transaction is being completed and that it is ready to start with the next bus transaction in the following cycle. In case of a fetch from memory, the processor will strobe the value on the data bus at the rising edge of CLK_IN following the assertion of -READY. Forthe case of awrite, the memory systemwill assert-READY when the appropriate access time has been met. In most cases, no additional logic is required to generate the -READY signal. On-chip circuitry can be programmed to assert -READY based on the address of the current transaction. The external system can override the internal ready generator to terminate the current bus cycle early. Up to 6 address ranges each with different transaction times can be programmed. CLK_ECB EXTERNAL CLOCK BYPASS: Tying this signal high causes the CLK_IN signal to bypass the Phases Lock Loop (PLL). This signal is used for testing of the chip. EMU_SD <3:0> VO EMULATOR STATUS/DATA BITS: Bi-directional pins used by a hardware emulator to control and monitor MB86930 execution. These pins should be left unconnected.oO FUJITSU MB86930 SIGNAL DESCRIPTIONS (Continued) SYMBOL TYPE DESCRIPTION EMU_D <3:0> Vo EMULATOR DATA BITS: Bi-directional pins used by a hardware emulator to control and monitor MB86930 execution. These pins should be left unconnected. -EMU_BRK I EMULATOR BREAK REQUEST LINE: Inputused by ahardware emulator to requesta trap when emulation is enabled. This pin should be left unconnected. -EMU_ENB I EMULATOR ENABLE: Tied low while the MB86930 is being reset to enable hardware emulator mode on the chip. This pin should be left unconnected. TCK | TEST CLOCK: JTAG compatible test clock input. TMS | TEST MODE: JTAG compatible test mode select pin. TDI | TEST DATA IN: JTAG compatible test data input. TDO oO TEST DATA OUT: JTAG compatible test data output. -TRST | TEST RESET: Asynchronous reset for JTAG logic. If not using JTAG, this signal must be pulled low. NOTE: | = Input Only Pin G(...) = While the bus is granted to another | (...) = While the bus is between bus O = Output Only Pin bus master (-BGRNT=asserted), the pir cycles (or being reset) and is not VO = Either Input or Output Pin is granted to another bus master, the = Pins must be ted as described G (1) is driven to Voc pin is = Pins "must be" connected as descr! G (0) is driven to Vsg 1 (1) is driven to Vec A(L)= Asynchronous: Inputs may be G (Z) floats 1 (0) is driven to Vssg asynchronous to CLKOUT. G(Q ) is a valid output 1(Z) floats S(L)= Synchronous: Inputs must meet setup 1(Q) is a valid output and hold times relative to CLK_IN Outputs are Synchronous to CLK_INMB86930 The Fujitsu MB86930 is a high-performance, 32-bit RISC processor which executes at 40 MIPs peak and 37 MIPs sustained performance with 40 MHz clock frequency. It is a fourth generation version of Fujitsus popular MB86900, MB86901 and MB86902 proces- sors. Like its predecessors, the MB86930 is based on the SPARC architecture and is upward code compatible with previous implementations. Most importantly, the MB86930 has been developed specifically with the needs of embedded applications in mind and offers high performance and high integration for these applications. The MB86930 instruction set is streamlined and hardwired for fast execution with most instructions executingina single cycle. The Integer Unit (IU) features a5-stage pipeline which has been designed to handledata interlocks, has an optimized branch handler for efficient control transfers, and a bus interface to handle single cycle bus accesses to on-chip memory. An internal register file consisting of 136 registers organized into eight overlapping windows speeds interruptresponse time and context switches. The register file minimizes accesses to memory during procedure linkages and facilitates passing of parameters and assignment of variables. On-chip 2 Kbyte data and instruction caches have been added to decouple the processor from external memory. These caches have been designed with maximum flexibility in mind and allow entries to be locked to improve overall system performance. Separate 32-bit on-chip instruction and data paths provide a high bandwidth interface between the IU and on-chip cache. These buses support single cycle instructionexecution as well as single cycle data transfers with the cache. Future expansion of the MB86930 design is supported by this bus definition as well. The MB86930 also includes hardware for integer multiply and divide. The hardware support significantly improves the performance of these operations with 32-bit integer multiplies executing in 5 clock cycles, 16-bit integer multiplies in 3 cycles, 8bit integer multiplies in 2 cycles, and a multiply by zero can complete in a single cycle. o) FUJITSU KEY FEATURES Fast Instruction Execution: Simple functions make up the bulk of instructions in most programs so that execution speed can be greatly improved by designing these instructions to execute in as short atime as possible. The majority of instructions execute in one cycle with only a few of the more complex, such as integer multiply, taking additional cycles. Large Register Set: The large register set reduces the number of required accesses to data memory. The registers are organized in overlapping groups called register windows which allows registers to be reserved for high priority tasks, such as interrupts, or for recurring requirementssuch as operating system working registers. The overlapping windows also simplify parameter passing during procedure linkage and reduce code in most programs. On-Chip Caches: To decouple the speed of the processor from the memory sub-system, data and instructions caches have been added. The caches are organized as two-way set-associative for improved hit rates. In addition, the setassociative caches allow entries to be locked, individually or as a bank, without significantly degrading the cache performance. . Cache Locking: Both data and instruction entries can be locked into their respective caches toensuredeterministic response and highest performance for critical or frequently recurring routines. Maximum flexibility has been designed into the cache to allow all or selected portions to be locked. Bus Interface: The requirement for glue logic between the MB86930 and the system is minimized by providing programmable chip selects, programmable wait-state circuitry, and support for connection to fast page-mode DRAM. Multiple bus masters are supported through a simple handshake protocol. Clock Generator: To simplify the clock design a crystal can be connected directly to the on-chip oscillator or an external clock source can be used. A built in phase-locked loop minimizes the skew between on and off-chip clocks. Enhanced Instruction Set: The MB86930 incorporates afast integer multiply instruction which executes ina fast , 3 or 2 cycles for 32-bit, 16-bit or 8bit multiplicands. An integer dividestep instruction cuts divide times by a factor of 10 over previous SPARC implementations. A scan instruction supports a single cycle search for the most significant 1 or 0 in a word.MB86930 Fully Static Circuit Design: Embedded applications that need a means to reduce power consumption can take advantage of the MB86930s fully static design. The processor clock can be slowed or stopped for arbitrary periods of time to reduce operating current with no loss of internal state. Noise immunity is improved as well. (Note: stopping the clock will result in the Phase-Lock Loop losing lock. Lock must be re-established before normal operation can be resumed.) Test and Debug Interface: The MB86930 supports production test through industry standard JTAG boundary scan. Hardware emulation is supported with on-chip breakpoint and single step logic. A dedicated emulator bus provides a means to trace transactions between the integer unit and on-chip cache. TABLE 1. MB86930 Instruction Set _ PP FUJITSU CPU The MB86930 core is a high performance full custom implementation of the SPARC architecture. The core is compact to leave room for peripheral integration and yet is designed in a way to allow the major blocks to be customized for varying application requirements. The core is made up of three functional units: the Instruction block, the Address block and the Execute block (see Figure 1). A five stage instruction pipeline is responsible for decoding all instructions and generating the control signals to the other blocks. The 5-stage pipeline consists of Fetch (F), Decode (D), Execute (E), Memory (M) and Writeback (W). Instruction memory is addressed and returns instructions in the (F) stage, the register file is addressed and returns operands in the (D) stage, the ALU computes results in the (E) stage, external memory is addressed in the (M) stage, and the register file is written back in the (W) stage. LOGICAL ARITHMETIC/SHIFT DATA MOVEMENT CONDITION CODES UNCHANGED CONDITION CODES UNCHANGED TO USER/SUPERVISOR SPACE SIGNED ADD LOAD BYTE OR SUBTRACT LOAD HALF-WORD XOR MULTIPLY (SIGNED/UNSIGNED) LOAD WORD AND SCAN LOAD DOUBLE WORD NOT SETHI STORE BYTE OR NOT SHIFT LEFT LOGICAL STORE HALF-WORD XNOR SHIFT RIGHT LOGICAL STORE WORD SHIFT RIGHT ARITHMETIC STORE DOUBLE WORD CONDITION CODES SET CONDITION CODES SET TO USER SPACE UNSIGNED AND LOAD BYTE OR SUBTRACT LOAD HALF-WORD ANONOT MOUMMULIIPLY STEP TO ALTERNATE SPACE SIGNED OR NOT DIVIDE STEP LOAD BYTE Nor LORDHAL Won EXTENDED AND CONDITION CODES CONTROL TRANSFER UNCHANGED LOAD DOUBLE WORD ADD TORE BYTE CONDITIONAL BRANCH SUBTRACT STORE HALF-WORD CONDITIONAL TRAP STORE WORD CALL EXTENDED AND CONDITION CODES STORE DOUBLEWORD RETURN SET SAVE ADD TO ALTERNATE SPACE UNSIGNED RESTORE SUBTRACT LOAD BYTE JUMP AND LINK TAGGED AND CONDITION CODES SET LOAD HALF-WORD (WITH AND WITHOUT OVERFLOW) | aTOMIC OPERATION IN USER SPACE SUBTRACT SWAP WORD LOAD/STORE UNSIGNED BYTE READ/WRITE CONTROL REGISTER ATOMIC OPERATION IN READ PSR READ WIM RDASR ALTERNATE SPACE WRITE PSR WRITE WIM WRASR SWAP WORD READ TBR READ Y LOAD/STORE UNSIGNED BYTE WRITE TBR WRITE YMB86930 ADDRESS SPACE The MB86930 offers a large addressing range and allows separate user and supervisor spaces to be defined. In addition to 32 address lines, 4 alternate address space identifiers (ASIs) distinguish between protected and unprotected space. Of the 256 possible ASI values, two define accesses to user data and user instruction space while the remaining ASI values define supervisor space. Anytime a reset, synchronous trap or asynchronous trap occurs, the processor is placed into the supervisor mode. In this mode, the processor executes instructions and moves data out of supervisor space. While in supervisor mode, the processor also has access to the remaining ASI values. Except for those mentioned and those reserved for control register space, the remaining ASI values can be used to access other alternate data spaces defined by the application. The distinction of user versus supervisor space allows the hardware to protect against accidental or unauthorized accessto system resources. Forreal time operating system (RTOS) development for example, the separate spaces Co FUJITSU provide a mechanism for effectively partitioning RTOS space from user space. REGISTERS The MB86930 register set is divided into those used for general purpose functions and those used for control and status. The 136 general purpose registers are divided into 8 global registers and 8 overlapping blocks or windows. Each window contains 24 registers. Of these, 8 are local to the window, 8 out registers overlap with the next window and 8 in registers overlap with the previous window (see Figure 2). This organization makes it easy to pass parameters to subroutines. Parameters that are to be passed along are written to the out registers and the subsequent procedure call decrements the window pointer to make a new set of registers available. The passed parameters are now available to the subroutine in the current window s in registers. {DATA 1ADDRESS ADDRESS BLOCK Figure-1. MB86930 Integer Unit Data Path REGISTER FILE DADDRESS DDATAMB86930 Register windows improve performance in embedded applications because they function as local variable caches which retain either interrupt, subroutine, context or operating system variables with no additional overhead. In addition, code can be reduced by exploiting the efficient execution of procedure linkage by preventing in-lining compiler optimizations. The registers that make up the register fileeach havethree read-only and one writeonly port. The use of a four port register file allows even store instructions, which may require that three operands be read out of the register file, to proceed at one instruction per cycle. The control and status registers include those defined by the SPARC architecture (see Table 1) and those mapped into alternate address space to control peripheral functions (see Table 2). INSTRUCTION SET The MB86930 is upward code compatible with other SPARC processors. Additional instructions, previously not directly supported, have been added to improve performancein embedded applications. Integer multiply, integer divide step, and scan for first changed bit have been added to the already powerful SPARC instruction set. See Table | for a list of supported instructions. CURRENT WINDOW Figure 2. General Purpose Register Organization co FUJITSU INTERRUPTS A key measure of a processors suitability for use in embedded application is in its ability to handle interrupts with a minimum of delay and in a deterministic fashion. The MB86930 implementation has been tailored to insure not only low average latency but low maximum latency as well. Interruptresponse time is made up of the sum of the times it takes the processor to finish its current task after recognizing an interrupt, and the time it takes to begin executing interrupt service routine instructions. The MB86930 implements numerous features to minimize both factors. To minimize the time it takes to finish the currenttask, the MB86930 is designed so that tasks can either be interrupted or completed in a minimum of cycles. Implementation details that accomplish this aim include cacheline misses that are filled one word at atime through a prefetch buffer, integer divide that is interruptible through the use of a divide step instruction, fast multiply and a 1 word write buffer to limit pending bus transactions. To minimize the time required to start executing the interrupt service routine the processor switches to anew register window when an interrupt is detected. This feature allows the service routine to be executed without firstrequiring that the current registers be saved. The user can also elect to lock the service routine into the cache. This makes the routine available for immediate access. The on-chip data cache can also serve the service routine as a fast local stack for minimum delay in accessing routine variables. The MB86930 provides for up to 15 different interrupt levelsand direct support for 15 separate interrupt sources. The highest interrupt level is nonmaskable. CACHE The MB86930 has separate on-chip data and instruction caches. This allows the user to build a high performance system without incurring the cost of requiring fast external memory and the associated control logic. The data and instruction caches are each organized as two banks of sixty-four 16byte lines (see Figure 4). The lines are organized as twoway setassociative for good performance even when cache locking is in effect. Lines are divided into four sub-blocks each four bytes wide. On a cache miss, the cache is updated in sub-block increments for efficient refill of typical code segments and to avoid interrupt latency incurred by long cache line replacements. An instruction prefetch buffer fetches the next sequential instruction anticipating that it will be needed to fill the next instruction cache miss.MB86930 The caches can be used in either normal or one of two lock modes. In normal mode, the caches use an LRU (least recently used) algorithm to replace one of the two appropriate entries. Alternately, the two locking modes allow the entire cache or just selected entries to be locked. The lock modes allow time critical routines to be locked in cache. Global locking allows the entire content of either the instruction or data cache to be frozen. Two control bits in the cache control register enable or disable locking for either cache. With the entire cache locked, no valid entry can be replaced. To insure best possible performance however, invalid entries will be updated if they are accessed. This is done automatically and incurs no time penalty. Local cache locking makes it possible to dynamically lock selected instructions or data entries into the appropriate cache. This feature gives the flexibility, for example, to assure deterministic response for certain critical interrupt routines by locking the routines code into the cache. Entries can also be locked where it is desirable to give performance priority to certain often used routines which might otherwise be removed from cache. The 2way setassociativity allows the cache to perform effectively even with some locked entries. In local lock mode, each entry can either be locked individually by software or automatically with hardware assist.For individual locking, software writes the lock bit in the appropriate cache tag line. For automatic locking, a bit in each cache control register enables or disables the feature. The enable bit is set at the beginning of a routine for which the entries are to be locked. This causes the location of any cache access occurring while the bit is enabled to be locked into the cache. In addition to requiring just one initial cycle to enable, automatic entry locking incurs no overhead while in effect. In unlocked operation, the data cache uses a write- through update policy and allocates acache entry only on a load. Writes are buffered so that the processor can continue executing while datais written back to memory. In contrast, writes to locked data cache locations are not written through to main memory. Besides reducing external bus activity, this design supports configuring a portion of data cache as on-chip RAM which does not map to external memory. The data and instruction caches are designed to be accessed independently over separate data and instruc- tion buses to allow data to be loaded from and stored to cache at peak rates of 1 CPI. FUJITSU BUS INTERFACE The Bus Interface Unit (BIU) is designed to simplify the interface between the MB86930 and the rest of the system. Separate address and data buses make it easy to build fast systems. At the same time, on-chip circuitry allows these systems to be built with a minimum of external hardware. The bus interface supports fully programmable wait state generation, address decoding with chip select outputs, same page detection to support pagemode DRAM, and an autoreload timer to support a refresh counter. CLOCK GENERATOR The on-chip clock generator provides a means to directly connect the MB86930 to either a crystal oscillator or an external clock source. For either case, the external frequency is the same as the chip operating frequency. A clock output signal provides the system with a referenceby which external timing can be synchronized when not using an external clock source. The skew between the internal clock and an external input clock sourceis minimized by the inclusion of an on-chip phase lock loop circuit. a 10 6 10 | | T [TJ o e e eo @ e ry ee e e e ee e [ address tag [ vatid bits | | | 1 | 127 Tag Entry Format lock fru protection block _I sub-block 3 sub-block 2. sub-block 1 sub-block 0 RB eeean = 0 I CL Data Entry Format Figure 3. Instruction and Data Cache Organizationco MB86930 FUJITSU TABLE 1. MB86930 Control and Status registers (All registers are read/write) 31 28 27 24 23 20 19 12, (11 6 7 6 5 4 0 ice 0 0 0 0/0 0 1 0 reserved PIL nlz|[vle VS Conditions I n: (Negative=1, NonNegative=0) z: (Zero=1, NonZero=0) v: (Overflow=1, No Overflow=0) c: (Carry=1, No Carry=0) Processor Interrupt Level (Value 1-15, RST=Undefined) S MODE (Supervisor=1, User=0, RST=Undefined) Prior S Mode Enable Trap (Enable=1, Disable=0, RST=0 Current Window Pointer (Value=0-7, RST=Undefined) 31 8 7 6 5 43 2 1 90 reserved w7| w6] w5 | w4 | w3 | w2] wi | wo VS YY Window Invalid Mask (Invalid=1, Valid=0, RST=Undetined) 4 31 12 11 4 3 0 Trap Base Address Trap Type (RST=Undefined) (RST=0) NULL reserved Reserved (Must Write 0, RST=1) _] Reserved (Must Write 0, RST=1) Single Vector Trapping (Enabled=1, Disabled=0, RST=0)MB86930 oO FUJITSU TABLE 2. MB86930 Memory Mapped Control Registers (All registers are read/write) Cache/BIU Control 31 543210 ADDRESS reserved Ox 1 0x 0000 0000 " " Write Buffer Enable (Enabled=1, Disabied=0, RST=0 ) Prefetch Buffer Enable (Enabled=1, Disabled=0, RST=0 ) Data Cache Lock (Lock=1, Unlock=0, RST=0 ) Data Cache Enable (Enabled=1, Disabled=0, RST=0 ) instruction Cache Lock (Lock=1, Uniock=0, RST=0 ) Instruction Cache Enable (Enabled=1, Disabled=0, RST=0 ) Lock Control a1 10 ADDRESS reserved 0x 0000 0004 Data Cache Entry Auto Lock (On=1, Off=0, RST=0 ) Instruction Cache Entry Auto Lock (On=1, Off=0, RST=0 ) Lock Control Save: at i Teserved Previous Instruction Cache Auto Lock (Off=0, On=1, RST=0 ) id Previous Data Cache Auto Lock (Off=0, On=1, RST=0 ) 31 0 reserved Auto Lock Failed (False=0, True=1, RST=0 ) ed 31 0 Ox 1 0x 0000 0010 : | Restore Lock Control Register (Restore=1, Ignore=0, RST=0 ) 31 6543210 reserved Ox 1 Ox 0000 0080 Same Page Enable (Enabled=1, Disabled=0, RST=0 ) | g Chip Select Enable (Enabled=1, Disabled=0, RST=0 } " & Programmable Wait-State (Enabled=1, Disabied=0, RST=1) 8 Timer On/Ott (Enabled=1, Disabled=0, RST=0 ) 31 30 23 22 10 ASI Mask Address Mask [Care=0, Don't Care=1, RST=0 [Care=0, Don't Care=1, RST=0]aese20 FUJITSU 1 Address Range 31 30 23 22 10 ASL : "ADDRESS ASI < 7:0> ADR < 31:10> (RST=Undefined) (RST=Undetined) c 0000 0124 0x1 Sep on ocoo oto NOTE: CSO is hardwired to ASI=0x9 ADR < 31:10> = <0..0> CS3 0x 0000 012C CS4 0x 0000 0130 C85 _0x 0000 0134 Address Mask 3130 2322 10 Ast | ADDRESS AS! Mask ADR <31:10> Mask _ (o-Ba =Gare. |=Dont a (0=Care, 1=Don't Care, AST=Undefined) c 0000 0140 Ox 1 Ges m 0000 ota NOTE: CSO is hardwired to ASI=0x9; At Reset, ADR < 31:15> = 0, ADR < 14:10> = 1 CS2 0x 0000 0148 CS3 0x 0000 014C CS4 0x 0000 0150 CS5 0x 0000 0154 Wait State Specifier _ 31 27 2625 24 23 22 2120 19 18 1413 98765 0 ( : yp Count! Count 2 Count Gount2 ASI ___ADORESS (HS 1=Undetined) | (RST=Undetined) (RST=Undefined) | (AST=Undefined) reserved 0x1 | CS1,cS0 ox 0000 a160 : = - Cer Sse 050000 0164] Wait Enable (On=1, Off=0, AST= 0 ) | J CS5,CS4 0x 0000 0168] Single Cycle (On=1, Off=0, RST=0 } Override (On=1, Off=0, RST=0 ) (CSO: RST=1 ) Timer mE 31 1615 0 ast ot ADDRESS Timer Value : reserved (RST=Undefined) Ox 1 Ox 0000 0174 . _Timer Pre-Load . 31 1615 9 ASI ADDRESS Timer Pre-Load Value : reserved (AST=Undefined) Ox 1 0x 0000 0178 Instruction Ta Lock Bits at 0 ASL doe AODRESS : reserved Ox 2 | Bank 1 0x 0000 0000 by 4 Entry Lock (Locked=1, Unlocked=0, RST=Undetined) Ox 0000 0400 Bank 2 Ox 8000 0000 by4 Ox 8000 0400 Data Tag Lock Bite : 31 a ast | ADDRESS | reserved 0x3. | Bank 1 0x 0000 0000 ] v by 4 Entry Lock (Locked=1, Unlocked=0, RST=Undefined) Ox 0000 0400 Bank 2 0x 8000 0000 y by4 Ox 8000 0400 1. This register is Write Onlyoe MB86930 FUJITSU TABLE 2. MB86930 Memory Mapped Control Registers (Continued) Instruction Cache Tag 31 10 9 6 5 4 210 __ADDRESS ADDRESS TAG [AST=Undefined] OxC | Bank 1 0x 0000 0000 I v by 4 Sub Block Valid (Valid=1, Invalid=0, RST=Undefined) Ox 0000 0400 User/Supervisor (User=0, Supervisor=1, RST=Undefined) Bank 2 0x 8000 0000 Least Recently Used (RST=Undefined) v by 4 Entry Lock (Locked=1, Uniocked=0, RST=Undefined) Ox 8000 0400 Data Cache Tag 31 10 9 6 5 4 210 ADDRESS | Ox E | Bank 1 0x 0000 0000 _] v by 4 Sub Block Valid (Valid=1, invalid=0, RST=Undefined) Ox 0000 0400 User/Supervisor (User=0, Supervisor=1, RST=Undefined) Bank 2 0x 8000 0000 Least Recently Used (RST=Undefined) by4 Entry Lock (Locked=1, Unlocked=0, RST=Undefined) Ox 8000 0400 ADDRESS TAG [AST=Undefined] Instruction Cache Data 31 3 TADORESS_| ADDRESS TAG [AST=Undefined] 0oxD Bank 1 Ox 0000 0000 by 1 word Ox 0000 0400 Bank 2 Ox 8000 0000 by 1 word Ox 8000 0400 ironsepetes 31 0 ADDRESS TAG [RST=Undefined] Ox 0000 0000 by 1 word Ox 0000 0400 Bank 2 0x 8000 0000 y by 1 word Ox 8000 0400 Bank 1MB86930 The Bus Interface Unit (BIU) has the logic which allows the MB86930 to interface with the system. The system interface is made up of the address and data buses, the interrupt request bus and various control signals. The BIU is either handling requests for external memory operations, arbitrating for bus access, or idle. Operation of the BIU The BIU receives requests for external memory operations from the Cache Control Logic (CCL). In the caseof reads from external memory, it performs the read operation and returns the data to the Cache and IU. A parallelpath is used to make the data available to the IU in the same cycle that it is written to the cache. Inthe case of a write to external memory, the BIU makes use of a write buffer which can hold a one word write transaction. When the BIU receives a request for a write transactionit stores the write data and address in the write buffer allowing the IU to continue operating out of on-chip cache and/or its register file. The BIU then proceeds to complete the write to external memory. In most cases the write buffer will hide external memory latency fromthe IU. Theexceptions are in cases where the write buffer is still filled from a previous transaction or if the subsequent IU cycle results in an instruction cache miss. In these cases, IU execution is held until the write buffer is emptied. The BIU includes a one stage prefetch buffer for instruction fetches. This buffer is used to fetch the next sequentialinstruction after an instruction cache miss. The instruction is prefetched only if the BIU does not have a request for a bus transaction from the IU nor is any external device requesting use of the bus. The prefetch buffer operation is suspended if the buffer is full. This occurs if the prefetched instruction is a hit in the instruction cache. The buffer restarts after another instruction cache miss. If an exception occurs during an instruction prefetch, the exception is not sent to the IU unless the instruction is actually requested by the IU. The prefetch buffer operates only when the instruction cache is on. In any cycle the BIU can receive a request for accesses to either or both instruction and/or data memory. If it receivesa request for both in the same cycle, it completes the data memory transaction first. Exception Handling The external memory system can indicate an exception during a memory operation. The BIU signals the appropriate data or instruction exception to the IU which will trap accordingly. oO FUJITSU As mentioned above, the IU can continue operation after putting the data and address for a store in the write buffer. If anexceptionis detected while completing this buffered write,then the BIU indicates adata access exception tothe IU. Any system which needs to recover from this error should store the address and data of such write transactions in hardware. If the system can generate both read and write exceptions, then the system must also provide a status bit which indicates whether the exception was generatedona read or on a write transaction. With access to this informationthe data access exception service routine can determine the cause of the exception and recover accordingly. Bus Cycles Timings 1 through 9 illustrate representative combina- tions of bus cycles. Load Whenever an instruction fetch or a load from data memory has a miss in the cache, the BIU performs a read from external memory. A read transaction begins with the BIU asserting AS, to indicate a new bus transaction. The -AS signal is deasserted after one cycle. At the same time the ADR < 31:2> and ASI < 7:0> bits are driven with the location to be read. The BIU drives the RD/-WR signal high to indicate a read transaction. The external memory system responds with the read data on pins D < 31:0 >. It also asserts the -READY signal when the data is ready. For slow memory, the -READY signal can be delayed until data is valid. A load double operation is treated as back-to-back reads. Load with Exception If the external memory system sees a memory exception it can terminate the current memory transaction by asserting the -MEXC and-READY signals. The data on the data bus is ignored by the MB86930. Store A write transaction begins with the BIU assertingAS, to indicate a new bus transaction. The AS signal is de-asserted after one phase. At the same time the ADR < 31:2> and ASI < 7:0> pins are driven with the location to be written while the D < 31:0> pins has corresponding write data. The -BEOQ-3 pins indicate byte, half-word or word transaction width. The BIU drives the RD/-WR signal low to indicate a write transaction.MB86930 The external memory system responds by asserting the -READY signal when it has stored the data. A store double operation is treated as back-to-back writes. Store with Exception If an access exception occurs on a write, the external memory system can terminate the current memory transaction by asserting the -MEXC and -READY signals. The external memory system is expected to ignore the data on the data bus in this situation. Atomic Load Store An atomic load store executes as a load followed by a store with no operation allowed in between. The -LOCK oO FUJITSU signal is asserted to indicate that the bus is being used for more than one external memory operation. Thereis one cycle between the termination of the read and the beginning of the write to provide time for the switching of the data bus drivers. External Bus Request and Grant Any external device can request ownership of the bus by asserting the -BREQ signal. The BIU asserts the BGRNT signal to indicate that itis relinquishing control of the bus and also threestates all of its bus drivers. In the following cycle, the external device can complete its transaction. On completion of its transaction the external device deasserts the -BREQ signal. The BIU responds by de-asserting the -BGRNT signal in the following cycle. The MB86930 is the default owner of the bus. ' LOAD 1 CLKIN / LOAD 2 ' ADR < 31:2> ASI < 7:0> ~BE < 3:0> RD/-WR READY D <31:0> Timing 1. Typical Back-to-Back Loads (Same as Load Double)co MB86930 FUJITSU ADR < 31:2> ASI < 7:0> BE < 3:0> RD/-WR READY MEXC D<31:0> Timing 2. Load with Exception STORE 1 STORE 2 CLK_IN ADR < 31:2> ASI <7:0> | Al A2 BE < 3:0> RD/-WR ' ' ' : ' : ' -READY | \ \ ' / | \ \ D < 31:0> \ D1 x D2 Timing 3. Typical Back-toBack Stores (Same as Store Double)co waese20 FUJITSU ADR < 31:2> ASI < 7:0> -BE < 3:0> RD/-WR -READY -MEXC DBD <31:0> CLK_IN ADR < 31:2> ASI < 7:0> BE < 3:0> RD/-WR READY -LOCK D<31:0> Note: A load followed by a store requires an intervening clock cycle on the bus while a store followed by a load can occur in consecutive clock cycles. Timing 5. Atomic OperationoO MB86930 FUJITSU Processor Bus Cycle n Complete > Processor Bus Cycle n+1 Start > i 1 ' ' 1 , 1 1 ' i i) 1 CLK_IN i ' 1 ' t ' ' i) t ' t ' ' 1 ' 1 ' MN ' ' 1 1 ' / | 1 -BREQ 1 1 ' Ly 1 ' 1 i ' ' 1 ' ' ' ' ' ' 4 1 1 ' 1 1 ' ' ' i) -BGRNT | ; \ ; /} ' ' _____ ALL BUS DRIVERS THREE-STATE Timing 6. Bus Request and Grant CycleoO MB86930 FUJITSU ABSOLUTE MAXIMUM RATINGS! Symbol Rating Conditions Min. Max. Units Veco Supply voltage 0.3 6 Vv V; Inputvoltage 0.3 Voc + 0.3 Vv Ty Operatingjunction temperature 125 C Notes: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods may affect device reliability. Recommended Connections: 1. Power and ground connections must be made to multiple Vcc and Vss pins. Every MB86930 based circuit board should include power (Vcc) and ground (Vgs) planes for power distribution. Every Vcc pin must be connected to the power plane, and every Vss pin must be connected to the ground plane. Pins identified as N.C. must not be connected in the system. 2. Liberal decoupling capacitance should be placed near the MB86930. The processor can cause transient power surges when its numerous output buffers transition, particularly when connected to large capacitive loads. 3. Low inductance capacitors and interconnections are recommended for best high frequency electrical performance. Inductance can be reduced by shortening the board traces between the processor and decoupling capacitors as much as possible. Capacitors specifically designed for PGA and QFP packages will offer the lowest possible inductance. 4. For reliable operation, alternate bus masters must drive any pins that are three-stated by the MB86930 when it has granted the bus, in particular -LOCK, ADR < 31:2 >, ASI < 7:0 >, -BE0-3, D < 31:0 >, -AS, and RD/-WR must be driven by alternate bus masters. These pins are normally driven by the processor during active and idle bus states and dont require external pullups. N.C. pins must always remain unconnected. PACKAGE THERMAL CHARACTERISTICS Symbol Parameter Package Value Units Bjc Thermal resistance junction to | 208 Plastic QFP 5.0 case 208 Ceramic QFP 1.8 C/W 208 Ceramic QFP w/ Heat Sink 1.6 179 Ceramic PGA 8.0 Om/s 1m/s 3 m/s On Thermal resistance junction to | 208 Plastic QFP 25 22 19 ambient 208 Ceramic QFP 19 15 13 C/W 208 Ceramic QFP w/ Heat Sink 16 12 8 179 Ceramic PGA 25 19 13 Note: All numbers for package thermal characteristics assume multilayer PCB, except for the numbers for PGA package, which assume a single layer PCB.MB86930 DC SPECIFICATIONS 3 Voc = 5V + 5% CO FUJITSU Symbol! Parameter Conditions Min. Typ. Max. Units VIL Inputlow voltage 0 - 0.8 Vv Vin Input high voltage (All pins except XTAL1) 2.0 - Voc Vv Input high voltage (Pin XTAL1) 2.8 - Vec Vv VoL Output iow voltage lol =3.2mMA 0 - 0.45 Vv Vor Output high voltage lon =-0.4mA 2.4 - Vec Vv tut Input leakage current Vin =9or Vcc -10 - 10 pA ILz 3-state output leakage current Vout = 0 or Voc -10 - 10 pA loc Operating power supply current. Use Icc 20 MHz - 330 440 mA (typ) to calculate maximum case and ambienttemperature allowed. Ambient 30 MHz - 410 470 mA temperature of die is 125C. For example, allowed ambient temperature | 49 MHz - 460 570 mA = 125C. (Icc) @ (5.25V) Syja CeIn Pin capacitance (All pins except XTAL2) Vec=V,=0 - - 13 pF Pin capacitance (Pin XTAL2) f= 1 MHz - - 16 pF AC CHARACTERISTICS1 24 Vog = 5V + 5%, Ta 0-70C . 20 MHz 30 MHz 40 MHz . Symbol Parameter Description Min, Max. Min. Max. Min. Max. Units tl CLKIN period 50 100 100 25 100 ns t2 CLKIN high Time 10 6 ns 3 CLKIN low time 14 10 ns t4 CLKIN rise time 4 3 2 ns tS CLKIN fall time 4 3 ns t6 CLKIN to CLKOUT delay ) 8 8 0 ns t7 CLKIN to CLKOUT2 delay 7 25 33 17 25 13 20 ns t8 CLKOUT1, CLKOUT2 high time 0.35xPeriod 0.3xPeriod 0.25xPeriod ns t9 CLKOUT1, CLKOUT2 low time 0.4xPeriod 0.4xPeriod 0.4xPeriod ns t10 CLKOUT1, CLKOUT2 fall time? 3 3 3 ns t11 CLKOUT1, CLKOUT2 rise time? - 4 4 3 ns 12 D<31:0> Output valid delay 21 19 16 Output hold 2 2 ns ADR < 31:2> Output valid delay 24 23 20 Output hold 2 2 ns -BE0-3 Output valid delay 19 18 16 Outputhold 2 2 ns ASI < 7:0> Output valid delay 22 20 17 Outputhold. 2 2 ns t13 -CS Output valid delay 24 23 20 Output hold 2 2 ns t14 -SAME_PAGE Output valid delay 23 22 20 Output hold 2 2 nsMB86930 AC CHARACTERISTICS1:2:4 Veg = 5V + 5%, Ta 0-70C (Continued) Cc FUJITSU 20 MHz 30 MHz 40 MHz Symbol! Parameter Description Units Min. Max. Min. Max. Min. Max. t15 RD/-WR Output valid delay 18 17 15 Output hold 2 2 2 ns t16 LOCK Output valid delay 19 18 16 Output hold 2 2 2 ns 17 -AS Output valid delay 21 20 18 Output hold 2 2 2 ns t18 -TIMER_OVF Output valid delay 20 19 18 Outputhold 2 2 2 ns t19 -BGRNT Output valid delay 20 18 . 15 Output hold 2 2 2 ns t20 MEXC input setup time 14 12 12 ns t21 READY input setup time 15 14 12 ns t22 D <31:0> input setup time 1 10 9 ns t23 BREQ input setup time 8 7 6 ns 124 IRL <3:0> input setup time & 6 6 6 ns t25 MEXC input hold time 2 2 1 ns 126 READY input hoid time 2 2 1 ns 127 D <31:0> input hold time 3 3 2 ns t28 BREQ input hold time 3 3 2 ns t29 IRL < 3:0> input hold time 5 5 5 ns 1. Parameters are valid over specitied temperature range and supply voltage range unless otherwise noted. 2. All voltage measurements are referenced to ground. All time measurements are referenced at input and output levels of 1.5V. For testing, all inputs swing between 0.4V and 2.4V (Except XTAL1 which swings from 0.4V to 3.0V). Input rise and fall times are 2ns or less. PNOoaPo Not more than one output may be shorted at a time for a maximum duration of one second. Timing specifications apply to frequency of operation listed at top of column. All output timings are based on a 50pF load. The IRL input setup and hold times are measured with respect to the midpoint of the input clock cycle. These specs will be improved in the future. Data bus output driver control is same as for RD/-WR so timing is similar.oo MB86930 FUJITSU ' 4 CLK_IN 7, <_ 4 Cycle Minimum > ' RESET |\ ' / ' ' ' 7. i 3Cycles*2 > ' ' ' 1 ' ' ' \ T 7%- 7 T ADDR : ' : x \ 0x0000 0000 X 1. CLK_IN must be stable for at jeast 100s before RESET is deasserted. *2, When RESET hold time (3ns) is met. Timing 7. Reset Timing 2.8v 2%, if 2.8v CLK_IN ON oa ov 16v ' a Lo ~~ 16 tio + ne ' fl Bo 20 \. L 20 CLKOUT1 iF 15 NC av osy <8 __> <9 > <_ 17 ; 2.0V 2.0v CLKOUT2 oy ow #, 1.5 \. oev <_ 19 __ << 8 __>' a HO Note: CLKOUT1 and CLKOUT2 are derived from non-overlapping internal clocks, however, the relative timing of these signals is not tested. Timing 8. Clock TimingoC MB86930 FUJITSU CLK_IN 1.5v t12d | D <31:0>, ADDR < 31:2> -BE0-3, ASI < 7:0> {13d > CS0-5 > t14h -SAME_PAGE \ \ 15d > > t15h RD/-WR Tf ti6h ; \ \ \ 117d > tt7h ' -AS > t18h -TIMER_OVF ' > tt9h ' -BGRNT ,; 1 Note: d=delay, h=hold Timing 9. /O Output TimingMB86930 FUJITSU -MEXC -READY D < 31:0> -BREQ IRL< 31:0> CLK-IN / 1.5v 120 NOTE: 126 t28 FA d=delay, h=hold Timing 10. I/O Output Timing TCK TMS TDI TDO NOTE: These specifications are based on sample characterization and should be considered as typical values. Timing 11. JTAG TimingMB86930 208-LEAD FLAT PACKAGE (SQFP) Ordering Information: MB86930-20PF-G co FUJITSU 208-LEAD FLAT PACKAGE (SQFP) (28.00 + 0.10) -12 (3.85) MAX 0 (0} MIN STAND OFF | .004 (0.10) 1.004 (25.50) REF 1.185 NOM (29.60) : 002 (0.15 + 0,05) Dimensions in inches (milim eters) Detalts of A partMB86930 Ordering Info : MB86930-30ZF-G (w/o heatsink) : MB86930-40ZF-G (w/ heatsink) oO FUJITSU | 1.205 + 008SQ (30.60 + 0.20) 1.071 22 | (27.20 *383) oo0o0o000 0 o0o0o0o0o000 0 oooo0o0o0 0 oo0oo0o0o000 J | 386 (9.80) MAX. .20 (5.08) TYP. - 002 (0.50) MIN. (STAND OFF) [ = [ .945 TYP 1.165 + 0.10 (24.00) (29.60 + 0.25) Cc. Cc .006 + .002 = .008 + .004 (0.15 + 0.05) .020 + .008 (0.20 + 0.10) .071 + .008 (0.50 + 0.20) (1.80 + 0.20)co MB86930 FUJITSU 179-LEAD CERAMIC (METAL SEAL) PIN GRID ARRAY PACKAGE Ordering Information: MB86930-40CR-G 179-LEAD CERAMIC (METAL SEAL) PIN GRID ARRAY PACKAGE (Case No.: PGA-179C-A03) re orvcreree 0993093000008 = 25 0000080000000 = lS 000000080008 fae 15 209000080008 = i> S| [90000 p= 15 gf |eoee i= Os LO i} jeeee _= e000 p= Sl. e000 = 5 -| leeeoe = 8S 200000930 * 0299090088 000009000 990399000 .050 + .010 \inoex anes aie 1.800 + .020 SQ 240 M. 134.016 | -050 (1.27) TYP DIA. (38.10 + 0.51) (6.10) (8.40 = 0.40) Dimensions in inches (millimeters)Cc MB86930 FUJITSU SPARClite is a trademark of Fujitsu Microelectronics, Inc. SPARC is a registered trademark of SPARC International based on technology developed by Sun Microsystems, Inc. All rights reserved. This publication contains information considered proprietary by Fujitsu Limited and Fujitsu Microelectronics, Inc. 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