IRS2330DJTRPBF - International Rectifier

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IRS233(0,2)(D)(S&J)PbF

3-PHASE-BRIDGE DRIVER

Product Summary

Description Packages

The IRS233(0,2)(D)(S & J) is a high voltage, high speed

power MOSFET and IGBT driver with three independent high

and low side referenced output channels. Proprietary HVIC

technology enables ruggedized monolithic construction.

Logic inputs are compatible with CMOS or LSTTL outputs,

down to 3.3 V logic. A ground-referenced operational

amplifier provides analog feedback of bridge current via an

external current sense resistor. A current trip function which

terminates all six outputs is also derived from this resistor.

An open drain FAULT signal indicates if an over-current or

undervoltage shutdown has occurred. The output drivers

feature a high pulse current buffer stage designed for

minimum driver cross-conduction. Propagation delays are

matched to simplify use at high frequencies. The floating

channel can be used to drive N-channel power MOSFET

or IGBT in the high side configuration which operates up

to 600 volts.

Absolute Maximum Ratings

Features

•

Floating channel designed for bootstrap operation

Fully operational to +600 V

• Tolerant to negative transient voltage – dV/dt immune

•

Gate drive supply range from 10 V to 20 V

•

Undervoltage lockout for all channels

•

Over-current shutdown turns off all six drivers

•

Independent half-bridge drivers

•

Matched propagation delay for all channels

•

3.3 V logic compatible

•

Outputs out of phase with inputs

•

Cross-conduction prevention logic

•

Integrated Operational Amplifier

•

Integrated Bootstrap Diode function (IRS233(0,2)D)

•

RoHS Compliant

June 1 2011

IRS233(0,2)(D)(S & J)PbF

V

OFFSET

600V max.

I

O+/-

200 mA / 420 mA

V

OUT

10 V – 20 V (233(0,2)(D))

t

on/off

(typ.) 500 ns

Deadtime (typ.) 2.0 us (IRS2330(D))

0.7 us (IRS2332(D))

28-Lead SOIC

44-Lead PLCC w/o 12 Leads

Typical Connection

Applications:

*Motor Control

*Air Conditioners/ Washing Machines

*General Purpose Inverters

*

Micro/Mini Inverter Drives

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IRS233(0,2)(D)(S&J)PbF

Qualification Information

†

Industrial

††

Qualification Level Comments: This family of ICs has passed JEDEC’s

Industrial qualification. IR’s Consumer qualification level is

granted by extension of the higher Industrial level.

SOIC28W MSL3

†††

, 260°C

(per IPC/JEDEC J-STD-020)

Moisture Sensitivity Level

PLCC44 MSL3

†††

, 245°C

(per IPC/JEDEC J-STD-020)

Human Body Model Class 2

(per JEDEC standard JESD22-A114)

ESD

Machine Model Class B

(per EIA/JEDEC standard EIA/JESD22-A115)

IC Latch-Up Test Class I, Level A

(per JESD78)

RoHS Compliant Yes

† Qualification standards can be found at International Rectifier’s web site http://www.irf.com/

†† Higher qualification ratings may be available should the user have such requirements. Please contact your

International Rectifier sales representative for further information.

†††

Higher MSL ratings may be available for the specific package types listed here. Please contact your

International Rectifier sales representative for further information.

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IRS233(0,2)(D)(S&J)PbF

Absolute Maximum Ratings

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to V

SO

. The thermal resistance and power dissipation ratings are

measured under board mounted and still air conditions.

Symbol

Definition Min. Max. Units

V

B1,2,3

High-side floating supply voltage -0.3 620

V

S1,2,3

High-side floating offset voltage V

B1,2,3

- 20 V

B1,2,3

+ 0.3

V

HO1,2,3

High-side floating output Voltage V

S1,2,3

- 0.3 V

B1,2,3

+ 0.3

V

CC

Low-side and logic fixed supply voltage -0.3 20

V

SS

Logic ground V

CC

- 20 V

CC

+ 0.3

V

LO1,2,3

Low-side output voltage -0.3 V

CC

+ 0.3

V

IN

_______ ______

Logic input voltage ( HIN1,2,3, LIN1,2,3 & ITRIP)

V

SS

-0.3

(V

SS

+ 15) or

(V

CC

+ 0.3)

Whichever is

lower

V

FLT

FAULT output voltage V

SS

-0.3 V

CC

+0.3

V

CAO

Operational amplifier output voltage V

SS

-0.3 V

CC

+0.3

V

CA-

Operational amplifier inverting input voltage V

SS

-0.3 V

CC

+0.3

V

dV

S

/dt Allowable offset supply voltage transient — 50 V/ns

(28 lead SOIC) — 1.6

P

D

Package power dissipation @ TA ≤ +25 °C (44 lead PLCC) — 2.0

W

(28 lead SOIC) — 78

Rth

JA

Thermal resistance, junction to ambient (44 lead PLCC) — 63 °C/W

T

J

Junction temperature — 150

T

S

Storage temperature -55 150

T

L

Lead temperature (soldering, 10 seconds) — 300

°C

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IRS233(0,2)(D)(S&J)PbF

Recommended Operating Conditions

The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the

recommended conditions. All voltage parameters are absolute voltage referenced to V

SO.

The V

S

offset rating is

tested with all supplies biased at 15 V differential.

Note 1: Logic operational for V

S

of (V

SO

-8 V) to (V

SO

+600 V). Logic state held for V

S

of (V

SO

-8 V) to (V

SO

– V

BS

)

.

Note 2: Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer to

the Application Information section of this datasheet for more details.

Note 3: CAO input pin is internally clamped with a 5.2 V zener diode.

Dynamic Electrical Characteristics

V

BIAS

(V

CC

, V

BS1,2,3

) = 15 V, V

SO1,2,3

= V

SS

, C

L

= 1000 pF, T

A

= 25 °C

unless otherwise specified.

Symbol Definition Min

Typ

Max

Units

Test Conditions

t

on

Turn-on propagation delay 400 500 700

t

off

Turn-off propagation delay 400 500 700 V

S1,2,3

= 0 V to 600 V

t

r

Turn-on rise time — 80 125

t

f

Turn-off fall time — 35 55 V

S1,2,3

= 0 V

t

itrip

ITRIP to output shutdown propagation delay 400 660 920

t

bl

ITRIP blanking time — 400 —

t

flt

ITRIP to FAULT indication delay 350 550 870

t

flt, in

Input filter time (all six inputs) — 325 —

t

fltclr

LIN1,2,3 to FAULT clear time (2330/2) 5300

8500

13700

1300

2000

3100

DT Deadtime: (IRS2330(D))

(IRS2332(D)) 500 700 1100

— — 400

MDT Deadtime matching: : (IRS2330(D))

(IRS2332(D)) — — 140

V

IN

= 0 V & 5 V

without

external deadtime

MT Delay matching time (t

ON

, t

OFF

) — — 50

V

IN

= 0 V & 5 V

without

external deadtime

larger than DT

PM Pulse width distortion — — 75

ns

PM input 10

µs

NOTE: For high side PWM, HIN pulse width must be > 1.5 usec

Symbol

Definition Min. Max. Units

V

B1,2,3

High-side floating supply voltage V

S1,2,3

+10 V

S1,2,3

+20

V

S1,2,3

Static high-side floating offset voltage V

SO

-8 (Note1)

600

V

St1,2,3

Transient high-side floating offset voltage -50 (Note2) 600

V

HO1,2,3

High-side floating output voltage V

S1,2,3

V

B1,2,3

V

CC

Low-side and Logic fixed supply voltage 10 20

V

SS

Logic ground -5 5

V

LO1,2,3

Low-side output voltage 0 V

CC

V

IN

Logic input voltage (HIN1,2,3, LIN1,2,3 & ITRIP) V

SS

V

SS

+ 5

V

FLT

FAULT output voltage V

SS

V

CC

V

CAO

Operational amplifier output voltage V

SS

V

SS

+ 5

V

CA-

Operational amplifier inverting input voltage V

SS

V

SS

+ 5

V

T

A

Ambient temperature -40 125 °C

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IRS233(0,2)(D)(S&J)PbF

Dynamic Electrical Characteristics

V

BIAS

(V

CC

, V

BS1,2,3

) = 15 V, V

SO1,2,3

= V

SS

, C

L

= 1000 pF, T

A

= 25 °C

unless otherwise specified.

Symbol Definition Min

Typ

Max

Units

Test Conditions

SR+ Operational amplifier slew rate (+) 5 10 —

SR- Operational amplifier slew rate (-) 2.4 3.2 —

V/µs 1 V input step

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IRS233(0,2)(D)(S&J)PbF

Static Electrical Characteristics

V

BIAS

(V

CC

, V

BS1,2,3

) = 15 V, V

SO1,2,3

= V

SS

and T

A

= 25 °C unless otherwise specified. The V

IN,

V

TH

and I

IN

parameters

are referenced to V

SS

and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The V

O

and I

O

parameters

are referenced to V

SO1,2,3

and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.

Symbol Definition Min

Typ

Max

Units

Test Conditions

V

IH

Logic “0” input voltage (OUT = LO) — — 2.2

V

IL

Logic “1” input voltage (OUT = HI) 0.8 — —

V

IT,TH+

ITRIP input positive going threshold 400 490 580

V

OH

High level output voltage, V

BIAS

- V

O

— — 1000

V

IN

= 0 V, I

O

= 20 mA

V

OL

Low level output voltage, V

O

— — 400

mV

V

IN

= 5 V, I

O

= 20 mA

I

LK

Offset supply leakage current — — 50 V

B

=

V

S

= 600 V

I

QBS

Quiescent V

BS

supply current — 30 50 µA V

IN

= 0 V or 4 V

I

QCC

Quiescent V

CC

supply current — 4.0 6.2 mA V

IN

= 4 V

I

IN+

Logic “1” input bias current (OUT =HI) -400

-300

-100

V

IN

= 0 V

I

IN-

Logic “0” input bias current (OUT = LO) -300

-220

-100

V

IN

= 4 V

I

ITRIP+

“High” ITRIP bias current — 5 10

µA

ITRIP = 4 V

I

ITRIP-

“LOW” ITRIP bias current — — 30 nA ITRIP = 0 V

V

BSUV+

V

BS

supply undervoltage

positive going threshold 7.5 8.35

9.2

V

BSUV-

V

BS

supply undervoltage

negative going threshold 7.1 7.95

8.8

V

CCUV+

V

CC

supply undervoltage

positive going threshold 8.3 9 9.7

V

CCUV-

V

CC

supply undervoltage

negative going threshold 8 8.7 9.4

V

CCUVH

Hysteresis — 0.3 —

V

BSUVH

Hysteresis — 0.4 —

V

R

on, FLT

FAULT low on-resistance — 55 75 Ω

I

O+

Output high short circuit pulsed current — -250

-180

V

O

= 0 V, V

IN

= 0 V

PW ≤ 10 us

I

O-

Output low short circuit pulsed current 420 500 —

mA V

O

= 15 V, V

IN

= 5 V

PW ≤ 10 us

R

BS

Integrated bootstrap diode resistance — 200 — Ω

V

OS

Operational amplifier input offset voltage — — 20 mV V

SO

= 0.2 V

I

CA-

CA- input bias current — — 100 nA V

CA-

= 1 V

CMRR Operational amplifier common mode

rejection ratio — 80 — V

SO

= 0.1 V & 5 V

PSRR Operational amplifier power supply

rejection ratio — 75 —

dB V

SO

= 0.2 V

V

CC

= 9.7 V & 20 V

V

OH,AMP

Operational amplifier high level output

voltage 4.8 5.2 5.6 V V

CA-

= 0 V, V

SO

=1 V

V

OL,AMP

Operational amplifier low level output

voltage — — 40 mV V

CA-

= 1 V, V

SO

=0 V

Note: The integrated bootstrap diode does not work well with the trapezoidal control.

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IRS233(0,2)(D)(S&J)PbF

Static Electrical Characteristics- Continued

V

BIAS

(V

CC

, V

BS1,2,3

) = 15 V, V

SO1,2,3

= V

SS

and T

A

= 25 °C unless otherwise specified. The V

IN,

V

TH

and I

IN

parameters

are referenced to V

SS

and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The V

O

and I

O

parameters

are referenced to V

SO1,2,3

and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.

Symbol Definition Min

Typ

Max

Units

Test Conditions

I

SRC,AMP

Operational amplifier output source current — -7 -4 V

CA-

= 0 V, V

SO

=1 V

V

CAO

= 4 V

I

SNK,AMP

Operational amplifier output sink current 1 2.1 — V

CA-

= 1 V, V

SO

=0 V

V

CAO

= 2 V

I

O+,AMP

Operational amplifier output high short circuit

current -30 -10 — V

CA-

= 0 V, V

SO

=5 V

V

CAO

= 0 V

I

O-,AMP

Operational amplifier output low short circuit

current — 4 —

mA

V

CA-

= 5 V, V

SO

=0 V

V

CAO

= 5 V

Functional Block Diagram

Note: IRS2330 & IRS2332 are without integrated bootstrap diode.

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IRS233(0,2)(D)(S&J)PbF

Lead Definitions

Symbol

Description

HIN1,2,3 Logic input for high-side gate driver outputs (HO1,2,3), out of phase

LIN1,2,3 Logic input for low-side gate driver output (LO1,2,3), out of phase

FAULT Indicates over-current or undervoltage lockout (low-side) has occurred, negative logic

V

CC

Low-side and logic fixed supply

ITRIP Input for over-current shutdown

CAO Output of current amplifier

CA- Negative input of current amplifier

V

SS

Logic Ground

V

B1,2,3

High-side floating supply

HO1,2,3 High-side gate drive output

V

S1,2,3

High-side floating supply return

LO1,2,3 Low-side gate drive output

V

SO

Low-side return and positive input of current amplifier

Lead Assignments

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IRS233(0,2)(D)(S&J)PbF

Application Information and Additional Details

Information regarding the following topics are included as subsections within this section of the datasheet.

• IGBT/MOSFET Gate Drive

• Switching and Timing Relationships

• Deadtime

• Matched Propagation Delays

• Input Logic Compatibility

• Undervoltage Lockout Protection

• Shoot-Through Protection

• Fault Reporting

• Over-Current Protection

• Over-Temperature Shutdown Protection

• Truth Table: Undervoltage lockout, ITRIP

• Advanced Input Filter

• Short-Pulse / Noise Rejection

• Integrated Bootstrap Functionality

• Bootstrap Power Supply Design

• Separate Logic and Power Grounds

• Negative V

S

Transient SOA

• DC- bus Current Sensing

• PCB Layout Tips

• Integrated Bootstrap FET limitation

• Additional Documentation

IGBT/MOSFET Gate Drive

The IRS233(2,0)(D) HVICs are designed to drive up to six MOSFET or IGBT power devices. Figures 1 and 2 illustrate several

parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of

the power switch, is defined as I

O

. The voltage that drives the gate of the external power switch is defined as V

HO

for the high-

side power switch and V

LO

for the low-side power switch; this parameter is sometimes generically called V

OUT

and in this case

does not differentiate between the high-side or low-side output voltage.

VS

(or COM)

HO

(or LO)

VB

(or VCC)

IO+

VHO (or VLO)

+

-

VS

(or COM)

HO

(or LO)

VB

(or VCC)

IO-

Figure 1: HVIC sourcing current Figure 2: HVIC sinking current

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IRS233(0,2)(D)(S&J)PbF

Switching and Timing Relationships

The relationship between the input and output signals of the IRS233(0,2)(D) are illustrated below in Figures 3. From these

figures, we can see the definitions of several timing parameters (i.e., PW

IN

, PW

OUT

, t

ON

, t

OFF

, t

R

, and t

F

) associated with this

device.

LINx

(or HINx) 50% 50%

PWIN

PWOUT

10% 10%

90% 90%

tOFF

tON tRtF

LOx

(or HOx)

Figure 3: Switching time waveforms

The following two figures illustrate the timing relationships of some of the functionality of the IRS233(0,2)(D); this functionality

is described in further detail later in this document.

During interval A of Figure 4, the HVIC has received the command to turn-on both the high- and low-side switches at the same

time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the high- and low-side output

are held in the off state.

Interval B of Figures 4 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a result, all of the

gate drive outputs have been disabled (i.e., see that HOx has returned to the low state; LOx is also held low) and a fault is

reported by the FAULT output transitioning to the low state. Once the ITRIP input has returned to the low state, the fault

condition is latched until the all LINx become high.

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IRS233(0,2)(D)(S&J)PbF

HIN1,2,3

LIN1, 2, 3

FAULT

ITRIP

HO1, 2, 3

LO1, 2, 3

AB

Figure 4: Input/output timing diagram

Deadtime

This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within

IR’s HVIC portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a

minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power

switch being turned off has fully turned off before the second power switch is turned on. This minimum deadtime is

automatically inserted whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified

by the gate driver. Figure 5 illustrates the deadtime period and the relationship between the output gate signals.

The deadtime circuitry of the IRS233(0,2)(D) is matched with respect to the high- and low-side outputs of a given channel;

additionally, the deadtimes of each of the three channels are matched.

Figure 5: Illustration of deadtime

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IRS233(0,2)(D)(S&J)PbF

Matched Propagation Delays

The IRS233(0,2)(D) family of HVICs is designed with propagation delay matching circuitry. With this feature, the IC’s

response at the output to a signal at the input requires approximately the same time duration (i.e., t

ON

, t

OFF

) for both the low-

side channels and the high-side channels. Additionally, the propagation delay for each low-side channel is matched when

compared to the other low-side channels and the propagation delays of the high-side channels are matched with each other.

The propagation turn-on delay (t

ON

) of the IRS233(0,2)(D) is matched to the propagation turn-on delay (t

OFF

).

Input Logic Compatibility

The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS233(0,2)(D) family has been designed to

be compatible with 3.3 V and 5 V logic-level signals. The IRS233(0,2)(D) features an integrated 5.2 V Zener clamp on the

HIN, LIN, and ITRIP pins. Figure 6 illustrates an input signal to the IRS233(0,2)(D), its input threshold values, and the logic

state of the IC as a result of the input signal.

Figure 6: HIN & LIN input thresholds

Undervoltage Lockout Protection

This family of ICs provides undervoltage lockout protection on both the V

CC

(logic and low-side circuitry) power supply and the

V

BS

(high-side circuitry) power supply. Figure 7 is used to illustrate this concept; V

CC

(or V

BS

) is plotted over time and as the

waveform crosses the UVLO threshold (V

CCUV+/-

or V

BSUV+/-

) the undervoltage protection is enabled or disabled.

Upon power-up, should the V

CC

voltage fail to reach the V

CCUV+

threshold, the IC will not turn-on. Additionally, if the V

CC

voltage decreases below the V

CCUV-

threshold during operation, the undervoltage lockout circuitry will recognize a fault

condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low state to inform

the controller of the fault condition.

Upon power-up, should the V

BS

voltage fail to reach the V

BSUV

threshold, the IC will not turn-on. Additionally, if the V

BS

voltage

decreases below the V

BSUV

threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and

shutdown the high-side gate drive outputs of the IC.

The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to

fully enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low

voltage, resulting in the power switch conducting current while the channel impedance is high; this could result in very high

conduction losses within the power device and could lead to power device failure.

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IRS233(0,2)(D)(S&J)PbF

Figure 7: UVLO protection

Shoot-Through Protection

The IRS233(0,2)(D) family of high-voltage ICs is equipped with shoot-through protection circuitry (also known as cross-

conduction prevention circuitry). Figure 8 shows how this protection circuitry prevents both the high- and low-side switches

from conducting at the same time. Table 1 illustrates the input/output relationship of the devices in the form of a truth table.

Note that the IRS233(0,2)(D) has inverting inputs (the output is out-of-phase with its respective input).

Figure 8: Illustration of shoot-through protection circuitry

IRS233(0,2)(D)

HIN LIN HO LO

0 0 0 0

0 1 1 0

1 0 0 1

1 1 0 0

Table 1: Input/output truth table

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IRS233(0,2)(D)(S&J)PbF

Fault Reporting

The IRS233(0,2)(D) family provides an integrated fault reporting output. There are two situations that would cause the HVIC

to report a fault via the FAULT pin. The first is an undervoltage condition of V

CC

and the second is if the ITRIP pin recognizes

a fault. Once the fault condition occurs, the FAULT pin is internally pulled to V

SS

and the fault condition is latched. The fault

output stays in the low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed,

the voltage on the FAULT pin will return to V

CC

.

Over-Current Protection

The IRS233(0,2)(D) HVICs are equipped with an ITRIP input pin. This functionality can be used to detect over-current events

in the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs are shutdown, a fault is

reported through the FAULT pin.

The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R

0

, R

1

, and R

2

)

connected to ITRIP as shown in Figure 9, and the ITRIP threshold (V

IT,TH+

). The circuit designer will need to determine the

maximum allowable level of current in the DC- bus and select R

0

, R

1

, and R

2

such that the voltage at node V

X

reaches the

over-current threshold (V

IT,TH+

) at that current level.

V

IT,TH+

= R

0

I

DC-

(R

1

/(R

1

+R

2

))

I RS233(0,2)(D)

Figure 9: Programming the over-current protection

For example, a typical value for resistor R

0

could be 50 mΩ. The voltage of the ITRIP pin should not be allowed to exceed 5

V; if necessary, an external voltage clamp may be used.

Over-Temperature Shutdown Protection

The ITRIP input of the IRS233(0,2)(D) can also be used to detect over-temperature events in the system and initiate a

shutdown of the HVIC (and power switches) at that time. In order to use this functionality, the circuit designer will need to

design the resistor network as shown in Figure 10 and select the maximum allowable temperature.

This network consists of a thermistor and two standard resistors R

3

and R

4

. As the temperature changes, the resistance of the

thermistor will change; this will result in a change of voltage at node V

X

. The resistor values should be selected such the

voltage V

X

should reach the threshold voltage (V

IT,TH+

) of the ITRIP functionality by the time that the maximum allowable

temperature is reached. The voltage of the ITRIP pin should not be allowed to exceed 5 V.

When using both the over-current protection and over-temperature protection with the ITRIP input, OR-ing diodes (e.g.,

DL4148) can be used. This network is shown in Figure 11; the OR-ing diodes have been labeled D

1

and D

2

.

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IRS233(0,2)(D)(S&J)PbF

Figure 10: Programming over-temperature protection Figure 11: Using over-current protection and over-temperature

protection

Truth Table: Undervoltage lockout and ITRIP

Table 2 provides the truth table for the IRS233(0,2)(D). The first line shows that the UVLO for V

CC

has been tripped; the

FAULT output has gone low and the gate drive outputs have been disabled. V

CCUV

is not latched in this case and when V

CC

is

greater than V

CCUV

, the FAULT output returns to the high impedance state.

The second case shows that the UVLO for V

BS

has been tripped and that the high-side gate drive outputs have been disabled.

After V

BS

exceeds the V

BSUV

threshold, HO will stay low until the HVIC input receives a new falling transition of HIN. The third

case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP trip threshold has been reached and

that the gate drive outputs have been disabled and a fault has been reported through the fault pin. The fault output stays in the

low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed, the voltage on the

FAULT pin will return to V

CC

.

VCC VBS ITRIP FAULT LO HO

UVLO V

CC

<V

CCUV

--- --- 0 0 0

UVLO V

BS

15 V <V

BSUV

0 V High impedance LIN 0

Normal operation 15 V 15 V 0 V High impedance LIN HIN

ITRIP fault 15 V 15 V >V

ITRIP

0 0 0

Table 2: IRS233(0,2)(D) UVLO, ITRIP & FAULT truth table

Advanced Input Filter

The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to reject noise

spikes and short pulses. This input filter has been applied to the HIN and LIN. The working principle of the new filter is shown

in Figures 12 and 13.

Figure 12 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms (Example 1)

show an input signal with a duration much longer then t

FIL,IN

; the resulting output is approximately the difference between the

input signal and t

FIL,IN

. The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer then

t

FIL,IN

; the resulting output is approximately the difference between the input signal and t

FIL,IN

.

Figure 13 shows the advanced input filter and the symmetry between the input and output. The upper pair of waveforms

(Example 1) show an input signal with a duration much longer then t

FIL,IN

; the resulting output is approximately the same

duration as the input signal. The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer

then t

FIL,IN

; the resulting output is approximately the same duration as the input signal.

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IRS233(0,2)(D)(S&J)PbF

Figure 12: Typical input filter Figure 13: Advanced input filter

Short-Pulse / Noise Rejection

This device’s input filter provides protection against short-pulses (e.g., noise) on the input lines. If the duration of the input

signal is less than t

FIL,IN

, the output will not change states. Example 1 of Figure 14 shows the input and output in the low state

with positive noise spikes of durations less than t

FIL,IN

; the output does not change states. Example 2 of Figure 19 shows the

input and output in the high state with negative noise spikes of durations less than t

FIL,IN

; the output does not change states.

Example 1

Example 2

Figure 14: Noise rejecting input filters

Figures 15 and 16 present lab data that illustrates the characteristics of the input filters while receiving ON and OFF pulses.

The input filter characteristic is shown in Figure 15; the left side illustrates the narrow pulse ON (short positive pulse)

characteristic while the left shows the narrow pulse OFF (short negative pulse) characteristic. The x-axis of Figure 20 shows

the duration of PW

IN

, while the y-axis shows the resulting PW

OUT

duration. It can be seen that for a PW

IN

duration less than

t

FIL,IN

, that the resulting PW

OUT

duration is zero (e.g., the filter rejects the input signal/noise). We also see that once the PW

IN

duration exceed t

FIL,IN

, that the PW

OUT

durations mimic the PW

IN

durations very well over this interval with the symmetry

improving as the duration increases. To ensure proper operation of the HVIC, it is suggested that the input pulse width for the

high-side inputs be ≥ 500 ns.

The difference between the PW

OUT

and PW

IN

signals of both the narrow ON and narrow OFF cases is shown in Figure 16; the

careful reader will note the scale of the y-axis. The x-axis of Figure 21 shows the duration of PW

IN

, while the y-axis shows the

resulting PW

OUT

–PW

IN

duration. This data illustrates the performance and near symmetry of this input filter.

www.irf.com 17

IRS233(0,2)(D)(S&J)PbF

Time (ns)

Figure 15: IRS233(0,2)(D) input filter characteristic

Figure 16: Difference between the input pulse and the output pulse

Integrated Bootstrap Functionality

The new IRS233(0,2)D family features integrated high-voltage bootstrap MOSFETs that eliminate the need of the external

bootstrap diodes and resistors in many applications.

There is one bootstrap MOSFET for each high-side output channel and it is connected between the V

CC

supply and its

respective floating supply (i.e., V

B1

, V

B2

, V

B3

); see Figure 17 for an illustration of this internal connection.

The integrated bootstrap MOSFET is turned on only during the time when LO is ‘high’, and it has a limited source current due

to R

BS

. The V

BS

voltage will be charged each cycle depending on the on-time of LO and the value of the C

BS

capacitor, the

drain-source (collector-emitter) drop of the external IGBT (or MOSFET), and the low-side free-wheeling diode drop.

The bootstrap MOSFET of each channel follows the state of the respective low-side output stage (i.e., the bootstrap MOSFET

is ON when LO is high, it is OFF when LO is low), unless the V

B

voltage is higher than approximately 110% of V

CC

. In that

case, the bootstrap MOSFET is designed to remain off until V

B

returns below that threshold; this concept is illustrated in Figure

18.

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IRS233(0,2)(D)(S&J)PbF

VCC

VB1

VB2

VB3

Figure 17: Internal bootstrap MOSFET connection Figure 18: Bootstrap MOSFET state diagram

A bootstrap MOSFET is suitable for most of the PWM modulation schemes and can be used either in parallel with the external

bootstrap network (i.e., diode and resistor) or as a replacement of it. The use of the integrated bootstrap as a replacement of

the external bootstrap network may have some limitations. An example of this limitation may arise when this functionality is

used in non-complementary PWM schemes (typically 6-step modulations) and at very high PWM duty cycle. In these cases,

superior performances can be achieved by using an external bootstrap diode in parallel with the internal bootstrap network.

Bootstrap Power Supply Design

For information related to the design of the bootstrap power supply while using the integrated bootstrap functionality of the

IRS233(0,2)D family, please refer to Application Note 1123 (AN-1123) entitled “Bootstrap Network Analysis: Focusing on the

Integrated Bootstrap Functionality.” This application note is available at www.irf.com.

For information related to the design of a standard bootstrap power supply (i.e., using an external discrete diode) please refer

to Design Tip 04-4 (DT04-4) entitled “Using Monolithic High Voltage Gate Drivers.” This design tip is available at www.irf.com.

Separate Logic and Power Grounds

The IRS233(0,2)(D) has separate logic and power ground pin (V

SS

and VSO respectively) to eliminate some of the noise

problems that can occur in power conversion applications. Current sensing shunts are commonly used in many applications

for power inverter protection (i.e., over-current protection), and in the case of motor drive applications, for motor current

measurements. In these situations, it is often beneficial to separate the logic and power grounds.

Figure 19 shows a HVIC with separate V

SS

and VSO pins and how these two grounds are used in the system. The V

SS

is

used as the reference point for the logic and over-current circuitry; V

X

in the figure is the voltage between the ITRIP pin and

the V

SS

pin. Alternatively, the VSO pin is the reference point for the low-side gate drive circuitry. The output voltage used to

drive the low-side gate is V

LO

-VSO; the gate-emitter voltage (V

GE

) of the low-side switch is the output voltage of the driver

minus the drop across R

G,LO

.

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IRS233(0,2)(D)(S&J)PbF

VS

(x3)

HVIC

HO

(x3)

VB

(x3)

LO

(x3)

COM

DC+ BUS

DC- BUS

VCC

DBS

CBS

VSS

RG,LO

RG,HO

VS1 VS2 VS3

R1

R2

R0

VGE1

+

-VGE2

+

-VGE3

+

-

ITRIP

VX

+

-

Figure 19: Separate V

SS

and VSO pins

Negative V

S

Transient SOA

A common problem in today’s high-power switching converters is the transient response of the switch node’s voltage as the

power switches transition on and off quickly while carrying a large current. A typical 3-phase inverter circuit is shown in Figure

20; here we define the power switches and diodes of the inverter.

If the high-side switch (e.g., the IGBT Q1 in Figures 21 and 22) switches off, while the U phase current is flowing to an

inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-side switch

of the same inverter leg. At the same instance, the voltage node V

S1

, swings from the positive DC bus voltage to the negative

DC bus voltage.

Figure 20: Three phase inverter

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IRS233(0,2)(D)(S&J)PbF

Q1

ON

D2

VS1

Q2

OFF

IU

DC+ BUS

DC- BUS

Figure 21: Q1 conducting Figure 22: D2 conducting

Also when the V phase current flows from the inductive load back to the inverter (see Figures 23 and 24), and Q4 IGBT

switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, V

S2

, swings from the

positive DC bus voltage to the negative DC bus voltage.

Figure 23: D3 conducting Figure 24: Q4 conducting

However, in a real inverter circuit, the V

S

voltage swing does not stop at the level of the negative DC bus, rather it swings

below the level of the negative DC bus. This undershoot voltage is called “negative V

S

transient”.

The circuit shown in Figure 25 depicts one leg of the three phase inverter; Figures 26 and 27 show a simplified illustration of

the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the die bonding to the

PCB tracks are lumped together in L

C

and L

E

for each IGBT. When the high-side switch is on, V

S1

is below the DC+ voltage

by the voltage drops associated with the power switch and the parasitic elements of the circuit. When the high-side power

switch turns off, the load current momentarily flows in the low-side freewheeling diode due to the inductive load connected to

V

S1

(the load is not shown in these figures). This current flows from the DC- bus (which is connected to the VSO pin of the

HVIC) to the load and a negative voltage between V

S1

and the DC- Bus is induced (i.e., the VSO pin of the HVIC is at a higher

potential than the V

S

pin).

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IRS233(0,2)(D)(S&J)PbF

Figure 25: Parasitic Elements Figure 26: V

S

positive Figure 27: V

S

negative

In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative V

S

transient voltage

can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in

normal operation.

International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding applications. An

indication of the IRS233(0,2)(D)’s robustness can be seen in Figure 28, where there is represented the IRS233(0,2)(D) Safe

Operating Area at V

BS

=15V based on repetitive negative V

S

spikes. A negative V

S

transient voltage falling in the grey area

(outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent damage to the IC

do not appear if negative Vs transients fall inside SOA.

At V

BS

=15V in case of -V

S

transients greater than -16.5 V for a period of time greater than 50 ns; the HVIC will hold by design

the high-side outputs in the off state for 4.5 µs.

Figure 28: Negative V

S

transient SOA for IRS233(0,2)(D)

Even though the IRS233(0,2)(D) has been shown able to handle these large negative V

S

transient conditions, it is highly

recommended that the circuit designer always limit the negative V

S

transients as much as possible by careful PCB layout and

component use.

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IRS233(0,2)(D)(S&J)PbF

DC- bus Current Sensing

A ground referenced current signal amplifier has been included so that the current in the return leg of the DC bus may be

monitored. A typical circuit configuration is provided in Fig.29. The signal coming from the shunt resistor is amplified by the

ratio (R1+R2)/R2. Additional details can be found on Design Tip DT 92-6. This design tip is available at www.irf.com.

Figure 29: Current amplifier typical configuration

In the following Figures 30, 31, 32, 33 the configurations used to measure the operational amplifier characteristics are shown.

VCC

CAO

VSO

CA-

VSS

15V

50 pF

1V

0V

90%

10%

1V

0V

T1 T2

V

T1

V

SR+T2

V

SR-

V

CC

CAO

V

SO

CA-

VSS

15V

+

1K

20K

0.2V

V

SO V

SO

21 -0.2V

Figure 30: Operational Amplifier Slew rate measurement Figure 31: Operational Amplifier Input Offset Voltage

measurement

www.irf.com 23

IRS233(0,2)(D)(S&J)PbF

V

CC

CAO

VSO

CA-

V

SS

15V

Measure V

CAO1at V

SO

= 0.1V

V

CAO2 at VSO

= 1.1V

CMRR

=

-20*LOG

(V

CAO1 – 0.1V) –(V

CAO2

–1.1V)

1V

(dB)

Figure 32: Operational Amplifier Common mode rejection

measurement

Figure 33: Operational Amplifier Power supply rejection

measurement

PCB Layout Tips

Distance between high and low voltage components: It’s strongly recommended to place the components tied to the floating

voltage pins (V

B

and V

S

) near the respective high voltage portions of the device. The IRS233(0,2)(D) in the PLCC44 package

has had some unused pins removed in order to maximize the distance between the high voltage and low voltage pins.

Please see the Case Outline PLCC44 information in this datasheet for the details.

Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high voltage

floating side.

Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 34). In order

to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as

much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic

capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage across the gate-emitter, thus

increasing the possibility of a self turn-on effect.

Figure 34: Antenna Loops

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IRS233(0,2)(D)(S&J)PbF

Supply Capacitor: It is recommended to place a bypass capacitor (C

IN

) between the V

CC

and V

SS

pins. This connection is

shown in Figure 35. A ceramic 1 µF ceramic capacitor is suitable for most applications. This component should be placed as

close as possible to the pins in order to reduce parasitic elements.

I RS233(0,2)(D)

Figure 35: Supply capacitor

Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at the switch

node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is recommended

to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side emitter to negative bus rail

stray inductance. However, where negative V

S

spikes remain excessive, further steps may be taken to reduce the spike. This

includes placing a resistor (5 Ω or less) between the V

S

pin and the switch node (see Figure 36), and in some cases using a

clamping diode between V

SS

and V

S

(see Figure 37). See DT04-4 at www.irf.com for more detailed information.

Figure 36: V

S

resistor Figure 37: V

S

clamping diode

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IRS233(0,2)(D)(S&J)PbF

Integrated Bootstrap FET limitation

The integrated Bootstrap FET functionality has an operational limitation under the following bias conditions applied to the

HVIC:

• VCC pin voltage = 0V AND

• VS or VB pin voltage > 0

In the absence of a VCC bias, the integrated bootstrap FET voltage blocking capability is compromised and a current

conduction path is created between VCC & VB pins, as illustrated in Fig.38 below, resulting in power loss and possible

damage to the HVIC.

Figure 38: Current conduction path between VCC and VB pin

Relevant Application Situations:

The above mentioned bias condition may be encountered under the following situations:

• In a motor control application, a permanent magnet motor naturally rotating while VCC power is OFF. In this

condition, Back EMF is generated at a motor terminal which causes high voltage bias on VS nodes resulting

unwanted current flow to VCC.

• Potential situations in other applications where VS/VB node voltage potential increases before the VCC

voltage is available (for example due to sequencing delays in SMPS supplying VCC bias)

Application Workaround:

Insertion of a standard p-n junction diode between VCC pin of IC and positive terminal of VCC capacitors (as illustrated in

Fig.39) prevents current conduction “out-of” VCC pin of gate driver IC. It is important not to connect the VCC capacitor

directly to pin of IC. Diode selection is based on 25V rating or above & current capability aligned to ICC consumption of IC

- 100mA should cover most application situations. As an example, Part number # LL4154 from Diodes Inc (25V/150mA

standard diode) can be used.

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IRS233(0,2)(D)(S&J)PbF

Figure 39: Diode insertion between VCC pin and VCC capacitor

Note that the forward voltage drop on the diode (V

F

) must be taken into account when biasing the VCC pin of the IC to

meet UVLO requirements. VCC pin Bias = VCC Supply Voltage – V

F

of Diode.

Additional Documentation

Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search function and

the document number to quickly locate them. Below is a short list of some of these documents.

DT97-3: Managing Transients in Control IC Driven Power Stages

AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality

DT04-4: Using Monolithic High Voltage Gate Drivers

AN-978: HV Floating MOS-Gate Driver ICs

VCC

VSS

(or COM)

VB

VCC

Capacitor

VCC

VSS

(or COM)

VB

VCC

Capacitor

www.irf.com 27

IRS233(0,2)(D)(S&J)PbF

Parameter Temperature Trends

Figures 40-78 provide information on the experimental performance of the IRS233(0,2)(D)(S&J) HVIC. The line plotted in each

figure is generated from actual lab data. A small number of individual samples were tested at three temperatures (-40 ºC, 25 ºC,

and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp. consist of three data points (one data point

at each of the tested temperatures) that have been connected together to illustrate the understood temperature trend. The

individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given

temperature).

0

100

200

300

400

500

600

700

800

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

ON

(ns)

Exp.

Fig. 40. Turn-on Propagation Delay vs.

Temperature

0

100

200

300

400

500

600

700

800

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

ON

(ns)

Exp.

Fig. 41. Turn-on Propagation Delay vs.

Temperature

0

100

200

300

400

500

600

700

800

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

OFF

(ns)

Exp.

Fig. 42. Turn-off Propagation Delay vs.

Temperature

0

100

200

300

400

500

600

700

800

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

OFF

(ns)

Exp.

Fig. 43. Turn-off Propagation Delay vs.

Temperature

www.irf.com 28

IRS233(0,2)(D)(S&J)PbF

0

20

40

60

80

100

120

140

160

180

200

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

R

(ns)

Exp.

Fig. 44. Turn-on Rise Time vs. Temperature

0

10

20

30

40

50

60

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

F

(ns)

Exp.

Fig.45. Turn-off Fall Time vs. Temperature

0

100

200

300

400

500

600

700

800

900

1000

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

ITRIP

(ns)

Exp.

Fig. 46. ITRIP to Output Shutdown Propagation

Delay vs. Temperature

0

100

200

300

400

500

600

700

800

900

1000

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

t

FLT

(ns)

Exp.

Fig. 47. ITRIP to FAULT Indication Delay vs.

Temperature

0

2000

4000

6000

8000

10000

12000

14000

16000

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

TFLTCLR (ns)

Exp.

Fig.48. FAULT Clear Time vs. Temperature

0

200

400

600

800

1000

1200

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

DLTon1 (ns)

Exp.

Fig. 49. Dead Time vs. Temperature

www.irf.com 29

IRS233(0,2)(D)(S&J)PbF

0

10

20

30

40

50

60

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

SR+_Amp (V/uS)

Exp.

Fig. 50. Operational Amplifier Slew Rate (+) vs.

Temperature

0

1

2

3

4

5

6

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

SR-_Amp (V/uS)

Exp.

Fig. 51. Operational Amplifier Slew Rate (-) vs.

Temperature

0.0

0.5

1.0

1.5

2.0

2.5

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

LIN1_VTH+ (V)

Exp.

Fig. 52. Input Positive Going Threshold vs.

Temperature

0.0

0.5

1.0

1.5

2.0

2.5

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

LIN1_VTH- (V)

Exp.

Fig. 53. Input Negative Going Threshold vs.

Temperature

0

100

200

300

400

500

600

700

800

-50 -25 0 25 50 75 100 125

Temperature (oC)

VIT,TH+ (mV)

EXP.

p.

Fig. 54. ITRIP Input Positive Going Threshold

vs. Temperature

0

100

200

300

400

500

600

700

800

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

IT,TH-

(mV)

Exp.

Fig. 55. ITRIP Input Negative Going Threshold

vs. Temperature

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IRS233(0,2)(D)(S&J)PbF

0

50

100

150

200

250

300

350

400

450

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

VOL_LO1 (mV)

Exp.

Fig. 56. Low Level Output Voltage vs.

Temperature

0

10

20

30

40

50

60

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

ileak1_VCCMAX (µA)

Exp.

Fig. 57. Offset Supply Leakage Current vs.

Temperature

0

2

4

6

8

10

12

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

I

QCC1

(mA)

Exp.

Fig. 58. Quiescent V

CC

Supply Current vs.

Temperature

0

1

2

3

4

5

6

7

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

I

QCC0

(mA)

Exp.

Fig. 59. Quiescent V

CC

Supply Current vs.

Temperature

0

10

20

30

40

50

60

70

80

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

I

QBS10

(µA)

Exp.

Fig. 60. Quiescent V

BS

Supply Current vs.

Temperature

0

10

20

30

40

50

60

70

80

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

I

QBS11

(µA)

Exp.

Fig. 61. Quiescent V

BS

Supply Current vs.

Temperature

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IRS233(0,2)(D)(S&J)PbF

7.8

8.0

8.2

8.4

8.6

8.8

9.0

9.2

9.4

9.6

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

CCUV-

(V)

Exp.

Fig. 62. V

CC

Supply Undervoltage Negative

Going Threshold vs. Temperature

8.2

8.4

8.6

8.8

9.0

9.2

9.4

9.6

9.8

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

CCUV+

(V)

Exp.

Fig. 63. V

CC

Supply Undervoltage Positive

Going Threshold vs. Temperature

6.0

6.5

7.0

7.5

8.0

8.5

9.0

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

BSUV-

(V)

Exp.

Fig. 64. V

BS

Supply Undervoltage Negative

Going Threshold vs. Temperature

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

V

BSUV+

(V)

Exp.

Fig. 65. V

BS

Supply Undervoltage Positive

Going Threshold vs. Temperature

0

10

20

30

40

50

60

70

80

90

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

R

ON,FLT

(Ω)

Exp.

Fig. 66. FAULT Low On-Resistance vs.

Temperature

-450

-400

-350

-300

-250

-200

-150

-100

-50

0

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

I

O+

(mA)

Exp.

p.

Fig. 67. Output High Short Circuit Pulsed

Current vs. Temperature

www.irf.com 32

IRS233(0,2)(D)(S&J)PbF

6

106

206

306

406

506

606

706

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

I

O-

(mA)

Exp.

Fig. 68. Output Low Short Circuit Pulsed

Current vs. Temperature

-20

-15

-10

-5

0

5

10

15

20

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

VOS_AMP (mV)

Exp.

p.

Fig. 69. Offset Opamp vs. Temperature

0

20

40

60

80

100

120

140

160

180

200

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

PSRR_AMP (dB)

Exp.

Fig. 70. Operational Amplifier Power Supply

Rejection Ratio vs. Temperature

0

20

40

60

80

100

120

140

160

180

200

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

CMRR_AMP (dB)

Exp.

Fig. 71. Operational Amplifier Common Mode

Rejection Ratio vs. Temperature

4.8

4.9

5.0

5.1

5.2

5.3

5.4

5.5

5.6

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

VOH_AMP (V)

Exp.

Fig. 72. Operational Amplifier High Level Output

Voltage vs. Temperature

0

5

10

15

20

25

30

35

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

VOH_AMP (mV)

Exp.

Fig. 73. Operational Amplifier Low Level

Output Voltage vs. Temperature

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IRS233(0,2)(D)(S&J)PbF

0

1

2

3

4

5

6

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

Isnk_AMP (mA)

Exp.

Fig. 74. Operational Amplifier Output Sink

Current vs. Temperature

0

2

4

6

8

10

12

14

16

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

Io-_AMP (mA)

Exp.

Fig. 75. Operational Amplifier Output Low

Short Circuit Current vs. Temperature

-16

-14

-12

-10

-8

-6

-4

-2

0

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

Isrc_AMP (mA)

Exp.

Fig. 76. Operational Amplifier Output Source

Current vs. Temperature

-35

-30

-25

-20

-15

-10

-5

0

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

Io+_AMP (mA)

Exp.

Fig. 77. Operational Amplifier Output High

Short Circuit Current vs. Temperature

-14

-12

-10

-8

-6

-4

-2

0

-50 -25 0 25 50 75 100 125

Temperature (

o

C)

Vs1_RST_domin (V)

Exp.

Fig. 78. Max –Vs vs. Temperature

www.irf.com 34

IRS233(0,2)(D)(S&J)PbF

Case Outlines

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IRS233(0,2)(D)(S&J)PbF

Case Outlines

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IRS233(0,2)(D)(S&J)PbF

Tape and Reel Details: SOIC28W

CARRIER TAPE DIMENSION FOR 28SOICW

Code Min Max Min Max

A 11.90 12.10 0.468 0.476

B 3.90 4.10 0.153 0.161

C 23.70 24.30 0.933 0.956

D 11.40 11.60 0.448 0.456

E 10.80 11.00 0.425 0.433

F 18.20 18.40 0.716 0.724

G 1.50 n/a 0.059 n/a

H 1.50 1.60 0.059 0.062

Metric Imperial

REEL DIMENSIONS FOR 28SOICW

Code Min Max Min Max

A 329.60 330.25 12.976 13.001

B 20.95 21.45 0.824 0.844

C 12.80 13.20 0.503 0.519

D 1.95 2.45 0.767 0.096

E 98.00 102.00 3.858 4.015

F n/a 30.40 n/a 1.196

G 26.50 29.10 1.04 1.145

H 24.40 26.40 0.96 1.039

Metric Imperial

E

F

A

C

D

G

A

B

H

NOTE : CONTROLLING

DIM ENSION IN M M

LOADED TAPE FEED DIRECTION

A

H

F

E

G

D

B

C

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IRS233(0,2)(D)(S&J)PbF

Tape and Reel Details: PLCC44

CARRIER TAPE DIMENSION FOR 44PLCC

Code Min Max Min Max

A 23.90 24.10 0.94 0.948

B 3.90 4.10 0.153 0.161

C 31.70 32.30 1.248 1.271

D 14.10 14.30 0.555 0.562

E 17.90 18.10 0.704 0.712

F 17.90 18.10 0.704 0.712

G 2.00 n/a 0.078 n/a

H 1.50 1.60 0.059 0.062

Metric Imperial

REEL DIMENSIONS FOR 44PLCC

Code Min Max Min Max

A 329.60 330.25 12.976 13.001

B 20.95 21.45 0.824 0.844

C 12.80 13.20 0.503 0.519

D 1.95 2.45 0.767 0.096

E 98.00 102.00 3.858 4.015

F n/a 38.4 n/a 1.511

G 34.7 35.8 1.366 1.409

H 32.6 33.1 1.283 1.303

Metric Imperial

E

F

A

C

D

G

A

B

H

NOTE : CONTROLLING

DIM ENSION IN M M

LOADED TAPE FEED DIRECTION

A

H

F

E

G

D

B

C

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IRS233(0,2)(D)(S&J)PbF

Ordering Information

Standard Pack

Base Part Number

Package Type

Form Quantity

Complete Part Number

Tube/Bulk 25 IRS233(0,2)(D)SPbF

SOIC28W

Tape and Reel 1000

IRS233(0,2)(D)STRPbF

Tube/Bulk 27 IRS233(0,2)(D)JPbF

IRS233(0,2)(D)

PLCC44

Tape and Reel 500

IRS233(0,2)(D)JTRPbF

The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility

for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other

rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or

patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document

supersedes and replaces all information previously supplied.

For technical support, please contact IR’s Technical Assistance Center

http://www.irf.com/technical-info/

WORLD HEADQUARTERS:

233 Kansas St., El Segundo, California 90245

Tel: (310) 252-7105

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IRS233(0,2)(D)(S&J)PbF

Change History

Revision Date Change comments

0.0 10/17/07 Initial data sheet converted from IRS2130xD data sheet

0.1 03/05/08 Initial Review

0.2 03/18/08 Included tri-temp plots

0.3 03/18/08 Updated test conditions

0.4 03/26/08 Updated limits using DR3 Limits table

0.5 03/27/08 Included application notes

0.6 03/27/08 Updated minor errors and completed review for DR3

0.7 03/28/08 Corrected reflow temperature for PLCC44 to 245°C

0.8 04/02/08 Added Integrated Operational Amplifier feature on front page

and RoHS compliant.

0.9 04/11/08 Corrected logic level compatible on Page1 from 2.5V to 3.3V

1.0 04/15/08 Added MDT parameter

1.1 04/16/08 Updated MDT spec. and changed latch-up level to A

1.2 04/28/08 Removed typical MDT spec.; MDT expected to be zero and

cannot be more than maximum spec.

May 8, 08 Changed file format from “rev1.2” to May 8, 2008. Corrected

part number in Fig. 15

July 8, 08 changed Iqcc test condition to Vin=4V from 0V.

June 1, 11 Add bootstrap fet limitation