stream 33 17, 1.5 Gbps a FUNCTIONAL BLOCK DIAGRAM CS INP RE INN A 7 5 FIRST RANK 177-BIT LATCH SECOND RANK 177-BIT LATCH INPUT DECODERS 33 D OUTPUT ADDRESS DECODER FEATURES Low Cost 33 17, Fully Differential, Nonblocking Array >1.5 Gbps per Port NRZ Data Rate Wide Power Supply Range: +5 V, +3.3 V, -3.3 V, -5 V Low Power 400 mA (Outputs Enabled) 30 mA (Outputs Disabled) PECL and ECL Compatible CMOS/TTL-Level Control Inputs: 3 V to 5 V Low Jitter: <50 ps p-p No Heat Sinks Required Drives a Backplane Directly Programmable Output Current Optimize Termination Impedance User-Controlled Voltage at the Load Minimize Power Dissipation Individual Output Disable for Busing and Building Larger Arrays Double Row Latch Buffered Inputs Available in 184-Lead LQFP Digital Crosspoint Switch AD8150* 33 17 OUTP 3317 DIFFERENTIAL SWITCH 17 MATRIX OUTN WE AD8150 UPDATE RESET APPLICATIONS HD and SD Digital Video Fiber Optic Network Switching PRODUCT DESCRIPTION AD8150 is a member of the X stream line of products and is a breakthrough in digital switching, offering a large switch array (33 x 17) on very little power, typically less than 1.5 W. Additionally, it operates at data rates in excess of 1.5 Gbps per port, making it suitable for HDTV applications. Further, the pricing of the AD8150 makes it affordable enough to be used for SD applications as well. The AD8150 is also useful for OC-24 optical network switching. The AD8150's flexible supply voltages allow the user to operate with either PECL or ECL data levels and will operate down to 3.3 V for further power reduction. The control interface is CMOS/ TTL compatible (3 V to 5 V). Its fully differential signal path reduces jitter and crosstalk while allowing the use of smaller single-ended voltage swings. 500mV 100mV /DIV -500mV 100ps/DIV Figure 1. Output Eye Pattern, 1.5 Gbps The AD8150 is offered in a 184-lead LQFP package that operates over the industrial temperature range of 0C to 85C. *Patent Pending. X stream is a trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000 (@ 25C, VCC = 3.3 V to 5 V, VEE = 0 V, RL = 50 (see Figure 22), IOUT = 16 mA, unless AD8150-SPECIFICATIONS otherwise noted) Parameter Conditions DYNAMIC PERFORMANCE Max Data Rate/Channel (NRZ) Channel Jitter RMS Channel Jitter Propagation Delay Propagation Delay Match Output Rise/Fall Time Data Rate < 1.5 Gbps VCC = 5 V Input to Output INPUT CHARACTERISTICS Input Voltage Swing Input Voltage Range Input Bias Current Input Capacitance Input VIN High Input VIN Low OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Range Output Current Output Capacitance POWER SUPPLY Operating Range PECL, VCC ECL, VEE VDD VSS Quiescent Current VDD VEE Min Max 1.5 50 10 650 50 100 20% to 80% Differential Common-Mode 200 VCC - 2 100 1000 VCC 2 2 VCC - 1.2 VCC - 2.4 Differential (See Figure 22) VCC - 0.2 VCC - 1.4 800 VCC - 1.8 5 VCC 25 2 VEE = 0 V VCC = 0 V 3.3 -5 3 5 -3.3 5 0 2 400 All Outputs Enabled, IOUT = 16 mA TMIN to TMAX All Outputs Disabled THERMAL CHARACTERISTICS Operating Temperature Range JA LOGIC INPUT CHARACTERISTICS Input VIN High Input VIN Low Typ 450 30 0 Unit Gbps ps p-p ps ps ps ps mV p-p V A pF V V mV p-p V mA pF V V V V mA mA mA mA 85 C C/W VDD 0.9 V V 30 VDD = 3 V dc to 5 V dc 1.9 0 -2- REV. 0 AD8150 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltage VDD - VEE . . . . . . . . . . . . . . . . . . . . . . . 10.5 V Internal Power Dissipation2 AD8150 184-Lead Plastic LQFP (ST) . . . . . . . . . . . . . 4.2 W Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . VCC - VEE Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range . . . . . . . . . . . . . -65C to +125C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300C The maximum power that can be safely dissipated by the AD8150 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air (T A = 25C): 184-lead plastic LQFP (ST): JA = 30C/W. While the AD8150 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figure 2. 6.0 MAXIMUM POWER DISSIPATION - Watts TJ = 150C 5.0 4.0 3.0 2.0 1.0 -10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE - C 70 80 90 Figure 2. Maximum Power Dissipation vs. Temperature ORDERING GUIDE Model Temperature Range Package Description Package Option AD8150AST 0C to 85C 184-Lead Plastic LQFP (20 mm x 20 mm) Evaluation Board ST-184 AD8150-EVAL CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8150 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 -3- WARNING! ESD SENSITIVE DEVICE -4- 92 91 90 89 88 87 85 86 84 83 81 82 80 79 78 77 76 75 74 73 72 25 71 24 70 23 69 21 22 67 68 66 65 64 62 63 61 60 59 58 57 56 55 53 54 52 51 50 3 4 49 2 48 47 VEE IN20P IN20N VEE IN21P IN21N VEE IN22P IN22N VEE IN23P IN23N VEE IN24P IN24N VEE IN25P IN25N VEE IN26P IN26N VEE IN27P IN27N VEE IN28P IN28N VEE IN29P IN29N VEE IN30P IN30N VEE IN31P IN31N VEE IN32P IN32N VEE VCC VEE OUT16N OUT16P VEEA16 VEE VEE OUT15N OUT15P VEEA15 OUT14N OUT14P VEEA14 OUT13N OUT13P VEEA13 OUT12N OUT12P VEEA12 OUT11N OUT11P VEEA11 OUT10N OUT10P VEEA10 OUT09N OUT09P VEEA9 OUT08N OUT08P VEEA8 OUT07N OUT07P VEEA7 OUT06N OUT06P VEEA6 OUT05N OUT05P VEEA5 OUT04N OUT04P VEEA4 OUT03N OUT03P VEEA3 OUT02N OUT02P VEEA2 OUT01N OUT01P VEEA1 139 VEE 140 IN13P 142 VEE 141 IN13N 143 IN14P 145 VEE 144 IN14N 146 IN15P 148 VEE 147 IN15N 150 VEEREF 149 VCC 152 VSS 151 REF 153 D6 154 D5 155 D4 157 D2 156 D3 158 D1 159 D0 160 A4 161 A3 162 A2 163 A1 165 UPDATE 164 A0 167 RE 166 WE 169 RESET 168 CS 172 VEE 171 VCC 170 VDD 173 IN16P 175 VEE 174 IN16N 178 VEE 177 IN17N 176 IN17P 179 IN18P 181 VEE 180 IN18N 182 IN19P 184 VEE 183 IN19N AD8150 PIN CONFIGURATION 1 PIN 1 IDENTIFIER 138 137 136 5 6 135 134 7 133 132 8 131 9 130 10 11 129 128 12 13 127 126 14 15 125 16 123 17 122 121 124 18 19 20 120 119 AD8150 118 184L LQFP 117 TOP VIEW (Not to Scale) 116 115 26 27 114 113 28 111 29 110 30 109 31 32 108 112 33 34 107 106 35 105 104 36 103 37 102 38 39 101 40 99 41 98 42 44 97 96 95 45 94 46 93 100 43 VEE IN12N IN12P VEE IN11N IN11P VEE IN10N IN10P VEE IN09N IN09P VEE IN08N IN08P VEE IN07N IN07P VEE IN06N IN06P VEE IN05N IN05P VEE IN04N IN04P VEE IN03N IN03P VEE IN02N IN02P VEE IN01N IN01P VEE IN00N IN00P VEE VCC VEEA0 OUT00P OUT00N VEE VEE REV. 0 AD8150 PIN FUNCTION DESCRIPTIONS Pin No. Signal Type Description 1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40, 42, 46, 47, 92, 93, 99, 102, 105, 108, 111, 114, 117, 120, 123, 126, 129, 132, 135, 138, 139, 142, 145, 148, 172, 175, 178, 181, 184 2 3 5 6 8 9 11 12 14 15 17 18 20 21 23 24 26 27 29 30 32 33 35 36 38 39 41, 98, 149, 171 VEE Power Supply Most Negative PECL Supply (Common with Other Points Labeled VEE) IN20P IN20N IN21P IN21N IN22P IN22N IN23P IN23N IN24P IN24N IN25P IN25N IN26P IN26N IN27P IN27N IN28P IN28N IN29P IN29N IN30P IN30N IN31P IN31N IN32P IN32N VCC PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL Power Supply 43 44 45 48 49 50 51 52 53 54 55 56 57 58 59 60 61 OUT16N OUT16P VEEA16 OUT15N OUT15P VEEA15 OUT14N OUT14P VEEA14 OUT13N OUT13P VEEA13 OUT12N OUT12P VEEA12 OUT11N OUT11P PECL PECL Power Supply PECL PECL Power Supply PECL PECL Power Supply PECL PECL Power Supply PECL PECL Power Supply PECL PECL High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement Most Positive PECL Supply (Common with Other Points Labeled VCC) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to This Output) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to this Output) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to this Output) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to this Output) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to this Output) High-Speed Output Complement High-Speed Output REV. 0 -5- AD8150 Pin No. Signal Type Description 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 94 95 96 97 100 101 103 104 106 107 109 110 112 113 115 116 118 119 121 122 VEEA11 OUT10N OUT10P VEEA10 OUT09N OUT09P VEEA9 OUT08N OUT08P VEEA8 OUT07N OUT07P VEEA7 OUT06N OUT06P VEEA6 OUT05N OUT05P VEEA5 OUT04N OUT04P VEEA4 OUT03N OUT03P VEEA3 OUT02N OUT02P VEEA2 OUT01N OUT01P VEEA1 OUT00N OUT00P VEEA0 IN00P IN00N IN01P IN01N IN02P IN02N IN03P IN03N IN04P IN04N IN05P IN05N IN06P IN06N IN07P IN07N Power Supply PECL PECL Power Supply PECL PECL Power Supply PECL PECL Power Supply PECL PECL Power Supply PECL PECL Power Supply PECL PECL Power Supply PECL PECL Power Supply PECL PECL Power Supply PECL PECL Power Supply PECL PECL Power Supply PECL PECL Power Supply PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL Most Negative PECL Supply (Unique to this Output) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to this Output) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to this Output) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to this Output) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to this Output) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to this Output) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to this Output) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to this Output) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to this Output) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to this Output) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to this Output) High-Speed Output Complement High-Speed Output Most Negative PECL Supply (Unique to this Output) High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement -6- REV. 0 AD8150 Pin No. Signal Type Description 124 125 127 128 130 131 133 134 136 137 140 141 143 144 146 147 150 IN08P IN08N IN09P IN09N IN10P IN10N IN11P IN11N IN12P IN12N IN13P IN13N IN14P IN14N IN15P IN15N VEEREF PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL R-Program 151 REF R-Program 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 173 174 176 177 179 180 182 183 VSS D6 D5 D4 D3 D2 D1 D0 A4 A3 A2 A1 A0 UPDATE WE RE CS RESET VDD IN16P IN16N IN17P IN17N IN18P IN18N IN19P IN19N Power Supply TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Power Supply PECL PECL PECL PECL PECL PECL PECL PECL High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement Connection Point for Output Logic Pull-Down Programming Resistor (Must be Connected to VEE) Connection Point for Output Logic Pull-Down Programming Resistor Most Negative Control Logic Supply Enable/Disable Output (32) MSB Input Select (16) (8) (4) (2) (1) LSB Input Select (16) MSB Output Select (8) (4) (2) (1) LSB Output Select Second Rank Program First Rank Program Enable Readback Enable Chip to Accept Programming Disable All Outputs (Hi-Z) Most Positive Control Logic Supply High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement High-Speed Input High-Speed Input Complement REV. 0 -7- AD8150-Typical Performance Characteristics 100 100 VEE = -3.3V (VOH - VOL = 800mV) VEE = -5V (VOH - VOL = 800mV) 80 JITTER - ps JITTER - ps 80 60 PK-PK 40 20 60 PK-PK 40 20 RMS 0 0 -0.2 -0.4 RMS -0.6 -0.8 VOH - Volts -1.0 -1.2 0 -1.4 Figure 3. Jitter vs. VOH 1.5 Gbps, PRBS 23 0 -0.2 -0.6 -0.8 VOH - Volts -1.2 -1.4 100 VEE = -3.3V (VIH - VIL = 800mV) VEE = -5V (VIH - VIL = 800mV) 80 JITTER - ps 80 60 PK-PK 40 20 60 PK-PK 40 20 RMS 0 -2.0 -1.5 RMS -1.0 -0.5 VIH - Volts 0.0 0 -2.0 0.5 Figure 4. Jitter vs. VIH 1.5 Gbps, PRBS 23 -1.5 -1.0 -0.5 VIH - Volts 0.0 0.5 Figure 7. Jitter vs. VIH 1.5 Gbps, PRBS 23 100 100 VEE = -3.3V VEE = -5V 80 80 JITTER - ps JITTER - ps -1.0 Figure 6. Jitter vs. VOH 1.5 Gbps, PRBS 23 100 JITTER - ps -0.4 60 40 PK-PK 20 60 40 PK-PK 20 RMS RMS 0 0.1 0.3 0.5 0.7 0.9 DATA RATE - Gbps 1.1 1.3 0 0.1 1.5 Figure 5. Jitter vs. Data Rate, PRBS 23 0.3 0.5 0.7 0.9 DATA RATE - Gbps 1.1 1.3 1.5 Figure 8. Jitter vs. Data Rate, PRBS 23 -8- REV. 0 AD8150 100 100 VEE = -5V VEE = -3.3V 80 JITTER - ps JITTER - ps 80 60 PK-PK 40 60 PK-PK 40 20 20 RMS RMS 0 0 0 5 10 15 20 0 25 5 Figure 9. Jitter vs. IOUT 1.5 Gbps, PRBS 23 VEE = -5V JITTER - ps JITTER - ps 25 80 80 60 PK-PK 40 60 PK-PK 40 20 20 RMS RMS 0 -25 0 25 50 75 TEMPERATURE - C 100 0 -25 125 0 50 75 25 TEMPERATURE - C 100 125 Figure 13. Jitter vs. Temperature 1.5 Gbps, PRBS 23 Figure 10. Jitter vs. Temperature 1.5 Gbps, PRBS 23 100 100 VOLTAGE (INNER EYE) 80 VOLTAGE (INNER EYE) 80 TIME DOMAIN TIME DOMAIN 60 PERCENT PERCENT 20 100 VEE = -3.3V VEE = -3.3V 40 223-1 PSEUDO-RANDOM BIT STREAM, ERROR-FREE AREA ERROR-FREE PERCENTAGE VALUE WAS COMPUTED USING THE FOLLOWING FORMULA: (DATA_PERIOD - PPJITTER) 100 / DATA_PERIOD TIME DOMAIN VINNER 100 / VINNER @500Mbps VOLTAGE (INNER EYE) 20 0 500 1000 60 VEE = -5V 40 223-1 PSEUDO-RANDOM BIT STREAM, ERROR-FREE AREA ERROR-FREE PERCENTAGE VALUE WAS COMPUTED USING THE FOLLOWING FORMULA: (DATA_PERIOD - PPJITTER) 100 / DATA_PERIOD TIME DOMAIN VINNER 100 / VINNER @500Mbps VOLTAGE (INNER EYE) 20 0 1500 0 DATA RATE - Mbps 1000 500 DATA RATE - Mbps Figure 14. AC Performance Figure 11. AC Performance REV. 0 15 Figure 12. Jitter vs. IOUT 1.5 Gbps, PRBS 23 100 0 10 IOUT - mA IOUT - mA -9- 1500 100 150 80 100 PROPAGATION DELAY - ps FREQUENCY AD8150 60 40 50 0 20 -50 0 560 580 600 620 640 660 DELAY - ps 680 700 -100 -25 710 25 50 TEMPERATURE - C 75 100 Figure 18. Propagation Delay, Normalized at 25 C vs. Temperature Figure 15. Variation in Channel-to-Channel Delay, All 561 Points 100 16.5 80 JITTER - ps 17.0 16.0 15.5 15.0 60 PK-PK 40 20 RMS 14.5 -3.3 -3.6 -3.9 -4.2 VEE - Volts -4.7 0 3.0 -5.0 Figure 16. IOUT vs. Supply, VEE 3.5 4.0 4.5 SUPPLY VOLTAGE - VCC, VEE 5.0 Figure 19. Jitter vs. Supply, 1.5 Gbps, PRBS 23 +1V +1V 95.55 RISE 96.32 FALL 20% PROXIMAL 80% DISTAL 87.11 RISE 87.36 FALL 20% PROXIMAL 80% DISTAL 200mV/DIV 200mV/DIV IOUT - mA 0 -1V -1V 200ps/DIV 200ps/DIV Figure 17. Rise/Fall Times, VEE = -3.3 V Figure 20. Rise/Fall Times, VEE = -5 V -10- REV. 0 AD8150 +500mV 100mV/DIV 100mV/DIV +500mV -500mV -500mV 200ps/DIV 100ps/DIV Figure 21. Eye Pattern, VEE = -3.3 V, 1.5 Gbps PRBS 23 VCC VCC HP8133A PRBS GENERATOR VTT RL = 50 1.65k Figure 23. Eye Pattern, VEE = -5 V, 1.5 Gbps PRBS 23 AD8150 p TEKTRONIX 11801B p 50 105 IN OUT n SD22 SAMPLING HEAD n 50 1.65k VEE VEE RL = 50 VTT VCC = 0V, VEE = -3.3V OR -5V, VTT = -1.6V RSET = 1.54k, IOUT = 16mA, VOH = -0.8V, VOL = -1.8V INTRINSIC JITTER OF HP8133A AND TEKTRONIX 11801B = 3ps RMS, 17ps PK-PK Figure 22. Eye Pattern Test Circuit REV. 0 -11- AD8150 Control Interface Truth Tables The following are truth tables for the control interface. Table I. Basic Control Functions Reset CS Control Pins WE RE Update Function 0 1 X 1 X X X X X X 1 0 0 X X 1 0 X 0 X 1 0 X X 0 1 0 0 1 0 Global Reset. Reset all second rank enable bits to zero (disable all outputs). Control Disable. Ignore all logic (but the signal matrix still functions as programmed). D[6:0] are high-impedance. Single Output Preprogram. Write input configuration data from data bus D[6:0]. into first rank of latches for the output selected by the output address bus A[4:0]. Single Output Readback. Readback input configuration data from second rank of latches onto data bus D[6:0] for the single output selected by the output address bus A[4:0]. Global Update. Copy input configuration data from all 17 first rank latches into second rank of latches, updating signal matrix connections for all outputs. Transparent Write and Update. It is possible to write data directly onto rank two. This simplifies logic when synchronous signal matrix updating is not necessary. Table II. Address/Data Examples Output Address Pins MSB-LSB Enable Bit Input Address Pins MSB-LSB A4 A3 A2 A1 A0 D6/E D5 D4 D3 D2 D1 D0 Function 0 0 0 0 0 X 0 0 0 0 0 0 Lower Address/Data Range. Connect Output #00 (A[4:0] = 00000) to Input #00 (D[5:0] = 000000). 1 0 0 0 0 X 1 0 0 0 0 0 Upper Address/Data Range. Connect Output #16 (A[4:0] = 10000) to Input #32 (D[5:0] = 100000). <Binary Output Number*> 1 <Binary Output Number*> 0 1 0 0 0 1 X 1 0 0 1 0 X <Binary Input Number> X X X X X Enable Output. Connect Selected Output (A[4:0] = 0 to 16) to Designated Input (D[5:0] = 0 to 32) and Enable Output (D6 = 1). X <Binary Input Number> 1 0 0 0 0 Disable Output. Disable Specified Output (D6 = 0). Broadcast Connection. Connect all 17 outputs to same designated input and set all 17 enable bits to the value of D6. Readback is not possible with the broadcast address. 1 Reserved. Any address or data code greater or equal to these are reserved for future expansion or factory testing. *The binary output number may also be the broadcast connection designator, 10001X. -12- REV. 0 AD8150 Control Interface Timing Diagrams CS INPUT WE INPUT A[4:0] INPUTS D[6:0] INPUTS tCSW tCHW tASW tAHW tWP tDSW tDHW Figure 25. First Rank Write Cycle Table III. First Rank Write Cycle Symbol Parameter tCSW tASW tDSW Setup Time Chip Select to Write Enable Address to Write Enable Data to Write Enable tCHW tAHW tDHW Hold Time Chip Select from Write Enable Address from Write Enable Data from Write Enable tWP Width of Write Enable Pulse Conditions Min Typ Max Unit TA = 25C VDD = 5 V VCC = 5 V 0 0 15 ns ns ns 0 0 0 ns ns ns 15 ns CS INPUT UPDATE INPUT ENABLING OUT[0:16][N:P] OUTPUTS DATA FROM RANK 1 TOGGLE OUT[0:16][N:P] OUTPUTS PREVIOUS RANK 2 DATA DISABLING OUT[0:16][N:P] OUTPUTS DATA FROM RANK 2 tCSU DATA FROM RANK 1 tCHU tUW tUOE tUOD tUOT Figure 26. Second Rank Update Cycle Table IV. Second Rank Update Cycle Symbol Parameter tCSU tCHU tUOE tUOT tUOD Setup Time Hold Time Output Enable Times Output Toggle Times Output Disable Times tUW Width of Update Pulse REV. 0 Chip Select to Update Chip Select from Update Update to Output Enable Update to Output Reprogram Update to Output Disabled Conditions Min TA = 25C VDD = 5 V VCC = 5 V 0 0 25 25 25 15 -13- Typ Max Unit 40 40 30 ns ns ns ns ns ns AD8150 CS INPUT UPDATE INPUT WE INPUT ENABLING OUT[0:16][N:P] OUTPUTS DISABLING OUT[0:16][N:P] OUTPUTS INPUT {DATA 1} INPUT {DATA 2} INPUT {DATA 1} INPUT {DATA 0} tCSU tCHU tUW tUOT tWOT tUOE tWHU tWOD Figure 27. First Rank Write Cycle and Second Rank Update Cycle Table V. First Rank Write Cycle and Second Rank Update Cycle Symbol Parameter Conditions Min 0 0 tCSU tCHU Setup Time Hold Time Chip Select to Update Chip Select from Update TA = 25C VDD = 5 V tUOE tWOE* Output Enable Times Update to Output Enable Write Enable to Output Enable VCC = 5 V tUOT tWOT Output Toggle Times tUOD* tWOD Typ Max Unit ns ns 25 25 40 40 ns ns Update to Output Reprogram Write Enable to Output Reprogram 25 25 30 30 ns ns Output Disable Times Update to Output Disabled Write Enable to Output Disabled 25 25 30 30 ns ns tWHU Setup Time Write Enable to Update tUW Width of Update Pulse 10 ns 15 ns *Not Shown. CS INPUT RE INPUT A[4:0] INPUTS ADDR 1 ADDR 2 DATA {ADDR1} D[6:0] OUTPUTS DATA {ADDR2} tCSR tRDE tAA tCHR tRHA tRDD Figure 28. Second Rank Readback Cycle Table VI. Second Rank Readback Cycle Symbol Parameter Conditions Min 0 0 5 tCSR tCHR tRHA Setup Time Hold Time Chip Select to Read Enable Chip Select from Read Enable Address from Read Enable TA = 25C VDD = 5 V VCC = 5 V tRDE tAA tRDD Enable Time Access Time Release Time Data from Read Enable Data from Address Data from Read Enable 10 k 20 pF on D[6:0] Bus -14- Typ Max Unit ns ns ns 15 15 15 30 ns ns ns REV. 0 AD8150 RESET INPUT DISABLING OUT[0:16][N:P] OUTPUTS tTOD tTW Figure 29. Asynchronous Reset Table VII. Asynchronous Reset Symbol tTOD tTW Parameter Disable Time Width of Reset Pulse Output Disable from Reset Conditions Min TA = 25C VDD = 5 V VCC = 5 V 15 Typ Max Unit 25 30 ns ns Control Interface Programming Example The following conservative pattern connects all outputs to input number 7, except output 16 which is connected to input number 32. The vector clock period, T0 is 15 ns. It is possible to accelerate the execution of this pattern by deleting vectors 1, 4, 7, and 9. Table VIII. Basic Test Pattern Vector No. Reset CS WE RE Update A[4:0] D[6:0] Comments 0 1 2 3 4 5 6 7 8 9 10 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 xxxxx xxxxx 10001 10001 10001 10000 10000 10000 xxxxx xxxxx xxxxx xxxxxxx xxxxxxx 1000111 1000111 1000111 1100000 1100000 1100000 xxxxxxx xxxxxxx xxxxxxx Disable All Outputs REV. 0 -15- All Outputs to Input #07 Write to First Rank Output #16 to Input #32 Write to First Rank Transfer to Second Rank Disable Interface AD8150 7 UPDATE RESET 7 7 7 7 7 7 D[0:6] 0 0 1 1 2 2 7 CONTROL PIN DESCRIPTION A[4:0] Inputs TO 1733 SWITCH MATRIX 33 7 7 7 33 7 7 33 7 33 Output address pins. The binary encoded address applied to these five input pins determines which one of the seventeen outputs is being programmed (or being read back). The most significant bit is A4. D[6:0] Inputs/Outputs 7 7 16 16 RANK 1 RANK 2 7 17 ROWS OF 7-BIT LATCHES Input configuration data pins. In write mode, the binary encoded data applied to pins D[6:0] determine which one of 33 inputs is to be connected to the output specified with the A[4:0] pins. The most significant bit is D5, and the least significant bit is D0. Bit D6 is the enable bit, setting the specified output signal pair to an enabled state if D6 is logic HIGH, or disabled to a high-impedance state if D6 is logic LOW. 1 OF 33 DECODERS WE In readback mode, pins D[6:0] are low-impedance outputs indicating the data word stored in the second rank for the output specified with the A[4:0] pins. The readback drivers were designed to drive high impedances only, so external drivers connected to the D[6:0] should be disabled during readback mode. 1 OF 17 DECODERS A[0:4] RE WE Input Figure 30. Control Interface (Simplified Schematic) AD8150 CONTROL INTERFACE The AD8150 control interface receives and stores the desired connection matrix for the 33 input and 17 output signal pairs. The interface consists of 17 rows of double-rank 7-bit latches, one row for each output. The 7-bit data word stored in each of these latches indicates to which (if any) of the 33 inputs the output will be connected. One output at a time can be preprogrammed by addressing the output and writing the desired connection data into the first rank of latches. This process can be repeated until each of the desired output changes has been preprogrammed. All output connections can then be programmed at once by passing the data from the first rank of latches into the second rank. The output connections always reflect the data programmed into the second rank of latches, and do not change until the first rank of data is passed into the second rank. If necessary for system verification, the data in the second rank of latches can be read back from the control interface. At any time, a reset pulse can be applied to the control interface to globally reset the appropriate second rank data bits, disabling all 17 signal output pairs. This feature can be used to avoid output bus contention on system start-up. The contents of the first rank remain unchanged. The control interface pins are connected via logic-level translators. These translators allow programming and readback of the control interface using logic levels different from those in the signal matrix. In order to facilitate multiple chip address decoding, there is a chip-select pin. All logic signals except the reset pulse are ignored unless the chip select pin is active. The chip select pin disables only the control logic interface, and does not change the operation of the signal matrix. The chip select pin does not power down any of the latches, so any data programmed in the latches is preserved. First Rank Write Enable. Forcing this pin to logic LOW allows the data on pins D[6:0] to be stored in the first rank latch for the output specified by pins A[4:0]. The WE pin must be returned to a logic HIGH state after a write cycle to avoid overwriting the first rank data. UPDATE Input Second Rank Write Enable. Forcing this pin to logic LOW allows the data stored in all 17 first rank latches to be transferred to the second rank latches. The signal connection matrix will be reprogrammed when the second rank data is changed. This is a global pin, transferring all 17 rows of data at once. It is not necessary to program the address pins. It should be noted that after initial power-up of the device, the first rank data is undefined. It may be desirable to preprogram all seventeen outputs before performing the first update cycle. RE Input Second Rank Read-Enable. Forcing this pin to logic LOW enables the output drivers on the bidirectional D[6:0] pins, entering the readback mode of operation. By selecting an output address with the A[4:0] pins and forcing RE to logic LOW, the 7-bit data stored in the second rank latch for that output address will be written to D[6:0] pins. Data should not be written to the D[6:0] pins externally while in readback mode. The RE and WE pins are not exclusive, and may be used at the same time, but data should not be written to the D[6:0] pins from external sources while in readback mode. CS Input Chip-Select. This pin must be forced to logic LOW in order to program or receive data from the logic interface, with the exception of the RESET pin, described below. This pin has no effect on the signal pairs and does not alter any of the stored control data. RESET Input Global Output Disable Pin. Forcing the RESET pin to logic LOW will reset the enable bit, D6, in all 17 second rank latches, regardless of the state of any other pins. This has the effect of immediately disabling the 17 output signal pairs in the All control pins are level-sensitive, not edge-triggered. -16- REV. 0 AD8150 matrix. It is useful to momentarily hold RESET at a logic LOW state when powering up the AD8150 in a system that has multiple output signal pairs connected together. Failure to do this may result in several signal outputs contending after power-up. The reset pin is not gated by the state of the chip-select pin, CS. It should be noted that the RESET pin does not program the first rank, which will contain undefined data after power-up. CONTROL INTERFACE TRANSLATORS The AD8150 control interface has two supply pins, VDD and VSS. The potential between the positive logic supply VDD and the negative logic supply VSS must be at least 3 V and no more than 5 V. Regardless of supply, the logic threshold is approximately 1.6 V above VSS, allowing the interface to be used with most CMOS and TTL logic drivers. In order to maintain signal fidelity at the high data rates supported by the AD8150, the input transmission lines should be terminated as close to the input pins as possible. The preferred input termination structure will depend primarily on the application and the output circuit of the data source. Standard ECL components have open emitter outputs that require pull-down resistors. Three input termination networks suitable for this type of source are shown in Figure 32. The characteristic impedance of the transmission line is shown as ZO. The resistors, R1 and R2, in the Thevenin termination are chosen to synthesize a VTT source with an output resistance of ZO and an open-circuit output voltage equal to VCC - 2 V. The load resistors (RL) in the differential termination scheme are needed to bias the emitter followers of the ECL source. VCC The signal matrix supplies, VCC and VEE, can be set independent of the voltage on VDD and VSS, with the constraints that (VDD-VEE) 10 V. These constraints will allow operation of the control interface on 3 V or 5 V while the signal matrix is operated on 3.3 V or 5 V PECL, or -3.3 V or -5 V ECL. VCC ECL SOURCE CIRCUIT DESCRIPTION The AD8150 is a high-speed 33 x 17 differential crosspoint switch designed for data rates up to 1.5 Gbps per channel. The AD8150 supports PECL-compatible input and output levels when operated from a 5 V supply (VCC = 5 V, VEE = GND) or ECL-compatible levels when operated from a -5 V supply (VCC = GND, VEE = -5 V). To save power, the AD8150 can run from a 3.3 V supply to interface with low-voltage PECL circuits or a -3.3 V supply to interface with low-voltage ECL circuits. The AD8150 utilizes differential current mode outputs with individual disable control, which facilitates busing together the outputs of multiple AD8150s to assemble larger switch arrays. This feature also reduces system crosstalk and can greatly reduce power dissipation in a large switch array. A single external resistor programs the current for all enabled output stages, allowing for user control over output levels with different output termination schemes and transmission line characteristic impedances. High-Speed Data Inputs (INxxP, INxxN) The AD8150 has 33 pairs of differential voltage-mode inputs. The common-mode input range extends from the positive supply voltage (VCC) down to include standard ECL or PECL input levels (VCC - 2 V). The minimum differential input voltage is less than 300 mV. Unused inputs may be connected directly to any level within the allowed common-mode input range. A simplified schematic of the input circuit is shown in Figure 31. VCC INxxN INxxP ZO INxxN ZO R1 ZO INxxP ZO ZO ZO ECL SOURCE R1 INxxN INxxP R2 R2 VEE VTT = VCG2V (a) (b) VCC ZO ZO ECL SOURCE RL INxxN 2ZO INxxP RL VEE (c) Figure 32. AD8150 Input Termination from ECL/PECL Sources: a) Parallel Termination Using VTT Supply, b) Thevenin Equivalent Termination, c) Differential Termination If the AD8150 is driven from a current mode output stage such as another AD8150, the input termination should be chosen to accommodate that type of source, as explained in the following section. High-Speed Data Outputs (OUTyyP, OUTyyN) The AD8150 has 17 pairs of differential current-mode outputs. The output circuit, shown in Figure 33, is an open-collector NPN current switch with resistor-programmable tail current and output compliance extending from the positive supply voltage (VCC) down to standard ECL or PECL output levels (VCC - 2 V). The outputs may be disabled individually to permit outputs from multiple AD8150's to be connected directly. Since the output currents of multiple enabled output stages connected in this way sum, care should be taken to ensure that the output compliance limit is not exceeded at any time; this can be achieved by disabling the active output driver before enabling any inactive driver. VEE Figure 31. Simplified Input Circuit REV. 0 VCC - 2V -17- AD8150 VCC VCC OUTyyP VCOM OUTyyN AD8150 VCC - 2V RCOM RL RL OUTyyN OUTyyP ZO ZO AD8150 OUTyyN OUTyyP ZO IOUT DISABLE RL ZO RL VEE VEE Figure 33. Simplified Output Circuit RECEIVER To ensure proper operation, all outputs (including unused output) must be pulled high using external pull-up networks to a level within the output compliance range. If outputs from multiple AD8150s are wired together, a single pull-up network may be used for each output bus. The pull-up network should be chosen to keep the output voltage levels within the output compliance range at all times. Recommended pull-up networks to produce PECL/ECL 100K and 10K compatible outputs are shown in Figure 34. Alternatively, a separate supply can be used to provide VCOM; making RCOM and DCOM unnecessary. VCC VCOM RL VCC RCOM VCOM DCOM RL RL OUTyyN OUTyyN OUTyyP OUTyyP AD8150 AD8150 RL Figure 35. Double Termination of AD8150 Outputs In this case, the output levels are: VOH = VCOM - (1/4) IOUTRL VOL = VCOM - (3/4) IOUTRL VSWING = VOH - VOL = (1/2) IOUTRL Output Current Set Pin (REF) A simplified schematic of the reference circuit is shown in Figure 36. A single external resistor connected between the REF pin and VEE determines the output current for all output stages. This feature allows a choice of pull-up networks and transmission line characteristic impedances while still achieving a nominal output swing of 800 mV. At low data rates, substantial power savings can be achieved by using lower output swings and higher load resistances. AD8150 Figure 34. Output Pull-Up Networks: a) ECL 100K, b) ECL 10K IOUT/25 VCC REF 1.25V The output levels are simply: RSET VOH = VCOM VEE VOL = VCOM - IOUTRL Figure 36. Simplified Reference Circuit VSWING = VOH - VOL = IOUTRL The resistor value current is given by the following expression: VCOM = VCC - IOUTRCOM (100K Mode) VCOM = VCC - V (DCOM) (10K Mode) The common-mode adjustment element (RCOM or DCOM) may be omitted if the input range of the receiver includes the positive supply voltage. The bypass capacitors reduce common-mode perturbations by providing an ac short from the common nodes (VCOM) to ground. When busing together the outputs of multiple AD8150s or when running at high data rates, double termination of its outputs is recommended to mitigate the impact of reflections due to open transmission line stubs and the lumped capacitance of the AD8150 output pins. A possible connection is shown in Figure 35; the bypass capacitors provide an ac short from the common nodes of the termination resistors to ground. To maintain signal fidelity at high data rates, the stubs connecting the output pins to the output transmission lines or load resistors should be as short as possible. RSET = 25 IOUT Example: RSET = 1.54 k for IOUT = 16.2 mA The minimum set resistor is RSET,min = 1 k resulting in IOUT,max = 25 mA. The maximum set resistor is RSET,max = 5 k resulting in IOUT,min = 5 mA. Nominal 800 mV output swings can be achieved in a 50 load using RSET = 1.56 k (IOUT = 16.2 mA) or in a doubly-terminated 75 load using RSET = 1.17 k (IOUT = 21.3 mA). To minimize stray capacitance and avoid the pickup of unwanted signals, the external set resistor should be located close to the REF pin. Bypassing the set resistor is not recommended. -18- REV. 0 AD8150 the part is to be ac coupled, it is not necessary to have the input/ output common mode at the same level as the other system circuits, but it will probably be more convenient to use the same supply rails for all devices. Power Supplies There are several options for the power supply voltages for the AD8150, as there are two separate sections of the chip that require power supplies. These are the control logic and the high-speed data paths. Depending on the system architecture, the voltage levels of these supplies can vary. Logic Supplies The control (programming) logic is CMOS and is designed to interface with any of the various standard single-ended logic families (CMOS or TTL). Its supply voltage pins are VDD (Pin 170, logic positive) and VSS (Pin 152, logic ground). In all cases the logic ground should be connected to the system digital ground. VDD should be supplied at between 3.3 V to 5 V to match the supply voltage of the logic family that is used to drive the logic inputs. VDD should be bypassed to ground with a 0.1 F ceramic capacitor. The absolute maximum voltage from VDD to VSS is 5.5 V. For PECL operation, VEE will be at ground potential and VCC will be a positive voltage from 3.3 V to 5 V. Thus, the common mode of the inputs and outputs will be at a positive voltage. These can then be dc coupled to other PECL operated devices. If the data paths are ac coupled, then the common-mode levels do not matter, see Figure 38. 3V TO 5V VDD VCC AD8150 DATA PATHS CONTROL LOGIC The data path supplies have more options for their voltage levels. The choices here will affect several other areas, like power dissipation, bypassing, and common mode levels of the inputs and outputs. The more positive voltage supply for the data paths is VCC (Pins 41, 98, 149 and 171). The more negative supply is VEE, which appears on many pins that will not be listed here. The maximum allowable voltage across these supplies is 5.5 V. The first choice in the data path power supplies is to decide whether to run the device as ECL (Emitter-Coupled Logic) or PECL (Positive ECL). For ECL operation, VCC will be at ground potential, while VEE will be at a negative supply between -3.3 V to -5 V. This will make the common-mode voltage of the inputs and outputs at a negative voltage, see Figure 37. 3V TO 5V GND VDD 0.1F (ONE FOR EACH VCC PIN, 4 REQ'D.) 0.1F Data Path Supplies 0.1F 3V TO 5V VEE VSS GND GND Figure 38. Power Supplies and Bypassing for PECL Operation POWER DISSIPATION For analysis, the power dissipation of the AD8150 can be divided into three separate parts. These are the control logic, the data path circuits and the (ECL or PECL) outputs, which are part of the data path circuits, but can be dealt with separately. The first of these, the control logic, is CMOS technology and does not dissipate a significant amount of power. This power will, of course, be greater when the logic supply is 5 V rather than 3 V, but overall it is not a significant amount of power and can be ignored for thermal analysis. VCC AD8150 VDD CONTROL LOGIC VCC ROUT AD8150 DATA PATHS IOUT DATA PATHS CONTROL LOGIC VSS VEE I, DATA PATH LOGIC 0.1F (ONE FOR EVERY TWO VEE PINS) GND VSS 3V TO 5V Figure 37. Power Supplies and Bypassing for ECL Operation If the data paths are to be dc-coupled to other ECL logic devices that run with ground as the most positive supply and a negative voltage for VEE, then this is the proper way to run. However, if REV. 0 GND VOUT LOW - VEE VEE GND Figure 39. Major Power Consumption Paths The data path circuits operate between the supplies VCC and VEE. As described in the power supply section, this voltage can range from 3.3 V to 5 V. The current consumed by this section will be constant, so operating at a lower voltage can save about 40 percent in power dissipation. -19- AD8150 The power dissipated in the data path outputs is affected by several factors. The first is whether the outputs are enabled or disabled. The worst case occurs when all of the outputs are enabled. the pin leads can provide an even lower thermal resistive path. If possible to use, 2 oz. copper foil will provide better heat removal than 1 oz. The current consumed by the data path logic can be approximated by: The AD8150 package has a specified thermal impedance JA of 30C/W. This is the worst case, still-air value that can be expected when the circuit board does not significantly enhance the heat removal from the package. By using the concept described above or by using forced-air circulation, the thermal impedance can be lowered. ICC = 30 mA + [4.5 mA + (IOUT/20 mA x 3 mA)] x (# of outputs enabled) This says that there will always be a minimum of 30 mA flowing. ICC will increase by a factor that is proportional to both the number of enabled outputs and the programmed output current. The power dissipated in this circuit section will simply be the voltage of this section (VCC - VEE) times the current. For a worst case, assume that VCC - VEE is 5.0 V, all outputs are enabled and the programmed output current is 25 mA. The power dissipated by the data path logic will be: P = 5.0 V {25 mA + [4.5 mA + (25 mA/20 mA x 3 mA)] x 17} = 826 mW APPLICATIONS AD8150 INPUT AND OUTPUT BUSING The power dissipated by the output current depends on several factors. These are the programmed output current, the voltage drop from a logic low output to VEE and the number of enabled outputs. A simplifying assumption is that one of each (enabled) differential output pair will be low and draw the full output current (and dissipate most of the power for that output), while the complementary output of the pair will be high and draw insignificant current. Thus, its power dissipation of the high output can be ignored and the output power dissipation for each output can be assumed to occur in a single static low output that sinks the full output-programmed current. The voltage across which this current flows can also vary, depending on the output circuit design and the supplies that are used for the data path circuitry. In general, however, there will be a voltage difference between a logic low signal and VEE. This is the drop across which the output current flows. For a worst case, this voltage can be as high as 3.5 V. Thus, for all outputs enabled and the programmed output current set to 25 mA, the power dissipated by the outputs: Although the AD8150 is a digital part, in any application that runs at high speed, analog design details will have to be given very careful consideration. At high data rates, the design of the signal channels will have a strong influence on the data integrity and its associated jitter and ultimately bit error rate (BER). While it might be considered very helpful to have a suggested circuit board layout for any particular system configuration, this is not something that can be practically realized. Systems come in all shapes, sizes, speeds, performance criteria and cost constraints. Therefore, some general design guidelines will be presented that can be used for all systems and judiciously modified where appropriate. High-speed signals travel best, i.e. maintain their integrity, when they are carried by a uniform transmission line that is properly terminated at either end. Any abrupt mismatches in impedance or improper termination will create reflections that will add to or subtract from parts of the desired signal. Small amounts of this effect are unavoidable, but too much will distort the signal to the point that the channel BER will increase. It is difficult to fully quantify these effects, because they are influenced by many factors in the overall system design. P = 3.5 V (25 mA) x 17 = 1.49 W HEAT SINKING Depending on several factors in its operation, the AD8150 can dissipate upwards of 2 W or more. The part is designed to operate without the need for an explicit external heatsink. However, the package design offers enhanced heat removal via some of the package pins to the PC board traces. The VEE pins on the input sides of the package (Pins 1 to 46 and Pins 93 to 138) have "finger" extensions inside the package that connect to the "paddle" upon which the IC chip is mounted. These pins provide a lower thermal resistance from the IC to the VEE pins than other pins that just have a bond wire. As a result these pins can be used to enhance the heat removal process from the IC to the circuit board and ultimately to the ambient. The VEE pins described above should be connected to a large area of circuit board trace material in order to take most advantage their lower thermal resistance. If there is a large area available on an inner layer that is at VEE potential, then vias can be provided from the package pin traces to this layer. There should be no thermal-relief pattern when connecting the vias to the inner layers for these VEE pins. Additional vias in parallel and close to For an extreme worst case analysis, the junction rise above the ambient can be calculated assuming 2 W of power dissipation and JA of 30C/W to yield a 60C rise above the ambient. There are many techniques described above that can mitigate this situation. Most actual circuits will not result in this high a rise of the junction temperature above the ambient. A constant-impedance transmission line is characterized by having a uniform cross-section profile over its entire length. In particular, there should be no "stubs," which are branches that intersect the main run of the transmission line. These can have an electrical "appearance" that is approximated by a lumped element, such as a capacitor, or if long enough, as another transmission line. To the extent that stubs are unavoidable in a design, their effect can be minimized by making them as short as possible and as high an impedance as possible. Figure 35 shows a differential transmission line that connects two differential outputs from AD8150s to a generic receiver. A more generalized system can have more outputs bused, and more receivers on the same bus, but all the same concepts apply. The inputs of the AD8150 can also be considered as a receiver. The transmission lines that bus all of the devices together are shown with terminations at each end. The individual outputs of the AD8150 are stubs that intersect the main transmission line. Ideally, their current-source outputs would be infinite impedance, and they would have no effect on signals that propagate along the transmission line. In reality, each -20- REV. 0 AD8150 external pin of the AD8150 projects into the package, and has a bond wire connected to the chip inside. On-chip wiring then connects to the collectors of the output transistors and to ESD protection diodes. Unlike some other high-speed digital components, the AD8150 does not have on-chip terminations. While this location would be closer to the actual end of the transmission line for some architectures, this concept can limit system design options. In particular, it is not possible to bus more than two inputs or outputs on the same transmission line and it is also not possible to change the value of these terminations to use for different impedance transmission lines. The AD8150, with the added ability to disable its outputs, is much more versatile in these types of architectures. If the external traces are kept to a bare minimum, then the output will present a mostly lumped capacitive load of about 2 pF. A single stub of 2 pF will not seriously adversely affect signal integrity for most transmission lines, but the more of these stubs, the more adverse their influence will be. One way to mitigate this effect is to locally reduce the capacitance of the main transmission line near the point of stub intersection. Some practical means for doing this are to narrow the PC board traces in the region of the stub and/or to remove some of the ground plane(s) near this intersection. The effect of these techniques will locally lower the capacitance of the main transmission line at these points, while the added capacitance of the AD8150 outputs will "compensate" for this reduction in capacitance. The overall intent is to create as uniform a transmission line as possible. In selecting the location of the termination resistors it is important to keep in mind that, as their name implies, they should be placed at either end of the line. There should be no or minimal projection of the transmission line beyond the point where the termination resistors connect to it. EVALUATION BOARD An evaluation board has been designed and is available to rapidly test the main features of the AD8150. This board lets the user analyze the analog performance of the AD8150 channels and easily control the configuration of the board by a standard PC. Differential inputs and outputs provide the interface for all channels with the connections made by a 50 , SMB-type connector. This type of connector was chosen for its rapid mating and unmating action. The use of SMB-type connectors minimizes the size and minimizes the effort of rearranging interconnects that would be required by using connectors such as SMA-type. Configuration Programming The board is configurable by one of two methods. For ease of use, custom software is provided that controls the AD8150 programming via the parallel port of a PC. This requires a usersupplied standard printer cable that has a DB-25 connector at one end (parallel- or printer-port interface) and a Centronixtype connector at the other that connects to P2 of the AD8150 evaluation board. The programming with this scheme is done in a serial fashion, so it is not the fastest way to configure the AD8150 matrix. However, the user interface makes it very convenient to use this programming method. of the program signals can be a piece of test equipment, like the Tektronix HFS-9000 digital test generator, or some other usersupplied hardware that generates programming signals. When using the PC interface, the jumper at W1 should be installed and no connections should be made to P3. When using the P3 interface, no jumper is installed at W1. There are locations for termination resistors for the address and data signals if these are necessary. Power Supplies The AD8150 is designed to work with standard ECL logic levels. This means that VCC is at ground and VEE is at a negative supply. The shells of the I/O SMB connectors are at VCC potential. Thus, when operating in the standard ECL configuration, test equipment can be directly connected to the board, as the test equipment will have its connector "shells" at ground potential also. Operating in PECL mode requires VCC to be at a positive voltage, while VEE is at ground. Since this would make the shells of the I/O connectors at a positive voltage, it can cause problems when directly connecting to test equipment. Some equipment, such as battery operated oscilloscopes, can be "floated" from ground, but care should be taken with line-powered equipment such that a dangerous situation is not created. Refer to the manual of the test equipment that is being used. The voltage difference from VCC to VEE can range from 3 V to 5 V. Power savings can be realized by operating at a lower voltage without any compromise in performance. A separate connection is provided for VTT, the termination potential of the outputs. This can be at a voltage as high as VCC, but power savings can be realized if VTT is at a voltage that is somewhat lower. Please consult elsewhere in the data sheet for the specification for the limits of the VTT supply. As a practical matter, current on the evaluation board will flow from the VTT supply, through the termination resistors and then through the AD8150 from its outputs to the VEE supply. When running in ECL mode, VTT will want to be at a negative supply. Most power supplies will not allow their ground to connect to VCC and then the negative supply to VTT. This will require them to source current from their negative supply, which will not return to the ground terminal. Thus, VTT should be referenced to VEE when running in ECL mode or a true bipolar supply should be used. The digital supply is provided to the AD8150 by the VDD and VSS pins. VSS should always be at ground potential to make it compatible with standard CMOS or TTL logic. VDD can range from 3 V to 5 V and should be matched to the supply voltage of the logic used to control the AD8150. However, since PCs use 5 V logic on their parallel port, VDD should be at 5 V when using a PC to program the AD8150. Software Installation The software to operate the AD8150 is provided on two 3.5" floppy disks. The software is installed by inserting Disk 1 into the floppy drive of a PC and running the "setup.exe" program. This will routinely install the software and prompt the user when to change to Disk 2. The setup program will also prompt the user to select the directory location to store the program. If a high-speed programming interface is desired, the AD8150 address and data buses are directly available on P3. The source REV. 0 -21- AD8150 After running the software, the user will be prompted to identify which (of three) software driver is used with the PC's parallel port. The default is LPT1, which is most commonly used. However, some laptops commonly use the PRN driver. It is also possible that some systems are configured with the LPT2 driver. If it is not known which driver is used, it is best to select LPT1 and proceed to the next screen. This will show a full array of "buttons" that allows the connection of any input to output of the AD8150. All of the outputs should be in the output "OFF" state right after the program starts running. Any of the active buttons can be selected with a mouse click which will send out one burst of programming data. After this, the PC keyboard's left or right arrow keyboard key can be held down to generate a steady stream of programming signals out of the parallel port. The CLOCK test point on the AD8150 evaluation board can be monitored with an oscilloscope for any activity (user-supplied printer cable must be connected). If there is a square-wave present, then the proper software driver is selected for the PC's parallel port. If there is no signal present, then another driver should be tried by selecting the Parallel Port menu item under the "File" pulldown menu selection just under the title bar. Select a different software driver and carry out the above test until signal activity is present at the CLOCK test point. Software Operation Any button can be clicked in the matrix to program the input to output connection. This will send the proper programming sequence out the PC parallel port. Since only one input can be programmed to a given output at one time, clicking a button in a horizontal row will cancel the other selection that is already selected in that row. However, any number of outputs can share the same input. Refer to Figure 40. A shortcut for programming all outputs to the same input is to use the broadcast feature. After clicking on the Broadcast Connection button, a window will appear that will prompt for the user to select which input should be connected to all outputs. The user should type in an integer from 0 to 32 and then click on OK. This will send out the proper program data and return to the main screen with a full column of buttons selected under the chosen input. The Off column can be used to disable to whichever output one chooses. To disable all outputs, the Global Reset button can be clicked. This will select the full column of OFF buttons. Two scratchpad memories (Memory 1 and Memory 2) are provided to conveniently save a particular configuration. However, these registers are erased when the program is terminated. For long-term storage of configurations, the disk-storage memory should be used. The Save and Load selections can be accessed from the "File" pull-down menu under the title bar. -22- REV. 0 AD8150 Figure 40. REV. 0 -23- AD8150 Figure 41. Component Side -24- REV. 0 AD8150 Figure 42. Circuit Side REV. 0 -25- AD8150 Figure 43. Silkscreen Top -26- REV. 0 AD8150 Figure 44. Soldermask Top REV. 0 -27- AD8150 Figure 45. Silkscreen Bottom -28- REV. 0 AD8150 Figure 46. Soldermask Bottom REV. 0 -29- AD8150 Figure 47. INT1 (VEE) -30- REV. 0 AD8150 Figure 48. INT2 (VCC) REV. 0 -31- VEE IN20P IN20N V C31 EE VCC 0.01F C32 VEE VCC 0.01F IN21P IN21N IN22P IN22N VEE IN23P IN23N VEE IN24P IN24N VEE IN25P IN25N VEE IN26P IN26N VEE IN27P IN27N VEE IN28P IN28N VEE IN29P IN29N VEE IN30P IN30N VEE IN31P IN31N VEE IN32P IN32N VEE VEE VCC C30 139 140 141 IN13N IN13P VEE 0.01F 0.01F VCC 0.01F C10 VEE 142 IN14N IN14P 143 144 145 146 147 IN15N IN15P VEE C9 VCC C8 0.01F VEE 148 149 150 151 152 153 154 155 157 156 158 159 160 163 161 164 162 165 166 167 168 169 VCC 0.01F VCC C12 R203 1.5k C14 VSS 0.01F 0.01F C13 VEE VDD RESET CS RE WE UPDATE A0 A1 A2 A3 A4 D0 D1 D2 D3 D4 D5 D6 170 172 171 IN16N IN16P 173 174 175 VDD VEE VEE VCC 0.01F VCC C5 0.01F VEE C6 176 177 IN17N IN17P VEE 178 IN18N IN18P 179 180 184 183 0.01F 181 C29 VEE VCC 182 IN19N IN19P VEE C4 0.01F VCC C7 0.01F VCC VEE AD8150 1 138 PIN 1 IDENTIFIER 2 3 4 137 136 135 134 5 6 7 133 132 8 131 9 130 10 129 11 128 12 13 127 126 14 15 125 16 123 17 122 18 121 19 120 124 20 119 21 22 118 AD8150 184L LQFP 23 24 117 116 115 TOP VIEW (Not to Scale) 25 114 26 113 27 112 28 111 110 29 30 31 109 108 32 33 107 106 34 105 35 104 36 103 37 102 38 101 39 40 100 VEE C11 VEE VCC OUT16N 0.01F VCC C15 OUT16P 0.01F V 41 42 98 EE 45 97 96 95 94 VEE 46 93 99 43 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 71 72 70 69 67 68 66 65 64 63 62 61 60 59 58 57 56 55 53 54 52 51 50 49 48 VCC VEE VEE OUT00P C60 OUT00N 0.01F VEE VEE VEE OUT15N OUT15P VEE OUT14N OUT14P VEE OUT13N OUT13P VEE OUT12N OUT12P VEE OUT11N OUT11P VEE OUT10N OUT10P VEE OUT09N OUT09P VEE OUT08N OUT08P VEE OUT07N OUT07P VEE OUT06N OUT06P VEE OUT05N OUT05P VEE OUT04N OUT04P VEE OUT03N OUT03P VEE OUT02N OUT02P VEE OUT01N OUT01P VEE 47 44 VEE IN12N IN12P VEE IN11N IN11P VEE IN10N IN10P VEE IN09N IN09P VEE IN08N IN08P VEE IN07N IN07P VEE IN06N IN06P VEE IN05N IN05P VEE IN04N IN04P VEE IN03N IN03P VEE IN02N IN02P VEE IN01N IN01P VEE IN00N IN00P VEE Figure 49. Bypassing Schematic -32- REV. 0 REV. 0 Figure 50. -33- P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 IN00N IN01N P20 P22 IN04N IN05N VEE R35 1.65k R36 105 P27 VCC IN11N VEE R55 1.65k R54 105 R53 1.65k IN11P VEE R37 1.65k IN05P IN10N R52 1.65k R51 105 VCC P26 P25 P24 R50 1.65k IN10P VEE R32 1.65k R33 105 R34 1.65k IN04P VEE VCC IN09N R49 1.65k VEE P23 R48 105 VCC IN03N R29 1.65k R30 105 R47 1.65k IN09P VCC VCC R31 1.65k IN03P VEE IN08N R46 1.65k R45 105 VEE IN02N R26 1.65k R27 105 P21 VCC VCC R44 1.65k IN08P VEE R28 1.65k IN02P IN07N R43 1.65k R42 105 VEE R23 1.65k R24 105 P19 VCC R41 1.65k IN07P VEE R25 1.65k IN01P IN06N R38 1.65k R39 105 VCC P18 P17 P16 R40 1.65k IN06P VCC VEE R21 1.65k R20 105 R19 1.65k IN00P VCC P39 P38 P37 P36 P35 P34 P33 P32 P31 P30 P29 P28 IN12N IN13N IN16N IN17N VEE R73 1.65k R72 105 R71 1.65k IN17P VCC VEE R70 1.65k R69 105 R68 1.65k IN16P VCC VEE IN15N R67 1.65k R66 105 R65 1.65k IN15P VCC VEE IN14N R64 1.65k R63 105 R62 1.65k IN14P VCC VEE R61 1.65k R60 105 R59 1.65k IN13P VCC VEE R56 1.65k R57 105 R58 1.65k IN12P VCC P51 P50 P49 P48 P47 P46 P45 P44 P43 P42 P41 P40 IN18N IN19N IN22N IN23N VEE R74 1.65k R75 105 R76 1.65k IN23P VCC VEE R77 1.65k R78 105 R79 1.65k IN22P VCC VEE IN21N R80 1.65k R81 105 R82 1.65k IN21P VCC VEE IN20N R83 1.65k R84 105 R85 1.65k IN20P VCC VEE R86 1.65k R87 105 R88 1.65k IN19P VCC VEE R91 1.65k R90 105 R89 1.65k IN18P VCC P63 P62 P61 P60 P59 P58 P57 P56 P55 P54 P53 P52 IN24N IN25N IN28N IN29N VEE R109 1.65k R108 105 R107 1.65k IN29P VCC VEE R106 1.65k R105 105 R104 1.65k IN28P VCC VEE IN27N R103 1.65k R102 105 R101 1.65k IN27P VCC VEE IN26N R100 1.65k R99 105 R98 1.65k IN26P VCC VEE R97 1.65k R96 105 R95 1.65k IN25P VCC VEE R92 1.65k R93 105 R94 1.65k IN24P VCC P69 P68 P67 P66 P65 P64 IN30N IN31N VEE IN32N R110 1.65k R111 105 R112 1.65k IN32P VCC VEE R113 1.65k R114 105 R115 1.65k IN31P VCC VEE R118 1.65k R117 105 R116 1.65k IN30P VCC OUT08P OUT16N OUT16P OUT15N OUT15P OUT14N OUT14P OUT13N OUT13P OUT12N OUT12P OUT11N OUT11P OUT10N OUT10P OUT09N OUT09P OUT08N R198 49.9 R200 49.9 R192 49.9 R190 49.9 R193 49.9 R195 49.9 R182 49.9 R180 49.9 R183 49.9 R185 49.9 R172 49.9 R170 49.9 R173 49.9 R175 49.9 R163 49.9 R165 49.9 R162 49.9 R160 49.9 OUT00P OUT06N OUT06P OUT05N OUT05P OUT04N OUT04P OUT03N OUT03P OUT02N OUT02P OUT01N OUT01P OUT00N P70 VTT P71 P72 VTT VTT VTT VTT OUT07N P73 OUT07P P74 VTT P75 P76 VTT P77 P78 VTT P79 P80 VTT P81 P82 VTT P83 P84 VTT P85 P86 VTT P87 C83 0.01F C82 0.01F C16 0.01F R153 49.9 R155 49.9 R152 49.9 R150 49.9 R143 49.9 R145 49.9 R142 49.9 R140 49.9 R133 49.9 R135 49.9 R132 49.9 R130 49.9 R127 49.9 R125 49.9 R122 49.9 R121 49.9 VCC VCC VCC P88 VTT P89 P90 VTT P91 P92 VTT P93 P94 VTT P95 P96 VTT P97 P98 VTT P99 P100 VTT P101 P102 VTT P103 AD8150 C3 + 10F VTT VTT VSS P2 25 DATA P2 5 VDD -34- P3 13 P3 7 P3 11 P3 27 P3 25 P3 23 P3 21 P3 19 P3 17 P3 39 P3 37 P3 35 P3 33 P3 31 P3 29 P3 15 P3 9 P3 5 WRITE RESET READ D0 A4 A3 A2 A1 A0 D6 D5 D4 D3 D2 D1 UPDATE CHIP_SELECT VDD VSS P3 14 P3 8 P3 12 P3 28 P3 26 P3 24 P3 22 P3 20 P3 18 P3 40 P3 38 P3 36 P3 34 P3 32 P3 30 P3 16 P3 10 P3 6 P2 7 P2 3 P2 8 P2 4 P2 2 READ RESET WRITE UPDATE CHIP_SELECT VSS C89 0.1F VDD VSS C88 0.1F VDD VSS C87 0.1F VDD A1, 4 PIN 14 IS TIED TO VDD. A1, 4 PIN 7 IS TIED TO VSS. VSS C86 0.1F P104 P105 VCC P1 1 VCC P1 2 + VCC C1 10F VEE VEE P1 3 VEE P1 4 VDD P1 7 V + C2 DD 10F VSS P1 5 VSS VTT P1 6 CLK P2 6 1 A1 2 VSS VDD VSS A1 VSS VSS VSS VSS VSS W1 R1 20k VSS VDD R2 49.0 49.0 R6 49.0 R5 49.0 R4 49.0 R3 6 74HC14 4 5 74HC14 VDD VSS 3 A1 DATA 74HC14 CLK A4 A2 19 20 VSS VSS VSS VSS VSS 162A2 163A1 164A0 49.0 R9 49.0 R10 49.0 R11 A4 READ 167 RESET 169 WRITE 166 UPDATE 165 CHIP_SELECT 168 TP7 TP8 TP4 TP5 TP6 74HC132 5 4 161A3 49.0 160A4 R7 VDD 49.0 R8 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 CLK VCC 74HC74 GND D6 D7 D4 D5 D2 D3 D0 D1 OUT_EN 74HC132 2 1 10 8 9 6 7 4 5 3 2 1 VSS VDD TP9 TP10 TP11 TP12 TP13 A3 OUT_EN VCC 19 20 VSS VSS VSS VSS VSS VSS VSS Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 CLK 74HC74 D0 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10 GND 2 1 49.0 49.0 R18 49.0 R17 49.0 R15 49.0 R16 49.0 R14 49.0 R13 R12 VDD 159D0 158D1 157D2 156D3 155D4 154D5 153D6 VDD A1 8 12 74HC132 74HC132 A4 12 13 10 74HC14 A4 9 74HC14 A1 13 74HC14 A1 11 10 9 TP14 TP15 TP16 TP17 TP18 TP19 TP20 11 8 VCC J1 J26 J35 J39 J16 J41 J49 J50 J24 J47 J48 J22 J23 J25 J45 J46 J20 J44 J43 J42 J21 J19 J18 J17 J40 J14 J15 J38 J37 J36 J13 J12 J11 J10 J33 J34 J8 J32 J31 J30 J9 J7 J6 J5 J28 J29 J27 J3 VCC J4 J2 VEE VEE AD8150 Figure 51. REV. 0 AD8150 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.063 (1.60) MAX 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) SEATING PLANE 0.866 (22.00) BSC SQ 0.787 (20.00) BSC SQ 186 1 139 138 PIN 1 C3765-3-3/00 (rev. 0) 184-Lead Plastic LQFP (ST-184) TOP VIEW (PINS DOWN) 0.003 (0.08) 0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.40) 0.048 (1.35) 46 47 93 92 0.016 (0.40) BSC 0.009 (0.23) 0.007 (0.18) 0.005 (0.13) PRINTED IN U.S.A. CONTROLLING DIMENSIONS ARE IN MILLIMETERS REV. 0 -35-