REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8150*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
FUNCTIONAL BLOCK DIAGRAM
CS
RE
D
A
WE
UPDATE
RESET
SECOND
RANK
177-BIT
LATCH
3317
DIFFERENTIAL
SWITCH
MATRIX
INPUT
DECODERS
17
OUTPUT
ADDRESS
DECODER
OUTP
OUTN
7
5
33 33
INP INN
AD8150
17
FIRST
RANK
177-BIT
LATCH
FEATURES
Low Cost
33 17, Fully Differential, Nonblocking Array
>1.5 Gbps per Port NRZ Data Rate
Wide Power Supply Range: +5 V, +3.3 V, –3.3 V, –5 V
Low Power
400 mA (Outputs Enabled)
30 mA (Outputs Disabled)
PECL and ECL Compatible
CMOS/TTL-Level Control Inputs: 3 V to 5 V
Low Jitter: <50 ps p-p
No Heat Sinks Required
Drives a Backplane Directly
Programmable Output Current
Optimize Termination Impedance
User-Controlled Voltage at the Load
Minimize Power Dissipation
Individual Output Disable for Busing and Building
Larger Arrays
Double Row Latch
Buffered Inputs
Available in 184-Lead LQFP
APPLICATIONS
HD and SD Digital Video
Fiber Optic Network Switching
33 17, 1.5 Gbps
Digital Crosspoint Switch
*Patent Pending.
X
stream
is a trademark of Analog Devices, Inc.
PRODUCT DESCRIPTION
AD8150 is a member of the X
stream
line of products and is
a breakthrough in digital switching, offering a large switch array
(33 × 17) on very little power, typically less than 1.5 W. Addi-
tionally, it operates at data rates in excess of 1.5 Gbps per port,
making it suitable for HDTV applications. Further, the pric-
ing of the AD8150 makes it affordable enough to be used for
SD applications as well. The AD8150 is also useful for OC-24
optical network switching.
The AD8150’s flexible supply voltages allow the user to operate
with either PECL or ECL data levels and will operate down to
3.3 V for further power reduction. The control interface is CMOS/
TTL compatible (3 V to 5 V).
Its fully differential signal path reduces jitter and crosstalk while
allowing the use of smaller single-ended voltage swings.
The AD8150 is offered in a 184-lead LQFP package that operates
over the industrial temperature range of 0°C to 85°C.
500mV
100mV
/DIV
–500mV
100ps/DIV
Figure 1. Output Eye Pattern, 1.5 Gbps
stream
ª
–2– REV. 0
AD8150–SPECIFICATIONS
(@ 25C, VCC = 3.3 V to 5 V, VEE = 0 V, RL = 50 (see Figure 22), IOUT = 16 mA, unless
otherwise noted)
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
Max Data Rate/Channel (NRZ) 1.5 Gbps
Channel Jitter Data Rate < 1.5 Gbps 50 ps p-p
RMS Channel Jitter V
CC
= 5 V 10 ps
Propagation Delay Input to Output 650 ps
Propagation Delay Match 50 100 ps
Output Rise/Fall Time 20% to 80% 100 ps
INPUT CHARACTERISTICS
Input Voltage Swing Differential 200 1000 mV p-p
Input Voltage Range Common-Mode V
CC
– 2 V
CC
V
Input Bias Current 2µA
Input Capacitance 2pF
Input V
IN
High V
CC
– 1.2 V
CC
– 0.2 V
Input V
IN
Low V
CC
– 2.4 V
CC
– 1.4 V
OUTPUT CHARACTERISTICS
Output Voltage Swing Differential (See Figure 22) 800 mV p-p
Output Voltage Range V
CC
– 1.8 V
CC
V
Output Current 5 25 mA
Output Capacitance 2pF
POWER SUPPLY
Operating Range
PECL, V
CC
V
EE
= 0 V 3.3 5 V
ECL, V
EE
V
CC
= 0 V –5 –3.3 V
V
DD
35V
V
SS
0V
Quiescent Current
V
DD
2mA
V
EE
All Outputs Enabled, I
OUT
= 16 mA 400 mA
T
MIN
to T
MAX
450 mA
All Outputs Disabled 30 mA
THERMAL CHARACTERISTICS
Operating Temperature Range 0 85 °C
θ
JA
30 °C/W
LOGIC INPUT CHARACTERISTICS V
DD
= 3 V dc to 5 V dc
Input V
IN
High 1.9 V
DD
V
Input V
IN
Low 0 0.9 V
AD8150
–3–
REV. 0
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8150 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8150
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of
the plastic, approximately 150°C. Temporarily exceeding this
limit may cause a shift in parametric performance due to a change
in the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can result in
device failure.
While the AD8150 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction temp-
erature (150°C) is not exceeded under all conditions. To ensure
proper operation, it is necessary to observe the maximum power
derating curves shown in Figure 2.
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage V
DD
–V
EE
. . . . . . . . . . . . . . . . . . . . . . . 10.5 V
Internal Power Dissipation
2
AD8150 184-Lead Plastic LQFP (ST) . . . . . . . . . . . . . 4.2 W
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . V
CC
–V
EE
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air (T
A
= 25°C):
184-lead plastic LQFP (ST): θ
JA
= 30°C/W.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD8150AST 0°C to 85°C 184-Lead Plastic LQFP ST-184
(20 mm × 20 mm)
AD8150-EVAL Evaluation Board
AMBIENT TEMPERATURE – C
MAXIMUM POWER DISSIPATION – Watts
–10 0 102030 405060708090
2.0
3.0
4.0
5.0
6.0
T
J
= 150C
1.0
Figure 2. Maximum Power Dissipation vs. Temperature
AD8150
–4– REV. 0
PIN CONFIGURATION
VEE
IN19N
IN19P
VEE
IN18N
IN18P
VEE
IN17N
IN17P
VEE
IN16N
IN16P
VEE
VCC
VDD
RESET
CS
RE
WE
UPDATE
A0
A1
A2
A3
A4
D0
D1
D2
D3
D4
D5
D6
VSS
REF
VEEREF
VCC
VEE
IN15N
IN15P
VEE
IN14N
IN14P
VEE
IN13N
IN13P
VEE
184
183
182
181
180
179
178
177
176
175
174
173
171
170
169
168
167
166
165
164
163
162
172
161
160
159
157
156
155
154
153
152
158
151
150
149
147
146
145
144
143
142
141
140
139
148
VEE
OUT15N
OUT15P
VEEA15
OUT14N
OUT14P
VEEA14
OUT13N
OUT13P
VEEA13
OUT12N
OUT12P
VEEA12
OUT11N
OUT11P
VEEA11
OUT10N
OUT10P
VEEA10
OUT09N
OUT09P
VEEA9
OUT08N
OUT08P
VEEA8
OUT07N
OUT07P
VEEA7
OUT06N
OUT06P
VEEA6
OUT05N
OUT05P
VEEA5
OUT04N
OUT04P
VEEA4
OUT03N
OUT03P
VEEA3
OUT02N
OUT02P
VEEA2
OUT01N
OUT01P
VEEA1
59
60
61
62
63
64
65
66
67
68
47
48
49
50
51
52
53
54
55
56
57
58
69
70
71
72
74
75
76
77
78
73
79
80
81
82
84
85
86
87
83
88
89
90
91
92
5
4
3
2
7
6
9
8
1
14
13
12
11
16
15
17
10
19
18
23
22
21
20
25
24
27
26
29
28
32
31
30
34
33
36
35
40
39
38
37
41
43
42
45
44
46
VEE
IN20P
IN20N
VEE
IN21P
IN21N
VEE
IN22P
IN22N
VEE
IN23P
IN23N
VEE
IN24P
IN24N
VEE
IN25P
IN25N
VEE
IN26P
IN26N
VEE
IN27P
IN27N
VEE
IN28P
IN28N
VEE
IN29P
IN29N
VEE
IN30P
IN30N
VEE
IN31P
IN31N
VEE
IN32P
IN32N
VEE
VCC
VEE
OUT16N
OUT16P
VEEA16
VEE
VEE
IN12N
IN12P
VEE
IN11N
IN11P
VEE
IN10N
IN10P
VEE
IN09N
IN09P
VEE
IN08N
IN08P
VEE
IN07N
IN07P
VEE
IN06N
IN06P
VEE
IN05N
IN05P
VEE
IN04N
IN04P
VEE
IN03N
IN03P
VEE
IN02N
IN02P
VEE
IN01N
IN01P
VEE
IN00N
IN00P
VEE
VCC
VEEA0
OUT00P
OUT00N
VEE
VEE
122
137
138
132
133
134
135
130
131
129
136
127
128
123
124
125
126
120
121
118
119
116
117
113
114
115
111
112
109
110
108
105
106
107
104
102
103
100
101
95
96
97
98
99
93
94
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD8150
184L LQFP
AD8150
–5–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin No. Signal Type Description
1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, V
EE
Power Supply Most Negative PECL Supply (Common with Other
34, 37, 40, 42, 46, 47, 92, 93, 99, 102, Points Labeled V
EE
)
105, 108, 111, 114, 117, 120, 123,
126, 129, 132, 135, 138, 139, 142,
145, 148, 172, 175, 178, 181, 184
2 IN20P PECL High-Speed Input
3 IN20N PECL High-Speed Input Complement
5 IN21P PECL High-Speed Input
6 IN21N PECL High-Speed Input Complement
8 IN22P PECL High-Speed Input
9 IN22N PECL High-Speed Input Complement
11 IN23P PECL High-Speed Input
12 IN23N PECL High-Speed Input Complement
14 IN24P PECL High-Speed Input
15 IN24N PECL High-Speed Input Complement
17 IN25P PECL High-Speed Input
18 IN25N PECL High-Speed Input Complement
20 IN26P PECL High-Speed Input
21 IN26N PECL High-Speed Input Complement
23 IN27P PECL High-Speed Input
24 IN27N PECL High-Speed Input Complement
26 IN28P PECL High-Speed Input
27 IN28N PECL High-Speed Input Complement
29 IN29P PECL High-Speed Input
30 IN29N PECL High-Speed Input Complement
32 IN30P PECL High-Speed Input
33 IN30N PECL High-Speed Input Complement
35 IN31P PECL High-Speed Input
36 IN31N PECL High-Speed Input Complement
38 IN32P PECL High-Speed Input
39 IN32N PECL High-Speed Input Complement
41, 98, 149, 171 V
CC
Power Supply Most Positive PECL Supply (Common with Other
Points Labeled V
CC
)
43 OUT16N PECL High-Speed Output Complement
44 OUT16P PECL High-Speed Output
45 V
EE
A16 Power Supply Most Negative PECL Supply (Unique to This Output)
48 OUT15N PECL High-Speed Output Complement
49 OUT15P PECL High-Speed Output
50 V
EE
A15 Power Supply Most Negative PECL Supply (Unique to this Output)
51 OUT14N PECL High-Speed Output Complement
52 OUT14P PECL High-Speed Output
53 V
EE
A14 Power Supply Most Negative PECL Supply (Unique to this Output)
54 OUT13N PECL High-Speed Output Complement
55 OUT13P PECL High-Speed Output
56 V
EE
A13 Power Supply Most Negative PECL Supply (Unique to this Output)
57 OUT12N PECL High-Speed Output Complement
58 OUT12P PECL High-Speed Output
59 V
EE
A12 Power Supply Most Negative PECL Supply (Unique to this Output)
60 OUT11N PECL High-Speed Output Complement
61 OUT11P PECL High-Speed Output
AD8150
–6– REV. 0
Pin No. Signal Type Description
62 V
EE
A11 Power Supply Most Negative PECL Supply (Unique to this Output)
63 OUT10N PECL High-Speed Output Complement
64 OUT10P PECL High-Speed Output
65 V
EE
A10 Power Supply Most Negative PECL Supply (Unique to this Output)
66 OUT09N PECL High-Speed Output Complement
67 OUT09P PECL High-Speed Output
68 V
EE
A9 Power Supply Most Negative PECL Supply (Unique to this Output)
69 OUT08N PECL High-Speed Output Complement
70 OUT08P PECL High-Speed Output
71 V
EE
A8 Power Supply Most Negative PECL Supply (Unique to this Output)
72 OUT07N PECL High-Speed Output Complement
73 OUT07P PECL High-Speed Output
74 V
EE
A7 Power Supply Most Negative PECL Supply (Unique to this Output)
75 OUT06N PECL High-Speed Output Complement
76 OUT06P PECL High-Speed Output
77 V
EE
A6 Power Supply Most Negative PECL Supply (Unique to this Output)
78 OUT05N PECL High-Speed Output Complement
79 OUT05P PECL High-Speed Output
80 V
EE
A5 Power Supply Most Negative PECL Supply (Unique to this Output)
81 OUT04N PECL High-Speed Output Complement
82 OUT04P PECL High-Speed Output
83 V
EE
A4 Power Supply Most Negative PECL Supply (Unique to this Output)
84 OUT03N PECL High-Speed Output Complement
85 OUT03P PECL High-Speed Output
86 V
EE
A3 Power Supply Most Negative PECL Supply (Unique to this Output)
87 OUT02N PECL High-Speed Output Complement
88 OUT02P PECL High-Speed Output
89 V
EE
A2 Power Supply Most Negative PECL Supply (Unique to this Output)
90 OUT01N PECL High-Speed Output Complement
91 OUT01P PECL High-Speed Output
94 V
EE
A1 Power Supply Most Negative PECL Supply (Unique to this Output)
95 OUT00N PECL High-Speed Output Complement
96 OUT00P PECL High-Speed Output
97 V
EE
A0 Power Supply Most Negative PECL Supply (Unique to this Output)
100 IN00P PECL High-Speed Input
101 IN00N PECL High-Speed Input Complement
103 IN01P PECL High-Speed Input
104 IN01N PECL High-Speed Input Complement
106 IN02P PECL High-Speed Input
107 IN02N PECL High-Speed Input Complement
109 IN03P PECL High-Speed Input
110 IN03N PECL High-Speed Input Complement
112 IN04P PECL High-Speed Input
113 IN04N PECL High-Speed Input Complement
115 IN05P PECL High-Speed Input
116 IN05N PECL High-Speed Input Complement
118 IN06P PECL High-Speed Input
119 IN06N PECL High-Speed Input Complement
121 IN07P PECL High-Speed Input
122 IN07N PECL High-Speed Input Complement
AD8150
–7–
REV. 0
Pin No. Signal Type Description
124 IN08P PECL High-Speed Input
125 IN08N PECL High-Speed Input Complement
127 IN09P PECL High-Speed Input
128 IN09N PECL High-Speed Input Complement
130 IN10P PECL High-Speed Input
131 IN10N PECL High-Speed Input Complement
133 IN11P PECL High-Speed Input
134 IN11N PECL High-Speed Input Complement
136 IN12P PECL High-Speed Input
137 IN12N PECL High-Speed Input Complement
140 IN13P PECL High-Speed Input
141 IN13N PECL High-Speed Input Complement
143 IN14P PECL High-Speed Input
144 IN14N PECL High-Speed Input Complement
146 IN15P PECL High-Speed Input
147 IN15N PECL High-Speed Input Complement
150 V
EE
REF R-Program Connection Point for Output Logic Pull-Down
Programming Resistor (Must be Connected to V
EE
)
151 REF R-Program Connection Point for Output Logic Pull-Down
Programming Resistor
152 V
SS
Power Supply Most Negative Control Logic Supply
153 D6 TTL Enable/Disable Output
154 D5 TTL (32) MSB Input Select
155 D4 TTL (16)
156 D3 TTL (8)
157 D2 TTL (4)
158 D1 TTL (2)
159 D0 TTL (1) LSB Input Select
160 A4 TTL (16) MSB Output Select
161 A3 TTL (8)
162 A2 TTL (4)
163 A1 TTL (2)
164 A0 TTL (1) LSB Output Select
165 UPDATE TTL Second Rank Program
166 WE TTL First Rank Program
167 RE TTL Enable Readback
168 CS TTL Enable Chip to Accept Programming
169 RESET TTL Disable All Outputs (Hi-Z)
170 V
DD
Power Supply Most Positive Control Logic Supply
173 IN16P PECL High-Speed Input
174 IN16N PECL High-Speed Input Complement
176 IN17P PECL High-Speed Input
177 IN17N PECL High-Speed Input Complement
179 IN18P PECL High-Speed Input
180 IN18N PECL High-Speed Input Complement
182 IN19P PECL High-Speed Input
183 IN19N PECL High-Speed Input Complement
AD8150
–8– REV. 0
–Typical Performance Characteristics
VOH – Volts
00
JITTER – ps
–0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4
20
40
60
80
100
VEE = –3.3V (VOH – VOL = 800mV)
PK-PK
RMS
Figure 3. Jitter vs. V
OH
1.5 Gbps, PRBS 23
VIH – Volts
0
–2.0
JITTER – ps
–1.5 –1.0 –0.5 0.0 0.5
20
40
60
80
100
VEE = –3.3V (VIH – VIL = 800mV)
PK-PK
RMS
Figure 4. Jitter vs. V
IH
1.5 Gbps, PRBS 23
0.3
DATA RATE – Gbps
0
0.1
JITTER – ps
0.5 0.7 0.9 1.1 1.3 1.5
20
40
60
80
100
V
EE
= –3.3V
PK-PK
RMS
Figure 5. Jitter vs. Data Rate, PRBS 23
VOH – Volts
00
JITTER – ps
–0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4
20
40
60
80
100
VEE = –5V (VOH – VOL = 800mV)
PK-PK
RMS
Figure 6. Jitter vs. V
OH
1.5 Gbps, PRBS 23
VIH – Volts
0
–2.0
JITTER – ps
–1.5 –1.0 –0.5 0.0 0.5
20
40
60
80
100
VEE = –5V (VIH – VIL = 800mV)
PK-PK
RMS
Figure 7. Jitter vs. V
IH
1.5 Gbps, PRBS 23
0.3
DATA RATE – Gb
p
s
0
0.1
JITTER – ps
0.5 0.7 0.9 1.1 1.3 1.5
20
40
60
80
100
V
EE
= –5V
PK-PK
RMS
Figure 8. Jitter vs. Data Rate, PRBS 23
AD8150
–9–
REV. 0
IOUT – mA
00
JITTER – ps
5 10152025
20
40
60
80
100
PK-PK
RMS
VEE = –3.3V
Figure 9. Jitter vs. I
OUT
1.5 Gbps, PRBS 23
TEMPERATURE – C
0
–25
JITTER – ps
0 50 75 100 125
20
40
60
80
100
PK-PK
RMS
VEE = –3.3V
25
Figure 10. Jitter vs. Temperature 1.5 Gbps, PRBS 23
DATA RATE – Mb
p
s
00
PERCENT
1000 1500
20
40
60
80
100
V
EE
= –3.3V
500
TIME DOMAIN
VOLTAGE (INNER EYE)
2
23
–1 PSEUDO-RANDOM BIT STREAM, ERROR-FREE AREA
ERROR-FREE PERCENTAGE VALUE WAS COMPUTED
USING THE FOLLOWING FORMULA:
(DATA_PERIOD – PPJITTER) 100 / DATA_PERIOD
TIME DOMAIN
V
INNER
100 / V
INNER
@500Mbps
VOLTAGE (INNER EYE)
Figure 11. AC Performance
IOUT – mA
00
JITTER – ps
5 10152025
20
40
60
80
100
PK-PK
RMS
VEE = –5V
Figure 12. Jitter vs. I
OUT
1.5 Gbps, PRBS 23
TEMPERATURE – C
0
–25
JITTER – ps
0 50 75 100 125
20
40
60
80
100
PK-PK
RMS
VEE = –5V
25
Figure 13. Jitter vs. Temperature 1.5 Gbps, PRBS 23
DATA RATE – Mb
p
s
00
PERCENT
1000 1500
20
40
60
80
100
V
EE
= –5V
500
TIME DOMAIN
VOLTAGE (INNER EYE)
2
23
–1 PSEUDO-RANDOM BIT STREAM, ERROR-FREE AREA
ERROR-FREE PERCENTAGE VALUE WAS COMPUTED
USING THE FOLLOWING FORMULA:
(DATA_PERIOD – PPJITTER) 100 / DATA_PERIOD
TIME DOMAIN
V
INNER
100 / V
INNER
@500Mbps
VOLTAGE (INNER EYE)
Figure 14. AC Performance
AD8150
–10– REV. 0
DELAY – ps
0
560
FREQUENCY
580 600 620 640 660 680 700
20
40
60
80
100
710
Figure 15. Variation in Channel-to-Channel Delay,
All 561 Points
VEE – Volts
14.5
–3.3
IOUT – mA
–3.6 –3.9 –4.2 –4.7 –5.0
15.0
15.5
16.0
16.5
17.0
Figure 16. I
OUT
vs. Supply, V
EE
+1V
–1V
200mV/DIV
200
p
s/DIV
95.55 RISE
96.32 FALL
20% PROXIMAL
80% DISTAL
Figure 17. Rise/Fall Times, V
EE
= –3.3 V
TEMPERATURE – C
–100
–25
PROPAGATION DELAY – ps
0 25 50 75 100
–50
0
50
100
150
Figure 18. Propagation Delay, Normalized at 25
°
C vs.
Temperature
SUPPLY VOLTAGE – VCC, VEE
0
JITTER – ps
3.0 3.5 4.0 4.5 5.0
20
40
60
80
100
PK-PK
RMS
Figure 19. Jitter vs. Supply, 1.5 Gbps, PRBS 23
+1V
–1V
200mV/DIV
200ps/DIV
87.11 RISE
87.36 FALL
20% PROXIMAL
80% DISTAL
Figure 20. Rise/Fall Times, V
EE
= –5 V
AD8150
–11–
REV. 0
+500mV
–500mV
100mV/DIV
200
p
s/DIV
Figure 21. Eye Pattern, V
EE
= –3.3 V, 1.5 Gbps PRBS 23
V
CC
HP8133A
PRBS
GENERATOR
AD8150
TEKTRONIX
11801B
SD22
SAMPLING
HEAD
50
50
R
L
= 50
V
CC
V
TT
V
TT
V
EE
V
EE
1.65k
105
1.65k
IN OUT
p
n
p
n
V
CC
= 0V, V
EE
= –3.3V OR –5V, V
TT
= –1.6V
R
SET
= 1.54k, I
OUT
= 16mA, V
OH
= –0.8V, V
OL
= –1.8V
INTRINSIC JITTER OF HP8133A AND TEKTRONIX 11801B = 3ps RMS, 17ps PK-PK
R
L
= 50
Figure 22. Eye Pattern Test Circuit
+500mV
–500mV
100mV/DIV
100ps/DIV
Figure 23. Eye Pattern, V
EE
= –5 V, 1.5 Gbps PRBS 23
AD8150
–12– REV. 0
Control Interface Truth Tables
The following are truth tables for the control interface.
Table I. Basic Control Functions
Control Pins
Reset CS WE RE Update Function
0 XXXX Global Reset. Reset all second rank enable bits to zero (disable all outputs).
1 1 X X X Control Disable. Ignore all logic (but the signal matrix still functions as
programmed). D[6:0] are high-impedance.
1 0 0 X X Single Output Preprogram. Write input configuration data from data bus D[6:0].
into first rank of latches for the output selected by the output address bus A[4:0].
1 0 X 0 X Single Output Readback. Readback input configuration data from second rank of latches
onto data bus D[6:0] for the single output selected by the output address bus A[4:0].
1 0 X X 0 Global Update. Copy input configuration data from all 17 first rank latches into second
rank of latches, updating signal matrix connections for all outputs.
1 0010 Transparent Write and Update. It is possible to write data directly onto rank two. This
simplifies logic when synchronous signal matrix updating is not necessary.
Table II. Address/Data Examples
Output Address Pins Enable Input Address Pins
MSB–LSB Bit MSB-LSB
A4 A3 A2 A1 A0 D6/E D5 D4 D3 D2 D1 D0 Function
00000X 000000Lower Address/Data Range. Connect Output #00
(A[4:0] = 00000) to Input #00 (D[5:0] = 000000).
10000X 100000Upper Address/Data Range. Connect Output #16
(A[4:0] = 10000) to Input #32 (D[5:0] = 100000).
<Binary Output Number*> 1 <Binary Input Number> Enable Output. Connect Selected Output (A[4:0] = 0
to 16) to Designated Input (D[5:0] = 0 to 32) and
Enable Output (D6 = 1).
<Binary Output Number*>0 XXXXXXDisable Output. Disable Specified Output (D6 = 0).
10001X <Binary Input Number> Broadcast Connection. Connect all 17 outputs to
same designated input and set all 17 enable bits to
the value of D6. Readback is not possible with the
broadcast address.
10010X 100001Reserved. Any address or data code greater or equal
to these are reserved for future expansion or factory
testing.
*The binary output number may also be the broadcast connection designator, 10001X.
AD8150
–13–
REV. 0
Control Interface Timing Diagrams
CS INPUT
t
ASW
t
AHW
t
DSW
WE INPUT
A[4:0] INPUTS
D[6:0] INPUTS
t
CSW
t
WP
t
CHW
t
DHW
Figure 25. First Rank Write Cycle
Table III. First Rank Write Cycle
Symbol Parameter Conditions Min Typ Max Unit
t
CSW
Setup Time Chip Select to Write Enable T
A
= 25°C0 ns
t
ASW
Address to Write Enable V
DD
= 5 V 0 ns
t
DSW
Data to Write Enable V
CC
= 5 V 15 ns
t
CHW
Hold Time Chip Select from Write Enable 0 ns
t
AHW
Address from Write Enable 0 ns
t
DHW
Data from Write Enable 0 ns
t
WP
Width of Write Enable Pulse 15 ns
PREVIOUS RANK 2 DATA
CS INPUT
UPDATE INPUT
ENABLING
OUT[0:16][N:P]
OUTPUTS
TOGGLE
OUT[0:16][N:P]
OUTPUTS
DISABLING
OUT[0:16][N:P]
OUTPUTS
DATA FROM RANK 1
t
CSU
t
UOE
t
CHU
DATA FROM RANK 1
DATA FROM RANK 2
t
UW
t
UOD
t
UOT
Figure 26. Second Rank Update Cycle
Table IV. Second Rank Update Cycle
Symbol Parameter Conditions Min Typ Max Unit
t
CSU
Setup Time Chip Select to Update T
A
= 25°C0 ns
t
CHU
Hold Time Chip Select from Update V
DD
= 5 V 0 ns
t
UOE
Output Enable Times Update to Output Enable V
CC
= 5 V 25 40 ns
t
UOT
Output Toggle Times Update to Output Reprogram 25 40 ns
t
UOD
Output Disable Times Update to Output Disabled 25 30 ns
t
UW
Width of Update Pulse 15 ns
AD8150
–14– REV. 0
CS INPUT
UPDATE INPUT
ENABLING
OUT[0:16][N:P]
OUTPUTS
DISABLING
OUT[0:16][N:P]
OUTPUTS
WE INPUT
tCSU
tUOT
tUOE
tWOT
tWHU
INPUT {DATA 1}
INPUT {DATA 1}
INPUT {DATA 2}
INPUT {DATA 0}
tCHU
tUW
tWOD
Figure 27. First Rank Write Cycle and Second Rank Update Cycle
Table V. First Rank Write Cycle and Second Rank Update Cycle
Symbol Parameter Conditions Min Typ Max Unit
t
CSU
Setup Time Chip Select to Update T
A
= 25°C0 ns
t
CHU
Hold Time Chip Select from Update V
DD
= 5 V 0 ns
t
UOE
Output Enable Times Update to Output Enable V
CC
= 5 V 25 40 ns
t
WOE
*Write Enable to Output Enable 25 40 ns
t
UOT
Output Toggle Times Update to Output Reprogram 25 30 ns
t
WOT
Write Enable to Output Reprogram 25 30 ns
t
UOD
*Output Disable Times Update to Output Disabled 25 30 ns
t
WOD
Write Enable to Output Disabled 25 30 ns
t
WHU
Setup Time Write Enable to Update 10 ns
t
UW
Width of Update Pulse 15 ns
*Not Shown.
A[4:0]
INPUTS
t
CSR
D[6:0]
OUTPUTS
t
RDE
t
AA
t
RHA
CS INPUT
RE INPUT
ADDR 1 ADDR 2
DATA
{ADDR1} DATA {ADDR2}
t
CHR
t
RDD
Figure 28. Second Rank Readback Cycle
Table VI. Second Rank Readback Cycle
Symbol Parameter Conditions Min Typ Max Unit
t
CSR
Setup Time Chip Select to Read Enable T
A
= 25°C0 ns
t
CHR
Hold Time Chip Select from Read Enable V
DD
= 5 V 0 ns
t
RHA
Address from Read Enable V
CC
= 5 V 5 ns
t
RDE
Enable Time Data from Read Enable 10 kΩ15 ns
t
AA
Access Time Data from Address 20 pF on D[6:0] 15 ns
t
RDD
Release Time Data from Read Enable Bus 15 30 ns
AD8150
–15–
REV. 0
DISABLING
OUT[0:16][N:P]
OUTPUTS
RESET INPUT
tTOD
tTW
Figure 29. Asynchronous Reset
Table VII. Asynchronous Reset
Symbol Parameter Conditions Min Typ Max Unit
t
TOD
Disable Time Output Disable from Reset T
A
= 25°C2530ns
t
TW
Width of Reset Pulse V
DD
= 5 V 15 ns
V
CC
= 5 V
Control Interface Programming Example
The following conservative pattern connects all outputs to input number 7, except output 16 which is connected to input number 32.
The vector clock period, T
0
is 15 ns. It is possible to accelerate the execution of this pattern by deleting vectors 1, 4, 7, and 9.
Table VIII. Basic Test Pattern
Vector No. Reset CS WE RE Update A[4:0] D[6:0] Comments
0 0 1 1 1 1 xxxxx xxxxxxx Disable All Outputs
1 1 1 1 1 1 xxxxx xxxxxxx
2 1 0 1 1 1 10001 1000111 All Outputs to Input #07
3 1 0 0 1 1 10001 1000111 Write to First Rank
4 1 0 1 1 1 10001 1000111
5 1 0 1 1 1 10000 1100000 Output #16 to Input #32
6 1 0 0 1 1 10000 1100000 Write to First Rank
7 1 0 1 1 1 10000 1100000
8 1 0 1 1 0 xxxxx xxxxxxx Transfer to Second Rank
9 1 0 1 1 1 xxxxx xxxxxxx
10 1 1 1 1 1 xxxxx xxxxxxx Disable Interface
AD8150
–16– REV. 0
UPDATE
7
0
1
2
16
33
1 OF 33
DECODERS
1 OF 17 DECODERS
WE
D[0:6]
RE
A[0:4]
RANK 1 RANK 2
17 ROWS OF 7-BIT
LATCHES
RESET
TO 1733
SWITCH
MATRIX
7
33
7
33
7
33
7
7
7
7
0
1
2
16
7
7
7
7
7
7
7
7
7
Figure 30. Control Interface (Simplified Schematic)
AD8150 CONTROL INTERFACE
The AD8150 control interface receives and stores the desired
connection matrix for the 33 input and 17 output signal pairs.
The interface consists of 17 rows of double-rank 7-bit latches,
one row for each output. The 7-bit data word stored in each
of these latches indicates to which (if any) of the 33 inputs the
output will be connected.
One output at a time can be preprogrammed by addressing the
output and writing the desired connection data into the first
rank of latches. This process can be repeated until each of the
desired output changes has been preprogrammed. All output
connections can then be programmed at once by passing the
data from the first rank of latches into the second rank. The out-
put connections always reflect the data programmed into the
second rank of latches, and do not change until the first rank of
data is passed into the second rank.
If necessary for system verification, the data in the second rank
of latches can be read back from the control interface.
At any time, a reset pulse can be applied to the control interface
to globally reset the appropriate second rank data bits, disabling
all 17 signal output pairs. This feature can be used to avoid out-
put bus contention on system start-up. The contents of the first
rank remain unchanged.
The control interface pins are connected via logic-level transla-
tors. These translators allow programming and readback of the
control interface using logic levels different from those in the
signal matrix.
In order to facilitate multiple chip address decoding, there is a
chip-select pin. All logic signals except the reset pulse are ignored
unless the chip select pin is active. The chip select pin disables
only the control logic interface, and does not change the opera-
tion of the signal matrix. The chip select pin does not power
down any of the latches, so any data programmed in the latches
is preserved.
All control pins are level-sensitive, not edge-triggered.
CONTROL PIN DESCRIPTION
A[4:0] Inputs
Output address pins. The binary encoded address applied to
these five input pins determines which one of the seventeen
outputs is being programmed (or being read back). The most
significant bit is A4.
D[6:0] Inputs/Outputs
Input configuration data pins. In write mode, the binary encoded
data applied to pins D[6:0] determine which one of 33 inputs is
to be connected to the output specified with the A[4:0] pins.
The most significant bit is D5, and the least significant bit is
D0. Bit D6 is the enable bit, setting the specified output sig-
nal pair to an enabled state if D6 is logic HIGH, or disabled
to a high-impedance state if D6 is logic LOW.
In readback mode, pins D[6:0] are low-impedance outputs indi-
cating the data word stored in the second rank for the output
specified with the A[4:0] pins. The readback drivers were designed
to drive high impedances only, so external drivers connected
to the D[6:0] should be disabled during readback mode.
WE Input
First Rank Write Enable. Forcing this pin to logic LOW allows
the data on pins D[6:0] to be stored in the first rank latch for
the output specified by pins A[4:0]. The WE pin must be returned
to a logic HIGH state after a write cycle to avoid overwriting
the first rank data.
UPDATE Input
Second Rank Write Enable. Forcing this pin to logic LOW allows
the data stored in all 17 first rank latches to be transferred to the
second rank latches. The signal connection matrix will be repro-
grammed when the second rank data is changed. This is a global
pin, transferring all 17 rows of data at once. It is not necessary
to program the address pins. It should be noted that after initial
power-up of the device, the first rank data is undefined. It may
be desirable to preprogram all seventeen outputs before performing
the first update cycle.
RE Input
Second Rank Read-Enable. Forcing this pin to logic LOW enables
the output drivers on the bidirectional D[6:0] pins, entering the
readback mode of operation. By selecting an output address with
the A[4:0] pins and forcing RE to logic LOW, the 7-bit data
stored in the second rank latch for that output address will be
written to D[6:0] pins. Data should not be written to the D[6:0]
pins externally while in readback mode. The RE and WE pins
are not exclusive, and may be used at the same time, but data
should not be written to the D[6:0] pins from external sources
while in readback mode.
CS Input
Chip-Select. This pin must be forced to logic LOW in order
to program or receive data from the logic interface, with the
exception of the RESET pin, described below. This pin has
no effect on the signal pairs and does not alter any of the stored
control data.
RESET Input
Global Output Disable Pin. Forcing the RESET pin to logic
LOW will reset the enable bit, D6, in all 17 second rank
latches, regardless of the state of any other pins. This has the
effect of immediately disabling the 17 output signal pairs in the
AD8150
–17–
REV. 0
matrix. It is useful to momentarily hold RESET at a logic LOW
state when powering up the AD8150 in a system that has mul-
tiple output signal pairs connected together. Failure to do this
may result in several signal outputs contending after power-up.
The reset pin is not gated by the state of the chip-select pin, CS.
It should be noted that the RESET pin does not program the
first rank, which will contain undefined data after power-up.
CONTROL INTERFACE TRANSLATORS
The AD8150 control interface has two supply pins, V
DD
and
V
SS
. The potential between the positive logic supply V
DD
and
the negative logic supply V
SS
must be at least 3 V and no more
than 5 V. Regardless of supply, the logic threshold is approxi-
mately 1.6 V above V
SS
, allowing the interface to be used with
most CMOS and TTL logic drivers.
The signal matrix supplies, V
CC
and V
EE
, can be set indepen-
dent of the voltage on V
DD
and V
SS
, with the constraints that
(V
DD
–V
EE
) ≤ 10 V. These constraints will allow operation of
the control interface on 3 V or 5 V while the signal matrix is
operated on 3.3 V or 5 V PECL, or –3.3 V or –5 V ECL.
CIRCUIT DESCRIPTION
The AD8150 is a high-speed 33 × 17 differential crosspoint switch
designed for data rates up to 1.5 Gbps per channel. The AD8150
supports PECL-compatible input and output levels when operated
from a 5 V supply (V
CC
= 5 V, V
EE
= GND) or ECL-compatible
levels when operated from a –5 V supply (V
CC
= GND, V
EE
=
–5 V). To save power, the AD8150 can run from a 3.3 V supply
to interface with low-voltage PECL circuits or a –3.3 V supply
to interface with low-voltage ECL circuits. The AD8150 utilizes
differential current mode outputs with individual disable control,
which facilitates busing together the outputs of multiple AD8150s
to assemble larger switch arrays. This feature also reduces sys-
tem crosstalk and can greatly reduce power dissipation in a large
switch array. A single external resistor programs the current for
all enabled output stages, allowing for user control over output
levels with different output termination schemes and transmis-
sion line characteristic impedances.
High-Speed Data Inputs (INxxP, INxxN)
The AD8150 has 33 pairs of differential voltage-mode inputs.
The common-mode input range extends from the positive sup-
ply voltage (V
CC
) down to include standard ECL or PECL input
levels (V
CC
– 2 V). The minimum differential input voltage is
less than 300 mV. Unused inputs may be connected directly to
any level within the allowed common-mode input range. A sim-
plified schematic of the input circuit is shown in Figure 31.
V
CC
INxxP INxxN
V
EE
Figure 31. Simplified Input Circuit
In order to maintain signal fidelity at the high data rates supported
by the AD8150, the input transmission lines should be terminated
as close to the input pins as possible. The preferred input termi-
nation structure will depend primarily on the application and
the output circuit of the data source. Standard ECL compo-
nents have open emitter outputs that require pull-down resistors.
Three input termination networks suitable for this type of source
are shown in Figure 32. The characteristic impedance of the trans-
mission line is shown as Z
O
. The resistors, R1 and R2, in the
Thevenin termination are chosen to synthesize a V
TT
source
with an output resistance of Z
O
and an open-circuit output volt-
age equal to V
CC
– 2 V. The load resistors (R
L
) in the differential
termination scheme are needed to bias the emitter followers of
the ECL source.
VCC
INxxP
INxxN
ZO
ZO
ZOZO
ECL SOURCE
VTT = VCG2V
(a)
VCC
INxxP
INxxN
ZO
ZO
R2 R2
R1
R1
VEE
ECL SOURCE
VCC – 2V
(b)
VCC
INxxP
INxxN
ZO
RL
ZO2ZO
RL
VEE
ECL SOURCE
(c)
Figure 32. AD8150 Input Termination from ECL/PECL
Sources: a) Parallel Termination Using V
TT
Supply, b)
Thevenin Equivalent Termination, c) Differential Termination
If the AD8150 is driven from a current mode output stage such
as another AD8150, the input termination should be chosen
to accommodate that type of source, as explained in the fol-
lowing section.
High-Speed Data Outputs (OUTyyP, OUTyyN)
The AD8150 has 17 pairs of differential current-mode outputs.
The output circuit, shown in Figure 33, is an open-collector
NPN current switch with resistor-programmable tail current and
output compliance extending from the positive supply voltage
(V
CC
) down to standard ECL or PECL output levels (V
CC
– 2 V).
The outputs may be disabled individually to permit outputs
from multiple AD8150’s to be connected directly. Since the
output currents of multiple enabled output stages connected
in this way sum, care should be taken to ensure that the out-
put compliance limit is not exceeded at any time; this can be
achieved by disabling the active output driver before enabling
any inactive driver.
AD8150
–18– REV. 0
VCC
VEE
DISABLE IOUT
OUTyyP OUTyyN
VCC – 2V
VEE
Figure 33. Simplified Output Circuit
To ensure proper operation, all outputs (including unused output)
must be pulled high using external pull-up networks to a level
within the output compliance range. If outputs from multiple
AD8150s are wired together, a single pull-up network may be
used for each output bus. The pull-up network should be chosen
to keep the output voltage levels within the output compliance
range at all times. Recommended pull-up networks to produce
PECL/ECL 100K and 10K compatible outputs are shown in
Figure 34. Alternatively, a separate supply can be used to pro-
vide V
COM
; making R
COM
and D
COM
unnecessary.
VCC
RCOM
VCOM
RL
OUTyyN
OUTyyP
AD8150
VCC
DCOM
VCOM
RL
OUTyyN
OUTyyP
AD8150
RL
RL
Figure 34. Output Pull-Up Networks: a) ECL 100K,
b) ECL 10K
The output levels are simply:
V
OH
= V
COM
V
OL
= V
COM
– I
OUT
R
L
V
SWING
= V
OH
– V
OL
= I
OUT
R
L
V
COM
= V
CC
– I
OUT
R
COM
(100K Mode)
V
COM
= V
CC
– V (D
COM
) (10K Mode)
The common-mode adjustment element (R
COM
or D
COM
) may
be omitted if the input range of the receiver includes the positive
supply voltage. The bypass capacitors reduce common-mode
perturbations by providing an ac short from the common nodes
(V
COM
) to ground.
When busing together the outputs of multiple AD8150s or when
running at high data rates, double termination of its outputs is
recommended to mitigate the impact of reflections due to open
transmission line stubs and the lumped capacitance of the
AD8150 output pins. A possible connection is shown in Figure
35; the bypass capacitors provide an ac short from the common
nodes of the termination resistors to ground. To maintain signal
fidelity at high data rates, the stubs connecting the output pins
to the output transmission lines or load resistors should be as
short as possible.
V
CC
OUTyyN
OUTyyP
OUTyyN
OUTyyP
R
L
R
L
Z
O
Z
O
Z
O
Z
O
R
L
R
L
AD8150
AD8150
V
COM
R
COM
RECEIVER
Figure 35. Double Termination of AD8150 Outputs
In this case, the output levels are:
V
OH
= V
COM
– (1/4) I
OUT
R
L
V
OL
= V
COM
– (3/4) I
OUT
R
L
V
SWING
= V
OH
– V
OL
= (1/2) I
OUT
R
L
Output Current Set Pin (REF)
A simplified schematic of the reference circuit is shown in Fig-
ure 36. A single external resistor connected between the REF
pin and V
EE
determines the output current for all output stages.
This feature allows a choice of pull-up networks and transmission
line characteristic impedances while still achieving a nominal
output swing of 800 mV. At low data rates, substantial power
savings can be achieved by using lower output swings and higher
load resistances.
AD8150
V
EE
R
SET
REF
V
CC
I
OUT
/25
1.25V
Figure 36. Simplified Reference Circuit
The resistor value current is given by the following expression:
RI
SET
OUT
=25
Example:
R
SET
= 1.54 kΩ for I
OUT
= 16.2 mA
The minimum set resistor is R
SET,min
= 1 kΩ resulting in I
OUT,max
=
25 mA. The maximum set resistor is R
SET,max
= 5 kΩ result-
ing in I
OUT,min
= 5 mA. Nominal 800 mV output swings can be
achieved in a 50 Ω load using R
SET
= 1.56 kΩ (I
OUT
= 16.2 mA)
or in a doubly-terminated 75 Ω load using R
SET
= 1.17 kΩ (I
OUT
= 21.3 mA).
To minimize stray capacitance and avoid the pickup of unwanted
signals, the external set resistor should be located close to the
REF pin. Bypassing the set resistor is not recommended.
AD8150
–19–
REV. 0
Power Supplies
There are several options for the power supply voltages for the
AD8150, as there are two separate sections of the chip that require
power supplies. These are the control logic and the high-speed
data paths. Depending on the system architecture, the voltage
levels of these supplies can vary.
Logic Supplies
The control (programming) logic is CMOS and is designed to
interface with any of the various standard single-ended logic
families (CMOS or TTL). Its supply voltage pins are V
DD
(Pin
170, logic positive) and V
SS
(Pin 152, logic ground). In all cases
the logic ground should be connected to the system digital ground.
V
DD
should be supplied at between 3.3 V to 5 V to match the
supply voltage of the logic family that is used to drive the logic
inputs. V
DD
should be bypassed to ground with a 0.1 µF ceramic
capacitor. The absolute maximum voltage from V
DD
to V
SS
is 5.5 V.
Data Path Supplies
The data path supplies have more options for their voltage lev-
els. The choices here will affect several other areas, like power
dissipation, bypassing, and common mode levels of the inputs
and outputs. The more positive voltage supply for the data paths
is V
CC
(Pins 41, 98, 149 and 171). The more negative supply is
V
EE
, which appears on many pins that will not be listed here.
The maximum allowable voltage across these supplies is 5.5 V.
The first choice in the data path power supplies is to decide
whether to run the device as ECL (Emitter-Coupled Logic) or
PECL (Positive ECL). For ECL operation, V
CC
will be at ground
potential, while V
EE
will be at a negative supply between –3.3 V
to –5 V. This will make the common-mode voltage of the inputs
and outputs at a negative voltage, see Figure 37.
DATA
PATHS
CONTROL
LOGIC
3V TO 5V
3V TO 5V
V
SS
V
EE
GND
GND
0.1F
(ONE FOR EVERY TWO V
EE
PINS)
0.1F
AD8150
V
DD
V
CC
Figure 37. Power Supplies and Bypassing for ECL
Operation
If the data paths are to be dc-coupled to other ECL logic devices
that run with ground as the most positive supply and a negative
voltage for V
EE
, then this is the proper way to run. However, if
the part is to be ac coupled, it is not necessary to have the input/
output common mode at the same level as the other system cir-
cuits, but it will probably be more convenient to use the same
supply rails for all devices.
For PECL operation, V
EE
will be at ground potential and V
CC
will be a positive voltage from 3.3 V to 5 V. Thus, the common
mode of the inputs and outputs will be at a positive voltage.
These can then be dc coupled to other PECL operated devices.
If the data paths are ac coupled, then the common-mode levels
do not matter, see Figure 38.
DATA
PATHS
CONTROL
LOGIC
3V TO 5V 3V TO 5V
VSS VEE
GND GND
0.1F
(ONE FOR EACH VCC PIN, 4 REQ'D.)
0.1F
AD8150
VDD VCC
Figure 38. Power Supplies and Bypassing for PECL
Operation
POWER DISSIPATION
For analysis, the power dissipation of the AD8150 can be divided
into three separate parts. These are the control logic, the data
path circuits and the (ECL or PECL) outputs, which are part of
the data path circuits, but can be dealt with separately. The first
of these, the control logic, is CMOS technology and does not
dissipate a significant amount of power. This power will, of
course, be greater when the logic supply is 5 V rather than 3 V,
but overall it is not a significant amount of power and can be
ignored for thermal analysis.
DATA
PATHS
CONTROL
LOGIC
V
SS
V
EE
GND GND
AD8150
V
DD
V
CC
I, DATA PATH
LOGIC V
OUT
LOW – V
EE
R
OUT
I
OUT
Figure 39. Major Power Consumption Paths
The data path circuits operate between the supplies V
CC
and
V
EE
. As described in the power supply section, this voltage can
range from 3.3 V to 5 V. The current consumed by this section
will be constant, so operating at a lower voltage can save about
40 percent in power dissipation.
AD8150
–20– REV. 0
The power dissipated in the data path outputs is affected by several
factors. The first is whether the outputs are enabled or disabled.
The worst case occurs when all of the outputs are enabled.
The current consumed by the data path logic can be approxi-
mated by:
I
CC
= 30 mA + [4.5 mA + (I
OUT
/20 mA × 3 mA)]
× (# of outputs enabled)
This says that there will always be a minimum of 30 mA flow-
ing. I
CC
will increase by a factor that is proportional to both the
number of enabled outputs and the programmed output current.
The power dissipated in this circuit section will simply be the
voltage of this section (V
CC
– V
EE
) times the current. For a worst
case, assume that V
CC
– V
EE
is 5.0 V, all outputs are enabled
and the programmed output current is 25 mA. The power dissi-
pated by the data path logic will be:
P = 5.0 V {25 mA + [4.5 mA + (25 mA/20 mA × 3 mA)]
× 17} = 826 mW
The power dissipated by the output current depends on several
factors. These are the programmed output current, the voltage
drop from a logic low output to V
EE
and the number of enabled
outputs. A simplifying assumption is that one of each (enabled)
differential output pair will be low and draw the full output cur-
rent (and dissipate most of the power for that output), while the
complementary output of the pair will be high and draw insig-
nificant current. Thus, its power dissipation of the high output
can be ignored and the output power dissipation for each output
can be assumed to occur in a single static low output that sinks
the full output-programmed current.
The voltage across which this current flows can also vary, depend-
ing on the output circuit design and the supplies that are used
for the data path circuitry. In general, however, there will be a
voltage difference between a logic low signal and V
EE
. This is
the drop across which the output current flows. For a worst
case, this voltage can be as high as 3.5 V. Thus, for all outputs
enabled and the programmed output current set to 25 mA, the
power dissipated by the outputs:
P = 3.5 V (25 mA) × 17 = 1.49 W
HEAT SINKING
Depending on several factors in its operation, the AD8150 can
dissipate upwards of 2 W or more. The part is designed to oper-
ate without the need for an explicit external heatsink. However,
the package design offers enhanced heat removal via some of the
package pins to the PC board traces.
The V
EE
pins on the input sides of the package (Pins 1 to 46 and
Pins 93 to 138) have “finger” extensions inside the package
that connect to the “paddle” upon which the IC chip is mounted.
These pins provide a lower thermal resistance from the IC to
the V
EE
pins than other pins that just have a bond wire. As a
result these pins can be used to enhance the heat removal pro-
cess from the IC to the circuit board and ultimately to the ambient.
The V
EE
pins described above should be connected to a large area
of circuit board trace material in order to take most advantage
their lower thermal resistance. If there is a large area available
on an inner layer that is at V
EE
potential, then vias can be pro-
vided from the package pin traces to this layer. There should be
no thermal-relief pattern when connecting the vias to the inner
layers for these V
EE
pins. Additional vias in parallel and close to
the pin leads can provide an even lower thermal resistive path. If
possible to use, 2 oz. copper foil will provide better heat removal
than 1 oz.
The AD8150 package has a specified thermal impedance θ
JA
of
30°C/W. This is the worst case, still-air value that can be expected
when the circuit board does not significantly enhance the heat
removal from the package. By using the concept described above
or by using forced-air circulation, the thermal impedance can be
lowered.
For an extreme worst case analysis, the junction rise above the
ambient can be calculated assuming 2 W of power dissipation
and θ
JA
of 30°C/W to yield a 60°C rise above the ambient. There
are many techniques described above that can mitigate this situa-
tion. Most actual circuits will not result in this high a rise of the
junction temperature above the ambient.
APPLICATIONS
AD8150 INPUT AND OUTPUT BUSING
Although the AD8150 is a digital part, in any application that
runs at high speed, analog design details will have to be given very
careful consideration. At high data rates, the design of the signal
channels will have a strong influence on the data integrity and
its associated jitter and ultimately bit error rate (BER).
While it might be considered very helpful to have a suggested cir-
cuit board layout for any particular system configuration, this is
not something that can be practically realized. Systems come in
all shapes, sizes, speeds, performance criteria and cost constraints.
Therefore, some general design guidelines will be presented
that can be used for all systems and judiciously modified where
appropriate.
High-speed signals travel best, i.e. maintain their integrity, when
they are carried by a uniform transmission line that is properly
terminated at either end. Any abrupt mismatches in impedance
or improper termination will create reflections that will add to
or subtract from parts of the desired signal. Small amounts of
this effect are unavoidable, but too much will distort the signal
to the point that the channel BER will increase. It is difficult to
fully quantify these effects, because they are influenced by many
factors in the overall system design.
A constant-impedance transmission line is characterized by
having a uniform cross-section profile over its entire length. In
particular, there should be no “stubs,” which are branches that
intersect the main run of the transmission line. These can have
an electrical “appearance” that is approximated by a lumped
element, such as a capacitor, or if long enough, as another trans-
mission line. To the extent that stubs are unavoidable in a design,
their effect can be minimized by making them as short as pos-
sible and as high an impedance as possible.
Figure 35 shows a differential transmission line that connects
two differential outputs from AD8150s to a generic receiver. A
more generalized system can have more outputs bused, and
more receivers on the same bus, but all the same concepts apply.
The inputs of the AD8150 can also be considered as a receiver.
The transmission lines that bus all of the devices together are
shown with terminations at each end.
The individual outputs of the AD8150 are stubs that intersect
the main transmission line. Ideally, their current-source outputs
would be infinite impedance, and they would have no effect on
signals that propagate along the transmission line. In reality, each
AD8150
–21–
REV. 0
external pin of the AD8150 projects into the package, and has a
bond wire connected to the chip inside. On-chip wiring then
connects to the collectors of the output transistors and to ESD
protection diodes.
Unlike some other high-speed digital components, the AD8150
does not have on-chip terminations. While this location would
be closer to the actual end of the transmission line for some
architectures, this concept can limit system design options. In
particular, it is not possible to bus more than two inputs or
outputs on the same transmission line and it is also not possible
to change the value of these terminations to use for different
impedance transmission lines. The AD8150, with the added
ability to disable its outputs, is much more versatile in these
types of architectures.
If the external traces are kept to a bare minimum, then the out-
put will present a mostly lumped capacitive load of about 2 pF.
A single stub of 2 pF will not seriously adversely affect signal in-
tegrity for most transmission lines, but the more of these stubs,
the more adverse their influence will be.
One way to mitigate this effect is to locally reduce the capacitance
of the main transmission line near the point of stub intersection.
Some practical means for doing this are to narrow the PC board
traces in the region of the stub and/or to remove some of the
ground plane(s) near this intersection. The effect of these tech-
niques will locally lower the capacitance of the main transmission
line at these points, while the added capacitance of the AD8150
outputs will “compensate” for this reduction in capacitance.
The overall intent is to create as uniform a transmission line as
possible.
In selecting the location of the termination resistors it is impor-
tant to keep in mind that, as their name implies, they should be
placed at either end of the line. There should be no or minimal
projection of the transmission line beyond the point where the
termination resistors connect to it.
EVALUATION BOARD
An evaluation board has been designed and is available to rapidly
test the main features of the AD8150. This board lets the user
analyze the analog performance of the AD8150 channels and
easily control the configuration of the board by a standard PC.
Differential inputs and outputs provide the interface for all chan-
nels with the connections made by a 50 Ω, SMB-type connector.
This type of connector was chosen for its rapid mating and
unmating action. The use of SMB-type connectors minimizes
the size and minimizes the effort of rearranging interconnects
that would be required by using connectors such as SMA-type.
Configuration Programming
The board is configurable by one of two methods. For ease of
use, custom software is provided that controls the AD8150
programming via the parallel port of a PC. This requires a user-
supplied standard printer cable that has a DB-25 connector at
one end (parallel- or printer-port interface) and a Centronix-
type connector at the other that connects to P2 of the AD8150
evaluation board. The programming with this scheme is done in
a serial fashion, so it is not the fastest way to configure the AD8150
matrix. However, the user interface makes it very convenient to
use this programming method.
If a high-speed programming interface is desired, the AD8150
address and data buses are directly available on P3. The source
of the program signals can be a piece of test equipment, like the
Tektronix HFS-9000 digital test generator, or some other user-
supplied hardware that generates programming signals.
When using the PC interface, the jumper at W1 should be in-
stalled and no connections should be made to P3. When using
the P3 interface, no jumper is installed at W1. There are loca-
tions for termination resistors for the address and data signals if
these are necessary.
Power Supplies
The AD8150 is designed to work with standard ECL logic levels.
This means that V
CC
is at ground and V
EE
is at a negative sup-
ply. The shells of the I/O SMB connectors are at V
CC
potential.
Thus, when operating in the standard ECL configuration, test
equipment can be directly connected to the board, as the test
equipment will have its connector “shells” at ground potential also.
Operating in PECL mode requires V
CC
to be at a positive volt-
age, while V
EE
is at ground. Since this would make the shells of
the I/O connectors at a positive voltage, it can cause problems
when directly connecting to test equipment. Some equipment,
such as battery operated oscilloscopes, can be “floated” from
ground, but care should be taken with line-powered equipment
such that a dangerous situation is not created. Refer to the manual
of the test equipment that is being used.
The voltage difference from V
CC
to V
EE
can range from 3 V to 5 V.
Power savings can be realized by operating at a lower voltage
without any compromise in performance.
A separate connection is provided for V
TT
, the termination po-
tential of the outputs. This can be at a voltage as high as V
CC
,
but power savings can be realized if V
TT
is at a voltage that is
somewhat lower. Please consult elsewhere in the data sheet for
the specification for the limits of the V
TT
supply.
As a practical matter, current on the evaluation board will flow
from the V
TT
supply, through the termination resistors and then
through the AD8150 from its outputs to the V
EE
supply. When
running in ECL mode, V
TT
will want to be at a negative supply.
Most power supplies will not allow their ground to connect to
V
CC
and then the negative supply to V
TT
. This will require them
to source current from their negative supply, which will not re-
turn to the ground terminal. Thus, V
TT
should be referenced to
V
EE
when running in ECL mode or a true bipolar supply should
be used.
The digital supply is provided to the AD8150 by the V
DD
and
V
SS
pins. V
SS
should always be at ground potential to make it com-
patible with standard CMOS or TTL logic. V
DD
can range from
3 V to 5 V and should be matched to the supply voltage of the
logic used to control the AD8150. However, since PCs use 5 V
logic on their parallel port, V
DD
should be at 5 V when using a
PC to program the AD8150.
Software Installation
The software to operate the AD8150 is provided on two 3.5"
floppy disks. The software is installed by inserting Disk 1 into
the floppy drive of a PC and running the “setup.exe” program.
This will routinely install the software and prompt the user when to
change to Disk 2. The setup program will also prompt the user
to select the directory location to store the program.
AD8150
–22– REV. 0
After running the software, the user will be prompted to identify
which (of three) software driver is used with the PC’s parallel
port. The default is LPT1, which is most commonly used. How-
ever, some laptops commonly use the PRN driver. It is also
possible that some systems are configured with the LPT2 driver.
If it is not known which driver is used, it is best to select LPT1
and proceed to the next screen. This will show a full array of
“buttons” that allows the connection of any input to output of
the AD8150. All of the outputs should be in the output “OFF”
state right after the program starts running. Any of the active
buttons can be selected with a mouse click which will send out
one burst of programming data.
After this, the PC keyboard’s left or right arrow keyboard key
can be held down to generate a steady stream of programming
signals out of the parallel port. The CLOCK test point on the
AD8150 evaluation board can be monitored with an oscilloscope
for any activity (user-supplied printer cable must be connected).
If there is a square-wave present, then the proper software driver
is selected for the PC’s parallel port.
If there is no signal present, then another driver should be tried
by selecting the Parallel Port menu item under the “File” pull-
down menu selection just under the title bar. Select a different
software driver and carry out the above test until signal activity
is present at the CLOCK test point.
Software Operation
Any button can be clicked in the matrix to program the input
to output connection. This will send the proper programming
sequence out the PC parallel port. Since only one input can be
programmed to a given output at one time, clicking a button in
a horizontal row will cancel the other selection that is already
selected in that row. However, any number of outputs can share
the same input. Refer to Figure 40.
A shortcut for programming all outputs to the same input is to
use the broadcast feature. After clicking on the Broadcast Con-
nection button, a window will appear that will prompt for the
user to select which input should be connected to all outputs.
The user should type in an integer from 0 to 32 and then click
on OK. This will send out the proper program data and return
to the main screen with a full column of buttons selected under
the chosen input.
The Off column can be used to disable to whichever output one
chooses. To disable all outputs, the Global Reset button can be
clicked. This will select the full column of OFF buttons.
Two scratchpad memories (Memory 1 and Memory 2) are pro-
vided to conveniently save a particular configuration. However,
these registers are erased when the program is terminated. For
long-term storage of configurations, the disk-storage memory
should be used. The Save and Load selections can be accessed
from the “File” pull-down menu under the title bar.
AD8150
–23–
REV. 0
Figure 40.
AD8150
–24– REV. 0
Figure 41. Component Side
AD8150
–25–
REV. 0
Figure 42. Circuit Side
AD8150
–26– REV. 0
Figure 43. Silkscreen Top
AD8150
–27–
REV. 0
Figure 44. Soldermask Top
AD8150
–28– REV. 0
Figure 45. Silkscreen Bottom
AD8150
–29–
REV. 0
Figure 46. Soldermask Bottom
AD8150
–30– REV. 0
Figure 47. INT1 (V
EE
)
AD8150
–31–
REV. 0
Figure 48. INT2 (V
CC
)
AD8150
–32– REV. 0
Figure 49. Bypassing Schematic
VEE
VCC
C9
0.01F
IN19N
IN19P
IN18N
IN18P
IN17N
IN17P
IN16N
IN16P
VDD
RESET
CS
RE
WE
UPDATE
A0
A1
A2
A3
A4
D0
D1
D2
D3
D4
D5
D6
VEE
IN15N
IN15P
IN14N
IN14P
IN13N
IN13P
VEE C30
0.01F
VCC
184
183
182
181
180
179
178
177
176
175
174
173
171
170
169
168
167
166
165
164
163
162
172
161
160
159
157
156
155
154
153
152
158
151
150
149
147
146
145
144
143
142
141
140
139
148
VEE
OUT15N
OUT15P
VEE
OUT14N
OUT14P
VEE
OUT13N
OUT13P
VEE
OUT12N
OUT12P
VEE
OUT11N
OUT11P
VEE
OUT10N
OUT10P
VEE
OUT09N
OUT09P
VEE
OUT08N
OUT08P
VEE
OUT07N
OUT07P
VEE
OUT06N
OUT06P
VEE
OUT05N
OUT05P
VEE
OUT04N
OUT04P
VEE
OUT03N
OUT03P
VEE
OUT02N
OUT02P
VEE
OUT01N
OUT01P
VEE
59
60
61
62
63
64
65
66
67
68
47
48
49
50
51
52
53
54
55
56
57
58
69
70
71
72
74
75
76
77
78
73
79
80
81
82
84
85
86
87
83
88
89
90
91
92
5
4
3
2
7
6
9
8
1
14
13
12
11
16
15
17
10
19
18
23
22
21
20
25
24
27
26
29
28
32
31
30
34
33
36
35
40
39
38
37
41
43
42
45
44
46
VEE
IN20P
IN20N
VEE
IN21P
IN21N
VEE
IN22P
IN22N
VEE
IN23P
IN23N
VEE
IN24P
IN24N
VEE
IN25P
IN25N
VEE
IN26P
IN26N
VEE
IN27P
IN27N
VEE
IN28P
IN28N
VEE
IN29P
IN29N
VEE
IN30P
IN30N
VEE
IN31P
IN31N
VEE
IN32P
IN32N
VEE
OUT16N
OUT16P
VEE
VEE
VEE
IN12N
IN12P
VEE
IN11N
IN11P
VEE
IN10N
IN10P
VEE
IN09N
IN09P
VEE
IN08N
IN08P
VEE
IN07N
IN07P
VEE
IN06N
IN06P
VEE
IN05N
IN05P
VEE
IN04N
IN04P
VEE
IN03N
IN03P
VEE
IN02N
IN02P
VEE
IN01N
IN01P
VEE
IN00N
IN00P
VEE
VEE
OUT00P
OUT00N
VEE
VEE
122
137
138
132
133
134
135
130
131
129
136
127
128
123
124
125
126
120
121
118
119
116
117
113
114
115
111
112
109
110
108
105
106
107
104
102
103
100
101
95
96
97
98
99
93
94
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD8150
184L LQFP
V
CC
C31
0.01F
VCC
C32
0.01F
VEE
VCC C11
0.01F
VEE
VCC
C15
0.01F
VEE
VCC
C60
0.01F
VEE
VCC
C10
0.01F
VEE
VCC
C8
0.01F
VEE
VCC C12
0.01F
R203
1.5k
VSS
VDD
C14
0.01F
VEE
VCC
C5
0.01F
VEE C7
0.01F
VCC
VEE
VCC
C6
0.01F
VEE
VCC
C4
0.01F
VEE
VEE
C13
0.01F
VEE
VCC
C29
0.01F
AD8150
–33–
REV. 0
Figure 50.
V
CC
P52
P53
V
EE
R93
105
IN24P
IN24N
R94
1.65k
R92
1.65k
V
CC
P54
P55
V
EE
R96
105
IN25P
IN25N
R95
1.65k
R97
1.65k
V
CC
P56
P57
V
EE
R99
105
IN26P
IN26N
R98
1.65k
R100
1.65k
V
CC
P58
P59
V
EE
R102
105
IN27P
IN27N
R101
1.65k
R103
1.65k
V
CC
P60
P61
V
EE
R105
105
IN28P
IN28N
R104
1.65k
R106
1.65k
V
CC
P62
P63
V
EE
R108
105
IN29P
IN29N
R107
1.65k
R109
1.65k
V
CC
P16
P17
V
EE
R39
105
IN06P
IN06N
R40
1.65k
R38
1.65k
V
CC
P18
P19
V
EE
R42
105
IN07P
IN07N
R41
1.65k
R43
1.65k
V
CC
P20
P21
V
EE
R45
105
IN08P
IN08N
R44
1.65k
R46
1.65k
V
CC
P22
P23
V
EE
R48
105
IN09P
IN09N
R47
1.65k
R49
1.65k
V
CC
P24
P25
V
EE
R51
105
IN10P
IN10N
R50
1.65k
R52
1.65k
V
CC
P26
P27
V
EE
R54
105
IN11P
IN11N
R53
1.65k
R55
1.65k
P103
P102
V
TT
R121
49.9
OUT00N R122
49.9
OUT00P
P101
P100
V
TT
R125
49.9
OUT01N R127
49.9
OUT01P
V
CC
V
TT
C16
0.01F
P99
V
TT
R130
49.9
OUT02N R132
49.9P98
OUT02P
P97
V
TT
R135
49.9
OUT03N R133
49.9P96
OUT03P
P95
V
TT
R140
49.9
OUT04N R142
49.9P94
OUT04P
P93
V
TT
R145
49.9
OUT05N R143
49.9P92
OUT05P
P91
V
TT
R150
49.9
OUT06N R152
49.9P90
OUT06P
P89
V
TT
R155
49.9
OUT07N R153
49.9P88
OUT07P
V
CC
V
TT
C82
0.01F
V
CC
V
TT
C83
0.01F
V
CC
P4
P5
V
EE
R20
105
IN00P
IN00N
R19
1.65k
R21
1.65k
V
CC
P6
P7
V
EE
R24
105
IN01P
IN01N
R25
1.65k
R23
1.65k
V
CC
P8
P9
V
EE
R27
105
IN02P
IN02N
R28
1.65k
R26
1.65k
V
CC
P10
P11
V
EE
R30
105
IN03P
IN03N
R31
1.65k
R29
1.65k
V
CC
P12
P13
V
EE
R33
105
IN04P
IN04N
R34
1.65k
R32
1.65k
V
CC
P14
P15
V
EE
R36
105
IN05P
IN05N
R37
1.65k
R35
1.65k
V
CC
P28
P29
V
EE
R57
105
IN12P
IN12N
R58
1.65k
R56
1.65k
V
CC
P30
P31
V
EE
R60
105
IN13P
IN13N
R59
1.65k
R61
1.65k
V
CC
P32
P33
V
EE
R63
105
IN14P
IN14N
R62
1.65k
R64
1.65k
V
CC
P34
P35
V
EE
R66
105
IN15P
IN15N
R65
1.65k
R67
1.65k
V
CC
P36
P37
V
EE
R69
105
IN16P
IN16N
R68
1.65k
R70
1.65k
V
CC
P38
P39
V
EE
R72
105
IN17P
IN17N
R71
1.65k
R73
1.65k
V
CC
P40
P41
V
EE
R90
105
IN18P
IN18N
R89
1.65k
R91
1.65k
V
CC
P42
P43
V
EE
R87
105
IN19P
IN19N
R88
1.65k
R86
1.65k
V
CC
P44
P45
V
EE
R84
105
IN20P
IN20N
R85
1.65k
R83
1.65k
V
CC
P46
P47
V
EE
R81
105
IN21P
IN21N
R82
1.65k
R80
1.65k
V
CC
P48
P49
V
EE
R78
105
IN22P
IN22N
R79
1.65k
R77
1.65k
V
CC
P50
P51
V
EE
R75
105
IN23P
IN23N
R76
1.65k
R74
1.65k
V
CC
P64
P65
V
EE
R117
105
IN30P
IN30N
R116
1.65k
R118
1.65k
V
CC
P66
P67
V
EE
R114
105
IN31P
IN31N
R115
1.65k
R113
1.65k
V
CC
P68
P69
V
EE
R111
105
IN32P
IN32N
R112
1.65k
R110
1.65k
P87
V
TT
R160
49.9
OUT08N R162
49.9P86
OUT08P
P85
V
TT
R165
49.9
OUT09N R163
49.9P84
OUT09P
P83
V
TT
R175
49.9
OUT10N R173
49.9P82
OUT10P
P81
V
TT
R170
49.9
OUT11N R172
49.9P80
OUT11P
P79
V
TT
R185
49.9
OUT12N R183
49.9P78
OUT12P
P77
V
TT
R180
49.9
OUT13N R182
49.9P76
OUT13P
P75
V
TT
R195
49.9
OUT14N R193
49.9P74
OUT14P
P73
V
TT
R190
49.9
OUT15N R192
49.9P72
OUT15P
P71
V
TT
R200
49.9
OUT16N R198
49.9P70
OUT16P
AD8150
–34– REV. 0
Figure 51.
+
V
TT
P1 6
V
CC
P1 1
P1 2
V
EE
P1 3
V
DD
P1 4
P1 7
V
SS
P1 5
C3
10F
C1
10F
V
TT
V
TT
V
CC
V
CC
V
EE
V
EE
+
V
DD
+C2
10F
V
SS
P104
P105
OUT_EN
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
GND
10
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
20
19
18
17
16
15
14
13
12
CLK 11
R12
49.0
R13
49.0
R14
49.0
R15
49.0
R16
49.0
49.0
R18
49.0
V
SS
V
SS
R17
V
SS
V
SS
V
SS
V
SS
V
SS
READ P2 7
RESET P2 3
WRITE P2 8
UPDATE P2 4
CHIP_SELECT P2 2
WRITE P3 13
RESET P3 7
READ P3 11
D0 P3 27
A4 P3 25
A3 P3 23
A2 P3 21
A1 P3 19
A0 P3 17
D6 P3 39
D5 P3 37
D4 P3 35
D3 P3 33
D2
D1 P3 29
UPDATE P3 15
CHIP_SELECT P3 9
V
DD
P3 5
V
SS
P3 14
P3 8
P3 12
P3 28
P3 26
P3 24
P3 22
P3 20
P3 18
P3 40
P3 38
P3 36
R2
49.0
R3
49.0
R4
49.0
R5
49.0
V
SS
V
SS
V
SS
V
SS
R6
49.0
V
SS
A2
DATA P2 5
CLK P2 6
CLK
DATA
V
SS
P2 25
V
DD
V
SS
V
DD
C86
0.1F
V
SS
V
DD
C87
0.1F
V
SS
V
DD
C88
0.1F
V
SS
V
DD
C89
0.1F
V
SS
A1, 4 PIN 14 IS TIED TO V
DD
.
A1, 4 PIN 7 IS TIED TO V
SS
.R7
49.0
R8
49.0
R9
49.0
R10
49.0
V
SS
V
SS
V
SS
V
SS
R11
49.0
V
SS
OUT_EN
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
GND
10
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
20
19
18
17
16
15
14
13
12
CLK 11
P3 31
A4
P3 34
P3 32
P3 30
P3 16
P3 10
P3 6
V
DD
V
SS
A3
V
DD
TP5
TP4
TP6
TP7
TP8
CHIP_SELECT
168
UPDATE
165
WRITE
166
RESET
169
READ
167
A4
74HC132
74HC132
R1
20k
1
24
5
W1
V
SS
74HC14
A1
74HC14
A1
74HC14
A1
12
345 6
74HC74 74HC74
160A4
161A3
162A2
163A1
164A0
TP9
TP10
TP11
TP12
TP13
TP20
TP14
TP15
TP16
TP17
TP18
TP19
153D6
154D5
155D4
156D3
157D2
158D1
159D0
V
DD
V
SS
V
SS
V
DD
V
DD
9
10 8
A4
A1
11 10
A1
13 12
12
13 11
A4
V
DD
74HC14
A1
98
74HC14
74HC14
74HC132
74HC132
J1
V
CC
V
EE
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
V
CC
V
EE
J27
J28
J29
J30
J31
J32
J33
J34
J35
J36
J37
J38
J39
J40
J41
J42
J43
J44
J45
J46
J47
J48
J49
J50
AD8150
–35–
REV. 0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
184-Lead Plastic LQFP
(ST-184)
139
138
47
46
92
93
186
PIN 1
TOP VIEW
(PINS DOWN)
1
0.016 (0.40)
BSC
0.009 (0.23)
0.007 (0.18)
0.005 (0.13)
0.787 (20.00) BSC SQ
0.866 (22.00) BSC SQ
SEATING
PLANE
0.003 (0.08)
0.006 (0.15)
0.002 (0.05)
0.063 (1.60)
MAX
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
0.057 (1.45)
0.053 (1.40)
0.048 (1.35)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
C3765–3–3/00 (rev. 0)
PRINTED IN U.S.A.
