Sipex SIGNAL PROCESSING EXCELLENCE @ Monolithic Construction @ 16-Bit Resolution M 0.003% Non-Linearity @ Four-Quadrant Multiplication @ Latch-up Protected @ Low Power - 30mW @ Single +15V Power Supply DESCRIPTION... SP7516 and HS3160 16-Bit Multiplying DACs The SP7516 and HS3160 are precision 16-bit multiplying DACs, that provide four-quadrant multiplication. Both parts accept both AC and DC reference voltages. The SP7516 is available for use in commercial and industrial temperatu re ranges, packaged in a 24-pin SOIC. The HS3160 is available in commercial and military temperature ranges, packaged in a 22-pin side-brazed DIP. 23 Var Fores O at se f REF 3 16 EQUAL 4BKQ Vaer Sense 9-241 96k. enpo4 [ + 21 wwe) [oeewoncane ] sprste 4 to 16 DECODE Lsersnecore ) sprsie: 5s. 6] 7 8 20 rat - 3 BIT? BIT2 BITS BIT4 BITI6 Reeepeack (MsB) (LSB) Switches shown in high state. 2 & lour2 Sense 3 lour2 Force lourt 21 Ver & Gnd o~4J Vpp 024 4to 16 [L serenecone | + 16 eOUAL a 96KQ SECTIONS 96ke Foon > 28 tour? 8 gurl HS3160 48 2 BIT! BIT2 BIT3 BIT4 (MSB) Switches shown in high state. arn 6 Areeogack (LSB) Sipex Conpontion SIGNAL PROCESSING EXCELLENCE 127SPECIFICATIONS (Typical @ 25C, nominal power supply, V REF = +10V, unipolar unless otherwise noted) CAUTION: ESD (ElectroStatic Discharge) sensitive device. Permanent damage may occur on . / unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foarn or shunts. Personnel should be property grounded prior to handling this device. The protective foam should ba dischargad to the destination socket bafore davices are removed. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS DIGITAL INPUT Resolution 16 Bits 2Quad, Unipolar Coding Binary 4Quad, Bipolar Coding Offset Binary Logic Compatibility CMOS, TTL Note 1 Input Current +1 HA REFERENCE INPUT Voltage Range +25 Vv Note 2 Input Impedance 3.25 9.75 KOhms ANALOG OUTPUT Scale Factor 75 225 PAV eee Scale Factor Accuracy +1 % Note 3 Output Leakage 10 nA Note 4 Output Capacitance Coy 1, all inputs high 100 pF Cour 1, all inputs low 50 pF Coy 2, all inputs high 50 pF Coy 2, all inputs low 100 pF STATIC PERFORMANCE Integral Linearity Note 5 SP7516KN/BN, HS3160-4 +0.003 | +0.006 % FSR SP7516JN/AN, HS3160-3 +0.006 | +0.012 % FSR Differential Linearity Note 6 SP7516KN/BN, HS3160-4 +0.003 | +0.006 %FSR SP7516JN/AN, HS3160-3 +0.006 | +0.012 % FSR Monotonicity SP7516KN/BN, HS3160-4 Guaranteed to 14 bits SP7516JN/AN, HS3160-3 Guaranteed to 13 bits STABILITY (Tray tO Tray) Scale Factor 4 ppm FSRA/C Note 7 and 8 Integral Linearity 05 1.0 ppm FSR&C Differential Linearity 0.5 1.0 ppm FSRC Monotonicity Temp. Range SP7516JN/KN, HS3160C 0 +70 C SP7516AN/BN 40 +85 C HS3160B_ 55 +125 C DYNAMIC PERFORMANCE Digital Small Signal Settling 1.0 us Digital Full Scale Settling 2.0 us Reference Feedthrough Error (Vper = 20Vpp) @ 1kHz 200 pv @ 10kHz 2 mV Reference Input Bandwidth 1 MHz POWER SUPPLY (V,,,) Operating Voltage +15 +5% Vv Voltage Range +8 +18 Vv Current 2.0 mA Note 9 Rejection Ratio 0.005 %ol%o 128 Si Corpormdon SIGNAL PROCESSING EXCELLENCE ISPECIFICATIONS (continued) (Typical @ 25C, nominal power supply, V,_.- = +10V, unipolar unless otherwise noted) PARAMETER | MIN. TYP. MAX. UNITS CONDITIONS ENVIRONMENTAL AND MECHANICAL Operating Temperature SP7516JN/KN 0 +70 C SP7516AN/BN 40 +85 C HS3160C 0 +70 C HS3160-B -55 +125 C HS3160-B/883 ~55 +125 C Storage Temperature -65 +150 C Package SP7516_N 24-pin SOIC HS3160 22-pin SideBrazed DIP I | Notes: 1. Digital input voltage must not exceed supply voltage or go below -0.5V ; 0 <0.8V; 2.4V < 1 <V.., 2. AC or DC; use R6758-1 for fixed reference applications 3. Using the intemal feedback resistor and an extemal op amp. The Scale Factor can be adjusted externally by variable resistors in series with the reference input and/or in series to the internal feedback resistor. Please refer to the Applications Information section. At 25C; the output leakage current will create an offset voltage at the extemal op amps output. It doubles every 10C temperature increase. Integral Linearity is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from the theoretical value for any given input combination. Differential Linearity is the deviation of an output step form the theoretical value of 1LSB for any two adjacent digital input codes. At 25C, the output leakage current will create an offset voltage output. It doubles every 10C temperature increase. Using the internal feedback resistor and an external op amp. . Use series 4700hm resistor to limit startup current. CHARACTERISTIC CURVES (Typical @ + 25C, V,,. = + 15VDC, V,., = + 10VDC, unless otherwise noted.) oe ODN .048 * * rc 2 7 ie 40 7 c / xc oa a 0.024 , 5 S 3 2LSB a rz s a c Y z 0.012 Ww 4 S a 5 0.006 20 / = 0.003 = 0.01 a4 1 10 z POTTER n 1LSB 4 * Vrer VOLTS 10 > Integral Linearity Error vs. Reference Voltage we L---4 ----|---~4 1/2 LSB @ 16 BITS 0.048% 0 = 0 10 20 30 40 50 Vos'm Additional Linearity Error vs. Output-Amplifier z ones. Offset-Voltage (V,,, = + 10V) a Zz s 0.012% 0.01 0.006% 0,003% \ 4 6 a 10 12 14 16 18 0.008 Vpp-VOLTS : . # Linearity vs. Supply Voltage a o.one wo. 28 2 \ a oO ~| Z 0.004 = 2 3 NX] n NK a 0,002 2 15 N NK 0 1.0 4 6 8 10 12 14 16 18 4 6 8 10 12 14 16 16 10 Vpp VOLTS Ypp VOLTS Gain Change vs. Supply Voltage Power Supply Current vs. Voltage Sipex 129 SIGNAL PROCESSING EXCELLENCEPIN ASSIGNMENTS HS3160 22-PIN Pin 1 IO, Current Output 1. Pin 2 -1O, Current Output 2. Pin 3 - GND Ground. Pin 4 - DB,, MSB, Data Bit 1. Pin 5 - DB,, Data Bit 2. Pin 6 DB,, Data Bit 3. Pin 7 DB,, Data Bit 4. Pin 8 DB, , Data Bit 5. Pin 9 DB,, Data Bit 6. Pin 10 DB, Data Bit 7. Pin 11 DB, Data Bit 8. Pin 12 DB, Data Bit 9. Pin 13 ~ DB, Data Bit 10. Pin 14 DB, Data Bit 11. Pin 15 DB, Data Bit 12. Pin 16 DB, Data Bit 13. Pin 17 DB, Data Bit 14. Pin 18 DB, Data Bit 15. Pin 19 ~ DB, LSB, Data Bit 16. Pin 20 V,,,, ~ Positive Supply Voltage. Pin 21 V,,,, Reference Voltage Input. Pin 22 Ryp Feedback Resistor. SP7516 24-PIN Pin 1 -1O, Current Output 1. Pin 2 - IO, Sense Current Output 2. Pin 3 IO, Force Current Output 3. Pin 4 - GND Ground. Pin 5 DB, MSB, Data Bit 1. Pin 6 DB, , Data Bit 2. Pin 7 DB, Data Bit 3. Pin 8 DB,, Data Bit 4. Pin 9 - DB, , Data Bit 5. Pin 10 - DB,, Data Bit 6. Pin 11 - DB, Data Bit 7. Pin 12 DB, Data Bit 8. Pin 13 DB, Data Bit 9. Pin 14 DB, Data Bit 10. Pin 15 DB, Data Bit 11. Pin 16 ~ DB, Data Bit 12. Pin 17 DB, Data Bit 13. Pin 18 DB, Data Bit 14. Pin 19 DB, Data Bit 15. Pin 20 DB, LSB, Data Bit 16. Pin 21 V,,, Positive Supply Voltage. Pin 22 Vp, Sense Reference Voltage Input. Pin 23 Vpp,Force Reference Voltage Input. Pin 24 R,,, Feedback Resistor. FEATURES... The SP7516 and HS3160 are precision 16-bit multi- plying DACs. The DACs are implemented as a one- chip CMOS circuit with a resistor ladder network. Three output lines are provided on the DACs to allow unipolar and bipolar output connection with a mini- mum of external components. The feedback resistor is internal. The resistor ladder network termination is externally available, thus eliminating an external re- sistor for the 1 LSB offset in bipolar mode. The SP7516 is available for use in commercial and industrial temperature ranges, packaged in a 24-pin SOIC. The HS3160 is available in commercial and military temperature ranges, packaged in a 24pin sidebrazed DIP. For product processed and screened to the requirements of MIL-M- 38510 and MIL-STD-883C, please consult the factory (HS3160B only). PRINCIPLES OF OPERATION The SP7516/HS3160achieve high accuracy by using a decoded or segmented DAC scheme to implement this function. The following is a brief description of this approach. Figure 1. SP7516/HS3160 Equivalent Output Circuit 130 Sipex SIGNAL PROCESSING EXCELLENCE ] woos2-(MSB) 0 Table 1. Contribution of the two MSB's The most common technique for building a D/A converter of n bits is to use n switches to turn n current or voltage sources on or off. The n switches and n sources are designed so that each switch or bit contrib- utes twice asmuch tothe D/A converter s outputas the preceding bit. This technique is commonly known as binary weighting and allows an n-bit converter to generate 2" output levels by turning on the proper combination of bits. In such a binary-weighted converter, the switch with the smallest contribution (the LSB) accounts for only 2 of the converters full-scale value. Similarly, the switch with the largest contribution (the MSB) accounts for 27! orhalf of the converters full-scale output. Thus it is easy to see that a given percent change in the MSB will have a greater effect on the converters output than would a similar percent change in the LSB. For example, a 1% change in the LSB of a 10 bit converter would only affect the output by 0.001% of full-scale. A 1% change in the MSB of the same converter would affect the output by 0.5% of FSR. In order to overcome the problem which results from the large weighting of the MSB, the two MSBs can be decoded to three equally weighted sources. Table J shows that all combinations of the two MSBs of a converter result in four output levels. So by replacing the two MSBs with three bits equally weighted at 1/ 4 full-scale and decoding the two MSB digital inputs 20082 | DIGITAL INPUTS 1 | Figure 2. Unipolar Operation the same functional performance can be obtained. Thus by replacing the two MSB switches of aconven- tional converter with three switches properly de- coded, the contribution of any switch is reduced from 1/2to 1/4. This reduction in sensitivity alsoreduces the accuracy required of any switch for a given overall converter accuracy. With the decoded converter described above, a 1% change in any of the converters switches will affect the output by no more than 0.25% of full-scale as compared to 0.5% for a conventional converter. In other words the conventional D/A converter can be made less sensitive to the quality of its individual bits by decoding. In the SP7516/HS3160 the first four MSBs are decodedinto 16levels whichdrive 1 5equally weighted current sources. The sensitivity of each switch on the output is reduced by a factor of 8. Each of the 15 sources contributes 6.25% output change rather than an MSB change of 50% for the common approach. 4002 . . . . a . v into three lines which drive the equally weighted bits, ero | ' | { TRANSFER FUNCTION (N=16) DIGITAL I BINARY INPUT| UNIPOLAR OUTPUT| BIPOLAR OUTPUT 114...111 Voge (1-24) | Voge (1-2 8-9 'o & 2 100...001 Voge (1/2 + 24) Voge (28-9) Rees A 100...000 Veeg (2 0 | oxo a Ross 011...111 Voce (1/2 ~ 24) Veer (248-1) ~ > Ake REE -____9 000...001 Vnee (20-") Vege (1-2 ~~) your 000...000 0 Veer - Ay, Ag, OP-07 Table 2. Transfer Function Figure 3. Bipolar Operation Cinayv vipex 131 SIGNAL PROCESSING EXCELLENCEa70n3 UNIPOLAR MODE (2-QUADRANT} SSSegegRes8 WA-G Gea 74L$138 BDSEL-Cj G28 Arc Ase AoA ADDRESS DECODER LATCHES Figure 4. Microprocessor Interface to SP7514 Following the decoded section of the DAC a standard binary weighted R-2R approach is used. This divides each of the 16 levels (or 6.25% of F.S.) into 4096 discrete levels (the 12 LSBs). Output Capacitance The SP7516/HS3160 have very low output ca- pacitance (Cy). This is specified both with all switches ON and all switches OFF. Output capaci- tance varies from 50pF to 100pF over all input codes. This low capacitance is due in part to the decoding technique used. Smaller switches are used with resulting less capacitance. Three impor- tant system characteristics are affected by C, and AC,; namely digital feedthrough, settling time, and bandwidth. The DAC output equivalent cir- cuit can be represented as shown in Figure /. Digital feedthrough is the change in analog output due to the toggling conditions on the converter input data lines when the analog input Vp... is at OV. The SP7516/HS3160 very low C,, and there- fore will yield low digital feedthrough. Inputs to the DAC can be buffered. This input latch with microprocessor control is shown in Figure 4. Settling time is directly affected by C,. In Figure i, Co combines with R, to add a pole to the open loop response, reducing bandwidth and causing excessive phase shift - which could result in ringing and/or oscillation. A feedback capaci- tor, C, must be added to restore stability. Even with C,, there is still a zero-pole mismatch due to RC, which is code dependent. This code dependent mismatch is minimized when C,R, = R,C,. How- ever C,must now be made larger to compensate for worst case AR C,, - resulting in reduced bandwidth and increased settling time. With the SP7516/ HS3160, small values for C, must be used. Resis- tor R, can be added, this will parallel R, decreasing the effective resistance. If C, is reduced the band- width will be increased and settling time decreased. However a system penalty for lowering C;, is to increase noise gain. The tradeoff is noise vs. set~ tling time. If R, is added then a large value (1pF or greater) non-polarizedcapacitorC_ should beadded in series with R. to eliminate any DC drifts. If settling time is not important, eliminate R, and C,, and adjust C, to prevent overshoot. Output Offset In most applications, the output of the DAC is fed into an amplifier to convert the DACs current output to voltage. A little known and not com- monly discussed parameter is the linearity error versus offset voltage of the output amplifier. All CMOS DACs must operate into a virtual ground, ie., the summing junction of an op amp. Any amplifier s offset from the amplifier will appear as an error at the output (which can be related to LSBs of error). Most all CMOS DACs currently available are implemented using an R-2R ladder network. The formula fornonlinearity is typically 0.67mV/MV o (not derived here). However the SP7516 has a coefficient of only 0.065mV/mV<. This is due to the decoding technique described earlier. CMOS DAC applications notes (including this one) al- ways show a potentiometer used to null out the amplifier s offset. If an amplifier is chosen having pretrimmed offset it may be possible to eliminate this component. Consider the following calcula- tions: Using LF441A amplifier (low power - 741 pinout) Specified offset: 0.5mV max poe Temperature coefficient of input offset: 1OWV/C max Vos max (0C to 70C) = 0.SmV + (7OUV)10 =1,2mV Add'l nonlinearity (max) = 1.2mV x 0.065mV/mV = 7BuUV (1/2 LSB @ 16 Bits!) Where: 78uV = 1/2 LSB @ 16 Bits (10V range) Via the above configuration, the SP7516/HS3160 can be used to divide an analog signal by digital code (i.e. for digitally controlled gain). The trans- fer function is given in Table 2, where the value of each bit is 0 or 1. Division by all 0s is undefined and causes the op amp to saturate. 132 SIGNAL PROCESSING EXCELLENCE IApplications Information Unipolar Operation Figure 2 shows the interconnections for unipolar operation. Connect I,, and FB, as shown in dia- gram. Tie I,, (Pin 7), FB, (Pin 3), and FB, (Pin 1) to Ground (Pin 8). As shown, a series resistor is recommended in the V,,,, supply line to limit current during turn-on. To maintain specified linearity, external amplifiers must be zeroed. Apply an ALL ZEROES digital input and adjust R,, for Voyp = 0+ ImV. The SP7516 and HS3160 have been used successfully with OP-07, OP-27 and LF441A. For high speed applications the SP2525 is recommended. Bipolar Operation Figure 3 shows the interconnections for bipolar operation. Connect I,,, Ip), FB,, FB;, FB, as shown in diagram. Tie LDTR to I,,. As shown, a series resistor is recommended in the V,,,, supply line to limit current during turn-on. To maintain specified linearity, external amplifiers must be zeroed. This is best done with V.,, set to zero and, the DAC register loaded with 10...0 MSB = 1). Set Ros; for Vo, =0. Set Rog, for Vou = 0. Set Verp to +10V and adjust R, for Vj7 to be OV. Grounding Connect all GND pins to system analog ground and tie this to digital ground. All unused input pins must be grounded. SIDEX SIGNAL PROCESSING EXCELLENCE 133ORDERING INFORMATION Model Monotonicity Temperature Range ....rscccscseaecneenes Package 16-Bit Multiplying DAC HS3160C-30 .. 0C to +70C ...... ... 22-pin, 0.4" Side-Brazed DIP HS3160B-30 .. . 55C to +125C ... 22-pin, 0.4" Side-Brazed DIP HS3160B-3/883 ... -55C to +125C 22-pin, 0.4" Side-Brazed DIP HS3160C-4Q 0C to +70C ... ... 22-pin, 0.4" Side-Brazed DIP ... 22-pin, 0.4" Side-Brazed DIP HS3160B-4Q - ... 22-pin , 6.4" Side-Brazed DIP HS3160B-4/883 .. .. 55C to +125C ... .. -B5C to +126C ... - 14-Bit .... SP7516JN.... C... ... 24-pin, 0.3" SOIC SP7515KN ... . ... 24-pin, 0.3" SOIC SP75164N ... ate . we 40C to +85C .. ... 24-pin, 0.3" SOIC SP7516BN ... . 14-Bit.... . 40C to +85C .. .. 24-pin, 0.3 SOIC Cinav 134 wi Corperation SIGNAL PROCESSING EXCELLENCE