Semiconductor Group 1 1998-10-01
• 4 194 304 words by 4-bit organization
• 0 to 70 °C operating temperature
• Hyper Page Mode - EDO - operation
• Performance:
• Power dissipation, refresh & addressing:
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
test mode and Self Refresh (on L-versions only)
• All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible
• Plastic Package: P-SOJ-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
-50 -60
tRAC RAS access time 50 60 ns
tCAC CAS access time 13 15 ns
tAA Access time from address 25 30 ns
tRC Read/Write cycle time 84 104 ns
tHPC Hyper page mode (EDO) cycle time 20 25 ns
HYB 5116405 HYB 3116405 HYB 5117405 HYB 3117405
-50 -60 -50 -60 -50 -60 -50 -60
Power supply 5 V ± 10% 3.3 V ±0.3 V 5 V ± 10% 3.3 V ±0.3 V
Addressing 12/10 12/10 11/11 11/11
Refresh 4096 cylces / 64 ms 2048 cycles / 32 ms
L-version 4096 cycles / 128 ms –
Active 275 220 180 144 440 385 288 252 mW
TTL Standby 11 7.2 11 7.2 mW
CMOS Standby 5.5 3.6 5.5 3.6 mW
CMOS Standby
(L-version) – 0.72 – – mW
4M × 4-Bit Dynamic RAM
2k & 4k Refresh
(Hyper Page Mode - EDO)
Advanced Information
HYB 5116405BJ-50/-60
HYB 5117405BJ-50/-60
HYB 3116405BJ/BT(L)-50/-60
HYB 3117405BJ/BT-50/-60
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 2 1998-10-01
The HYB 5(3)116(7)405 are 16 MBit dynamic RAMs based on die revisions “G” & “F” and organized
as 4 194 304 words by 4-bits. The HYB 5(3)116(7)405BJ/BT(L) utilizes a submicron CMOS silicon
gate process technology, as well as advanced circuit techniques to provide wide operating margins,
both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)116(7)405
to be packaged in a standard SOJ-26/24 and TSOPII-26/24 plastic package with 300 mil width.
These packages provide high system bit densities and are compatible with commonly used
automatic testing and insertion equipment. The HYB 3116(7)405BTL have a very low power “sleep
mode” supported by Self Refresh.
Ordering Information
Type Ordering Code Package Descriptions
2k-Refresh Versions:
HYB 5117405BJ-50 Q67100-Q1101 P-SOJ-26/24-1 300 mil 5 V 50 ns EDO-DRAM
HYB 5117405BJ-60 Q67100-Q1102 P-SOJ-26/24-1 300 mil 5 V 60 ns EDO-DRAM
HYB 3117405BJ-50 on request P-SOJ-26/24-1 300 mil 3.3 V 50 ns EDO-DRAM
HYB 3117405BJ-60 on request P-SOJ-26/24-1 300 mil 3.3 V 60 ns EDO-DRAM
HYB 3117405BT-50 on request P-TSOPII-26/24-1 300 mil 3.3 V 50 ns EDO-DRAM
HYB 3117405BT-60 on request P-TSOPII-26/24-1 300 mil 3.3 V 60 ns EDO-DRAM
4k-Refresh Versions:
HYB 5116405BJ-50 Q67100-Q1098 P-SOJ-26/24-1 300 mil 5 V 50 ns EDO-DRAM
HYB 5116405BJ-60 Q67100-Q1099 P-SOJ-26/24-1 300 mil 5 V 60 ns EDO-DRAM
HYB 3116405BJ-50 on request P-SOJ-26/24-1 300 mil 3.3 V 50 ns EDO-DRAM
HYB 3116405BJ-60 on request P-SOJ-26/24-1 300 mil 3.3 V 60 ns EDO-DRAM
HYB 3116405BT-50 on request P-TSOPII-26/24-1 300 mil 3.3 V 50 ns EDO-DRAM
HYB 3116405BT-60 on request P-TSOPII-26/24-1 300 mil 3.3 V 60 ns EDO-DRAM
HYB 3116405BTL-50 on request P-TSOPII-26/24-1 300 mil 3.3 V 50 ns LP-EDO-DRAM
HYB 3116405BTL-60 on request P-TSOPII-26/24-1 300 mil 3.3 V 60 ns LP-EDO-DRAM
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 3 1998-10-01
Pin Configuration
(top view)
Pin Names
HYB 5(3)16405
4k-Refresh HYB 5(3)17405
2k-Refresh
Row Address Inputs A0 - A11 A0 - A10
Column Address Inputs A0 - A9 A0 - A10
Row Address Strobe RAS
Column Address Strobe CAS
Output Enable OE
Data Input/Output I/O1 - I/O4
Read/Write Input WE
Power Supply VCC
Ground (0 V) VSS
Not Connected – N.C.
P-SOJ-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
CC
V
A0 9
10
12
11
2
3
4
5
1
13 14
26
18
17
16
15
22
23
24
25
SPP03454
6
819
21
A10
SS
V
A4
I/O3
I/O4
CAS
OE
SS
V
I/O1
A11 / N.C.
RAS
WE
V
CC
I/O2
A1
A2
A3 A5
A6
A7
A8
A9
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 4 1998-10-01
Block Diagram for HYB 5(3)116405 (4k-refresh)
SPB03455
&
No.2 Clock
Generator
Address
Column
Buffers (10)
Controller
Refresh
Refresh
Counter (12)
Buffers (12)
Row
Address
Generator
No.1 Clock
12
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
12 Row
Decoder
RAS
4096 x 1024 x 4
Memory Array
4096
1024
x 4
Sense Amplifier
I/O Gating
10 Column
Decoder
Buffer
Data IN Data OUT
Buffer
I/O1
44
OE
Voltage Down
V
CC
V
CC
12
4
A9
(internal)
Generator
CAS
WE
A10
I/O2 I/O3 I/O4
A11
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 5 1998-10-01
Block Diagram for HYB 5(3)117405 (2k-refresh)
Data In
Buffer Data Out
Buffer
I/O1 I/O2 I/O4
OE
Column
Decoder
Sense Amplifier
I/O Gating
&
No.2 Clock
Generator
Column
Address
Buffers (11)
Refresh
Controller
Refresh
Counter (11)
Buffers (11)
Address
Row
No.1 Clock
Generator
11 Memory Array
Decoder
Row 2048
.
.
.
.
.
.
2048
.
.
.
.
.
.
4
4
4
11
11
WE
CAS
RAS
11
2048 2048x 4
x
x4
I/O3
(internal)
V
Generator
Voltage Down
CC
CC
V
SPB02823
11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 6 1998-10-01
Absolute Maximum Ratings
Operating temperature range ........................................................................................... 0 to 70 ˚C
Storage temperature range........................................................................................ – 55 to 150 ˚C
Input/output voltage (5 V versions)................................................... – 0.5 to min (VCC + 0.5, 7.0) V
Input/output voltage (3.3 V versions)................................................ – 0.5 to min (VCC + 0.5, 4.6) V
Power supply voltage (5 V versions) ....................................................................... – 1.0 V to 7.0 V
Power supply voltage (3.3 V versions) .................................................................... – 1.0 V to 4.6 V
Power dissipation (5 V versions) ............................................................................................ 1.0 W
Power dissipation (3.3 V versions) ......................................................................................... 0.5 W
Data out current (short circuit) ............................................................................................... 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns
Parameter Symbol Limit Values Unit Test
Condition
min. max.
5 V Versions
Power supply voltage VCC 4.5 5.5 V
Input high voltage VIH 2.4 VCC + 0.5 V 1
Input low voltage VIL – 0.5 0.8 V 1
Output high voltage (IOUT = – 5 mA) VOH 2.4 – V 1
Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V 1
3.3 V Versions
Power supply voltage VCC 3.0 3.6 V
Input high voltage VIH 2.0 VCC + 0.5 V 1
Input low voltage VIL – 0.5 0.8 V 1
TTL Output high voltage (IOUT = – 2 mA) VOH 2.4 – V 1
TTL Output low voltage (IOUT = 2 mA) VOL – 0.4 V 1
CMOS Output high voltage (IOUT = – 100 µA) VOH VCC – 0.2 – V
CMOS Output low voltage (IOUT = 100 µA) VOL – 0.2 V
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 7 1998-10-01
DC Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns
Parameter Symbol Limit Values Unit Notes
min. max.
2k 4k
Common Parameters
Input leakage current
(0 V ≤VIH ≤VCC + 0.3 V, all other pins = 0 V) II(L) – 10 10 µA1
Output leakage current
(DO is disabled, 0 V ≤VOUT ≤VCC + 0.3 V) IO(L) – 10 10 µA1
Average VCC supply current -50 version
-60 version
(RAS, CAS, address cycling: tRC = tRC MIN.)
ICC1 –
–80
70 50
40 mA
mA
2, 3, 4
2, 3, 4
Standby VCC supply current
(RAS = CAS = VIH)ICC2 – 2 mA –
Average VCC supply current, during RAS-only
refresh cycles -50 version
-60 version
(RAS cycling, CAS = VIH,tRC = tRC MIN.)
ICC3 –
–80
70 50
40 mA
mA
2, 4
2, 4
AverageVCC supply current,during hyper page
mode (EDO) -50 version
-60 version
(RAS = VIL, CAS, address cycling:
tPC = tPC MIN.)
ICC4 –
–35
30 mA
mA
2, 3, 4
2, 3, 4
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V) ICC5 –1
200 mA
µA
1
L-version
Average VCC supply current, during CAS-
before-RAS refresh mode -50 version
-60 version
(RAS, CAS cycling: tRC = tRC MIN.)
ICC6 –
–80
70 50
40 mA
mA
2, 4
2, 4
Average Self Refresh current
(CBR cycle with tRAS >tRASS MIN.,CAS held
low, WE = VCC – 0.2 V, Address and
Din = VCC – 0.2 V or 0.2 V)
ICC7 – 250 µAL-
version
only
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 8 1998-10-01
Capacitance
TA = 0 to 70 °C, f = 1 MHz
Parameter Symbol Limit Values Unit
min. max.
Input capacitance (A0 to A11) CI1 –5pF
Input capacitance (RAS, CAS, WE, OE) CI2 –7pF
I/O capacitance (I/O1 to I/O4) CIO –7pF
AC Characteristics 5, 6
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter Symbol Limit Values Unit Note
-50 -60
min. max. min. max.
Common Parameters
Random read or write cycle time tRC 84 – 104 – ns
RAS precharge time tRP 30 – 40 – ns
RAS pulse width tRAS 50 10k 60 10k ns
CAS pulse width tCAS 8 10k 10 10k ns
Row address setup time tASR 0–0–ns
Row address hold time tRAH 8–10–ns
Column address setup time tASC 0–0–ns
Column address hold time tCAH 8–10–ns
RAS to CAS delay time tRCD 12 37 14 45 ns
RAS to column address delay tRAD 10 25 12 30 ns
RAS hold time tRSH 13 – 15 – ns
CAS hold time tCSH 40 – 50 – ns
CAS to RAS precharge time tCRP 5–5–ns
Transition time (rise and fall) tT1 50 1 50 ns 7
Refresh period for 2k-refresh version tREF – 32 – 32 ms
Refresh period for 4k-refresh version tREF – 64 – 64 ms
Refresh period for Low Power Version tREF – 128 – 128 ms
Read Cycle
Access time from RAS tRAC – 50 – 60 ns 8, 9
Access time from CAS tCAC – 13 – 15 ns 8, 9
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 9 1998-10-01
Access time from column address tAA – 25 – 30 ns 8, 10
OE access time tOEA – 13 – 15 ns
Column address to RAS lead time tRAL 25 – 30 – ns
Read command setup time tRCS 0–0–ns
Read command hold time tRCH 0–0–ns
11
Read command hold time referenced to RAS tRRH 0–0–ns
11
CAS to output in low-Z tCLZ 0–0–ns
8
Output buffer turn-off delay tOFF 0 13 0 15 ns 12
Output turn-off delay from OE tOEZ 0 13 0 15 ns 12
Data to CAS low delay tDZC 0–0–ns
13
Data to OE low delay tDZO 0–0–ns
13
CAS high to data delay tCDD 10 – 13 – ns 14
OE high to data delay tODD 10 – 13 – ns 14
Write Cycle
Write command hold time tWCH 8–10–ns
Write command pulse width tWP 8–10–ns
Write command setup time tWCS 0–0–ns
15
Write command to RAS lead time tRWL 8–10–ns
Write command to CAS lead time tCWL 8–10–ns
Data setup time tDS 0–0–ns
16
Data hold time tDH 8–10–ns
16
Read-Modify-Write Cycle
Read-write cycle time tRWC 113 – 138 – ns
RAS to WE delay time tRWD 64 – 77 – ns 15
CAS to WE delay time tCWD 27 – 32 – ns 15
Column address to WE delay time tAWD 39 – 47 – ns 15
OE command hold time tOEH 10 – 13 – ns
AC Characteristics (cont’d) 5, 6
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter Symbol Limit Values Unit Note
-50 -60
min. max. min. max.
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 10 1998-10-01
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time tHPC 20 – 25 – ns
CAS precharge time tCP 8–10–ns
Access time from CAS precharge tCPA – 27 – 32 ns 7
Output data hold time tCOH 5–5–ns
RAS pulse width in EDO mode tRAS 50 200k 60 200k ns
CAS precharge to RAS delay tRHCP 27 – 32 – ns
OE setup time prior to CAS tOES 5–5–ns
Hyper Page Mode (EDO) Read-Modify-Write Cycle
Hyper page mode (EDO) read-write cycle
time tPRWC 58 – 68 – ns
CAS precharge to WE tCPWD 41 – 49 – ns
CAS-before-RAS Refresh Cycle
CAS setup time tCSR 10 – 10 – ns
CAS hold time tCHR 10 – 10 – ns
RAS to CAS precharge time tRPC 5–5–ns
Write to RAS precharge time tWRP 10 – 10 – ns
Write hold time referenced to RAS tWRH 10 – 10 – ns
CAS-before-RAS Counter Test Cycle
CAS precharge time (CAS-before-RAS
counter test cycle) tCPT 35 – 40 – ns
Self Refresh Cycle (L-Version only)
RAS pulse width tRASS 100k – 100k – ns 17
RAS precharge time tRPS 95 – 110 – ns 17
CAS hold time tCHS – 50 – – 50 – ns 17
AC Characteristics (cont’d) 5, 6
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter Symbol Limit Values Unit Note
-50 -60
min. max. min. max.
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 11 1998-10-01
Test Mode
Write command setup time tWTS 10 – 10 – ns
Write command hold time tWTH 10 – 10 – ns
CAS hold time tCHRT 30 – 30 – ns
RAS hold time in test mode tRAHT 30 – 30 – ns
AC Characteristics (cont’d) 5, 6
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter Symbol Limit Values Unit Note
-50 -60
min. max. min. max.
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 12 1998-10-01
Notes
1. All voltages are referenced to VSS.
2. ICC1,ICC3,ICC4 and ICC6 depend on cycle rate.
3. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
4. Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once
or less during a hyper page mode (EDO) cycle
5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of
8 RAS cycles are required.
6. AC measurements assume tT = 2 ns.
7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times
are also measured between VIH and VIL.
8. Measured with the specified current load and 100 pF at VOL = 0.8 V and VOH = 2.0 V. Access
time is determined by the latter of tRAC,tCAC,tAA,tCPA,tOEA .tCAC is measured from tristate.
9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as
a reference point only. If tRCD is greater than the specified tRCD (MAX.) limit, then access time is
controlled by tCAC.
10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as
a reference point only. If tRAD is greater than the specified tRAD (MAX.) limit, then access time is
controlled by tAA.
11.Either tRCH or tRRH must be satisfied for a read cycle.
12.tOFF (MAX.),tOEZ (MAX.) define the time at which the output achieves the open-circuit conditions and
are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or
CAS, whichever occurs last.
13.Either tDZC or tDZO must be satisfied.
14.Either tCDD or tODD must be satisfied.
15.tWCS,tRWD,tCWD and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle and
data out pin will remain open-circuit (high impedance) through the entire cycle; if
tRWD >tRWD (MIN.),tCWD >tCWD (MIN.) and tAWD >tAWD (MIN.), the cycle is a read-write cycle and I/O will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the
condition of I/O (at access time) is indeterminate.
16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
leading edge in read-write cycles.
17.When using Self Refresh mode, the following refresh operations must be performed to ensure
proper DRAM operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval
using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit
from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-
Burst) over the refresh interval, then a full set of row refreshes must be performed immediately
before entry to and immediately after exit from Self Refresh.
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 13 1998-10-01
Read Cycle
SPT03025
"H" or "L"
OEA
CAC
RAL
t
OH
OL
V
(Inputs)
(Outputs)
I/O
I/O
V
IH
V
IL
V
OE
WE
V
IL
V
IH
V
IL
V
IH
RAC
t
Hi
DZO
Z
t
CLZ
tt
DZC
t
RCS
AA
tt
V
Address
V
IL
V
IH
IL
CAS
RAS
IL
V
IH
V
V
IH
t
RAD
ASR
t
Row
t
Column
RAH
ASC
t
CAH
tt
RCD
t
CSH
t
t
RAS
t
t
ODD
RRH
Valid Data OUT
OEZ
t
t
CDD
OFF
t
Hi Z
t
t
RSH
CAS
t
RC
t
RCH
ASR
t
Row
CRP
t
t
RP
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 14 1998-10-01
Write Cycle (Early Write)
SPT03026
"H" or "L"
RWL
RAL
WCS
OH
(Inputs)
(Outputs)
I/O
I/O
IL
V
OL
V
V
V
IH
OE
WE
IH
V
IL
V
V
IL
V
IH
t
Valid
DS
t
DH
Data IN
WCH
t
t
WP
t
V
Address
IH
V
V
IL
IL
CAS
RAS
V
IH
IH
V
V
IL
t
RAD
ASR
t
t
RAH
Row
t
Column
ASC
t
CWL
t
CAH
tt
RCD
t
CSH
t
t
RAS
t
ZHi
t
RC
CAS
RSH
t
ASR
t
Row
CRP
t
t
RP
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 15 1998-10-01
Write Cycle (OE Controlled Write)
SPT03027
"H" or "L"
DS
RAL
CAS
V
OH
V
(Inputs)
(Outputs)
I/O
I/O
V
V
OL
IL
V
IH
OE
WE
V
IL
IL
V
IH
V
IH
t
DZO
Hi Z
t
CLZ
t
OEA
t
OEZ
t
DZC
ODD
t
t
V
Address
IL
V
V
IH
CAS
RAS
V
IL
V
IH
IL
V
IH
RAD
ASR
t
RAH
t
Row
tt
Column
ASC
t
CAH
RCD
t
t
t
CSH
t
RAS
t
Hi
Valid Data
t
DH
OEH
t
Z
RWL
CWL
tt
WP
t
RSH
t
ASR
t
Row
CRP
t
t
RC
t
RP
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 16 1998-10-01
Read-Write (Read-Modify-Write) Cycle
SPT03028
"H" or "L"
AWD
OEA
CSH
RWD
OH
I/O
(Outputs)
V
OL
(Inputs)
I/O
IL
V
V
V
IH
OE
WE
V
IL
V
IH
V
IL
V
IH
RAC
t
t
DZC
t
DZO
t
CLZ
t
CAC
t
RCS
t
AA
t
V
Address
V
IL
V
IH
CAS
RAS
IH
V
IL
V
V
IL
IH
RAH
Row
ASR
t
t
RAD
t
Column
ASC
t
t
t
CAH
t
RCD
t
t
t
WP
Data
OUT
DS
ODD
OEZ
t
t
t
t
Data IN
Valid
t
DH
OEH
Row
t
CWD
t
CAS
tt
RSH
RWL
t
t
CWL
ASR
t
CRP
t
RP
t
RWC
t
RAS
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 17 1998-10-01
Hyper Page Mode (EDO) Read Cycle
SPT03038
"H" or "L"
Data
Column
t
t
OH
OL
IL
IH
IL
IH
I/O
(Output)
V
V
V
OE
WE
V
V
V
RCS
CAC
t
CLZ
RAC
t
AA
tt
OES
OEA
tt
IH
IL
IL
IH
IH
IL
Address
V
V
CAS
RAS
V
V
V
V
RCD
ASC
ColumnRow
ASR
t
RAD
t
t
RAH
t
t
CRP
t
1
CSH CAH
t
ASC
t
HPC
CAS
t
tt
CP
t
RCH
t
OUTOUT
t
COH
OUT 1 Data
AA
t
CPA
t
CAC
t
t
COH
2 Data
t
AA
CPA
t
CAC
t
t
N
OEZ
OFF
CRP
RP
RHCP
Column2
CAH
t
CAS
t
N
t
CAH
ASC
t
t
RAL
RRH
t
RSH
t
CAS
t t
t
RAS
t
t
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 18 1998-10-01
Hyper Page Mode (EDO) Early Write Cycle
SPT03039
"H" or "L"
DS
Data
Column
t
IH
V
I/O
(Input)
OE
V
V
IL
IH
V
IL
WE
V
V
IL
IH
Data
t
DS
WCS
t
IN 1
t
DH
t
WP
CWL
t
t
WCH
t
t
WCS
CAS
Address
V
IL
V
IH
IL
V
RAS
V
IH
IL
V
V
IH
t
t
ASC
Column
Address
Row
ASR
t
RAD
t
RAH
tt
CRP
t
RCD
1
t
CSH
CAH
ASC
t
HPC
CAS
t
t
CP
t
Data
DS
IN 2
t
DH
t
CWL
WCH
WP
tt
tt
WCS
IN N
t
DH
t
t
WCH
WP
t
CWL
CRP
RP
t
Column2
CAH
t
ASC
t
t
CAS
RWL
t
N
t
CAH
t
RAL
RSH
t
CAS
t
RHCP
t
t
RAS
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 19 1998-10-01
Hyper Page Mode (EDO) Late Write and Read-Modify Write Cycle
SPT03031
"H" or "L"
IL
Data
RAC
(Outputs)
I/O
V
OH
OL
V
OUT
Data
OEZ
t
I/O
(Inputs)
OE
CLZ
t
V
IL
V
IH
DZC
t
t
CAC
t
DS
DZO
t
ODD
t
V
IL
IH
V
t
AWD
t
AA
t
OEA
t
t
OEH
AADSAA
OUT
Data
t
OUT
Data
OEZ OEZ
t
ODD
IN
DH
t
t
CPA
t
DZC
tt
INData
DH
t
tt
CAC
t
DZC
tt
CPA
OEH
CLZ
t
WP
tt
OEA
t
AWD
t
CLZ
t
WP
t
OEA
t
AWD
t
INData
DS
t
DH
t
ODD
t
WP
t
OEH
t
Address
WE
CAS
V
RCS
V
V
IH
t
Row
V
IL
IH
t
CWD
t
CWL
RWD
t
Column
IL
V
ASR
tt
RAH ASC
t
RAD
t
IH
V
RCD
t
t
CAH
CAS
t
RAS
IL
V
V
IH
t
CSH
CWD
CWL
t
CWD
t
Column
CPWD
tt
t
CPWD
Column
PRWC
ASC
t
CAH
t
t
CP
CAS
tt
ASC
t
t
CAH
CWL
t
RWL
t
Row
CRP
t
RAL
RSH
CAS
ttt
ASR
t
RAS
t
t
RP
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 20 1998-10-01
RAS-only Refresh Cycle
SPT03032
"H" or "L"
OH
OL
(Outputs)
Address
I/O
V
V
V
IL
IH
V
Row
CAS
RAS
IL
V
V
IH
V
IL
IH
V
RAH
ASR
tt
RAS
t
Row
ZHi
t
RC
t
RPC
ASR
t
CRP
t
RP
t
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 21 1998-10-01
CAS-before-RAS Refresh Cycle
SPT03033
"H" or "L"
V
IL
IH
IH
IL
OL
OH
IL
(Outputs)
I/O
V
V
(Inputs)
OE
I/O
V
V
V
V
t
OFF
OEZ
t
t
CDD
ODD
t
IH
IL
IH
IH
IL
WE
CAS
V
V
V
RAS
V
V
WRP
CSR
t
t
CP
t
RPC
t
RP
t
t
WRH
t
CHR
Hi Z
RAS
t
RC
t
t
RPC
t
RP
t
CRP
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 22 1998-10-01
Hidden Refresh Cycle (Read) Cycle
V
CLZ
I/O
(Outputs)
OL
V
"H" or "L"
OH
V
I/O
(Inputs)
IL
V
IH
V
t
RAC
t
DZO
t
OE
V
IL
IH
V
WE
IL
IH
V
DZC
t
Valid Data OUT
SPT03034
t
CAC
OEA
AA
t
t
OFF
OEZ
t
t
Hi
t
ODD
Z
CDD
t
Column
RAS
ASR
V
Address
IL
IH
V
t
RCS
t
Row
RAH
ASC
tt
CAS
IL
V
IH
V
RAS
IL
V
IH
V
t
RCD
RAD
t
t
WRP
t
RRH
CAH
t
t
WRH
t
t
RSH
t
CHR
RAS
t
ASR
t
Row
CRP
t
RC
tt
RP
RC
t
RP
t
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 23 1998-10-01
Hidden Refresh Early Write Cycle
SPT03035
"H" or "L"
WRP
ColumnRow
Address
(Output)
(Input)
I/O
I/O
OL
V
OH
V
IN
V
V
IL
WE
IL
V
IH
V
V
IL
Valid Data
t
DS
t
WCS
t
DH
WP
t
WCH
tt
ASR
V
CAS
IH
V
t
IL
IH
V
RAS
V
IL
IH
V
RAS
ASC
RAH
tt
t
RAD
RCD
t
t
CAH
t
RSH
t
RC
t
RP
t
Row
Hi Z
t
WRH
RC
t
RAS
CHR
tt
ASR
t
CRP
t
RP
t
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 24 1998-10-01
Self Refresh
SPT03058
"H" or "L"
V
IL
IH
IH
IL
OL
OH
IL
(Outputs)
I/O
V
V
(Inputs)
OE
I/O
V
V
V
V
t
t
t
OEZ
CDD
ODD
t
~
~~
~~
~~
~
~
~
IH
IL
IH
IH
IL
CAS
WE
V
V
V
RAS
V
V
CSR
t
WRP
t
CP
t
RPC
t
RP
t
WRH
t
~
~~
~ ~
~
t
RASS
Hi Z
CHS
t
CRP
t
RPS
t
OFF
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 25 1998-10-01
CAS-before-RAS Refresh Counter Test Cycle
SPT03036
"H" or "L"
t
WCH
t
t
DZC
t
(Inputs)
I/O
(Outputs)
I/O
OH
OL
V
IL
V
V
IH
V
OE
WE
Write Cycle
IL
IL
V
IH
V
V
IH
V
I/O
(Inputs)
I/O
(Outputs)
OL
V
OH
V
IL
V
IH
V
t
DS
ZHi
Data IN
t
WRP
WRH
t
DH
t
t
DZO
WCS
t
tt
CLZ
OE
WE
IL
V
IH
V
IL
V
IH
V
Address
CAS
IH
IL
V
V
V
IL
IH
V
Read Cycle
RAS
V
IH
IL
V
WRP
t
WRH
t t
RCS
AA
t
CAC
t
ASC
tt
CAH
Column
CSR
t
CHR
t
CP
t
RAS
t
RWL
CWL
t
Data OUT
t
OEZ
t
OFF
t
ODD
OEA
t
RRH
RAL
CAS
t
CDD
t
RCH
t
t
ASR
Row
RSH
t
t
RP
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 26 1998-10-01
Test Mode Entry
SPT03042
"H" or "L"
OL
OH
I/O
(Inputs)
(Outputs)
I/O
V
V
V
IL
OE
WE
V
IH
V
IH
V
IL
V
IL
V
IH
OFF
t
OEZ
t
CDD
t
Hi Z
ODD
t
CAS
Address
IH
V
V
IL
V
IL
RAS
V
IH
V
IH
V
IL
RPC
t
t
CP
t
RP
RAH
WTS
t
Row
ASR
tt
t
WTH
CSR
tt
CHR
Hi Z
t
RC
RAS
t
t
RPC
CRP
t
t
RP
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 27 1998-10-01
Package Outlines
0.8 min
-0.25
8.63
±0.2
6.8
-0.5
3.75
±0.1
2.64
1.27 0.85 max
-0.1
0.51
Index Marking -0.25
17.27
26
1
1)
0.1
0.5
30˚
7.75
-0.25
0.2
+0.1
21
6
19
8
14
13
0.18 24x
15.24
A
0.25
B
0.18
B
0.25
B
A
1) Does not include plastic or metal protrusions of 0.15 max per side
M
1)
M
Plastic Package P-SOJ-26/24-1 (SMD) (300mil)
(Plastic small outline J-leaded)
GPJ05628
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm
SMD = Surface Mounted Device
HYB 5116(7)405BJ-50/-60
HYB 3116(7)405BJ/BT(L)-50/-60
4M × 4 EDO-DRAM
Semiconductor Group 28 1998-10-01
GPX05857
17.14
±0.131)
26
Index Marking
1.27
0.4
+0.12
-0.1
0.2
M
24x
0.1
1.2 max
0.1
7.62
±0.13
±0.2
9.22
-0.2
0.6
0.15
+0.06
-0.03
5˚ max
2119 14
16813
±0.05
1
±0.05
Does not include plastic or metal protrusion of 0.15 max per side
1)
Plastic Package P-TSOPII-26/24-1 (400 mil) (SMD)
(Plastic Thin Small Outline Package (Type II))
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm
SMD = Surface Mounted Device