Rev. 4180E–8051–10/06
Features
•80C52 Compatibl e
– 8051 Pin and I nstruction Compatible
– Four 8-bit I/O Ports
– Three 16-bit Timer/ Counters
– 256 Bytes Scratch Pad RAM
– 9 Interrupt Sources with 4 Priorit y Levels
– Dual Data Pointer
•Variable Lengt h MOVX for Slow RAM/Peripherals
•ISP (In-system Programming) Using Standard VCC Power Suppl y
•Boot ROM Contains Low Level Flash Progr am ming Routi nes and a Default Serial
Loader
•High-speed Architecture
– In Standard Mod e:
40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code executio n on ly)
– In X2 mode (6 Clocks/machine cycle)
20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code executio n on ly)
– 16K /32K Bytes On-chip Flash Program/Data Memory
– Byte and Page (128 Bytes) Erase and Write
– 100K Write Cycles
•On-chip 1024 Bytes Expanded RAM (XRAM)
– Software Selectable Size (0 , 256, 512, 768, 1024 Bytes)
– 256 Bytes Sel ected at Reset for TS87C51RB2/RC2 Comp atibility
•Keyboard Interrupt Interface on Port P1
•SPI Int erface (Master/Sl ave Mode)
•8-bit Clo ck Prescaler
•Improved X2 Mode with Inde pendent Selecti on for CPU and Each Periphe ral
•Programmable Counter Array 5 Channel s
– High-speed Output
– Compare/Capture
– Pulse Width Modulator
– W atchdog Timer Capabilities
•Asynchronous Port Reset
•Full Duplex Enhanced UART
•Dedicated Baud Rat e Generat or fo r UART
•Low EMI (Inhibit ALE)
•Hardware Watchdog Timer (One-time Enabl ed wit h Reset- out)
•Power Contr ol Modes
– Idle Mode
– Power-down Mode
– Power-off Flag
•Power Supply:
– 2.7 to 3.6 (3V Version)
– 2.7 to 5.5V (5V Version)
•Tem perature Ranges : Commercial (0 to +70°C) and Industri al ( -40°C to + 85 °C)
•Packages: PDIL40, PLCC44, VQFP44
Description
The AT89C51RB2/RC2 is a high-performance Flash version of the 80C51 8-bit micro-
controllers. It contains a 16K or 32K Bytes Flash memory block for program and data.
The F lash m em ory c an be p rogram med either in parallel mode or in seria l mo de with
the IS P c apability or wi th software . Th e prog ramm ing voltage i s int ernally gene rate d
from the standard V CC pin.
8-bit
Microcontroller
with 16K/
32K Bytes Flash
AT89C51RB2
AT89C51RC2
2
AT89C51RB2/RC2
4180E–8051–10/06
The AT89C51RB2/RC2 retains all features of the 80C52 with 256 Bytes of internal
RAM, a 9-source 4-level interrupt controller and three timer/coun ters.
In addition, the AT89C51RB2/RC2 has a Programmable Counter Array, an X RAM of
1024 Bytes, a Hardware Watchdog Timer, a Keyboard Interface, an SPI Interface, a
more versatile serial channel that facilitates multiproc essor communication (EUART)
and a speed improvement mechanism (X2 mode).
The Pinout is the standard 40/44 pins of the C52.
The fully static design reduces s ystem power con sumption of the AT89C51RB2/ RC2 by
allowing it to br ing the clock frequency down to any value, even DC, without loss of dat a.
Th e AT 89C5 1RB 2/RC 2 has 2 soft ware -sel ecta ble mo des of redu ced acti vity and 8 -bit
clock pr escaler for further reduc tion in power consumption. In Idle mode, the CPU is fro-
zen while the peripherals and the interrupt s ys tem are still operating. In power-down
mode, the RAM is saved and all other functions are inoperat ive.
The added features of the AT89C51RB2/RC2 make it more powerful for applicat ions
that need pulse width modulation, high sp eed I/O and counting capabilities such as
alarms, motor control , corded phones, and smart card readers.
Table 1. Memory Size
Par t Number Flash (Bytes) XR AM (Byt es) TOTA L RAM
(Bytes) I/O
AT89C51RB2 16K 1024 1280 32
AT89C51RC2 32K 1024 1280 32
AT89C51IC2 32K 1024 1280 32
3
AT89C51RB2/RC2
4180E–8051–10/06
Block Diagram
Figu re 1. Block Diagram
Notes: 1. Alter nate funct ion of Port 1.
2. Alter nate funct ion of Port 3.
Timer 0 INT
RAM
256x8
T0
T1 RxD
TxD
WR
RD
EA
PSEN
ALE/
XTAL2
XTAL1
EUART
CPU
Timer 1
INT1
Ctrl
INT0
(2)
(2)
C51
CORE
(2) (2) (2) (2)
Port 0
P0
Port 1 Port 2 Port 3
Parallel I/O Ports & Ext. Bus
P1
P2
P3
XRAM
1Kx8
IB-bus
PCA
RESET
PROG
Watch
Dog
PCA
ECI
Vss
VCC
(2)(2) (1)(1)
Timer2
T2EX
T2
(1) (1)
Flash
32Kx8 or
16Kx8
Key
Board
ROM
2Kx8
Boot
+
BRG
SPI
MISO
MOSI
SCK
(1)(1) (1)
SS
(1)
4
AT89C51RB2/RC2
4180E–8051–10/06
SFR Mapping The Specia l Function Registers (SFRs) o f the AT89C 51RB2 /RC2 fall into t he follo wing
categories:
• C51 core registers: ACC, B, DPH, DP L, PSW, SP
• I/O port registers: P0, P1, P2, P3
• T i m er registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
• Se rial I/O port registers: SADDR, SADEN, SBUF, SCON
• PCA (Programmable Count er Array) registers: CCON, CCAPMx, CL, CH, CCAPxH,
CCAPxL (x: 0 t o 4)
• Power and clock control regist ers: PCON
• Hardware Watchdog Timer registers: WDTRST, WDTPRG
• Interrupt system registers: IEN0, IPL0, IPH 0, IE N1, IPL1, IPH1
• Keyboard Interface registers: KBE, KBF, KBLS
• S PI r e gisters: SPCON , SPSTR, SPDAT
• BRG (Baud Rate Generator) registers: BRL, BDRCON
• Flash register: FCON
• Clock Prescaler register: CKRL
• Others: A UXR, AUXR1, CKCON0, CKCON1
5
AT89C51RB2/RC2
4180E–8051–10/06
Table 2. C51 Core SFRs
MnemonicAddName 76543210
ACC E0h Accumulator
B F0h B Register
PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P
SP 81h Stac k Pointe r
DPL 82h Data Pointer Low Byte
DPH 83h Data Pointer High Byte
Table 3. System Management SFRs
MnemonicAddName 76543210
PCON 87h Power Control SMOD1 SMOD0 - POF GF1 GF0 PD IDL
AUXR 8Eh Auxiliary Register 0 DPU - M0 XRS2 XRS1 XRS0 EXTRAM A O
AUXR1 A2h Auxiliary Register 1 - - ENBOOT - GF3 0 - DPS
CKRL 97 h Clock Reload Register CKRL7 CKRL6 CKRL5 CKRL4 CKRL3 CKRL2 CKRL1 CKRL0
CKCKON0 8Fh Clock Control Register 0 - WDTX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
CKCKON1AFhClock Control Register 1-------SPIX2
Table 4. Interrupt SFRs
MnemonicAddName 76543210
IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0
IEN1B1hInterrupt Enable Control 1 -----ESPI EI2C KBD
IPH0 B7h Interrupt Priority Control High 0 - PPCH PT2H PHS PT1H PX1H PT0H PX0H
IPL0 B8h Interrupt Priority Control Low 0 - PPCL PT2L PLS PT1L PX1L PT0L PX0L
IPH1B3hInterrupt Priority Control High 1-----SPIHIE2CHKBDH
IPL1B2hInterrupt Priority Control Low 1-----SPILIE2CLKBDL
Table 5. Port SFRs
MnemonicAddName 76543210
P0 80h 8-bit Port 0
P1 90h 8-bit Port 1
P2 A0h 8-bit Port 2
P3 B0h 8-bit Port 3
6
AT89C51RB2/RC2
4180E–8051–10/06
Table 6. Ti mer S FR s
MnemonicAddName 76543210
TCO N 88 h Time r/C o unte r 0 and 1 Co nt r ol T F1 TR1 TF0 TR 0 IE1 IT1 IE0 IT0
T MOD 89h Time r /Coun te r 0 and 1 Mo de s G AT E 1 C/ T1 # M11 M0 1 GATE 0 C/ T0 # M1 0 M0 0
TL0 8Ah Timer/Counter 0 Low Byte
TH0 8Ch Timer/Counter 0 High Byte
TL1 8Bh Timer/Counter 1 Low Byte
TH1 8Dh Timer/Counte r 1 High Byte
WD TRST A6h Watchdog Timer Reset
WDTPRGA7hWatchdog Timer Program -----WTO2WTO1WTO0
T2CON C8h Tim er/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
T2MODC9hTimer/Counter 2 Mode ------T2OEDCEN
RCAP2H CBh T imer/C ounter 2 Re load /Cap ture
High Byte
RCAP2L CAh T im er/Cou nter 2 Re load/C aptur e
Low Byte
TH2 CDh Ti mer/Counte r 2 High Byte
TL2 CCh Timer/Counter 2 Low Byte
Table 7. PCA SFRs
Mnemo-
nic AddName 76543210
CCON D8h PCA Ti mer/Counter Control CF CR - CCF4 CCF3 CCF2 CCF1 CCF0
CMOD D9h PCA Timer/Counter Mode CIDL WDTE - - - CPS1 CPS0 ECF
CL E9h P CA Timer/Counter Low Byte
CH F9h PCA Timer/Counter High Byte
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
DAh
DBh
DCh
DDh
DEh
PCA Timer/Counter Mode 0
PCA Timer/Counter Mode 1
PCA Timer/Counter Mode 2
PCA Timer/Counter Mode 3
PCA Timer/Counter Mode 4
-
ECOM0
ECOM1
ECOM2
ECOM3
ECOM4
CAPP0
CAPP1
CAPP2
CAPP3
CAPP4
CAPN0
CAPN1
CAPN2
CAPN3
CAPN4
MAT0
MAT1
MAT2
MAT3
MAT4
TOG0
TOG1
TOG2
TOG3
TOG4
PWM0
PWM1
PWM2
PWM3
PWM4
ECCF0
ECCF1
ECCF2
ECCF3
ECCF4
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
FAh
FBh
FCh
FDh
FEh
PC A Compare Captu re Module 0 H
PC A Compare Captu re Module 1 H
PC A Compare Captu re Module 2 H
PC A Compare Captu re Module 3 H
PC A Compare Captu re Module 4 H
CCAP0H7
CCAP1H7
CCAP2H7
CCAP3H7
CCAP4H7
CCAP0H6
CCAP1H6
CCAP2H6
CCAP3H6
CCAP4H6
CCAP0H5
CCAP1H5
CCAP2H5
CCAP3H5
CCAP4H5
CCAP0H4
CCAP1H4
CCAP2H4
CCAP3H4
CCAP4H4
CCAP0H3
CCAP1H3
CCAP2H3
CCAP3H3
CCAP4H3
CCAP0H2
CCAP1H2
CCAP2H2
CCAP3H2
CCAP4H2
CCAP0H1
CCAP1H1
CCAP2H1
CCAP3H1
CCAP4H1
CCAP0H0
CCAP1H0
CCAP2H0
CCAP3H0
CCAP4H0
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
EAh
EBh
ECh
EDh
EEh
PCA Compare Capture Module 0 L
PCA Compare Capture Module 1 L
PCA Compare Capture Module 2 L
PCA Compare Capture Module 3 L
PCA Compare Capture Module 4 L
CCAP0L7
CCAP1L7
CCAP2L7
CCAP3L7
CCAP4L7
CCAP0L6
CCAP1L6
CCAP2L6
CCAP3L6
CCAP4L6
CCAP0L5
CCAP1L5
CCAP2L5
CCAP3L5
CCAP4L5
CCAP0L4
CCAP1L4
CCAP2L4
CCAP3L4
CCAP4L4
CCAP0L3
CCAP1L3
CCAP2L3
CCAP3L3
CCAP4L3
CCAP0L2
CCAP1L2
CCAP2L2
CCAP3L2
CCAP4L2
CCAP0L1
CCAP1L1
CCAP2L1
CCAP3L1
CCAP4L1
CCAP0L0
CCAP1L0
CCAP2L0
CCAP3L0
CCAP4L0
7
AT89C51RB2/RC2
4180E–8051–10/06
Table 8. Serial I/O Port SFRs
MnemonicAddName 76543210
SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
SBUF 99h Serial Data Buffer
SADE N B9h Slave Addre ss Mask
SADDR A9h Slave Addre ss
BDRCON 9Bh Baud Rate Control BRR TBCK RBCK SPD SRC
BRL 9Ah Baud Rate Reload
Table 9. SPI Controller SFRs
MnemonicAddName 76543210
SPCON C3h SPI Control SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPSTA C4h SPI Status SPIF WCOL SSERR MODF ----
SPDAT C5h SPI Data SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0
Table 10. Keyboard Interface SF Rs
MnemonicAddName 76543210
KBLS 9Ch Keyboard Level Selector KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
KBE 9Dh Keyboard Input Enable KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
KBF 9Eh Keyboard Flag Register KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
8
AT89C51RB2/RC2
4180E–8051–10/06
Table 11 shows all SFRs with their address and their res et va lue.
Table 1 1. SFR Mapping
Bit
addressable Non Bit addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h CH
0000 0000 CCAP0H
XXXX CCAP1H
XXXX CCAPL2H
XXXX CCAPL3H
XXXX CCAPL4H
XXXX FFh
F0h B
0000 0000 F7h
E8h CL
0000 0000 CCAP0L
XXXX XXXX CCAP1L
XXXX XXXX CCAPL2L
XXXX XXXX CCAPL3L
XXXX XXXX CCAPL4L
XXXX XXXX EFh
E0h ACC
0000 0000 E7h
D8h CCON
00X0 0000 CMOD
00XX X000 CCAPM0
X000 0000 CCAPM1
X000 0000 CCAPM2
X000 0000 CCAPM3
X000 0000 CCAPM4
X000 0000 DFh
D0h PSW
0000 0000 FCON (1)
XXXX 0000
1. FCON access is reserved for the Flash API and ISP softw are.
Reserved
D7h
C8h T2CON
0000 0000 T2MOD
XXXX XX00 RCAP2L
0000 0000 RCAP2H
0000 0000 TL2
0000 0000 TH2
0000 0000 CFh
C0h SPCON
0001 0100 SPSTA
0000 0000 SPDAT
XXXX XXXX C7h
B8h IPL0
X000 000 SADEN
0000 0000 BFh
B0h P3
1111 1111 IEN1
XXXXX 000 IPL1
XXXXX000 IPH1
XXXX X00 0 IPH0
X000 0000 B7h
A8h IEN0
0000 0000 SADDR
0000 0000 CKCON1
XXXX XXX0 AFh
A0h P2
1111 1111 AUXR1
XXXXX0X0 WDTRST
XXXX XXXX WDTPRG
XXXX X00 0 A7h
98h SCON
0000 0000 SBUF
XXXX XXXX BRL
0000 0000 BDRCON
XXX0 0000 KBLS
0000 0000 KBE
0000 0000 KBF
0000 0000 9Fh
90h P1
1111 1111 CKRL
1111 1111 97h
88h TCON
0000 0000 TMOD
0000 0000 TL0
0000 0000 TL1
0000 0000 TH0
0000 0000 TH1
0000 0000 AUXR
XX0X 0000 CKCON0
0000 0000 8Fh
80h P0
1111 1111 SP
0000 0111 DPL
0000 0000 DPH
0000 0000 PCON
00X1 0000 87h
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
9
AT89C51RB2/RC2
4180E–8051–10/06
Pin C onfigurations
Figu re 2. Pin Confi gurations
P1.7CEX4/MOSI
P1.4/CEX1
RST
P3.0/RxD
P3.1/TxD
P1.3CEX0
1
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
P2.7/A15
P2.5/A13
P2.6/A14
P1.0/T2
P1.2/ECI
P1.1/T2EX/SS VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
PDIL40
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
43 42 41 40 3944 38 37 36 35 34
P1.4/CEX1
P1.0/T2
P1.1/T2EX/SS
P1.3/CEX0
P1.2/ECI
NIC*
VCC
P0.0/AD0
P0.2/AD2
P0.3/AD3
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
NIC*
P2.7/A15
P2.5/A13
P2.6/A14
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
NIC*
1213 17161514 201918 2122
33
32
31
30
29
28
27
26
25
24
23
VQFP44 1.4
1
2
3
4
5
6
7
8
9
10
11
18 19 23222120 262524 27 28
5 4 3 2 1 6 44 43 42 41 40
P1.4/CEX1
P1.0/T2
P1.1/T2EX/SS
P1.3/CEX0
P1.2/ECI
NIC*
VCC
P0.0/AD0
P0.2/AD2
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
NIC*
P2.7/A15
P2.5/A13
P2.6/A14
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEx4/MOSI
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P0.3/AD3
NIC*
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
PLCC44
*NIC: No Internal Connection
10
AT89C51RB2/RC2
4180E–8051–10/06
Tab le 12. Pin Descr iption for 40 - 44 Pin Packages
Mnemonic
Pin Number
Type Name and FunctionDIL LCC VQFP44 1.4
VSS 20 22 16 I Ground: 0V reference
VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle and power-down
operation
P0.0 - P0.7 39 - 32 43 - 36 37 - 30 I/O Po rt 0: Port 0 is an open-drain, bi -directional I/O port . Port 0 pins that have 1 s
written t o them float and can be used as high impedance inputs. Port 0 mu st be
pola r ize d to V CC or VSS in order to prevent any parasitic current consumption. Port 0
is also the multiplexed low-order address and da ta bus during ac cess to e xtern al
program and dat a memory. In this application, it uses strong internal pull-up when
emitting 1s. Por t 0 also input s the code Bytes duri ng F lash pr ogramming. External
pull-up s are required during program verificati on dur ing which P0 outputs t he code
Bytes.
P1.0 - P1.7 1 - 8 2 - 9 40 - 44
1 - 3 I/O Po r t 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 1 pins that are externally pulled low will source current
because of the internal pull-ups. Port 1 also receives the low-order address Byte
during mem ory programmi ng and verification.
A lter nate func tion s for AT89 C51 RB2 /R C2 Port 1 incl ude:
1 2 40 I/O P1.0: Input/Output
I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout
2 3 41 I/O P1.1: Input/Output
IT2EX: Timer/Counter 2 Reload/Capture/Direction Control
ISS: SPI Slave Se lect
3 4 42 I/O P1.2: Input/Output
IECI: Extern al Clock for th e PCA
4 5 43 I/O P1.3: Input/Output
I/O CEX0: Capture/Compare External I/O for PCA Module 0
5 6 44 I/O P1.4: Input/Output
I/O CEX1: Capture/Compare External I/O for PCA Module 1
6 7 1 I/O P1.5: Input/Output
I/O CEX2: Capture/Compare External I/O for PCA Module 2
I/O MISO: SPI Master Input Slave Output line
When SP I is in mast er mode, MISO receives data from the slave peripheral. When
SPI is in slave mode, MISO output s data to the master controller .
7 8 2 I/O P1.6: Input/Output
I/O CEX3: Capture/Compare External I/O for PCA Module 3
I/O SCK: SPI Ser ial Clock
SCK outputs clock to the slave peripheral
8 9 3 I/O P1.7: Input/Output:
11
AT89C51RB2/RC2
4180E–8051–10/06
I/O CEX4: Capture/Compare External I/O for PCA Module 4
P1.0 - P1.7 I/O MOSI: SPI Master Output Slave Input line
When SPI is in master mode , MOSI outputs data to the slave peripheral. When SPI
is in slave mode, MOSI receives data fr om the master controller.
XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generat or circuits.
XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier
P2.0 - P2.7 21 - 28 24 - 31 18 - 25 I/O Po rt 2 : Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 2 pins that are externally pulled low will source current
because of the internal pull-ups. Port 2 emits the high - order address Byte during
fetches f rom external program memory and during accesses to external da ta
mem ory tha t use 16- bit addresses (MOV X @DPTR). In this app lication, it uses
strong internal pull-ups emitting 1s. During accesses to external data memory that
use 8-bit addresses (MO VX @Ri), port 2 em its the contents of the P2 SFR. S ome
Port 2 pins receive the high order address bits during EPR OM programming a nd
verification:
P2.0 to P2.5 for 16 KB devices
P2.0 to P2.6 for 32KB devices
P3.0 - P3.7 10 - 17 11,
13 - 19 5,
7 - 13 I/O Po rt 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally pulled low will source current
because of the internal pull-ups. Port 3 also serves the special features of the
80C51 fam ily, as listed below.
10 11 5 I RXD (P3.0): Seri al inpu t port
11 13 7 O TXD (P3.1): Serial output port
12 14 8 I INT0 (P3.2): Exte rna l in terr up t 0
13 15 9 I INT1 (P3.3): Exte rna l in terr up t 1
14 16 10 I T 0 (P3.4): Timer 0 external input
15 17 11 I T1 (P3.5): Timer 1 external input
16 18 12 O WR (P3.6): External dat a memory write strobe
17 19 13 O RD (P3.7): External data memory read strobe
RST 9 10 4 I/O
Reset: A high on this p in for two machine cycles whil e the oscilla tor is ru nning,
resets the device. An internal diffused resistor to VSS permits a power-on reset u sing
only an external capacitor to VCC. This pin is an outpu t when th e hardware
watchdog forces a system reset.
ALE/PROG 30 33 27 O (I) Add ress Latch Enable/Program Pu lse: Ou tp ut puls e for la tc hin g th e low Byte of
the addres s during an access to external m emory. In normal oper ation, A LE is
emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can
be us ed for external timing or clocking. Note t hat one ALE pulse is s kipped during
each access to external data memory. This pin is also the program pulse input
(PROG) d uri ng Flas h p rogr a mmi ng. ALE can be disa bl ed by s ett in g SF R’ s A UX R. 0
bit. With this bit set, ALE will be inactive during internal fetches.
Tab le 12. Pin Descr iption for 40 - 44 Pin Packages (Continued)
Mnemonic
Pin Number
Type Name and FunctionDIL LCC VQFP44 1.4
12
AT89C51RB2/RC2
4180E–8051–10/06
PSEN 29 32 26 O Program Strobe Enable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is acti vate d tw ic e ea ch
machine cycle, except that two PSEN activ at io ns are sk ip pe d dur i ng ea ch ac ces s t o
external data memory. PSEN is not activated during fetches from internal program
memory.
EA 31 35 29 I External Access Enable: EA must be externally held low to enable the device to
fetch code from external program memory locations 0000H to FFFFH (RD). If
sec urity level 1 is pro grammed, EA will be internally latched on Reset.
Tab le 12. Pin Descr iption for 40 - 44 Pin Packages (Continued)
Mnemonic
Pin Number
Type Name and FunctionDIL LCC VQFP44 1.4
13
AT89C51RB2/RC2
4180E–8051–10/06
Port Types AT 89C51RB 2/RC 2 I/O ports (P1, P2 , P3) implemen t the q uasi- bidirectio nal output th at
is c om mon on th e 80C 51 and mos t o f its d eriva tive s. Th is outp ut ty pe ca n b e used as
both an input an d outpu t w ithout the need to reconfigure the port. This is possible
because when the port outputs a logic high, it is weakly driven, allowing an external
device to pull t he pin low. When the pin i s pull ed low, i t is driven st rongly and able to sink
a fairly large current. These features are somewhat similar to an open drain output
except tha t there are three pull-up transistors in the quasi-bidirectional outpu t that serve
different purpo ses. One o f these pull-ups, c alled the "weak" pull-up, is turned on when-
ever the port latch for the pin contains a logic 1. The weak pull-up sources a very small
current that will pull the pin high if it is left f l oating. A second pull- up, called the "medium"
pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is
also at a logic 1 level. This pu ll-up provides t he primary source current for a quasi-bidi-
rectional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an
externa l device, the m edium pull-u p turns o ff, and only the we ak pull-up rem ains on. In
order to pull the pin low under these cond iti ons, the external device has to sink enou gh
cu rr ent to o verpow er the me dium pull -up and take the v oltage on the po rt pin bel ow its
input threshold.
The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up
low-to-high transit i ons on a quasi-bidirectional port pi n when the port latch changes from
a logic 0 to a lo gic 1. When this oc curs , the strong pull-up t urns on for a brief t ime, two
CPU clocks, in order to pull t he port pin high quickly. Then it turns off again.
The DP U bit (bit 7 in AUX R register) allows to disable the perman ent we ak pull up of all
ports when latch data is logical 0.
The quasi-bid irectional port configuration is shown in Figure 3.
Figu re 3. Quasi-B idire ctional Out put
2 CPU
Input
Pin
Strong Medium
N
Weak
P
Clock Delay
Port Latch
Data
Data
DPU
AUXR.7
PP
14
AT89C51RB2/RC2
4180E–8051–10/06
Oscillator To optim ize th e p ower co nsu mpti on an d ex ecut ion ti me n eede d fo r a speci fic task, a n
internal, pr escaler feature has been implemented between the oscillator and the CPU
and peripherals.
Registers Table 13. CK RL Register
CKRL – Clock Reload Register (97h)
Rese t Value = 1111 1111b
Not bit addressable
Table 14. PCO N Regist er
PCO N – Power Control Register (87h)
Rese t Value = 00X1 0000b Not bit addressable
76543210
CKRL7 CKRL6 CKRL5 CKRL4 CKRL3 CKRL2 CKRL1 CKRL0
Bit Number Mnemonic Description
7:0 CKRL Clo ck Reload Register
Prescaler valu e
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit Number Bit Mnemonic Description
7SMOD1
Serial Port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6SMOD0
Serial Port Mode bit 0
Cl ea red to selec t SM0 bit in SCON re gi ster.
Set to select FE bit in SCON register .
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4POF
Power-off Flag
Cleared to recognize next reset type.
Set by ha rdw ar e when VCC ris es from 0 to it s nomina l vo lt a ge. Can
also be set by software.
3GF1
Gen era l-pu r pos e Fla g
Cleared by software for general-purpose usage.
Set b y sof twa r e fo r ge ner al -pu rp os e usa ge .
2GF0
Gen era l-pu r pos e Fla g
Cleared by software for general-purpose usage.
Set b y sof twa r e fo r ge ner al -pu rp os e usa ge .
1PD
Power-down Mo de bit
Cleared by hardware when reset o ccurs.
Set to enter power-down mode.
0IDL
Idle Mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
15
AT89C51RB2/RC2
4180E–8051–10/06
Fu nct ional Block
Diagram
Figu re 4. Functional Oscillator Block Diagram
Prescaler Divid er • A hardwa re RESET puts the prescaler divider in the following state:
•CKRL = FFh: F
CLK CPU = FCLK PERIPH = FOSC/2 (S tandard C51 feature)
• Any value between FFh down to 00h can be written by software into CKR L register
in order to divide frequency of the sele cted os c illator:
• CKRL = 00h: minimum frequen cy
FCLK CPU = F CLK PERIPH = FOSC/1020 (Standard Mode )
FCLK CPU = F CLK PERIPH = FOSC/510 (X2 Mode)
• CKRL = FF h: maximum freque ncy
FCLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode)
FCLK CPU = FCLK PERIPH = FOSC (X2 Mode)
FCLK CPU and FCLK PERIPH
In X2 Mode, for CKRL<>0xFF:
In X1 Mode, for CKRL<>0xF F then:
Xtal2
Xtal1
Osc
CLK
Idle
CPU clock
CKRL
Reload
8-bit
Prescaler-Divider
Reset
Peripheral Clock
:2
X2
0
1
FOSC
CKCON0
CLK
PERIPH
CPU
CKRL = 0xFF?
0
1
F
CPU F=CLKPERIPH
F
OSC
2 255 CKRL
–
()×
--------------------------------------------
---
=
F
CPU F=CLKPERIPH
F
OSC
4 255 CKRL
–
()×
--------------------------------------------
---
=
16
AT89C51RB2/RC2
4180E–8051–10/06
Enhanced Features I n comp arison to the original 80C52, the AT 89C51RB2/ RC2 implem ents some new fea-
tures, which are:
• X2 option
• Dual Data Pointer
• Extended RAM
• Programmable Counter Array (PCA)
• Hardware Wa tchdog
• SPI interface
• 4-level interrupt prio rity system
• power-off f lag
• ONCE mode
• ALE disabling
• Some enha nced features are also located in the U ART and the timer 2
X2 Feature The AT89C51RB2/RC2 core needs only 6 clock periods per machine cycle. This feature
called ‘X2’ provides the following advantages :
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consum ption by dividing dynam ical ly the operating frequency by 2 in
operating and idle modes.
• Increase CPU power by 2 while keeping same crystal f requency.
In order to keep the original C51 com patibility, a divider by 2 is inserted between the
XT AL1 signal and the m ain clo ck input of t he core (phase gene rator). This divi der may
be disabled by software.
Description The c lo ck for the whole ci rcuit and peri pherals is first divided by 2 bef ore being used by
the CPU core and the peripherals.
This allows any cyclic ratio to be acc epted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 5 shows the clock generation block diagram. X2 bit is validated on the rising edge
of the XTAL1÷2 to avoid g litches whe n swi tchin g from X 2 to X1 mod e. Figure 6 show s
the switching mode waveforms.
Fi gure 5 . Clock Generation Diagram
XTAL1 2
CKCON0
X2
8 bit Prescaler
FOSC
FXTAL 0
1
XTAL1:2 FCLK CPU
FCL K PE RIPH
CKRL
17
AT89C51RB2/RC2
4180E–8051–10/06
Figu re 6. Mode Switching Waveforms
The X2 bit in the CKCON0 register (see Table 15) allows a switch from 12 clock periods
per instruc tion to 6 clo ck periods and vice versa. A t res et, the s pe ed is set ac cording t o
X2 bit of Hardware Security B yte (HSB). By default, Standard mode is act ive. Setting the
X2 bit activates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, UARTX2, PCAX2, and WDX2 bits in the CKCON0 register
(Table 15) and SPIX2 bit in the CKCON1 register (see Table 16) allow a switch from
sta ndard peri phera l s peed ( 12 clo ck p eriod s per p eriph eral clock cyc le) to fa st pe riph-
eral speed (6 clock periods p er peripheral clock cycle). These bits are active only in X2
mode.
XTAL1:2
XTAL1
CPU Clock
X2 Bit
X2 Modex1 Mode X1 Mode
FOSC
18
AT89C51RB2/RC2
4180E–8051–10/06
Table 15. CKC ON0 Register
CKCON0 - Clock Contro l Register (8Fh)
Rese t Value = 0000 000’HSB. X2’b (see Table 65 “Hardware Security Byte”)
Not bit addressable
76543210
- WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
Bit
Number Bit
Mnemonic Description
7 Reserved
6WDX2
Watchdog Cloc k
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, this bi t
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock per iods per peri pheral clock cycle.
5PCAX2
Programmable Counter Array Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, this bi t
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
4SIX2
Enhanced UART Clock (Mode 0 and 2)
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, this bi t
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
3T2X2
Timer 2 Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, this bi t
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock per iods per peri pheral clock cycle.
2T1X2
Timer 1 Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, this bi t
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
1T0X2
Timer0 Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, this bi t
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
0X2
CPU Clock
Cleared to select 12 clock periods per machine cycle (STD, X1 mode) for CPU
and all the peripherals. Set to select 6 clock periods per machine cycle (X2
m ode) and to enable the individual peripher als’X2’ bits. Program m ed by
hardware after Power-up regarding Hardware Security Byte (HSB), Default
setting, X2 is cleared.
19
AT89C51RB2/RC2
4180E–8051–10/06
Table 16. CKC ON1 Register
CKCON1 - Clock Contro l Register (AFh)
Reset Value = XXXX XXX0b
Not bit addressable
76543210
-------SPIX2
Bit
Number Bit
Mnemonic Description
7-Reserved
6-Reserved
5-Reserved
4-Reserved
3-Reserved
2-Reserved
1-Reserved
0SPIX2
SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,
this bit has no effect).
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock per iods per peri pheral clock cycle.
20
AT89C51RB2/RC2
4180E–8051–10/06
Dual Data Pointer
Register (DPTR) The ad dit ional data po int er can b e u sed to spe ed up c ode execut ion and red uce cod e
size.
T he du al D PT R st ru c tur e is a way by w hic h the c hip will s p ec ify the addre ss of an ext er -
nal data memor y l ocation. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = A UXR1.0 (see Table 17) that allows t he program
code to swi tch between them (see Figure 7).
Figu re 7. Use of Dual P ointer
Exte rna l Data Memory
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
07
DPTR0
DPTR1
21
AT89C51RB2/RC2
4180E–8051–10/06
Table 17. AUXR1 regist er
AUXR 1- Auxiliary Register 1(0A2h)
Reset Value = XXXX XX0X0b
Not bit addressable
Note: 1. Bit 2 stuck at 0; this allo ws using INC AUXR1 to toggle DPS withou t changing GF3.
ASSEM BLY LAN GUA GE
; Block move usin g dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DP S exits op posite of entry st ate
; unless an extra I NC AUXR1 i s added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,# SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DES T ; addre ss of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a Byte from SOURCE
000B A3 INC DPTR ; incr ement SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the Byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ L OOP ; ch eck for 0 terminator
0012 05A2 INC AU XR 1 ; (op tional) restore DPS
76543210
- - ENBOOT - GF3 0 - DPS
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 ENBOOT Enab le Boot Fla sh
Cle ared t o disa ble boot ROM .
Set to map the boot ROM between F800h - 0FFFFh.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3GF3This bit is a general-purpose user flag.(1)
20Always Cleared
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0DPS
Data Pointer Sel ec tion
Cleared to select DPTR0.
Set to select DPTR1.
22
AT89C51RB2/RC2
4180E–8051–10/06
INC is a short (2 Bytes) and fast (12 clocks) way to manipulate the DPS bit in the
AUXR 1 SFR. However, note t hat the I NC i nstruction does not directly force the DP S bit
to a particular state, but simply toggles it. In simple routines, suc h as the block move
example, only the fact that DPS is toggled in the proper sequence matters, not its actual
value. In other words, the block move routine works the same w hether DPS is '0' or '1'
on entry. Observe that without the last instruction (INC AUX R1), the routine w ill exit with
DPS in the opposite state.
23
AT89C51RB2/RC2
4180E–8051–10/06
Expanded RAM
(XRAM) The AT89C51RB2/RC2 provides additional bytes of random access memory (RAM)
space for increased data parameter handling and high-level language usage.
AT 89C51RB2/ RC2 devices have expanded RAM in external data space; maximu m size
and location ar e des cribed in Table 18.
Table 18. Expa nded RA M
The A T89C51RB2/RC2 has internal data memory that is mapped into four separate
segments.
The fou r segments are:
1. The Lower 128 Bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
addressable.
2. The Upper 128 Bytes of RAM (addresses 80h to FFh) are indirectly addressable
only.
3. The S pecial Function Registers, SFRs, (addresses 80h to FFh) are directly
addressable only.
4. The expanded RAM Bytes are indirectly accessed by MOVX inst ructions, and
with the EX T R AM bit cleared in the AUX R register (see Table 18 ).
The lower 128 Bytes can be accessed by either direct or indirect addr essing. The Upper
128 Bytes can be accessed by indirect addressing only. The Upper 128 Bytes occupy
the sam e ad dres s sp ace as the S FR. Th at means they h ave th e sam e addres s, but are
physi cally separate from SFR space.
Figu re 8. Internal and External Data Memory Address
W hen an instruction ac cesses an i nternal location ab ove addre ss 7Fh, the CPU kn ows
whether the access is to the upper 128 Bytes of data RAM or to SFR space by the
address ing mode used in the instruction.
• Instructions that use direct address ing acc ess SFR space. For example:
MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2).
Part Number XRAM Size
Address
Start End
AT89C51RB2/RC2 1024 00h 3FFh
XRAM
Upper
128 Bytes
Internal
RAM
Lower
128 Bytes
Internal
RAM
Special
Function
Register
80h 80h
00
0FFh or 3FFh 0FFh
00
0FFh
External
Data
Memory
0000
00FFh up to 03FFh
0FFFFh
Indirect Accesses Direct Accesses
Direct or Indire ct
Accesses
7Fh
24
AT89C51RB2/RC2
4180E–8051–10/06
• Instructions that use indirect addressing access the Upper 128 Bytes of data RAM.
For example: MOV @R0, # data where R0 contains 0A0h, accesses the data Byte
at address 0A0h, rather than P2 (whose address is 0A0h).
• The XRAM Bytes can be accessed by indirect addressing, with EXTRAM bit cleared
and MOVX instructions. This part of memory that is physically located on-chip,
logically occupies the first Bytes of external data memory. The bit s X RS0 and XRS1
are used to hide a part of the available XRAM as explained in Table 18. This can be
useful if external peripherals are mapped at addresses already used by the internal
XRAM.
• With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX inst ruction in
combination with any of the registers R0, R1 of the selected bank or DPTR. An
acces s to XRAM will not af fect port s P0 , P2 , P3 .6 (WR) and P3.7 ( RD) . For
example, with EXTRA M = 0, MOVX @R 0, # data where R0 contains 0A0H,
accesses the XRAM at address 0A0H rather than external memory. An access to
external data memory locations higher than the accessible size of the XRAM will be
performed with the MOVX DPTR instructions in the same way as in the standard
80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and
read timing signals. Accesses to XRAM abov e 0FFH can only be done by the use of
DPTR.
• With EXTR AM = 1, MOVX @RI and MOVX @DPTR will be si milar to the standard
80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0
and any output port pins can be used to output higher order address bits. This is to
pro v ide the exte rn al pa g ing c apa b ility. MOV X @ D PTR w ill g ener ate a s ix teen- bit
address. Port2 outputs the high-order eight address bit s (the contents of DPH) while
Port0 multiplexes the low-order eight address bits (DPL) with dat a. MOV X @ RI and
MOVX @DPTR will generate either rea d or write signals on P3.6 (WR) and P3.7
(RD).
The stack pointer (SP) may be located anywhere in the 256 Bytes RAM (lower and
upper RAM) int ernal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch th e XRAM timings; if M 0 is set, the rea d and write pu lses
are extended from 6 to 30 clock periods. This is useful to access external slow
peripherals.
25
AT89C51RB2/RC2
4180E–8051–10/06
Registers Table 19. AU XR Regi ster
AUXR - Auxiliary Register (8Eh)
Rese t Value = XX0X 00’HSB. XRA M’0b (see Table 65)
Not bit addressable
76543210
DPU - M0 - XRS1 XRS0 EXTRAM AO
Bit
Number Bit
Mnemonic Description
7DPU
Disable Weak Pull-up
Cleared to activate the permanent weak pull up when latch data is logical 1
Set to disactive the weak pull-up (reduce power consumption)
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5M0
Pulse Le ngth
Cleared to stretch MOVX control: the RD and the WR pu lse length is 6 clock
periods (default).
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock
periods.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3XRS1XRAM Size
XRS1 XRS0 XRAM size
0 0 256 Bytes (default)
0 1 512 Bytes
1 0 768 Bytes
1 1 1024 Bytes
2XRS0
1 EXTRAM
EXTRAM Bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
Set to access external memory.
Programmed by hardware aft er Power-up regarding Hardware Security Byte
(HSB), defa ult sett ing, XRAM selecte d.
0AO
ALE Output Bit
Cl e ared , ALE is emi tte d at a con st ant r ate of 1/ 6 the osci ll a tor freq ue nc y (o r 1/ 3 if
X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC
instr u c tio n is use d.
26
AT89C51RB2/RC2
4180E–8051–10/06
Timer 2 The Timer 2 in the AT89C51RB2/RC2 is the standard C52 Timer 2.
It is a 16-bit timer/counter: t he c ou nt is maintaine d by tw o e ight-bit timer registe rs, TH 2
and TL2 are cascaded. It is controlled by T2CON (Table 20) and T2M OD (Table 21)
registers. Timer 2 operation is similar to Timer 0 and Timer 1C/T2 sel e cts FOSC/12 (timer
operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2
allows TL2 to increment by the selected input.
Timer 2 has 3 ope rating modes : capture, autoreload and Ba ud Rate Generator. These
modes are se lected by the combination of RCLK, TCLK and CP/RL2 (T2CON).
se e the Atm el 8-bit M icrocont roller Hardw are d escription f or the des criptio n of Cap ture
and Baud Rate Generator Modes.
Timer 2 includes the follo wing enhancements:
• Auto-reload mode with up or down count er
• Programmable clock-output
Auto-reload Mode The aut o-relo ad mode c onfigu res Timer 2 a s a 16 -bit time r or event counter with a uto-
ma tic reload . If DCEN b it in T2MO D is clea red, Timer 2 behav es as in 8 0C52 (see the
Atme l C51 Microcontroller Hardware description). If DCEN bit is set, Timer 2 acts a s an
Up/down timer/counter as shown in Figure 9. In this m ode the T2EX pin controls the
direction of count .
W hen T 2EX is hi gh, Timer 2 c ounts up. T im er overf low occurs at F FF Fh which set s t he
TF2 flag and gen erates an interrupt request. The overf low also causes t he 16-bit value
in RCAP2H and RCAP 2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the
timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.
The underf low sets TF2 flag and reloads FFFFh into the timer registers.
The EX F2 bit toggles when Timer 2 overflows or underflows according to the direction of
the count . EXF2 doe s not generate any interrupt. This bit can be used to provide 17-bit
resolution.
27
AT89C51RB2/RC2
4180E–8051–10/06
Fi gure 9 . Auto-Reload Mode Up/Down Counter (DCEN = 1)
Programmable Clock-out
Mode In the clock-out mode, Timer 2 operates as a 50% duty-cycle, programmable clock gen-
er ator (see Figure 10 ). The input clock i ncremen ts TL2 at frequen cy FCLK PERIPH/2. The
timer repeatedly counts to over flow f rom a loaded value. At overflow, the contents of
RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2
overflows do not generate interrupts. The formula gives the clock-out frequency as a
function of the system oscillator frequency and the value in the RCAP2H and RCAP2L
registers:
For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz
(FCLK PERIPH/216) to 4 M H z (F CLK PERIPH/4). The generated clock signal is brought out to
T2 pin (P1.0).
Timer 2 is programmed for the clock-out mode as follows:
• Set T2OE bit in T2MOD register.
• Clear C/T2 bit in T2CON register.
• Determine the 16- bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the
reload value or a different one depend ing on the application.
• To start the timer, set TR2 run control bit in T2CON register .
It is possible to use Timer 2 as a baud rate generator and a clock generator simulta-
neously. For this configuration, the baud rates and clock frequencies are not
independent since both functions use the values in the RCAP2H and RCAP2L registers.
(DOWN COUNTING RE LOAD VALUE)
C/T2
TF2
TR2
T2
EXF2
TH2
(8-bit)
TL2
(8-bit)
RCAP2H
(8-bit)
RCAP2L
(
8-bit)
FFh
(8-bit) FFh
(8-bit)
TOGGLE
(UP COUNTING RELOAD VALUE)
TIMER 2
INTERRUP
T
FCLK PERIPH
0
1
T2CON T2CON
T2CON
T2CON
T2EX:
if DCEN = 1, 1 = UP
if DCEN = 1, 0 = DOWN
if DCEN = 0, up countin
g
:6
Clock O
–
utFrequency
F
CLKPERIPH
4 65536 RCAP2HRCAP2L⁄)
–
(×
---------------------------------------------------------------------------------------------
=
28
AT89C51RB2/RC2
4180E–8051–10/06
Fi gure 1 0 . Clock-Out Mode C/T2 = 0
:6
EXF2
TR2
OVER-
FLOW
T2EX
TH2
(8-bit)
TL2
(8-bit)
TIMER 2
RCAP2H
(8-bit)
RCAP2L
(8-bit)
T2OE
T2
FC LK PERIP H
T2CON
T2CON
T2CON
T2MOD
INTERRUPT
QD
Toggle
EXEN2
29
AT89C51RB2/RC2
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Registers Table 20. T 2CON Register
T2CON – Timer 2 Control Register (C8h)
Rese t Value = 0000 0000b
Bit addressable
76543210
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
Bit
Number Bit
Mnemonic Description
7 TF2 Timer 2 Overflow Flag
Must be cleared by software.
Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.
6EXF2
Timer 2 External Flag
Set when a capture or a reload is cau s ed by a negative transition on T2EX pin if
EXEN 2 = 1 .
When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2
interrupt is enabled.
Must be clear ed by software. EXF2 doesn’t caus e an i nterrupt in Up/down
counter mode (DCEN = 1).
5 RCLK Receive Clock Bit
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
4TCLK
Transmit Clock Bit
Cleared to use timer 1 overflow as transmit clock for serial port in m ode 1 or 3 .
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3 EXEN2
Timer 2 External Enable Bit
Cleared to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if Timer 2 is not used to clock the serial port.
2TR2
Timer 2 Run Control Bit
Cleared to turn off Timer 2.
Set to turn on Timer 2.
1C/T2#
Timer/Coun t er 2 Select B it
Cleared for timer o perat ion (input from internal clock system: F CL K PERIPH).
Set fo r coun t er op erat i on (inp ut fro m T2 inp ut pi n, fall i ng edg e tri gg er) . Mus t be 0
for clock out mode.
0CP/RL2#
Timer 2 Capture/Reload Bit
If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload
on Timer 2 overflow.
Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin
if EXEN2 = 1.
Set to cap ture o n negative transitions on T2EX pin if E XEN2 = 1.
30
AT89C51RB2/RC2
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Table 21. T2MOD Regi ster
T2MOD – Timer 2 Mode Control Register (C9h)
Reset Value = XXXX XX00b
Not bit addressable
76543210
------T2OEDCEN
Bit
Number Bit
Mnemonic Description
7-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. D o no t set this bit.
6-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. D o no t set this bit.
5-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. D o no t set this bit.
4-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. D o no t set this bit.
3-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. D o no t set this bit.
2-
Reserved
T he valu e rea d fro m thi s bi t is indet erm in at e. D o no t set this bit.
1T2OE
Timer 2 Output Enable Bitt
Cleared to program P1.0/T2 as clock input or I/O port.
Set to program P 1.0/T2 a s clock output.
0 DCEN Down Counter Enable Bit
Cleared to disa ble Timer 2 as up/down counter.
Set to enable Timer 2 as up/down counter.
31
AT89C51RB2/RC2
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Programmable
Counter Array (PCA) The PCA provides more timing capabilit ies with less CPU int ervention than the st andard
timer/c ounters. I ts adva ntages in clude reduced software ove rhead and im proved ac cu-
racy. The PCA con si sts of a dedic ated timer/cou nter which serves as t he time base for
an array of five com pare/ca pture Modu les. Its clock i nput can b e program med to co unt
any one of the following signals:
• Peripheral clock frequency (FCLK PERIPH) ÷ 6
• Peripheral clock frequency (FCLK PERIPH) ÷ 2
• Timer 0 overflow
• External input on ECI (P1.2)
Each compare/capture Modules can be programmed in any one of the following modes:
• Rising and/or falling edge capture
• Software timer
• High-speed output
• Pulse width modu la t or
Mo dule 4 ca n als o be pro grammed as a w atchd og time r (see Se ction "PCA Wa tchdo g
Timer" , page 42).
When the compare/captur e Modules are programmed in the capture mode, software
timer, or high speed out put m ode, an interrupt can be gene rated when the M odule exe-
cutes its function. All five Modules plus the PCA time r overflow share one interrupt
vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O.
These pins a re listed belo w. If one or se veral bits in the po rt are not us ed for the PCA ,
they ca n still be us ed for standard I/O.
Th e PC A ti mer is a c om mon t im e bas e fo r all f ive M odu les ( see Fig ure 11). T he t im er
count source is determined from the CPS1 and CPS0 bits in the CMOD register
(Table 22) and can be programmed to run at:
• 1/6 the peripheral c l oc k f requenc y (F CLK PE RIPH)
• 1/2 the peripheral c l oc k f requenc y (F CLK PE RIPH)
• The Timer 0 overflow
• The input on the ECI pin (P1.2)
PCA Component External I/O Pin
16-bit Counter P1.2/ECI
16-bit Module 0 P1.3/CEX0
16-bit Module 1 P1.4/CEX1
16-bit Module 2 P1.5/CEX2
16-bit Module 3 P1.6/CEX3
32
AT89C51RB2/RC2
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Figu re 11 . PCA Timer/Count er
CIDL CPS1 CPS0 ECF
It
CH CL
16- bi t up Coun ter
To PCA
Modules
FCLK PERIPH/6
FCLK PERIPH/2
T0 OVF
P1.2
Idle
CMOD
0xD9
WDTE
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
overflow
33
AT89C51RB2/RC2
4180E–8051–10/06
Registers Table 22. CM OD Regist er
CMOD – PCA Counter Mode R egister (D9h)
Rese t Value = 00XX X000b
Not bit addressable
The CMO D register includes three additional bits associated with the PCA.
• The CIDL bit whic h allows the PCA to stop during idle mode.
• The WDTE bit which enables or disables the watchdog function on Mo dule 4.
• The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in
the CCON SFR) to be set when the PCA timer overflows.
The CCON register contains the run control bit for the PCA and the flags for the PCA
timer (CF) and each Module (see Table 23).
• Bit CR (CCON. 6) must be s et by software to run the PCA . The PCA is shut off by
clearing this bit.
• Bit CF: Th e CF bit (CCON. 7) is set when the PCA counter overflows and an
interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can
only be cleared by software.
• Bits 0 through 4 are the flags for the Modules (bit 0 for Module 0, bit 1 for Module 1,
etc. ) and are set by hardware when either a match or a capture occurs. These flags
also can only be cleared by sof t ware.
76543210
CIDL WDTE - - - CPS1 CPS0 ECF
Bit
Number Bit
Mnemonic Description
7CIDL
Coun ter Idle Co ntrol
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
6WDTE
Wat c hd og Timer Enable
Cleared to di sable Watchdog Time r func tion on PCA Modul e 4.
Set to enable Watchdog Timer function on PCA Module 4.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 CPS1 PCA Coun t Pulse Select
CPS1 CPS0 Selecte d PCA input
0 0 Internal cloc k FCL K PERIPH/6
0 1 Internal clock FLK PERIPH/2
1 0 Timer 0 Overflow
1 1 External clock at ECI/P1.2 pin (ma x rate = fC LK PERIPH/ 4)
1 CPS0
0ECF
PCA Enab le Coun ter O ve rflow Inte rrupt
Cleared to disable CF bit in CCON to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
34
AT89C51RB2/RC2
4180E–8051–10/06
Table 23. CCON Register
CCON – PCA Counter Control Register ( D8h)
Rese t Value = 000X 0000b
Bit addressable
The watchd og timer function is implemented in Mod ule 4 (see Figure 14).
The PCA interrup t system is sho wn in Figu re 12.
76543210
CF CR - CCF4 CCF3 CCF2 CCF1 CCF0
Bit
Number Bit
Mnemonic Description
7CF
PCA Counter Overflow Flag
Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in
CMOD is set. CF may be set by either hardware or software but can only be
c leared by software.
6CR
PCA Counter Run Control Bit
Must be cleared by software to turn the PCA counter off.
Set by software to turn the PCA counter on.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 CCF4 PCA Module 4 Interrupt Flag
Must be cleared by software.
Set by ha rdware when a match or capture occurs.
3 CCF3 PCA Module 3 Interrupt Flag
Must be cleared by software.
Set by ha rdware when a match or capture occurs.
2 CCF2 PCA Module 2 Interrupt Flag
Must be cleared by software.
Set by ha rdware when a match or capture occurs.
1 CCF1 PCA Module 1 Interrupt Flag
Must be cleared by software.
Set by ha rdware when a match or capture occurs.
0 CCF0 PCA Module 0 Interrupt Flag
Must be cleared by software.
Set by ha rdware when a match or capture occurs.
35
AT89C51RB2/RC2
4180E–8051–10/06
Figu re 12. PCA Inte r r u p t Sy s tem
PCA Modules: ea ch o ne of t he f ive comp are /cap ture M odul es has s ix po ssi ble fu nc-
tions. It can perform:
• 16-bit Capture, positive-edge triggered
• 16-bit Capt ure, negative-edge triggered
• 16-bit Capture, both positive and negative-edge triggered
• 16-bit Software Timer
• 16-bit High-speed Output
• 8-bit Pulse Width Modulator
In addition, Mod ule 4 can be used as a Watchdog Timer.
Each Mo dule in the PCA has a spec ial function register associa ted with it. These regis-
ters are: CCAPM0 for Module 0, CCAPM1 for Module 1 , e tc. (see Table 24). The
registers contain the bits that control the mode that each Module will operate in.
• The ECCF bit (CCAPM n. 0 where n = 0, 1, 2, 3, or 4 depending on the Module)
enables the CCF f lag in the CCON SFR to generate an interrupt when a matc h or
compare occurs in the associated Module.
• PWM (CCAPMn. 1) enables the pulse width m odul ation mod e.
• The TOG bit (CCAPMn. 2) when set causes the CEX output associated with the
Module to toggle when there is a match between the PCA counter and the Module' s
capture/compare register.
• The match bit M AT (CCAPMn. 3) when set will ca use the CCFn bit in the CCON
register to be set when there is a match between the PCA counter and the Module's
capture/compare register.
• The next two bits CAPN (CCAPMn. 4) and CAPP (CCAPMn. 5) determine the edge
that a capture input will be active on. The CAPN bit enables the negative edge, and
the CAPP bit enables the positive edge. If both bits are set both edges will be
enabled and a capture will oc c ur for eit her transit ion.
• The last bit in th e register ECOM (CCAPMn. 6) when set enables the comparator
function.
Table 24 shows the CCAPMn settings for t he various PCA fu nctions.
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
Module 4
Module 3
Module 2
Module 1
Module 0
ECF
PCA Time r/Co un ter
ECCFn CCAPMn. 0CMOD. 0 IEN0. 6 IEN0. 7
To Interrupt
Priority Decoder
EC EA
36
AT89C51RB2/RC2
4180E–8051–10/06
Table 24. CCA PMn Registers (n = 0-4)
CCAPM0 – PCA Module 0 Compare/Capture Control Register (0DAh)
CCAPM1 – PCA Module 1 Compare/Capture Control Register (0DBh)
CCAPM2 – PCA Module 2 Compare/Capture Control Register (0DCh)
CCAPM3 – PCA Module 3 Compare/Capture Control Register (0DDh)
CCAPM4 – PCA Module 4 Compare/Capture Control Register (0DEh)
Rese t Value = X000 0000b
Not bit addressable
76543210
- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6ECOMn
Enable Comparator
Cleared to disable the comparator function.
Set to enable the comparator function.
5 CAPPn Capture Pos itiv e
Cleared to disable positive edge capture.
Set to enable positive edge capture.
4 CAPNn Capt ure Neg ative
Cleared to disable negative edge capture.
Set to enable negative edge c apture.
3MATn
Match
When MATn = 1, a match of the PCA counter with this Module's
c ompare/capture register causes th e CCFn bit in CCON to be set, f lagging an
interrupt.
2 TOGn Toggle
When TOGn = 1, a match of the PCA counter with this Module's
compare/capture register causes theCEXn pin to toggle.
1PWMn
Pulse Wid th Modulation Mode
Cleared to disable the CEXn pin to be used as a pulse w idth modul ated output.
Set to enable the CEXn pin to be used as a pulse width modulated output.
0 CCF0
Enable CCF Interrupt
Cl ea red to di sa ble co mp ar e/ cap t ure f lag C CFn in the CCON regi st er t o ge nera t e
an interrupt.
Set to enable compare/capture flag CCFn in the CCON register to generate an
interrupt.
37
AT89C51RB2/RC2
4180E–8051–10/06
Table 25. PCA M odule M odes (CC APM n Registers)
The re are two a dditiona l regist ers associ ated with each of the PC A Mo dules. The y are
CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a
ca pture oc curs or a com pare s hould occur. W hen a M odul e is used in the PWM m ode
these re gisters are used to control the duty cycle of the output (see Table 26 and
Table 27).
Table 26. CCAPn H Registers (n = 0-4)
CCAP0H – PCA Mo dule 0 Compare/Captu re Control Register High (0FAh)
CCAP1H – PCA Mo dule 1 Compare/Captu re Control Register High (0FBh)
CCAP2H – PCA Mo dule 2 Compare/Captu re Control Register High (0FCh)
CCAP3H – PCA Mo dule 3 Compare/Captu re Control Register High (0FDh)
CCAP4H – PCA Mo dule 4 Compare/Captu re Control Register High (0FEh)
Rese t Value = 0000 0000b
Not bit addressable
ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn Module Function
0000000 No Operation
X10000X
16-bit c aptur e by a positive-edge
trigger on CEXn
X01000X
16-bit capture by a negativ e t rigger
on CEXn
X11000X
16-bit capture by a transition on
CEXn
100100X
16-bit Sof tware Timer/Compare
mode.
100110X 16-bit High-speed Output
1000010 8-bit PWM
1001X0X Watchdog Timer (Module 4 only)
76543210
--------
Bit
Number Bit
Mnemonic Description
7 - 0 - PCA Module n Compare/Capture Cont rol
CCAPnH Value
38
AT89C51RB2/RC2
4180E–8051–10/06
Table 27. CCAP nL Registers (n = 0-4)
CCAP0L – PCA M odule 0 Compare/ Captu re Control Register Low (0EAh)
CCAP1L – PCA M odule 1 Compare/ Captu re Control Register Low (0EBh)
CCAP2L – PCA M odule 2 Compare/ Captu re Control Register Low (0ECh )
CCAP3L – PCA M odule 3 Compare/ Captu re Control Register Low (0EDh )
CCAP4L – PCA M odule 4 Compare/ Captu re Control Register Low (0EEh)
Rese t Value = 0000 0000b
Not bit addressable
Table 28. CH Regist er
CH – PCA Counter Register High (0F9h)
Rese t Value = 0000 0000b
Not bit addressable
Table 29. CL Regist er
CL – PCA Counter Register Low (0E9h)
Rese t Value = 0000 0000b
Not bit addressable
76543210
--------
Bit
Number Bit
Mnemonic Description
7 - 0 - PCA Module n Compare/Capture Cont rol
CCAPnL Value
76543210
--------
Bit
Number Bit
Mnemonic Description
7 - 0 - PCA Counter
CH Value
76543210
--------
Bit
Number Bit
Mnemonic Description
7 - 0 - PCA Counter
CL Value
39
AT89C51RB2/RC2
4180E–8051–10/06
PCA Capture Mode To use on e of the P CA M odules in the ca ptur e mode eith er one or both of the CCA PM
bits CAP N and CAPP for th at Modu le m ust b e set. T he exte rnal CEX inpu t for the M od-
ule (on port 1) is sampled for a transition. When a valid transiti on occurs the PCA
hard wa re lo ads the val ue of t he PC A cou nte r regi sters ( CH and CL) i nto th e Mo dule 's
cap ture regist ers (CCAPnL and CCAPnH). If the CC Fn bit for the Module in the CCO N
SF R and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated
(see Figure 1 3).
Figu re 13. PCA Capture Mode
CF CR CCON
0xD8
CH CL
CCAPnH CCAPnL
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
PCA Counter/Timer
ECOMn C CAP Mn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
Cex. n
Capture
40
AT89C51RB2/RC2
4180E–8051–10/06
16-bit Software Timer/
Compare Mode The P CA Modules can be used a s software timers by setting both the ECOM and MAT
bits in the Modules CCA PMn register. The PCA timer will be compared t o the Module's
ca pture registers and wh en a ma tch occurs, an interrup t will occur if the C CFn (CCO N
SF R) and the ECCFn (CCAPMn SFR) bits for t he Modu le are both set (see Figure 14 ).
Figu re 14. PCA Compare Mode and PCA Wat chdog Timer
Note: 1. Only for Module 4
Before enabling ECOM b it, CCAPnL and CCAPnH should be set with a no n zero v alue,
otherwise an unwanted match could occur. Writing to CCAPnH will set the ECOM bit.
Onc e ECOM set, wr iting CCAPnL will clear E COM so tha t an un wanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn r egister.
CH CL
CCAPnH CCAPnL
ECOMn CCAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
16 bit Comparat or Match
CCON
0xD8
PCA IT
Enable
PCA Counter/Timer
RESET(1)
CIDL CPS1 CPS0 ECF CMOD
0xD9
WDTE
Reset
Write to
CCAPnL
Write to
CCAPnH
CF CCF2 CCF1 CCF0
CR CCF3
CCF4
10
41
AT89C51RB2/RC2
4180E–8051–10/06
High-speed Output Mode I n this mode the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the modules capture registers.
To activate this mode the TOG, MAT, and ECOM bits in the modules CCAPMn SFR
must be set (see Figure 15).
A prior write must be done to CCA PnL and CCA PnH before writing the ECOMn bit.
Figu re 15. PCA High-speed Output Mode
Before enabl ing ECOM bit, CCAPnL and CCAPnH sho uld be set with a non-zero v alue,
otherwise an unwanted match could occur.
Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn r egister.
CH CL
CCAPnH CCAPnL
ECOMn C CAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
16-bit Comparator Match
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
Enable
CEXn
PCA Counter/Timer
Write to
CCAPnH
Reset
Write to
CCAPnL
10
42
AT89C51RB2/RC2
4180E–8051–10/06
Pulse Width Modulator
Mode All of the PCA Mod ules c an be used as PW M ou tputs. Fi gure 1 6 shows the P WM f unc-
tion. The frequency of the output depends on the source for the PCA timer. All of the
Mod ules will have t he same freque ncy of ou tput because t hey all share the P CA timer.
The duty cycle of each Module is independently variable using the module's capture
register CCAPLn. When the value of the PCA CL SFR is less than the value in the mod-
ule's CCA PLn SFR the output will be low, when it is equal to or greater than the out put
w ill be hig h. Wh en CL ov erfl ows f rom FF to 00 , CC APL n is r el oade d wi th th e val ue i n
CC APHn. This allows updat ing the PWM without g litches. The PWM and ECOM bit s i n
the module's CCA PMn regist er must be set to enable the PWM mo de.
Fi gure 1 6 . PCA PWM Mode
PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the
system without increasing chip count. Watchdog tim ers are useful for systems that a re
susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only
PCA Mod ule that can be program m ed as a watchdog. Howev er, this Module can still be
used for other modes if th e watchd og is not needed. Figure 14 shows a d iagram of how
the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just
like the other compa re modes, this 16-bit value is comp ared to the PCA timer value . If a
match is allowed to occur, an internal reset will be generated. This will not cause the
RST pin to be driven high.
In order to hold off the reset, the user has the following three options:
1. Periodically change the compare value so it will never match the PCA timer.
2. Periodically change the PCA timer value so it will never match the compare
values.
3. Disable the watchdog by clearing the WDTE bit before a match occurs and then
re-enable it.
The f irst two options are mo re reliable bec ause th e watchdo g timer is never disabled as
in option #3. If the program c ounter ev er g oes ast ray, a ma tch wi ll eve ntually occur and
cause a n internal reset . The second option is also not recomm ended if other PCA M od-
ules are being used. Remember, the PCA timer is the tim e base for all modules;
CL
CCAPnH
CCAPnL
ECOMn CCAPMn, n = 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
8-b it C om p arator CEXn
“0”
“1”
Enable
PCA Counter/Timer
Overflow
43
AT89C51RB2/RC2
4180E–8051–10/06
changing the time base for other Modules would not be a good idea. Thus, in most appli-
cations the first solution is the best option.
This watchdog timer won’t generate a reset out on the reset pin.
44
AT89C51RB2/RC2
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Serial I/O Port The serial I/O port in the AT89C51RB 2/RC2 is compatible wi th the serial I /O port in the
80C52.
It provides both synchronous and asynchronous communication modes. It operates as a
Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes
(Modes 1, 2 and 3). Asynchronous trans mission and reception can occur simultaneously
and at different baud rates
Serial I/O port includes the following enhancements:
• Framing error detection
• Automatic address recognition
Framing Error Detection F rami ng bi t error de tectio n is pro vided f or t he three asyn chro nous m odes (m odes 1 , 2
and 3). T o enable the framing bit error de tection feat ure, set SMOD0 bit in PCON regis-
ter (See Figure 17).
Fi gure 1 7 . Framing Error Block Diagram
W hen this feature is enabl ed, the receiver chec ks each incom ing data frame for a valid
stop bit. An invalid stop bit may result f rom noise on the serial l ines or f rom simultaneous
tran smissio n by two C PUs . If a valid st op bit is n ot found, t he Fram ing Error bit (FE) i n
SCON register ( See Table 33.) bit is set.
Softwa re may exa mine FE b it after each reception to ch eck for data erro rs. Once set,
only s oftware or a reset can clear FE bi t. Subsequ ently received fram es with valid stop
bits cannot clear FE bit. When FE f eature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 18. and Figu re 19.).
Fi gure 1 8 . UART Timings in Mode 1
RITIRB8TB8RENSM2SM1SM0/FE
IDLPDGF0GF1POF-SMOD0SMOD1
To UART framing error control
SM0 to UART mode control (SMOD0 = 0)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SCON (98h)
PCON (87h)
Da ta byte
RI
SMOD0=X
Stop
bit
Start
bit
RXD D7D6D5D4D3D2D1D0
FE
SMOD0=1
45
AT89C51RB2/RC2
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Fi gure 1 9 . UART Timings in Modes 2 and 3
Automatic Address
Recognition T he automatic address recognition feature is e nabled when t he multiprocessor com m u-
nication feature is enabled (SM2 bit in SCON register is set).
Impl ement ed in hard ware, auto matic add ress recog nition enh ances t he mult iprocessor
communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address, the
receiver sets RI bit i n SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command f rames address ed to other devices.
If desired , the user may ena ble the a utomatic addres s recog nition feature in m ode 1.In
this configuration, the stop bit takes the place of the ninth data bit. B it RI i s set only when
the re ceived comma nd frame ad dress m atches t he device’ s address an d is termina ted
by a valid stop bit.
To support aut om atic addres s rec ognition, a device is identified b y a given address and
a broadca st address.
Note: The multiprocessor communication and automatic address recognition features cannot
be enabled i n mod e 0 (i. e. set ting SM2 bit in SCON register in mode 0 has no effect).
Given Address Each de vice has an individual address that is specified in SADDR register; the SADEN
regi ster is a mask byte that contains don’t-care bits (d efined by zeros) to form the
dev ice’s given address. The don’t-care bits provide the flexibility to address one or more
sla ve s at a time. The follow ing ex am ple illu str at es how a given address is form ed.
To address a device by its individual address, the SADEN mask byte must be 1111
1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to addre ss different slaves:
Sl av e A: SADD R1111 00 01b
SADEN1111 1010b
Given1 11 1 0X0Xb
Slave B:SA DD R1111 00 11b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0010b
SADEN1111 1101b
Given1111 00X1b
RI
SMOD0=0
Data byte Ninth
bit Stop
bit
Start
bit
RXD D8D7D6D5D4D3D2D1D0
RI
SMOD0=1
FE
SMOD0=1
46
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The SADEN by te is selected so that each slave may be addressed separately.
For slave A, bi t 0 (t he LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1.To commu-
nicate with slave A only, the master m ust send an address where bit 0 is clear (e. g.
1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bi t 1 is a don’t care bit. To communicate with
slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both
set (e. g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set,
bit 1 clear, and bit 2 cle ar (e. g. 1111 0001b).
Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t-care bits, e. g. :
SADDR0101 0110b
SADEN1111 1100b
Broadcast =SADDR OR SADEN1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however
in m ost applicat ions, a broa dcast addre ss is FFh. The f ollowing is an e xample of us ing
broadc ast addresses :
Sl av e A: SADD R1111 00 01b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SA DD R1111 00 11b
SADEN1111 1001b
Broadcast1111 1X11B,
Sl av e C: SAD D R =1111 0011 b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’ t care bit; f or slave C, bit 2 is set. To communicate with
all o f the s laves, the m as ter must send an ad dress FF h. To c om mu nicat e with slav es A
and B, but not slave C, the mas ter can send and address FBh.
Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i. e. the giv en and
broadc ast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial
port will reply to any addres s, and so, that it is backwards compatible with the 80C51
microcont rollers that do not support automatic address recog nition.
47
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Registers Table 30. SA DEN Register
SADE N - Slave Address Mask Register (B9h)
Rese t Value = 0000 0000b
Not bit addressable
Table 31. SADDR Regi ster
SADDR - Slave Address Register (A9 h)
Rese t Value = 0000 0000b
Not bit addressable
Baud Rate Selection for
UART for Mode 1 and 3 The Baud Rate Generator for transmit and receiv e clocks can be selec ted separately via
the T2CON and BDRC ON registers.
Fi gure 2 0 . Baud Rate Selec tion
76543210
76543210
RCLK
/ 16
RBCK
INT_BRG
0
1
TIMER1
0
1
0
1
TIMER2
INT_BRG
TIMER1
TIMER2
TIMER_BRG_RX
Rx Clock
/ 1 6
0
1
TIMER_BRG_TX
Tx Clock
TBCK
TCLK
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Table 32. Ba ud Rate Selection Table UART
Internal Baud Rate Gene rator
(BRG) When t he i nternal Baud Rate Generator is used, the Ba ud Rat es are determined by t he
BRG overflow depen ding on t he BRL re load value , the value of S PD bit (Speed Mode)
in BDRCON register and the value of the SMOD1 bit in PCON register.
Figu re 21. Internal Baud Rate
• The baud rate for UART is t oken by formula:
TCLK
(T2CON) RCLK
(T2CON) TBCK
(BDRCON) RBCK
(BDRCON) Clock Source
UART Tx Clock Source
UART Rx
0000Timer 1Timer 1
1000Timer 2Timer 1
0100Timer 1Timer 2
1100Timer 2Timer 2
X010INT_BRGTimer 1
X110INT_BRGTimer 2
0 X 0 1 Tim er 1 INT_BRG
1 X 0 1 Tim er 2 INT_BRG
X X 1 1 INT_BRG INT_BRG
0
1
Overflow
SPD
BDRCON.1
BRG
(8 bits)
BRL
(8 bits)
FClk Perip h ÷ 6
BRR
BDRCON.4
0
1
SMOD1
PCON.7
÷ 2 INT_BRG
Baud_Rate = 6(1-SPD) ⋅ 32 ⋅ (256 -BRL)
2SMOD1 ⋅ FPER
BRL = 256 - 6(1-SPD) ⋅ 32 ⋅ Baud_Rate
2SMOD1 ⋅ FPER
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Table 33. SCO N Regist er
SCON - Ser ial Control Register (98h)
Rese t Value = 0000 0000b
Bit addressable
76543210
FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
Bit
Number Bit
Mnemonic Description
7
FE
Framing Error bit (SMOD0=1)
Clear to re set the error state, not cleared by a valid stop bi t.
Set by ha rdware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit.
SM0 Seri al port Mo de bit 0
Refer to SM1 for serial po rt mode selection.
SMOD0 must be cleared to enable access to the SM0 bit.
6SM1
Seri al port Mode bit 1
SM0 SM1 Mode Baud Rate
0 0 Shift Register FXTAL/12 (or FXTAL /6 in mode X2)
0 1 8-bit UART Variable
1 0 9-bit UARTF
XTAL/64 or FXTAL/32
1 1 9-bit UART Variable
5SM2
Seri al port Mo de 2 bit / M ul tiprocess or Co mm un ica tio n Enab le bit
Clear to disable multiprocessor communication feat ure.
Se t to en ab le multi pr o ces sor commu ni cati o n feat ur e in mo de 2 and 3, an d
ev entually mo de 1.Th is bit should be cle ared in mode 0.
4REN
Reception En a ble bit
Clear to disable serial reception.
Set to enable serial reception.
3TB8
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit .
2RB8
Recei ver Bit 8 / Ninth b it received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by ha rdware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not
used.
1TI
Tra nsm it Inte r rup t flag
Clear to acknowledge interrupt.
Se t by har d war e at t he en d of t h e 8 th bi t time i n mo de 0 or at the be gi n ning
of the stop bit in the other modes.
0RI
Recei ve Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit ti me i n mode 0, see Figure 18.
and Figure 19. in the other modes.
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Table 34. Example of Computed Value When X2=1, SMOD1=1, SPD=1
Table 35. Example of Computed Value When X2=0, SMOD1=0, SPD=0
The b aud rate g enerator can be u sed for m ode 1 or 3 (ref er to Figure 20 .), but also for
mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 42.)
UART Registers Table 36. SADEN Register
SADE N - Slave Address Mask Register for UA RT (B9h)
Rese t Value = 0000 0000b
Table 37. SADDR Regi ster
SADDR - Slave Address Register fo r UART (A9h)
Rese t Value = 0000 0000b
Baud Rates FOSC = 16. 384 MHz FOSC = 24MHz
BRL Error (%) BRL Error (%)
115200 247 1.23 243 0.16
57600 238 1.23 230 0.16
38400 229 1.23 217 0.16
28800 220 1.23 204 0.16
19200 203 0.63 178 0.16
9600 149 0.31 100 0.16
4800 43 1.23 - -
Baud Rates FOSC = 16. 384 MHz FOSC = 24MHz
BRL Error (%) BRL Error (%)
4800 247 1.23 243 0.16
2400 238 1.23 230 0.16
1200 220 1.23 202 3.55
600 185 0.16 152 0.16
76543210
76543210
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Table 38. SBUF Register
SBUF - Serial B uff er Register for UART (99h)
Reset Value = XXXX XXXXb
Table 39. BRL Re gister
BRL - Baud Rate Reload Register for the i nte rnal baud rate generator, UART (9Ah)
Rese t Value = 0000 0000b
76543210
76543210
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Table 40. T2CON Regist er
T2CON - Timer 2 Control Register (C8h)
Rese t Value = 0000 0000b
Bit addressable
76543210
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
Bit
Number Bit
Mnemonic Description
7TF2
Timer 2 ove rf low Fla g
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
6EXF2
Timer 2 External Flag
Set when a cap tu re or a rel oa d is cau sed by a ne ga tive tra nsi t io n on T2E X pi n if
EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter mode (DCEN = 1)
5RCLK
Receive Clock bit for UART
Cleared to use timer 1 overflow a s receive clo c k for serial p ort in mode 1 or 3 .
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
4TCLK
Transmit Clock bit for UART
Cleared to use timer 1 overflow a s tran smit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3EXEN2
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if timer 2 is not used to clock the serial port.
2TR2
Timer 2 Run control bit
Cleared to turn off timer 2.
Set to turn on timer 2.
1C/T2#
Timer/Counter 2 select bit
Cle are d fo r ti mer op er ati on (inp ut fro m in ter na l cloc k sy ste m: FC L K PERIPH).
Set for count er op erat ion (input from T2 input pin, falli ng edge trigger). Mu st be
0 for clock out mode.
0CP/RL2#
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on
t im er 2 ov er fl ow.
Cle are d to auto- re lo ad on time r 2 overf lo ws or negat i ve tran si tion s on T2EX pin
if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
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Table 41. PCO N Regist er
PCO N - Power Control Register (87h)
Rese t Value = 00X1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset
doesn’t affect the value of this bit.
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number Bit
Mnemonic Description
7SMOD1
Serial port Mode bit 1 for UART
Set to select double baud rate in mode 1, 2 or 3.
6SMOD0
Serial port Mode bit 0 for UART
Cleared to select SM0 bit in SCON register .
Set to se le ct FE bit in SCON r e gist er.
5-
Reserved
The va lu e read fr om this bi t is in de ter mi nate . Do no t se t thi s bi t.
4POF
Power-Off Flag
Cleared to recognize next reset type.
Set by h ardwar e when VCC rises f rom 0 to its no minal volt age. Can also be set
by software.
3GF1
Ge ne ral purpose Flag
Cle are d b y u ser fo r gen era l p ur pos e u sag e.
Set by us er f or g ener al p urpo se us ag e.
2GF0
Ge ne ral purpose Flag
Cle are d b y u ser fo r gen era l p ur pos e u sag e.
Set by us er f or g ener al p urpo se us ag e.
1PD
Power-Down mode bit
Cle are d b y hard war e whe n rese t oc curs .
Set to enter power-down mode.
0IDL
Idle mode bit
Cleared by hardware when interrupt or res et oc curs .
Set to enter idle mode.
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Table 42. BDR C ON Register
BDRCO N - Baud Rate Control Register (9Bh)
Rese t Value = XXX0 0000b
Not bit addressablef
76543210
- - - BRR TBCK RBCK SPD SRC
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value r ead from this bit is indete rminat e. Do not set t his bit
6-
Reserved
The value r ead from this bit is indete rminat e. Do not set t his bit
5-
Reserved
The va lu e read fr om this bi t is in de ter mi nate . Do no t se t thi s bi t.
4BRR
Baud Rate Run Control bit
Cleared to stop the internal Baud Rate Generator .
Set to start the internal Baud Rate Generator .
3TBCK
Transmission Baud rate Generator Selection bit fo r UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator .
Set to select internal Baud Rate Generator .
2RBCK
Reception Baud Rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator .
Set to select internal Baud Rate Generator .
1 SPD Baud Rate Speed Control bit for UART
Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
0SRC
Baud Rate Source select bit in Mode 0 fo r UART
Cleared to select FOSC/12 as the Baud Rate Generator (FCLK PERIP H/6 in X2
mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
55
AT89C51RB2/RC2
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Inter r upt S yst em The A T89C51 RB2/RC2 has a tot al of 9 interrupt vectors: two e xternal interrupt s (INT0
and I NT1), t hree timer i nterrupt s ( timers 0, 1 a nd 2) , the serial po rt interrupt, SPI inter-
rupt, K eyboard interrupt and the PCA global interrupt. These interrupts are shown in
Figure 22.
Figu re 22. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in t he Interrupt Enabl e register (Table 45 and Table 47). T his register also
contain s a global disable bit, which must be cleared to disable all int errupt s at once.
Each interrupt source can also be individually programmed to one out of f our priority lev-
els by setting or clearing a bit in the Interrupt Priority register (Table 48) and in the
Interrupt Prio rity High regi ster (Table 4 6 and Tabl e 47 ) s hows t he bit v alues an d priority
levels associa ted with each combination.
IE1
0
3
High Priority
Interrupt
Interrupt
Polling
Sequence, Decreasing Fr
om
High to Low Priority
Low Priority
Interrupt
Global Disable
Individual Enable
EXF2
TF2
TI
RI
TF0
INT0
INT1
TF1
IPH, IPL
IE0
0
3
0
3
0
3
0
3
0
3
0
3
PCA IT
KBD IT
SPI IT
0
3
0
3
56
AT89C51RB2/RC2
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Registers A low-priority interrupt can be interrupted by a high-priori ty interrupt, but not by anot her
low-p riority inte rrupt. A high-pr iority interru pt can’t be i nterrup ted by any othe r inte rrupt
source.
Table 43. Priority Level Bit Values
If two interrupt requests of different priority leve ls are received simultan eously, the
reques t of higher-priority level is s erviced. If interrupt reque sts of t he sa me priority l evel
ar e received simul taneous ly, an in terna l polling sequenc e determ ines wh ich requ est is
se rviced. Thu s within ea ch priori ty level there is a s econd p riority stru cture de term ined
by the polling sequence.
IPH. x IP L. x Int e rrupt Le ve l Prior ity
0 0 0 (Lowest)
011
102
113 (Highest)
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Table 44. IENO Regi ster
IEN0 - Interrupt Enable Register (A8h)
Rese t Value = 0000 0000b
Bit addressable
76543210
EA EC ET2 ES ET1 EX1 ET0 EX0
Bit
Number Bit
Mnemonic Description
7EA
Enable All Interr upt Bi t
Cleared to disable all interrupts.
Set to enable all interrupts.
6EC
PCA Interrupt Enabl e Bit
Cleared to disable.
Set to enable.
5ET2
Timer 2 Overflow Interrupt Enable Bit
Cleared to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
4ES
Serial Port Enable Bit
Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
3ET1
Timer 1 Overflow Interrupt Enable Bit
Cleared to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2 EX1 External Inter rup t 1 Enable Bit
Cleared to disable external interrupt 1.
Set to enable external interrupt 1.
1ET0
Timer 0 Overflow Interrupt Enable Bit
Cleared to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0 EX0 External Inter rup t 0 Enable Bit
Cleared to disable external interrupt 0.
Set to enable external interrupt 0.
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Table 45. IPL0 Register
IPL0 - Interrupt Priority Register (B8h)
Rese t Value = X000 0000b
Bit addressable
76543210
- PPCL PT2L PSL PT1L PX1L PT0L PX0L
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 PPCL PCA Interrupt Priority Bit
see PPCH for priority level.
5PT2L
Timer 2 Overflow Interrupt Priority Bit
see PT2H for priority level.
4 PSL Serial Port Priority Bit
see PSH for priority level.
3PT1L
Timer 1 Overflow Interrupt Priority Bit
see PT1H for priority level.
2PX1L
External Interrupt 1 Priority Bit
see PX1H for priority level.
1PT0L
Timer 0 Overflow Interrupt Priority Bit
see PT0H for priority level.
0PX0L
External Interrupt 0 Priority Bit
see PX0H for priority level.
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Table 46. IPH0 Register
IPH0 - Interrupt Priority High Register (B 7h)
Rese t Value = X000 0000b
Not bit addressable
76543210
- PPCH PT2H PSH PT1H PX1H PT0H PX0H
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 PPCH
PCA Interrupt Priority High Bit
PPCHPPCL Priority Level
00Lowest
01
10
1 1 Highest
5PT2H
Timer 2 Overflow Interrupt Priority High Bit
PT2HPT2L Priority Level
00Lowest
01
10
1 1 Highest
4 PSH
Serial Port Priority High Bit
PSH PSL Priority Level
00Lowest
01
10
1 1 Highest
3PT1H
Timer 1 Overflow Interrupt Priority High Bit
PT1HPT1L Priority Level
00Lowest
01
10
1 1 Highest
2 PX1H
External Interrupt 1 Priority High Bit
PX1HPX1L Priority Level
00Lowest
01
10
1 1 Highest
1PT0H
Timer 0 Overflow Interrupt Priority High Bit
PT0HPT0L Priority Level
00Lowest
01
10
1 1 Highest
0 PX0H
External Interrupt 0 Priority High Bit
PX0H PX0L Priority Level
00Lowest
01
10
1 1 Highest
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Table 47. IEN1 Register
IEN1 - Interrupt Enable Register (B1h)
Reset Value = XXXX X000 b
Bit addressable
76543210
-----ESPI-KBD
Bit
Number Bit
Mnemonic Description
7-Reserved
6-Reserved
5-Reserved
4-Reserved
3-Reserved
2ESPI
SPI Interrupt Enable Bit
Cleared to disable SPI interrupt.
Set to enable SPI interrupt.
1-Reserved
0 KBD Keyboard Interrupt Enable Bit
Cleared to disable keyboard interrupt.
Set to enable keyboard interrupt.
61
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Table 48. IPL1 Register
IPL1 - Interrupt Priority Register (B2h)
Reset Value = XXXX X000 b
Bit addressable
76543210
- - - - - SPIL - KBDL
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 SPIL SPI Interrupt Priority Bit
see SPIH for priority level.
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0 KBDL Keyboard Interrupt Priority Bit
see KBDH for priority level.
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Table 49. IPH1 Register
IPH1 - Interrupt Priority High Register (B 3h)
Reset Value = XXXX X000 b
Not bit addressable
76543210
- - - - - SPIH - KBDH
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2SPIH
SPI Interrupt Priority High Bit
SPIHSPIL Priority Level
00Lowest
01
10
1 1 Highest
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0 KBDH
Keyboard Interrupt Priority High Bit
KB DHKBDL Priority Level
00Lowest
01
10
1 1 Highest
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Interrupt Sources and
Vector Addr ess es Table 50. Int errupt Sources and Ve ctor Addresses
Number Polling Priority Interrupt Source Interrupt
Request Vector
Address
0 0 Reset 0000h
1 1 INT0 IE0 0003h
2 2 Timer 0 TF0 000Bh
3 3 INT1 IE1 0013h
4 4 Timer 1 IF1 001Bh
5 6 UART RI+TI 0023h
6 7 Timer 2 TF2+EXF2 002Bh
7 5 PCA CF + CCFn ( n = 0-4) 0033h
8 8 Keyboard KBDIT 003Bh
9 9 SPI SPIIT 004Bh
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Keyboard Interface The AT89C51RB2/RC2 implements a keyboard interface allowing the connection of a
8 x n matrix ke yboard. It is based on 8 i nputs with p rogrammable interrupt capability on
both high or low level. These inputs are available as alternate f unction of P1 and all ow to
exit from idle and power-down mode s.
The key board interfac es with the C51 core through 3 s pecial function reg isters: KBLS,
the Keybo ard Level Selection register (Table 53), KBE, the Ke yboard interru pt Enable
register (Table 52 ), and KBF, the Keyboard Flag register (Table 51).
Interrupt The keyboard inputs are considered as 8 independent interrupt sources sharing the
same interrupt vector. An interrupt enable bit (KBD in IE N1) allows global enab le or dis-
able of the ke yboa rd interru pt (see F igure 23). A s deta iled i n Figu re 24 e ach ke yboard
inpu t has the capability to de tect a p rogramm able lev el accordin g to KBL S. x bit value.
Level det ection is then reported in interrupt flags KBF. x that can be masked by software
using KBE. x bits.
This structure allows keyboard arrangement from 1 by n to 8 by n matrix and allow
usag e of P1 inputs for other purpose.
Fi gure 2 3 . Keyboard Interface Bloc k Diagram
Fi gure 2 4 . Keyboard Input Circuitry
Power Reduction Mode P1 inputs allow exit from idle and power down modes as detailed in Sect ion “P ower-
down Mode”, page 82.
P
1:x
KBE. x
KBF. x
KBLS. x
0
1
VCC
Internal Pull-up
P1.0
Keyboa rd Interface
Interrupt Request
KBD
IEN1
Input Circuitry
P1.1 Input Circuitry
P1.2 Input Circuitry
P1.3 Input Circuitry
P1.4 Input Circuitry
P1.5 Input Circuitry
P1.6 Input Circuitry
P1.7 Input Circuitry
KBDIT
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Registers Table 51. KBF Register
KBF - Keyboard Flag Register (9Eh)
Rese t Va lue = 0000 0000b
This register is read only access, all fl ags are automatically cleared by reading the
register.
76543210
KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
Bit
Number Bit
Mnemonic Description
7KBF7
Keyboard Line 7 Flag
Set by h ardwa r e whe n t he Por t li ne 7 det ec ts a pr ogr amm ed l ev el. I t g ener at es a
Keyboard interrupt request if the KBKBIE. 7 bit in KBIE register is set.
Must be cleared by s oftware.
6KBF6
Keyboard Line 6 Flag
Set by h ardwa r e whe n t he Por t li ne 6 det ec ts a pr ogr amm ed l ev el. I t g ener at es a
Keyboard interrupt request if the KBIE. 6 bit in KBIE register is set.
Must be cleared by s oftware.
5KBF5
Keyboard Line 5 Flag
Set by h ardwa r e whe n t he Por t li ne 5 det ec ts a pr ogr amm ed l ev el. I t g ener at es a
Keyboard interrupt request if the KBIE. 5 bit in KBIE register is set.
Must be cleared by s oftware.
4KBF4
Keyboard Line 4 Flag
Set by h ardwa r e whe n t he Por t li ne 4 det ec ts a pr ogr amm ed l ev el. I t g ener at es a
Keyboard interrupt request if the KBIE. 4 bit in KBIE register is set.
Must be cleared by s oftware.
3KBF3
Keyboard Line 3 Flag
Set by h ardwa r e whe n t he Por t li ne 3 det ec ts a pr ogr amm ed l ev el. I t g ener at es a
Keyboard interrupt request if the KBIE. 3 bit in KBIE register is set.
Must be cleared by s oftware.
2KBF2
Keyboard Line 2 Flag
Set by h ardwa r e whe n t he Por t li ne 2 det ec ts a pr ogr amm ed l ev el. I t g ener at es a
Keyboard interrupt request if the KBIE. 2 bit in KBIE register is set.
Must be cleared by s oftware.
1KBF1
Keyboard Line 1 Flag
Set by h ardwa r e whe n t he Por t li ne 1 det ec ts a pr ogr amm ed l ev el. I t g ener at es a
Keyboard interrupt request if the KBIE. 1 bit in KBIE register is set.
Must be cleared by s oftware.
0KBF0
Keyboard Line 0 Flag
Set by h ardwa r e whe n t he Por t li ne 0 det ec ts a pr ogr amm ed l ev el. I t g ener at es a
Keyboard interrupt request if the KBIE. 0 bit in KBIE register is set.
Must be cleared by s oftware.
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Table 52. KBE Regist er
KBE - K ey boa r d In p ut Enab le Re g ister (9Dh)
Rese t Va lue = 0000 0000b
76543210
KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
Bit
Number Bit
Mnemonic Description
7 KBE7 Keyboard Line 7 Enable Bit
Cleared to enable standard I/O pin.
Set to enable KBF. 7 bit in KBF register to generate an interrupt request.
6 KBE6 Keyboard Line 6 Enable Bit
Cleared to enable standard I/O pin.
Set to enable KBF. 6 bit in KBF register to generate an interrupt request.
5 KBE5 Keyboard Line 5 Enable Bit
Cleared to enable standard I/O pin.
Set to enable KBF. 5 bit in KBF register to generate an interrupt request.
4 KBE4 Keyboard Line 4 Enable Bit
Cleared to enable standard I/O pin.
Set to enable KBF. 4 bit in KBF register to generate an interrupt request.
3 KBE3 Keyboard Line 3 Enable Bit
Cleared to enable standard I/O pin.
Set to enable KBF. 3 bit in KBF register to generate an interrupt request.
2 KBE2 Keyboard Line 2 Enable Bit
Cleared to enable standard I/O pin.
Set to enable KBF. 2 bit in KBF register to generate an interrupt request.
1 KBE1 Keyboard Line 1 Enable Bit
Cleared to enable standard I/O pin.
Set to enable KBF. 1 bit in KBF register to generate an interrupt request.
0 KBE0 Keyboard Line 0 Enable Bit
Cleared to enable standard I/O pin.
Set to enable KBF. 0 bit in KBF register to generate an interrupt request.
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Table 53. KBLS Register
KBLS - Keyboard Level Selector Register (9Ch)
Rese t Va lue = 0000 0000b
76543210
KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
Bit
Number Bit
Mnemonic Description
7KBLS7
Keyboard Line 7 Level Selection Bit
Cleared to enable a low leve l detection on Port li ne 7.
Set to enable a high level detection on Port line 7 .
6KBLS6
Keyboard Line 6 Level Selection Bit
Cleared to enable a low leve l detection on Port li ne 6.
Set to enable a high level detection on Port line 6 .
5KBLS5
Keyboard Line 5 Level Selection Bit
Cleared to enable a low leve l detection on Port li ne 5.
Set to enable a high level detection on Port line 5 .
4KBLS4
Keyboard Line 4 Level Selection Bit
Cleared to enable a low leve l detection on Port li ne 4.
Set to enable a high level detection on Port line 4 .
3KBLS3
Keyboard Line 3 Level Selection Bit
Cleared to enable a low leve l detection on Port li ne 3.
Set to enable a high level detection on Port line 3 .
2KBLS2
Keyboard Line 2 Level Selection Bit
Cleared to enable a low leve l detection on Port li ne 2.
Set to enable a high level detection on Port line 2 .
1KBLS1
Keyboard Line 1 Level Selection Bit
Cleared to enable a low leve l detection on Port li ne 1.
Set to enable a high level detection on Port line 1 .
0KBLS0
Keyboard Line 0 Level Selection Bit
Cleared to enable a low leve l detection on Port li ne 0.
Set to enable a high level detection on Port line 0 .
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Serial Port Interface
(SPI) The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial
comm unication bet ween the MCU and peripheral devices, including other MCUs.
Features Features of the SPI Module include the following:
• Full-duplex, three-wir e synchronous transfers
• Master or Slave operation
• Eight programmable Master clock rates
• Serial clock with programmable polarity and phase
• Master Mode fault err or flag with MCU interrupt capability
• Write co llis ion flag pr o t ec tion
Signal Description Fig ure 25 shows a typi cal SPI bus configura tion usi ng one M aster con troller and man y
Slave peripherals. The bus is made of three wires connecting all the devices.
Fi gure 2 5 . SPI Master/S laves Interconnection
The Mast er de vi ce se lects the ind ivid ual S lave dev ices by usin g fo ur pin s of a paral lel
port to control the four SS pins of the Slave devices.
Master Output Slave Inp ut
(MOSI) Thi s 1-bit s igna l is direct ly conne cted b etwe en the Mast er Devi ce an d a Slave Devi ce.
The MOSI line is used to trans fer data in series from the Master to the Slave. Therefore,
it is an output signal from the Ma ster, and an input s ignal to a Slave. A Byte (8-bit word)
is transmitted most significant bit (MSB) first, least significant bit (LS B ) last.
Master Inpu t Slave Output
(MISO) Thi s 1-bit sig nal i s direct ly conne cted b etwe en the Slave De vice and a M aste r Device.
The MISO line is used to trans fer data in series from the Slave to the Master. Therefore,
it is an out put signal from the Slave, and an input signal to the Master. A Byte (8-bit
word) is transmitted most significant bit (M S B) first, least significant bit (LSB) last.
SPI Serial Clock (SCK) This signal is used to synchronize the data movem ent both in and out of the devices
through their MOSI and MISO lines. It is driven by the Master for eig ht clock cycles
which allows to exchange one Byte on the serial lines.
Slave Select (SS)Each Slave peripheral is selected by one Slave Select pin (SS). Thi s si gnal mus t stay
low for any message f or a Slave. It is obvious t hat only one M aster (SS high level) can
Slave 1
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
PORT
0
1
2
3
Slave 3
MISO
MOSI
SCK
SS
Slave 4
MISO
MOSI
SCK
SS
Slave 2
MISO
MOSI
SCK
SS
VDD
Master
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drive the network. The Master may select each Slave device by software through port
pins (Figure 26). To prevent bus conflicts on the MISO line, only one slave should be
select ed at a time by the Master for a transmis sion.
In a M aster confi guration, t he S S l ine can be used i n c onj unction wi th the M ODF f lag i n
the SPI Status register (SPSTA) to prev ent multiple masters from driving MOS I and
SCK (see Error conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a hi gh-impedanc e state.
The SS pin could be used as a general-purpose if the following conditions are met:
• The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master i s driving the network
and there is no way that the SS pin could be pulled low . Therefore, the MODF flag in
the SPSTA will never be set(1).
• The Device is confi gured as a Slave with CPHA and SSDIS control bits set(2). This
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the S S pin to select the communicat ing Slave device.
Note: 1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because
in this mode, the SS is used to start the transm ission.
Baud Rate In Master mode, the baud rate can be selected from a baud rate generator which is con-
trolled by three bit s i n the SPCON regis ter: SPR2, SPR1 and SPR0.The Master clock is
selected from one of seven clock rates resulting from the division of the internal clock by
2, 4, 8, 16, 32, 64 or 128.
Table 54 gives the different clock rates selected by SPR2:SPR1: S PR0.
Table 54. SPI Master Baud Rate Selection
SPR2 SPR1 SPR0 Clock Rate Baud Rate Divisor (BD)
000 F
CLK PERIPH /2 2
001 F
CLK PERIPH /4 4
010 F
CLK PERIPH/8 8
011 F
CLK PERIPH /16 16
100 F
CLK PERIPH /32 32
101 F
CLK PERIPH /64 64
110 F
CL K PERIPH /128 128
1 1 1 Don’t Use No B RG
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Functional Description F igure 26 shows a detailed structure of the SPI Module.
Fi gure 2 6 . SPI Module B lock Diagram
Operati ng Mod es T he Serial P eri pheral Interface can be configured in on e of the two mod es: Master
mode or Slave mode. The configuration and init ialization of the SPI Module is made
through one register:
• The Serial Peripheral Control register (SPCON )
Onc e the SPI is configured, the data exchange is made using:
•SPCON
• The Serial Peripheral STA tus register (SPSTA)
• The Serial Peripheral DATa register (SPD AT )
During an S PI trans mis sion, data is simul taneous ly transmitte d (shifted ou t serially) and
received (shifted in serially). A s erial clock line (SCK) synchronizes shifting and sam-
pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows
individual selection of a Slave SP I device; Slave devices that are not selected do not
interfere with SPI bus activ i ties.
W hen the Mast er device transm its data to the Slave device via the MOS I line, the Slave
device responds by sending data to the Master device v ia the MISO line. This implies
full-duplex transmission with both data out and data in synchronized with the s ame clock
(Figure 27).
Sh i ft R e gi s te r01
234567
Internal Bus
Pin
Control
Logic MISO
MOSI
SCK
M
S
Clock
Logic
Clock
Divider
Clock
Select
/4
/64
/128
SPI Interrupt Request
8-bit bus
1-bit signa
l
SS
FC LK PERIP H
/32
/8
/16 Recei ve Data Register
SPDAT
SPI
Control
SPSTA
CPHA SPR0SPR1CPOLMSTRSSDISSPEN
SPR2 SPCON
WCOL MODFSPIF -----
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Fi gure 2 7 . Full-Duplex Master-Slave Interconnection
Ma st er Mo de The SPI operates in Master mode when the Master bit, MSTR (1), in the SPCO N register
is set. Only one Master SPI device can initiate transmis sions. Software begins the trans-
mission from a Master SPI Module by writing to the Serial Peripheral Data Register
(SPD AT). If the shift re gister is e mpty, th e Byte is imme diately transferred to the sh ift
regist er. The Byte begi ns shifting out on M OSI pin u nder the con trol of the seri al clock,
SC K. S imultan eou sly, a noth er Byte shifts i n fro m the S lave on th e Mas ter’s MISO pin.
The transm iss ion end s when t he Serial Perip heral transfe r data fla g, SPIF, in SPSTA
becomes set. At the same time that S PIF becomes set, t he received Byte f rom the Slave
is t ran sfe rred t o th e recei ve data re giste r in S P DAT. Soft war e c lear s SP IF by r eadi ng
the Serial P eripheral Status r egister (SPST A) with the SPIF bit se t, and then reading the
SPDAT.
Slave Mod e The SPI operates in Slave mode when the Master bit , MSTR (2) , in the SPCON register is
cleare d. Before a data transmission occurs, the Slave Select pin, SS, of the Slave
device must be set to ’0’ . SS must remain low until the t ransm iss ion is complete.
In a Sl ave SPI Mod ule, da ta enters t he shift regis ter under the c ontrol of the SCK from
the Master SPI Module. After a Byte enters the shift register, it is immediately trans-
ferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an
overflow condition, Slave software must then read the SPDAT before another Byte
enters the shift register (3). A Slave SPI must complete the write to the SPDAT (shift reg-
ister) at least one bus cycle before the Master SPI starts a transmission. If the write to
the da ta register is late, the SPI t ransmits the dat a already in the shift reg ister from the
previous transmission. The maximum SCK frequency allowed in slave mode is FCLK PERI PH
/4.
Transm issio n Form ats So ft ware c an selec t any of fo ur c omb inati ons of seri al cl ock ( SCK) phas e an d pol arity
using two bits in the SPCON: the Clock Polarity (CPOL (4)) and the Clock Phase
(CPHA4). CPOL defines the de fault SCK line level in idle state. It has no significant
effect on the tran smissio n format. CPHA defines the edges on which the input data are
sample d and the edges on which the output data are shif ted (Figure 28 a nd Figure 29).
The clock phase and polarity should be identical for the Master SPI device and the com-
municating Slave device.
8- bit Shi ft register
SPI
Clock Ge nerator
Master MCU
8- bit Shi ft register
MISOMISO
MOSI MOSI
SCK SCK
VSS
VDD SSSS Slave MCU
1. The SPI Modul e should be configured as a Master bef ore it is enabled (SPEN set ). Also,
the Master SPI sho uld be confi gured before the Sla ve SPI.
2. The SPI Modul e should be configured as a Slav e before it is enabled (SPEN set).
3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock
speed.
4. Before writing to the CPOL and CPHA bit s, t he SPI should be disabled (SPEN = ’0’).
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Figu re 28. Data Transmission Format (CPHA = 0)
Figu re 29. Data Transmission Format (CPHA = 1)
Figu re 30. CPHA/SS Ti ming
As shown in Figure 28, the first SC K edge is the MSB capture strobe. Therefore, the
Slave must begin driving its data before the first SCK edge, and a falling edge on the SS
pin is used to start the transmission. The SS pin must be toggled high and then low
between each Byte transmitted (Figure 30).
Figure 29 shows an SPI transmission in which CPHA is ’1’. In this case, the Master
begins driving its M OSI pin on the first SC K edge. Therefore, the Slav e uses the first
SCK edge as a start transmis sion signal. The SS pin can remain low between transmis-
sions (Figure 30 ). T his form at may be preffered in systems having on ly one Ma ster a nd
only one Slave driving the MISO data line.
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
bit6 bit5 bit4 bit3 bit2 bit1MSB LSB
132 45678
Capture Point
SS (to Slave)
MISO (from Slave)
MOS I (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (Internal)
SCK Cycle Nu mber
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
bit6 bit5 bit4 bit3 bit2 bit1
MSB LSB
132 45678
Capture Point
SS (to Slave)
MISO (from Sl ave)
MOSI (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (Internal)
SCK Cycle Nu mber
Byte 1 Byte 2 Byte 3
MISO/MOSI
Master SS
Slave SS
(CPHA = 1)
Slave SS
(CPHA = 0)
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Error Conditions The following flags in the SPSTA signal SPI error conditions:
Mode Fault (MODF) Mo de Fa ult error i n Ma ster m ode SP I indi cate s that t he lev el on the Sl ave S elect (S S)
pin is i nconsistent wi th the a ctual mode of the device. MO DF is set to warn th at there
may be a multi-master conflict for system control. In this case, the SPI system is
affected in the following ways:
• An SPI receiver/error CPU i nte rrupt request is generated
• The SPEN bit in SPCON is cleared. This disabl es the SPI
• The MSTR bit in SPCON is cleared
When SS Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set
when the SS signal become s ’0’.
However, as stated before, for a s ystem with one Master, if the S S pin of the Master
dev ice is pulle d low, there is no way that another M aster attempts to drive the netwo rk.
In this case, to prevent the MO DF flag from bei ng set, software can set the S SD IS bit in
the SPCON register and therefore making the SS pin as a general-purpose I/O pin.
Clearing the M ODF bit is accom plished b y a read of SPSTA regi s ter with MODF bit s et,
followed by a write to the SPCON register. SPEN Control bit may be restored to i ts orig-
inal set state after the MODF bit has been cleared.
Writ e C ollis ion (WCOL ) A Write Collision (WCOL) flag in t he SPSTA is set when a write to the SPDAT register is
done during a transm it sequenc e.
W COL does not cause an interruption, and the transfer continues uninterrupte d.
Clearing the WCOL bit is done through a softwar e sequence of an access to SPSTA
and an access to SPDAT.
Overrun Condition An ove rrun co ndition occu rs wh en the M aster device tries to send s evera l data Bytes
and the Slave devise has not cleared the SPIF bit issuing from the previous data Byte
transmit ted. In this case, the receiver buffer contains the Byte sent after the SPIF bit was
last cleared. A read of the S P DA T returns this Byte. All others Bytes are lost.
This condition is not detecte d by the SPI peripheral.
SS Error Flag (SSERR) A Synchronous Serial Slave Error occurs when SS goes high before the end of a
rec eived data in slave mode . SSERR d oes n ot cau se in i nterrupt ion, thi s bit is cleare d
by writing 0 to SPEN bit (reset of the SPI state machine).
Interrupts Two SPI status flags can generate a CPU interrupt requests:
Table 55. SPI Inter ru p ts
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer
has been completed. SPIF bit generates transmitter CPU interrupt requests .
Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is
inconsist ent wi th the mode of t he SPI. MODF with SSDIS reset, generates receiver/error
CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated.
Figure 31 gives a l ogical view of the above statements.
Flag Request
SPIF (SP data transfer) SPI Transmitter Interrupt request
MODF (Mode Fault) SPI Receiver/Error Interrupt Request (if SSDIS = ’0’)
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Fi gure 3 1 . SPI Interrupt Requests Ge neration
Registers There are three registers in the Module that provide control, status and data storage functions. These registers
ar e de sc r i be s in the foll ow i ng parag r a ph s.
Serial Peripheral Control
Register (SPCON) • The Serial Peripheral Control Register does the following:
• Selects one of the Master clock rates
• Configure the SPI Module as Master or Slave
• Selects serial clock polarity and phase
• Enables the SPI Module
• Frees t he SS pin for a general-purpose
Table 56 des cribes this register and explains the use of each bit
Table 56. SPCON Register
SPCON - Serial Peripheral Control Register (0C3H )
SSDIS
MODF
CPU Inter rupt Request
SPI Receiver/error
CPU Interrupt Request
SPI Transmitter SPI
CPU Interrupt Request
SPIF
76543210
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
Bit Number Bit Mnemonic Description
7 SPR2 Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate.
6 SPEN Serial Peripheral Enable
Cleared to disable the SPI interface.
Set to en able the SPI interface.
5SSDIS
SS Disable
Cleared to enable SS in both Mast er and Slave modes.
Set to disa ble SS in both Master and Slave modes. In Slave mode,
this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF
interrupt re quest is generated.
4MSTR
Ser ial Per iphe ral Master
Cleared to conf igur e the SPI as a Sla ve.
Set to configure the SPI as a Master.
3CPOL
Clock Polarity
Cleared to have the SCK set to ’0’ in idle state.
Set to have the SCK set to ’1’ in idle low.
2CPHA
Clock Phase
Cleared to have the data samp led wh en the SCK leaves the idl e
state (see CPOL).
Set to h ave t he data sample d w hen th e SC K r etur n s to i dl e s tat e ( s ee
CPOL).
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Rese t Value = 0001 0100b
Not bit addressable
Serial Peripheral Status Register
(SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions:
• Data transfer c om ple te
• Write co llis ion
• Inconsistent logic level on SS pin (mode fault error)
Table 57 describes the SPSTA register and explains the use of every bit i n the register.
Table 57. SPSTA Register
SPSTA - Serial Peripheral Status and Control register (0C4H)
1SPR1 SPR2 SPR1 SPR0 Serial Peripheral Rate
00 0F
CLK PERIPH /2
00 1 F
CLK PERIPH /4
01 0 F
CLK PERIPH /8
01 1F
CLK PERIPH /16
10 0F
CLK PERIPH /32
10 1F
CLK PERIPH /64
11 0F
CLK PERIPH /128
1 1 1 Invalid
0 SPR0
Bit Number Bit Mnemonic Description
76543210
SPIF WCOL SSERR MODF - - - -
Bit
Number Bit
Mnemonic Description
7 SPIF
Ser ial Peripheral Data Transfer Flag
Cleared by hardware to indicate data transfer is in progress or has been
approved by a clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
6WCOL
Write Collision Flag
Cleared by hard ware to indicate that no collisi on has occurred or ha s been
approved by a clearing sequence.
Set by hardware to indicate that a collision has been detected.
5 SSERR Synchronous Serial Slave Error Flag
Set by hardware wh en SS is d easser ted bef ore the end of a r eceived dat a.
Cleared by disabling the SPI (clearing SPEN bit in SPCON).
4MODF
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or
has been approv ed by a cle aring sequence.
Set by hardware to indicate that the SS pin is at inappropriate logic level.
3-
Reserved
Th e va lu e r ea d from thi s bit is ind eterm inat e. D o no t set this bit
2-
Reserved
Th e va lu e r ea d from thi s bit is ind eterm inat e. D o no t set this bit.
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Reset Value = 00X0 XXXXb
Not Bit addressable
Serial Peripheral DATa Register
(SPDAT) The Se rial Peripheral Data Register (Table 58) is a read/write buff er for the receive data
register. A write to SPDAT places data di rectly into the s hift register. No transmit buff er i s
available in this model.
A Read of the SPDAT returns the value located in the rec eive buffer and not t he content
of the shift regist e r.
Table 58. SPDAT Regi ster
SPDAT - Serial Peripheral Data Register (0C5H)
Reset Val u e = In de termin ate
R7:R0: Receive data bits
SPCON, SPSTA and SPD AT registe rs may be read and written at any time while there
is no on -going ex chang e. Howeve r, spec ial care sh ould be tak en whe n writing to t hem
while a transmission is on-going:
• Do not change SPR 2, SPR1 and SPR0
• Do not change CPHA and CPOL
• Do not change MS TR
• Cl e a ring SPEN w o uld imme dia tely disabl e the peripheral
• Writ ing to the SPDAT will cause an overflow.
1-
Reserved
Th e va lu e r ea d from thi s bit is ind eterm inat e. D o no t set this bit.
0-
Reserved
Th e va lu e r ea d from thi s bit is ind eterm inat e. D o no t set this bit.
Bit
Number Bit
Mnemonic Description
76543210
R7 R6 R5 R4 R3 R2 R1 R0
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Hardware Watchdog
Timer The WDT is intended as a recovery method in situations where the CPU may be sub-
jected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer
Reset (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable
the WDT, user m ust write 01 EH and 0 E1H in seque nce to t he WDTR ST, SFR l ocation
0A6 H. When WDT is enab led, it will increment every machine cycle wh ile t he oscillator
is running and there is no way to disable the WDT except through reset ( eit her hardware
reset or WDT overflow reset). When WDT overflows, it wi ll drive an output RESET HIGH
pulse at t he RST-pin.
Using the WDT To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, S FR
location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH
and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it
reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. This means the user must
reset the WDT at least every 16383 machine cycle. To reset the WDT the user must
write 01E H and 0E1H to WDT R ST. WDTRST is a write only reg ister. The WDT c ounter
cannot be read or written. When WDT overflows, it wil l generate an output RESET pulse
at the RST-pin. The RESET pulse duration i s 96 x T C L K PE RI PH , where TCLK PERIPH= 1 /F CLK
PERIPH. To make the best use of the WDT, it s hould be serviced in those sections of c ode
that will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 27 counter has been added to extend the Time-out
ca pability , ra nking fro m 16 ms t o 2 s @ FOSCA = 1 2 MHz. To ma na ge th is fea ture, se e
W DTPRG register des cription, Table 59.
Table 59. WDTRST Register
WD TRST - Watchdog Res et Register (0A6h )
Reset Value = XXXX XXXXb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
76543210
--------
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Table 60. WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset Value = XXXX X000
WDT During Power-down
and Idle In P owe r-do wn mode th e os cil lato r st ops, wh ich m ea ns the W DT a ls o stop s. Wh ile i n
Power-do wn m ode the user does not need to serv ice the WDT. T here a re t wo m et hods
of exiting Power-down mode: by a hardware reset or via a level activated external inter-
rupt wh ich is enabled prior to ent ering Power-down mode. When Pow er-down is exited
with hardware reset, servicing the WDT should occur as it normally should whenever the
AT89 C51 RB2/RC 2 is reset . Exiting P ower-d own with a n interru pt is si gnifican tly differ-
ent. The interrupt is held low long enough for the oscillator to stabilize. When the
interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the
device while the interrupt pin is held low, the WDT is not started until the interrupt is
pulled high. It is suggested that the WDT be reset during the interrupt service routine.
To ensure th at the WDT does not overflow within a few states of exiting of power-down,
it is better to reset the WD T just before entering power-down.
In the Idle m ode, the osc illator co ntinues t o run. To prevent the WD T from resetting the
AT89C51RB2/RC2 while in Idle mode, the user should always set up a timer that will
periodical ly exit Idle, servi c e the WDT, and re-enter Idle mode.
76543210
- - - - - S2 S1 S0
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
6-
5-
4-
3-
2S2WDT Time-out Select Bit 2
1S1WDT Time-out Select Bit 1
0S0WDT Time-out Select Bit 0
S2 S1 S0Selected Time-out
000(2
14 - 1) mach in e cy c les, 16 . 3 ms @ F OSC A = 12 MHz
001(2
15 - 1) mach in e cy c les , 32 .7 ms @ F OSCA = 12 MHz
010 (2
16 - 1) machine cycles, 65. 5 ms @ FOSCA = 12 MHz
011(2
17 - 1) machine cycles, 131 ms @ FOSCA = 12 MHz
100(2
18 - 1) machine cycles, 262 ms @ FOSCA = 12 MHz
101 (2
19 - 1) machine cycles, 542 ms @ FOSCA = 12 MHz
110(2
20 - 1) mach in e cy c l es , 1.0 5 s @ FOSCA = 12 MHz
111 (2
21 - 1) machine cycles, 2.09 s @ FOSCA = 12 M Hz
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ONCE™ Mode (ON
Chip Emula tion) The ONCE m ode facilitates testing and debugg ing of systems using AT89C51RB 2/RC2
without remo ving the circuit fr om the board. Th e O NCE m ode is i nv oked by driving cer-
tain pins of the AT89C51RB2/RC2 ; the following sequence m us t be exercised:
• Pull ALE low while the device is in res et (R ST high) and PSEN is high.
• Hold ALE low as RST is deactivated.
While the AT89C51RB2/RC2 is in ONCE mode, an emulator or test CPU can be used to
drive the circuit. Table 61 shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 61. External Pin Status during ONCE Mod e
ALE PS EN Port 0 Port 1 Port 2 Po rt 3 XTAL1/2
Weak pull-up Weak pull-up Float Weak pull-up Weak pull-up Weak pull-up A c tive
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Power Management T wo powe r redu ction mod es are implemented in t he AT89C51RB 2/RC2: the Idle mode
and the Power-down mode. These modes are detailed in the following sections. In addi-
tion to these power reduction modes, the clocks of the core and peripherals can be
dynamically divided by 2 using the X2 mode detailed in Section “X2 Feature”.
Reset In order to start-up (cold reset) or to restart (warm reset) properly the microcont roller, an
high level has to be applied on the RST pin. A bad level leads to a wrong initialization of
the internal registers like SFRs, Program Counter… and to unpredictable behavior of
the microco ntroller. A proper device reset initializes the AT89C51RB2/ RC2 and vectors
the CPU t o add ress 0000h. RST in put has a pull-down resistor allowing po wer-on res et
by sim ply connecting an ex t ernal capac itor to V DD as shown in Figure 3 2. A warm reset
can be applied either directly on the RST pin or indirectly by an internal reset source
such as the watchdog timer. Resistor value and input characteristics are discussed in
the Section “DC Characteristics” of the A T 89C51RB 2/RC2 dat asheet .
Fi gure 3 2 . Reset Circuitry and Power-On Reset
Cold Reset 2 conditions are required before enabling a CPU start-up:
•V
DD must reach the specified VDD range
• The level on X1 input pin must be outside the specification (VIH, VIL)
If one of these 2 conditions are not met, the microcontroller does not start correctly and
c an exe cu te a n ins truc tion f etc h fr om a nywh ere in th e pr ogra m sp ace . An acti ve le ve l
appli ed on the R ST pin must be mai ntained t ill bot h of the a bove con ditio ns are met. A
reset is active when the level VIH1 is reache d and when the p ulse width covers the
period of time where VDD an d the osc illator are not stabi lized. 2 param eters ha ve to be
taken into account to determine the reset pulse width:
•V
DD rise time,
• Os c illator s tar tup time .
To determine the capacitor value to implement, t he highest value of these 2 parameters
has to be chosen. Table 1 gives some capacit or values examples for a minimum RRST of
50 KΩ and different oscillator st artu p and VDD rise times.
RRST
RST
VSS
To CPU Core
and Peripherals
RST
VDD
+
Power-on ResetRST in put circuitry
P
VDD From Int ernal
Reset Source
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Table 1. M in imum Reset Capac itor Value for a 50 kΩ Pull-down Resistor(1)
Note: These values assume VDD starts from 0V to the nominal value. If the time between 2
on/off sequences is too fast, the power-supply de-coupling capacitors may not be fully
discharged, leadi ng to a bad reset sequence.
Warm Reset To ac hi eve a valid reset, the reset signal must be maintained for at least 2 machine
cyc les ( 24 oscil lator cl ock p eriods) w hile the o scilla tor is ru nn ing. Th e num ber of c lock
periods is mode independent (X2 or X1).
Watchdog Reset As deta iled in Section “Hardw are W atchdog Timer”, page 77, t he WDT generates a 96-
clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of
th e appl ication in cas e of ext ernal cap acitor or pow er-supp ly su perv isor circ uit, a 1 kΩ
resistor must be added as shown Figure 33.
Fi gure 3 3 . Reset Circuitry for WDT Reset-out Usa ge
Oscillator
Start-Up Time
VDD Rise Time
1 ms 10 ms 100 ms
5 ms 820 nF 1.2 µF 12 µF
20 ms 2.7 µF 3.9 µF 12 µF
RRST
RST
VSS
To CPU Core
and Peripherals
VDD
+
P
VDD From WDT
Rese t Source
VSS
VDD
RST
1K
To Other
On-board
Circuitry
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Reset Recomme nd ation
to Pr event Flash
Corruption
An example of bad initialization situation may occur in an instance where the bit
ENBOO T in AUXR1 register is initialized from the hardwa re bit BLJB upon res et. Since
this bit allows mapping of the bootloader in the code area, a reset failure can be critical.
If on e w ants th e EN BOO T cle ared i n orde r to u nmap the boo t from the code a rea (yet
due to a bad reset) the bit ENBOOT in SFRs m ay be set. If the value of Program
C ounter i s ac cidentl y in t he ran ge of the b oot m emory addres ses then a Flash acc ess
(write or erase) may corrupt the Flash on-chip memory.
It is recommended to use an ext ernal reset circuitry featuring power supply monitoring to
preve nt system malfunction during periods of ins uffici ent power su pply voltage (pow er
supp ly failure, power supply switched off).
Idle Mode An instruction that sets PCON.0 indic ates that it is the last instruction to be executed
before going into Idle mode. In Idle mode, the internal clock signal is gated off to the
C PU, b ut not t o the i nterr upt, Ti mer, a nd Seri al Po rt func tion s. The CPU status is p re-
served in its entirety: the Stack Pointer, Prog ram Counter, Program Status Word,
Accumulator and all other registers maintain their data during idle. The port pins hold the
logical state s they had at the time Idle was activated. AL E and PSEN hold at logic high
level.
The re are tw o ways to term inate t he Idle mode. A ctivation o f any en abled i nterru pt will
cau se PCON.0 to be cleared by hardware, te rminating the Idle mode . The interrupt will
be s erviced , and fol lowin g RETI th e nex t inst ruction t o be exec uted wi ll be the one fo l-
lowing the instruction that put the device into idle.
The flag bits GF0 and GF1 c an be used to give an indic ation if an interrupt occurred dur-
ing normal operation or during idle. For example, an instruction that activates idle can
also s et one or both f lag bits. When idle is terminat ed by an interrupt , the interrupt ser-
vice routine can exami ne the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycl es ( 24 osci ll ato r p e riod s) to complete the rese t.
Power-down Mode To sav e maximum pow er, a Power-down mo de can be invoked by softw are (se e Table
14, PCON register).
In Po wer-down mode, the os cillato r i s stopp ed a nd the instruc tion tha t invoke d Pow er-
down mode is the last instruction executed. The internal RAM and SFRs retain their
value until the Power-down mode is terminated. VCC can be lowered to save further
powe r. Eith er a ha rdwa re reset or an exte rnal int errupt ca n ca use an e xit fro m Powe r-
down . To p roperly te rminate P ower-do wn, the reset o r extern al interr upt sho uld no t be
executed before VCC is restored to its normal operating level and must be held active
long enough for the oscillat or to res ta rt and stabi lize.
Only external interrupts INT0, INT1 and Keyboard Interrupts are useful to exit from
Power-do wn. F or that, interrupt mus t be enabled and c onfigured as level or edge s ensi-
tive int errupt input. When K ey board Interrupt occurs after a power down mode, 1024
clocks are necessary to exit to power down mode and enter in operating mode.
Holding the p in low restarts the os cillator b ut bringing the pi n high com pl etes the exit as
det ailed in F igure 34. W hen b oth in terrupts are enable d, the osc illator restarts as soon
as one of the two inputs is held low and power down exit will be completed when the f irst
input will be released. In this case, the higher priorit y interrupt service routine is exe-
cuted. Onc e the interrupt is serviced, the next instruction to be executed after RETI will
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be the one following the instruction that puts the AT89C51RB2/RC2 into Power-dow n
mode.
Figu re 34. Po wer-down Exi t Waveform
Exi t from Power-d own by reset re defines all the S FRs, exit fro m Power-do wn by exter-
nal interrupt does no affect the SFRs.
Exit from Power-down by either reset or ext ernal interrupt or keyboard interrupt does not
affect th e int e rn al RAM cont e n t.
Note: If idle mode is activated with Power-down mode (I DL and PD bit s set), the exit sequence
is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and
idle mode i s not ent ered.
Table 62 shows the state of ports during idle and power-down mode s.
Port 0 can force a 0 lev el. A "one" wil l leave port fl oating.
INT1
INT0
XTALA
Power-down Phase Oscillator Restart Phase Active PhaseActive Phase
or
XTALB
Tab le 62. Sta te of Ports
Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle Internal 1 1 Port Data(1) Port Data Po r t Data Port Data
Idle Exte rna l 1 1 Float in g Port D ata Ad dr es s P ort Data
Power Down Internal 0 0 Port Data(1) Port Data Po rt D ata Port Data
Power Down Ex ternal 0 0 Floating P ort Data Port Data P ort Data
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Powe r-off Fla g The Power-off flag allows the user to distinguish between a “cold start” reset and a
“warm start” reset.
A cold s tart reset is the on e induced by VCC switch-on. A wa rm start reset occurs whil e
VCC is still applied to the device and could be generated by an exit from Power-down.
Th e P ower- off f la g (P OF) is lo cat ed i n PCO N r egis ter (Tab le 63). P OF i s se t b y hard -
ware when VCC r ises f rom 0 to i ts n omi nal volt age. T h e POF ca n be set o r cle are d by
software allowing the user to determine the type of reset.
Table 63. PCO N Regist er
PCO N - Power Control Register (87h)
Rese t Value = 00X1 0000b
Not bit addressable
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number Bit
Mnemonic Description
7SMOD1
Serial port Mode Bit 1
Set to select double baud rate in mode 1, 2 or 3.
6SMOD0
Serial port Mode Bit 0
Cleared to select SM0 bit in SCON register .
Set to select FE bit in SCON register.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4POF
Power-off Flag
Cleared to recognize next reset type.
Set by hardware when VCC r is es fr om 0 to i t s n omina l v ol t age. Can al so be set by
software.
3GF1
General-purpose Flag
Cle ared by use r for ge neral- purp ose usa ge.
Set by user for general-purpose usage.
2GF0
General-purpose Flag
Cle ared by use r for ge neral- purp ose usa ge.
Set by user for general-purpose usage.
1PD
Power-down mode bit
Cle ared by ha rdware wh en reset oc curs.
Set to e nt er po wer -d ow n mo de .
0IDL
Idle Mode Bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
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Reduced EMI Mode The ALE si gnal is used to demult iplex address and data buses on port 0 when used with
external program or data mem ory. Nevertheless, during internal code execution, ALE
sign al is s till g enerate d. In o rder to red uce EM I, ALE sign al can be d isabl ed by s etting
AO bit.
The A O bit is located in AUXR registe r at bit locat ion 0.As s oon as A O is s et, ALE is no
longer output but remains active during MOVX and MOVC instructions and external
fetches . During ALE disabling, ALE pin is weakly pulled high.
Table 64. AUXR Regi ster
AUXR - Auxiliary Register (8Eh)
76543210
DPU - M0 - XRS1 XRS0 EXTRAM AO
Bit
Number Bit
Mnemonic Description
7DPU
Disable Weak Pu ll-up
Cleared to activate the permanent weak pull up when latch data is logic 1
Set to disactive the weak pull-up.
6-
Reserved
Th e valu e r ea d from thi s bi t is ind eterm inat e. D o no t set this bit.
5M0
Pulse Length
Cleared to stretch MOVX control: the RD an d the WR pulse length is 6 clock
periods (default).
Set to stretch MOVX control: the RD and t he W R pulse length is 30 clock
periods.
4-
Reserved
Th e valu e r ea d from thi s bi t is ind eterm inat e. D o no t set this bit.
3XRS1XRAM Size
XRS1 XRS0 XRAM size
0 0 256 Bytes (default)
0 1 512 Bytes
1 0 768 Bytes
1 1 1024 Bytes
2XRS0
1 EXTRAM
EXTRAM Bit
Clear ed to access internal XR AM using movx @ Ri @ D PT R .
Set to access external memory.
Programmed by hard ware after Power-up rega rding Hardware Security B yte
(HSB), default setting, XRAM selected.
0AO
ALE Output Bit
Cleared, ALE is emitted at a const ant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used). ( default) Se t, ALE is active only during a M O VX or MOVC
instruction is used.
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Flas h EEPRO M
Memory The Flash memory increases EPROM and ROM functionality with in-circ uit electrical
erasu re and programm ing. It c ontains 16K o r 32K Bytes of program memory organized
in 128 or 256 pages of 128 Bytes. This memory is both parallel and serial In-system Pro-
grammable (ISP). ISP allows devices to alter their own program memory in the actual
end produc t under softw are co ntrol. A default serial loader (bootloader) program allows
ISP of the Flash.
The program mi ng doe s not re quire e xterna l dedi cated program ming vo lta ge. The n ec-
essary high programming voltage is generated on-chip using the standard VCC pins of
the microco ntroller.
Features • Flash EEP ROM internal program memory.
• Boot vector allows user provided Flash loader code to reside anywhere in the Flash
mem or y spa c e. Th is config u ra ti o n p ro v ide s flex ibilit y to the user.
• Default loader in Boot ROM allows programming via the serial port wit hout the need
of a user-provided loader.
• Up to 64K Byt e external program memory if the internal program memory is
disabled (EA = 0).
• Programming and erase voltage with standard 5V or 3V VCC supply.
• Read/Programming/Erase:
– Byte-wise read without wait state
– B yte or page erase and programming (10 ms)
• Typical programm ing time (32K Bytes) in 10 s
• Parallel programming with 87C51 compatible hardware interface to programmer
• Programmable security for the code in the Flash
• 100K write cycles
• 10 years data retention
Flash Programming and
Erasure The 16K or 32K Bytes Flash is programmed by Bytes or by pages of 128 Bytes. It is not
nec essa ry t o eras e a Byte or a pa ge be fore program min g. The pro gramm ing of a By te
or a page includes a self erase before programming.
There are three methods of programming the Flash memory :
• First, the on-chip ISP boot loader may be invoked which will use low level routines to
program the pages. The interface used for serial downloading of Flash is the UART.
• Second, the Flash may be programmed or erased in the end-user application by
calling low-level routines through a common entry point in the Boot ROM.
• Third, the Flash may be programme d using the parallel method by using a
conventional EPROM programmer. The parall el programming method used by
these devices is similar to that used by EPROM 87C51 but it is not identical and the
commercially available programm ers need to have support for the
AT89C51RB2/RC2. The bootloader and the Application Programming Interface
(API) routines are located in t he B OOT ROM .
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Flash Registers and
Memory Map The AT89C51RB2/RC2 Flash memory uses several registers for it s manag em ent:
• Hardware registers can only be accessed through the parallel pr ogramming modes
which are handled by the parallel programmer .
• Software registers are in a spec ial page of the Flash memory which can be
accessed through the API or with the parallel programming modes. This page,
called "Extra Flash Memory", is not in the internal Flas h program mem ory
addressing space.
Hardware Regist er The onl y hard ware regi ster of the A T89C51RB 2/R C2 is called Ha rdware S ecurity B yte
(HSB).
Table 65. H a rdw a r e Security By te (HSB)
Boot Loader Jump Bit (BLJB)
One bit of the HSB, the BLJB bit, is used to force the boot address:
• When this bit is programmed (‘1’ value) the boot address is 0000h.
• When this bit is unprogrammed (‘1’ value) the boot address is F800h. By default,
this bit is unprogrammed and the I SP is enabled.
Flash Memory Lock Bits T he thre e lock bits pro vid e differe nt le vels of protec tion fo r the o n-ch ip cod e and d ata,
when programm ed as sh own in Table 66 .
76543210
X2 BLJB - - XRAM LB2 LB1 LB0
Bit
Number Bit
Mnemonic Description
7X2
X2 Mode
Programmed (‘0’ value) to force X2 mode (6 clocks per instruction) after reset.
Unprogrammed (‘1’ V alue) to force X1 mode, Standard Mode, after reset
(Default).
6BLJB
Boot Loader Jump Bit
Unprogrammed (‘1’ va lue) t o start the user’s application on next res et at address
0000h.
Pr ogr am med (‘0’ val ue ) to st art the bo ot loa der at addr e ss F800 h on ne xt rese t
(Default).
5-Reserved
4-Reserved
3XRAM
XRAM Config Bit (only programmable by programmer tools)
Programmed to inhibit XRAM after reset.
Unprogrammed, this bit to valid XRAM after reset (Default).
2-0 LB2-0 User Memory Lock Bit s (only programmable by programmer tools)
See Table 66.
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Table 66. Prog ram Lock Bits
Note: U: unprogram med or "one" level.
P: programmed or "zero" level.
X: d on’t care
WARNING: Security level ‘2’ and ‘3‘ should only be programmed after Flash and code
verification.
These s ecurity bits prote ct the code access through the parallel progra mm ing interface.
They are set by def ault to level 4. T he co de acc ess through the I SP i s still po ssi ble a nd
is co ntrolled by the " software sec urity bits" whic h are stored i n the extr a Flash mem ory
accessed by the ISP firmware.
To load a new application with the parallel pr ogrammer, a chip erase must first be done.
Th is will set th e H S B i n it s i nac ti ve s ta te and w ill eras e the F lash memor y. The part r ef-
erence can always be read using Flash parallel programming mo des.
Default Values The default value of the HSB provides parts ready to be programmed with ISP:
• BLJB: Programmed force ISP operation.
• X2: Unprogrammed to force X1 mode (Standard Mode).
• XRAM: Unprogrammed to valid XRAM
• LB2-0: S ecurity level four to protect the code from a parallel access with maximum
security.
Software Registers Several registers are used, in factory and by parallel programmers, to make c opies of
hard ware registers contents. These values are used by Atmel ISP.
These re gisters are in the "Extra Flash Mem ory" part of the Flash memory. This block is
also called "XAF" or eXtra Array Flash. They are accessed in the following ways:
• Comman ds issued by the parallel mem ory programm er.
• Comman ds issued by the ISP software.
• Calls of API issued by the application soft ware.
Several software registers are described in Table 67.
Program Lock Bits
Prote cti on Des crip tion
Security
Level LB0 LB1 LB2
1 U U U No program lock features enabled.
2PUU
M O VC instructio n executed from external program memory i s disabled
from fetching code Bytes from internal memory, EA is sampled and
latched on reset, an d further parallel programming of the Flas h is
disabled. ISP and software p rogramming w ith API are still allowed.
3XPU
Same as 2, also verify through parallel programming interface is
disabled.
4 X X P Same as 3, also external execution is disabled. (Default)
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Table 67. Default Values
After programming the part by ISP, the BSB must be cl eared (00h) in order to allow the
applicat ion to boot at 0000h.
The co ntent of the Software Security Byte (SSB) is described in Table 67 and Table 69.
To ass ure code protection from a p arallel ac ces s, the HSB m ust al so be at the requi red
level.
Table 68. Softwa r e Se cur ity Byte
The two lock bits provide different levels of protection for the on-chip code and data,
when programm ed as sh own in Table 69 .
Mnemonic Definition Default value D escr iption
SBV Software Boot Vector FCh
HSB Hardware security Byte 101x 1011b
BSB Boot Status Byte 0FFh
SSB Software Security Byte FFh
Copy of the Manufacturer Code 58h ATMEL
Copy of the Device ID #1: Family Code D7h C51 X2, Electrically Erasable
Copy of the Device ID #2: memories F7h AT89C51RB2/RC2 32KB
size and type FBh AT89C51RB2/RC2 16 KB
Copy of the Device ID #3: name and
revision EFh AT89C51RB2/RC2 32KB,
Revision 0
FFh A T89C51RB2/RC2 16 KB,
Revision 0
76543210
------LB1LB0
Bit
Number Bit
Mnemonic Description
7-
Reserved
Do not clear this bit.
6-
Reserved
Do not clear this bit.
5-
Reserved
Do not clear this bit.
4-
Reserved
Do not clear this bit.
3-
Reserved
Do not clear this bit.
2-
Reserved
Do not clear this bit.
1-0 LB1-0 User Memory Lock Bits
se e Tab le 69
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Table 69. Program Lock Bits of the SSB
Note: U: unprogram med or "one" level.
P: programmed or "zero" level.
X: d on’t care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
Flash Memory Status A T89C51RB2/RC2 part s are delivered in standard with the ISP bo ot in the Flash mem-
or y. Afte r ISP or p arall el pro grammi ng, the p ossi ble con tents o f the F lash m em ory a re
summarized on Figur e 35.
Figu re 35. Fla sh Memory Possible Contents
Memory Organization In the AT89C51RB2/RC2, the lowest 16K or 32K of the 64 KB program memor y address
space is filled by internal Flash.
When t he E A pin is high, the processor fetches instr uctions from internal program Flash.
Bus expansion for accessing program memory f rom 16K or 32K upward automatic since
external instruction fetches occur automatically when the program counter exceeds
3FF Fh (16K) or 7FFFh (32K ). If the EA pin is tied low, all prog ram memory f etches are
from external memory.
Program Lock Bits
Prote cti on Des cri ptio n
Security
level LB0 LB1
1 U U No program lock features enabled.
2 P U ISP programming of the Flash is disabled.
3 X P Same as 2, also verify through ISP programming interface is disabled.
0000h
Virgin
3FFFh
Default A f te r ISP After Parallel
Programming After Paralle l
Programming
ApplicationApplication Virgin
After ISP
or
Dedicated
ISP Dedicated
ISP
7FFFh T89C51RC2 32KB
T89C51RB2 16KB
Application
Virgin
or
Application
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Bo otl oad er Architec tur e
Introduction The bootloader manages a communication according to a specific defined protocol to
provide th e whole acces s and serv ice on F lash m emo ry. Furthermore, a ll access es and
routines can be called from the user application.
Fi gure 3 6 . Diagram Context Description
Acronyms ISP: In-system Programming
SBV: Software Bo ot Vector
BSB: Boot Sta tus Byte
SSB: Software Security Bi t
HW : Hardware Byte
Bootloader Flash Memo
ry
Acce ss vi a
Specific
Protocol
Access From
User
Application
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Functional Description
Figu re 37. Bootloader Functional Description
On the above diag ram, the on-chip bootloader proce sses are:
• ISP Communication Management
The p urpose o f this p rocess is to manag e the com munic ation and its prot ocol bet ween
the on-chip boot loader and a external dev ice. The on-chip ROM imp lement a serial pro-
tocol (s ee section Bootloader Protocol). This proces s translate serial communication
frame (UART ) into Flash memory acess (read, write, erase ...).
• User Call Management
Several Applica tion Program Interface (API) calls are available for use by an application
program to permit selective erasing and programming of Flash pages. All calls are made
through a com m on in terface (A P I ca lls), included in the ROM bootloader. Th e program -
ming functions are selected by sett ing up the microcontroller’s registers before making a
cal l to a co mmon en try point (0xF FF0). Resul ts are returned in the re gisters. The pur-
pose on this process is to translate the registers values into internal Flash Memory
Management.
• Flash Memory Managem ent
This process manages l ow level access to Flash memory (performs read and write
access).
I SP Com munication
Management
User
Application
Specific Pro tocol
Communication
Management
Flash
Memory
Exernal Hos t with
Flash Memory
User Call
Managem ent (API )
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Bootl oade r Functionality
Introduction
The bootloader can be activated by tw o means: Hardware conditions or regular boot
process.
The Hardwa re co nditi ons ( EA = 1 , PS EN = 0) during t he Re set# fa llin g edge force th e
on-chip bootloader execution. This allows an application to be built that w ill normally
execute the end user’s code but can be manually forced into default ISP operation.
As P SEN is an output port in normal o perating mode (running use r ap plication or boor-
loader code ) after reset, it is recommended to rele ase PSEN after falling edge of reset
signal. The hardware conditio ns a re sampl ed at rese t signal falling edge, thus they can
be released at any time when reset input is low.
To ensure correct microcontroller startup, the PSEN pin should not be tied to ground
during power-on (Se e Figure 38).
Figu re 38. Hardware conditions ty pi cal sequence during power-on.
The on-chip bootload er boot process is shown in Fig ure 39.
VCC
PSEN
RST
Purpose
Hardware Conditions The Hardware Conditions force the bootloader execution whatever BLJB, BSB
and SBV values.
BLJB
T he Boot Lo ad er Jum p Bit f orc e s the app lic a tion ex ec ut io n.
BLJB = 0 => Boot loader execution.
BLJB = 1 => Applica tion execution.
The BLJB is a fuse bit in the Hardware Byte.
That can be modified by hardware (programmer) or by software (API).
Note:
The BLJB test is pe rform by hardware to prevent any program execution.
SBV
The Softw are Boot Vector contains the high address of custumer bootloader
stored in the application.
SBV = FCh (default value) if no custumer bootloader in user Flash.
Note:
The costumer bootloader is ca lled by JMP [SBV]00h instru ction.
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Boot Process
Figu re 39. Bootloader process
RESET
Hardware
Condition?
BLJB!= 0
?
USER AP PLIC ATION
Hardware
Software
FCON = 00h
FC ON = F0h
FCON = 00h
?
Atmel BOOT LOADERUSER BOOT LOADER
yes = hardware boot
F800h
BLJB = 1
BSB = 00h
?
SBV = FCh
?
PC = 0000h
PC= [SBV]0 0h
conditions
BLJB = 0
If BLJB = 0 th en ENBOOT bit (AUXR1) is set
else ENBOOT bit (AUXR1) is cleared
ENBOOT = 1
ENBOOT = 0
Yes (PSEN = 0, EA = 1, and ALE = 1 or not connected)
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ISP Protocol Description
Physical Layer The UAR T used to transmit information has the following configuration:
• Character: 8-bit data
• Parity: none
• Stop: 1 bit
• Flow control: none
• Baud rate: autobaud is performed by the bootloader to compute the baud rate
choosen by the host.
Frame Description The Serial Protocol is based on the Intel Hex-type records.
Intel Hex records consist of ASCII characters used to represent hexadecimal values and
are summa rized below.
Table 70. Intel Hex Type Frame
• Record Mark:
– Record Mark is the start of frame. This field must contain ’:’.
• Reclen:
– Reclen specifies the number of Bytes of inf orm ation or data which follows
the Record Ty pe field of the record .
• Load Offset:
– Load Offset specifies the 16-bit sta rting load off s et of the data Bytes,
therefore this field is used only for
– Data Program Record (see Section “ISP Commands Summary ”).
• Record Type:
– Record Type specifies the command type. This field is used to interpret the
remaining information within the frame. The encoding for all the c urrent
record types is described in Section “ISP Commands Summary”.
• Data/Info:
– Data/I nfo is a variable length field. It consist s of zero or more Bytes encoded
as pairs of hexadecimal digit s. The meaning of dat a depends on the Record
Type.
• Checksum:
– The two’ s complement of t he 8-bit Bytes that result from converting each pair
of ASCII hexadecimal digits to one Byte of binary, and including the Reclen
field to and inc lu ding the last Byte of the Data/Info field. Therefore, the sum
of all t he ASCII pairs in a record after converting to binary, from the Reclen
field to and inc lu ding the Checksum field, is zero.
Record Mark ‘:’ Reclen Load Offset Record Type Data or Info Checksum
1 byte 1 byte 2 bytes 1 by tes n byte 1 byte
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Functional Description
Software Security Bi ts (SSB) The SSB protects any Flash access from ISP comma nd.
The comm and "P rogram Software Security bit" c an onl y write a higher priority level.
There are three levels of security:
• level 0: NO_SECURITY (FFh)
This is the default level.
From level 0, one can write level 1 or l evel 2.
• level 1: WRITE_SECURITY (F Eh )
For this level it is impossible to write in the Flash memo ry, BSB and SBV.
The Bo otloader returns ’P’ on write access.
From level 1, one can write only level 2.
• level 2: RD_WR_SECURITY (F Ch
T he lev e l 2 forbids all read and write access es to/from the Flash/EEPROM memory.
The Bo otloader returns ’L’ on read or wri te access .
Only a full chip erase in parall el mode (using a programmer) or ISP command can reset
the software security bits.
From level 2, one c annot read and write anything.
Table 71. Softwa r e Se cur ity Byte Be ha vior
Level 0 Level 1 Level 2
Flash/EE PROM Any access allowed Read only access allow ed Any access n ot allo wed
Fuse Bit Any access al lowed Read only acce ss allowed Any access n ot allo wed
BSB & SBV Any access allowed Read only access al lowed Any access n ot allo wed
SSB Any access allowed Write level 2 allowed Read only access allowed
Manufacturer
Info Read only access allowed Read only access allowed Read only access allowed
Bootloader Info Read only access allowed Read only access allowed Read only access allowed
Erase Block Allowed Not allowed Not allowed
Full-chip Erase Allowed Allowed Allowed
Blank Check Allowed Allowed Allowed
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Full Chip Erase The IS P comma nd "Full C hip Erase" e rases al l User Flash mem ory (fills with F Fh) and
sets some Bytes used by the bootloader at their default values:
• BSB = FFh
• SBV = FCh
• SSB = FFh and finally erase the Software Secu rity Bits
The Full Chip Erase does not affect the bootloader.
Checksum E rro r When a checksum error is detected send ‘X’ followed with CR&LF.
Flow Description
Overview An initializat ion step must be performed after each Reset. After microcontroller reset,
the bootload er waits for an autobaud sequence ( see section ‘autobaud performance’).
When the communication is initialized the protocol depends on the record type
requested by the host.
FLIP , a so ftware u tility to im plemen t ISP p rogra mming with a P C, is av ailable f rom the
Atme l the web site.
Communication Initialization T he hos t initializes the comm unicat ion by sending a ’U’ character to help the bootloader
to compu te the baudrate (autobaud).
Fi gure 4 0 . Initialization
Host
Bootloader
"U" Performs Auto baud
Init Communication
If (not received "U") "U"
Communication Opened
Else Sends Back ‘U’ Characte
r
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Autobau d Pe rf orm ances The ISP feature allows a wide range of baud rates in the user application. It is also
adapt able to a wide range of oscillator frequencies. This is accompl ished by measuri ng
the b it-tim e of a single bi t in a recei ved cha racter. Thi s inform ation is th en used to pro-
gra m the baud rate in terms of timer counts based on the oscillator frequ ency. The ISP
feature requires that an initial character (an uppercase U) be sent to the
AT89C51RB2/RC2 to establish the baud rate. Table 72 shows the autobaud capabil ity.
Command Data Stream
Protocol A ll command s are sent using the s ame flow. E ach frame sent by th e host is echoed by
the bootload er.
Table 72. Aut obaud Performances
Fre qu enc y (MH z)
Baudrate (bit/s) 1.8432 2 2.4576 3 3.6864 4 5 6 7.3728 8
2400 OK OK OK OK OK OK OK OK OK OK
4800 OK - OKOKOKOKOKOKOKOK
9600 OK - OKOKOKOKOKOKOKOK
19200 OK - OK OK OK - - OK OK OK
38400 - - OK OK - OK OK OK
57600 ----OK---OK
115200 --------OK
Fre qu enc y (MH z)
Baudrate (bit/s) 10 11.0592 12 14.318 14.746 16 20 24 26.6
2400 OK OK OK OK OK OK OK OK OK
4800 OK OK OK OK OK OK OK OK OK
9600 OK OK OK OK OK OK OK OK OK
19200 OKOKOKOKOKOKOKOKOK
38400 - OK OK OK OK OK OK OK OK
57600 - OK - OKOKOKOKOKOK
115200 -OK-OKOK----
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Figu re 41. Command Flow
Wr ite/Prog ram Commands This flow is common to the following frames:
• Flash/EEPROM Programmi ng Data Frame
• EOF or Atmel Frame (only Programming Atmel Frame)
• Config Byte Programm ing Data Frame
• Baud Rate Frame
Description
Figu re 42. Writ e/Program Flow
Bootloader
":"
Sends first character of t he
Frame If (not received ":")
Sends frame (ma de of 2 ASCII Get s frame, and sends back
ec
for each received Byte
Host
Else
":" Sends echo and start
reception
characters per Byte)
Echo analysis
Host Bootloader
Write Command
’X’ & CR & LF
NO_SECURITY
Wait Wr ite Comm an d
Checksum error
Wait Programming
Send Security error
Send COMMAND_OK
Send Write Command
Wait Checksum Error
Wait COMMAND_OK
Wait Security Error
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum error
COMMAND ABORTED
’P’ & CR & LF
OR
’.’ & CR & LF
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Example
HOST : 01 0010 00 55 9A
BOOTLOADER : 01 0010 00 55 9A . CR LF
Programming Data (write 55h at address 0010h in the Flash)
HOST : 02 0000 03 05 01 F5
BOOTLOADER : 02 0000 03 05 01 F5. CR LF
Programming Atmel function (write SSB to level 2)
HOST : 03 0000 03 06 00 55 9F
BOOTLOADER : 03 0000 03 06 00 55 9F . CR LF
Writing Frame (write BSB to 55h)
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Blank Check Command
Description
Figu re 43. Blank Check Flow
Example
Host Bootloader
Blank Check Comman d
’X’ & CR & LF
Flash blank
Wait Blan k Check Comma nd
Send first Address
Send COMMAND_OK
Send Blank Check Command
Wait Checksum Error
Wait Address not
erased
Wait COMMAND_OK
OR
COMMAND ABORTED
COMMAND FINI S HED
Send Checksum error
COMMAND FINISHED
’.’ & CR & LF
OR
address & CR & LF not erased
Checksum error
HOST : 05 0000 04 0000 7FFF 01 78
BOOTLOADER : 05 0000 04 0000 7FFF 01 78 . CR LF
Blank Check ok
BOOTLOADER : 05 0000 04 0000 7FFF 01 70 X CR LF CR LF
Blank Check with checksum error
HOST : 05 0000 04 0000 7FFF 01 70
BOOTLOADER : 05 0000 04 0000 7FFF 01 78 xxxx CR LF
Blank Check ko at address xxxx
HOST : 05 0000 04 0000 7FFF 01 78
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Display Data
Description
Figu re 44. Display Flo w
Note: The maximum size of bl ock is 400h. To read more than 400h Bytes, the Host must send a new command.
Host
Bootloader
Display Command
’X’ & CR & LF
RD_WR_SECURITY
Wait Display Command
Read Data
Send Security Error
Send Display Data
Send Display Command
Wait Checksum Error
Wait D is pla y Data
Wait Security Error
OR
COMMAND ABORTED
COMMAND FINI S HED
Send Checksum Error
COMMAND ABORTED
’L’ & CR & LF
OR
"Address = "
All data read
Complete Frame
"Read ing value"
CR & LF
All data readAll data read
COMMAND FINISHED
Checksum error
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Example
Re ad Func t ion This flow is similar for th e following frames:
• Reading Frame
• EOF Frame/ Atmel Fram e (only reading Atmel Frame)
Description
Figu re 45. Read Flo w
Example
HOST : 05 0000 04 0000 0020 00 D7
BOOTLOADER : 05 0000 04 0000 0020 00 D7
BOOTLOADER 0000=-----data------ CR LF (16 data)
BOOTLOADER 0010=-----data------ CR LF (16 data)
BOOTLOADER 0020=data CR LF ( 1 data)
Display data from address 0000h to 0020h
Host Bootloader
Read Command
’X’ & CR & LF
RD_WR_SECURITY
Wait Read Command
Read Value
Send Security error
Send Data Read
Send Read Command
Wait Checksum Error
Wait Value of Data
Wait Security Error
OR
COMMAND ABORTED
COMMAND FINISHED
Send Checksum error
COMMAND ABORTED
’L’ & CR & LF
OR
’v alue’ & ’.’ & CR & LF
Checksum error
HOST : 02 0000 05 07 02 F0
BOOTLOADER : 02 0000 05 07 02 F0 Value . CR LF
HOST : 02 0000 01 02 00 FB
BOOTLOADER : 02 0000 01 02 00 FB Value . CR LF
Read function (read SBV)
Atmel Read function (read Bootloader version)
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ISP Comm an ds Sum mary Table 73. ISP Commands Summary
Command Command Name Data[0] Data[1] Command Effect
00h Program Data
Program Nb Data Byte.
Bootloader will accept up to 128 (80h)
data Bytes. The data Bytes should be
128 Byte page Flash boundary.
03h Write Function
01h
00h Erase block0 (0000h-1FF Fh)
20h Erase block1 (2000h-3FF Fh)
40h Erase block2 (4000h-7FF Fh)
80h Erase block3 (8000h- BFFFh)
C0h Erase block4 ( C000h- FFFFh)
03h 00h Hardware Reset
04h 00h Erase SBV & BSB
05h 00h Program S SB level 1
01h Program SSB level 2
06h 00h Program BSB (value to write in data[2])
01h Program SBV (value to write in data[2])
07h - Ful l Chi p Er as e (T hi s c omm an d nee ds
about 6 sec to be executed)
0Ah
02h Program Osc fuse (value to write in
data[2])
04h Program BLJB fuse (value to write in
data[2])
08h Program X2 fuse (value to w rite i n
data[2])
04h Display Function
Data[0:1] = start address
Data [2:3] = end address
Data[4] = 00h -> Display data
Data[4] = 01h -> Blank ch eck
Display Data
No te: The ma xim um num b er of da ta
that can be read with a single
command frame (differ ence between
start and end address) is 1kbyte.
Blank Check
05h Read Function
00h
00h Manufacturer ID
01h D ev ic e ID #1
02h D ev ic e ID #2
03h D ev ic e ID #3
07h
00h Read SSB
01h Read BSB
02h Read SBV
06h Rea d Extra B y te
0Bh 00h Read Hardware Byte
0Eh 00h Read Device Boot ID1
01h Read Device Boot ID2
0Fh 00h Read Bootloader Version
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API Call Description Sev eral Applica tion Program Interface (API) calls are available for use by an application
program to permit selective erasing and programming of Flash pages. All calls are made
through a common interface, PGM_MTP. The programming functions are selected by
se tting up the m icro con trol ler’s re gisters befor e mak ing a call to PG M_MT P at F FF0 h.
Results are returned in the registers.
When several Bytes have to be programmed, it is highly recommended to use the Atmel
API “P ROGRAM DATA PAGE” call. Indeed, this API call writes up to 128 By tes in a sin-
gle command.
All routines for software access are provided in the C Flash driver available at Atmel’s
web site.
The API calls description and arguments are shown in Table 74.
Tab le 74. API Call Summary
Command R1 A DPTR0 DPTR1 Returned Value Command Effect
READ MANUF ID 00h XXh 0000h XXh ACC = Manufacturer
Id Read Manufactu rer identif ier
READ DEVICE ID1 00h XXh 0001h XXh ACC = Device Id 1 Read Device identifier 1
READ DEVICE ID2 00h XXh 0002h XXh ACC = Device Id 2 Read Devic e identifier 2
READ DEVICE ID3 00h XXh 0003h XXh ACC = Device Id 3 Read Devic e identifier 3
ER ASE BLOCK 0 1h XXh
DPH = 00h
00h ACC = DPH
Er ase block 0
DPH = 20h Erase block 1
DPH = 40h Erase block 2
PROGRAM DATA
BYTE 0 2h Vaue to writ e Ad dress of
by te to
program XXh ACC = 0: DONE Program up on e data byte i n the on-c hip
flash memory.
PROGRAM SSB 05h XXh
DPH = 00h
DPL = 00h
00h ACC = SSB value
S et SSB level 1
DPH = 00h
DPL = 01h S et SSB level 2
DPH = 00h
DPL = 10h S et SSB level 0
DPH = 00h
DPL = 11h Set SSB leve l 1
PROGRAM BSB 06h New BSB
value 0000 h XXh none Program bo ot status byt e
PROGRAM SBV 06h New SBV
value 0 001h XXh no ne Pr o gr a m soft ware bo ot ve ct or
READ SSB 07h XXh 0000h XXh ACC = SSB Read Software Security Byte
READ BSB 07h XXh 0001h XXh ACC = BSB Read Boot Sta tus Byte
READ SBV 07h XXh 0002h XXh ACC = SBV Read Software Boot Vector
PROGRAM DATA
PAGE 09h Number of
byte to
program
Addres s of
the first byte
to program in
the Flash
memory
Address in
XRAM of the
first data to
program
ACC = 0: DONE
Program up to 128 bytes in user Flash.
Remark: number of bytes to program is
li mit e d suc h as the Fl as h wri te r ema ins i n a
single 128 bytes page. Hence, when ACC
is 128, valid values of DPL are 00h, or , 80h.
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PROGRAM X2 FUSE 0Ah Fuse value
00h or 01h 0008h XXh none Program X2 fuse bit with ACC
PROGRAM BLJB
FUSE 0Ah Fuse value
00h or 01h 0004h XXh none Program BLJB fuse bit with ACC
READ HSB 0Bh XXh XXXXh XXh ACC = HSB Read Hardware Byte
READ BOOT ID1 0Eh XXh DPL = 00h XXh ACC = ID1 Read boot ID1
READ BOOT ID2 0Eh XXh DPL = 01h XXh ACC = ID2 Read boot ID2
READ BOOT VERSION 0Fh XXh XXXXh XXh ACC = Boot_Version Read bootloader version
Tab le 74. AP I Call Summary (Continued)
Command R1 A DPTR0 DPTR1 Returned Value Command Effect
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Electrical Characteristics
Ab solu te Maximum Rati ngs
DC Parameters for
Standard Voltage
C = commercial......................................................0°C to 70°C
I = industrial .. ..... ..... ........................ ..... ..... ..... .....-40°C to 85°C
Sto rage Tem p e ra t ur e....... ... ..... .. ..... .. ..... ... .... -6 5°C to + 150°C
Voltage on VCC to VSS (st andard voltage).........-0.5V to + 6.5V
Voltage on VCC to VSS (low voltage)..................-0.5V to + 4.5V
Voltage on Any Pin to VSS..........................-0.5V to VCC + 0. 5V
Power Dissipation.............................................................. 1 W
Note: Stresses at or above those listed under “Absolute
Maximu m Ratings” may cause perman ent damage
to the device. This is a stress rating only and func-
tional operat ion of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions may
affect device reliability.
Power dissipation value is based on the maximum
allowable die temperature and the thermal resis-
tance of t he package.
TA = -40°C to +85°C; VSS = 0V;
VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)
VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only)
Symbol Parameter Min Typ Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.2 VCC - 0.1 V
VIH Input High Voltage except RST, XTAL1 0.2 VCC + 0.9 VCC + 0.5 V
VIH1(9) Input High Voltage RST, XT AL 1 0.7 VCC VCC + 0.5 V
VOL Outpu t Low Volt ag e, por ts 1, 2, 3, 4 (6)
0.3
0.45
1.0
V
V
V
VC C = 4.5V to 5.5V
IOL = 100 μA(4)
IOL = 1.6 mA(4)
IOL = 3.5 mA(4)
0.45 V VCC = 2.7V to 5.5V
IOL = 0.8 mA(4)
VOL1 Output Low Voltage, port 0, ALE, PSEN (6)
0.3
0.45
1.0
V
V
V
VC C = 4.5V to 5.5V
IOL = 200 μA(4)
IOL = 3.2 mA(4)
IOL = 7.0 mA(4)
0.45 V VCC = 2.7V to 5.5V
IOL = 1.6 mA(4)
VOH Output High Voltage, ports 1, 2, 3, 4
VCC - 0.3
VCC - 0.7
VCC - 1.5
V
V
V
VCC = 5 V ± 10%
IOH = -10 μA
IOH = -30 μA
IOH = -60 μA
0.9 VCC VVCC = 2.7V to 5.5V
IOH = -10 μA
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Notes: 1. Operating I CC is measured with all output pins disconnected; XTAL1 driven with T CLCH, TCHCL = 5 ns (see Figure 49.) , VIL =
VSS + 0.5V,
VIH = V CC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure
46).
2. Idle ICC is measured wi th all out put pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, V IL = VSS + 0.5V, VIH = VCC -
0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 47).
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Fig-
ure 48).
4. Capa citance loading on Ports 0 and 2 may cause spur ious noise pulses to b e superimpose d on the VOLs of ALE and Port s 1
and 3. The noise is due to external bus capac it ance disc harging into t he Port 0 and Port 2 pins when these p ins make 1 to 0
transi tions duri ng bu s operation. In the worst cases (capacitive lo ading 100pF), the noise puls e on the AL E li ne may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typical are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
6. Under steady state (non-transi ent) conditions, IOL must be externally limited as fol lows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit po rt :
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, V OL may exceed t he related specificat ion. Pins are not guaranteed to sink current greater
than the listed test conditi ons.
7. For other values, please contact your sal es office.
8. Icc Flash W rite operat ion current while an on-chip flash page write is on going.
9. Flash Retenti on is guaranteed with the sa me formula for VCC Min down to 0.
VOH1 Output High Voltage, port 0 , ALE, PS EN
VCC - 0.3
VCC - 0.7
VCC - 1.5
V
V
V
VCC = 5 V ± 10%
IOH = -200 μA
IOH = -3.2 mA
IOH = -7.0 mA
0.9 VCC VVCC = 2.7V to 5.5V
IOH = -10 μA
RRST R ST Pulldown R esistor 50 200(5) 250 kΩ
IIL L ogical 0 Input Current ports 1, 2, 3, 4 and 5 -50 μAV
IN = 0.45V
ILI Input Leakage Current for P0 only ±10 μA 0.45V < VIN < VCC
ITL L ogical 1 to 0 Tra nsition Current, port s 1, 2, 3, 4 -650 μAV
IN = 2.0V
CIO Capacitance of I/O Buffer 10 pF Fc = 3 MHz
TA = 25°C
IPD Power Down Current 100 150 μA4.5V < V
CC < 5.5V(3)
ICCOP P ower Supply Current on normal mode 0.4 x Frequency (MHz) + 5 mA VCC = 5.5V(1)
ICCIDLE Pow er Supply Current on idle mode 0.3 x Frequency (MHz) + 5 mA VCC = 5.5V(1)
ICCProg Power S upply Current dur ing flash W rite / Er ase 0.4 x
Frequency
(MHz) + 20 mA VCC = 5.5V(8)
TA = -40°C to +85°C; VSS = 0V;
VCC =2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)
VCC =4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued)
Symbol Parameter Min Typ Max Unit Test Conditions
109
AT89C51RB2/RC2
4180E–8051–10/06
DC Parameters for Low
Voltage
TA = 0°C to +70°C; VSS = 0V; VCC = 2.7 V to 3.6V; F = 0to 40 MHz
TA = -4 0°C to +85°C; VSS = 0V; VCC = 2.7V to 3.6V; F = 0 to 40 MHz
Notes: 1. Operating I CC is measured with all output pins disconnected; XTAL1 driven with T CLCH, TCHCL = 5 ns (see Figure 49.) , VIL =
VSS + 0.5V,
VIH = V CC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure
46).
2. Idle ICC is measured wi th all out put pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, V IL = VSS + 0.5V, VIH = VCC -
0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 47).
3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Fig-
ure 48).
4. Capa citance loading on Ports 0 and 2 may cause spur ious noise pulses to b e superimpose d on the VOLs of ALE and Port s 1
and 3. The noise is due to external bus capac it ance disc harging into t he Port 0 and Port 2 pins when these p ins make 1 to 0
transi tions duri ng bu s operation. In the worst cases (capacitive lo ading 100pF), the noise puls e on the AL E li ne may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typical are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
6. Under steady state (non-transi ent) conditions, IOL must be externally limited as fol lows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit po rt :
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
Symbol Parameter Min Typ Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.2 VCC - 0.1 V
VIH Input High Voltage except RST, XTAL1 0.2 VCC + 0.9 VCC + 0.5 V
VIH1 Input High Voltage, RST, XTAL1 0.7 VCC VCC + 0.5 V
VOL Output Low Vol tage, port s 1, 2, 3, 4(6) 0.45 V IOL = 0.8 mA(4)
VOL1 Output Low Voltage, port 0, ALE, PSEN (6) 0.45 V IOL = 1.6 mA(4)
VOH Output Hig h Volt ag e, por ts 1, 2, 3, 4 0.9 VCC VI
OH = -10 μA
VOH1 Output High Voltage, port 0, ALE, PSEN 0.9 VCC VI
OH = -40 μA
IIL Logical 0 Input Current ports 1, 2, 3, 4 -50 μAV
IN = 0.45 V
ILI Input Leakage Current for P0 only ±10 μA 0.45V < VIN < VCC
ITL Logical 1 to 0 Transition Current, ports 1, 2, 3, -650 μAV
IN = 2.0V
RRST RST Pulld own Resistor 50 200 (5) 250 kΩ
CIO Capacitance of I/O Buffer 10 pF Fc = 3 MHz
TA = 25°C
IPD Power Down Current 10 (5) 50 μAVCC = 2.7V to
3.6V(3)
ICCOP Power Supply Cur rent on normal mode 0.4 x Frequency (MHz) + 5 mA VCC = 3.6 V(1)
ICCIDLE Power Supply C urrent on idle mode 0.3 x Frequency (MHz) + 5 mA VCC = 3.6 V(2)
ICCProg Power Supply Current during flash Write / Erase
0.4 x
Frequency
(MHz) +
20
mA VCC = 5.5V(8)
110
AT89C51RB2/RC2
4180E–8051–10/06
If IOL exceeds the test condition, V OL may exceed t he related specificat ion. Pins are not guaranteed to sink current greater
than the listed test conditi ons.
7. For other values, please contact your sal es office.
8. Icc Flash W rite operat ion current while an on-chip flash page write is on going.
Fi gure 4 6 . ICC Test Condition, Active Mode
Fi gure 4 7 . ICC Test Condition, Idle Mode
Fi gure 4 8 . ICC Test Condition, Power-down Mode
Fi gure 4 9 . Clock Signal Waveform for ICC Tests in Active and Idle Modes
EA
VCC
V
CC
ICC
(NC)
CLOCK
SIGNAL
VCC
All othe r pins a re disconnected.
RST
XTAL2
XTAL1
VSS
VCC
P0
RST EA
XTAL2
XTAL1
VSS
VCC
V
CC
ICC
(NC)
P0
VCC
All othe r pins are disconnected.
CLOCK
SIGNAL
RST EA
XTAL2
XTAL1
VSS
VCC
V
CC
ICC
(NC)
P0
VCC
All othe r pins a re disconnected.
VCC-0.5V
0.45V 0.7VCC
0.2VCC-0.1
TCLCH
TCHCL
TCLCH = TCHCL = 5ns .
111
AT89C51RB2/RC2
4180E–8051–10/06
AC Parameters
Explanation of the AC
Symbols Each timing symbol has 5 characters . The f irst c harac ter is always a “T” (stands for
time). The other characters, depending on their positions, stand f or the name of a signal
or the logical status of that signal. The following is a list of all the characters and what
they stand for.
Example:TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
(Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capa citance for all other
outputs = 80 pF.)
Table 75 Table 78, and Table 80 give the description of each AC symbols.
Table 77, Table 79 and Table 81 give the AC paramete rfor each range.
Table 76, Table 77 and Table 82 gives the frequency derating formula of the AC param-
ete r for ea ch speed ra nge de scription. T o calculate eac h AC sym bols, take the x value
in the correponding column (-M or -L) and use this value in the formula.
Example: TLLIU for -M and 20 MHz, Standard c lock.
x = 35 ns
T 50 ns
TCCIV = 4T - x = 165 ns
Ext ernal Prog ram Mem o ry
Characteristics Tabl e 75. Symbol Description
Symbol Parameter
T Oscillator clock period
TLHLL ALE pulse width
TAVLL Address Valid to ALE
TLLAX Ad dress Hold af ter ALE
TLLIV ALE to Valid Instruction In
TLLPL ALE to PSEN
TPLPH PSEN Pulse Width
TPLIV PSEN to Vali d Inst ru c tio n In
TPXIX In put Instruction Hold after PSEN
TPXIZ Input Instruction Float after PSEN
TAVIV Address to Valid Instruction In
TPLAZ PSEN Low to Address Float
112
AT89C51RB2/RC2
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Table 76. AC Parameters for a Fi x C l o c k
Table 77. AC Param eters for a Variable Clock
Symbol -M -L Units
Min Max Min Max
T25 25 ns
TLHLL 35 35 ns
TAVLL 55ns
TLLAX 55ns
TLLIV n 65 65 ns
TLLPL 55ns
TPLPH 50 50 ns
TPLIV 30 30 ns
TPXIX 00ns
TPXIZ 10 10 ns
TAVIV 80 80 ns
TPLAZ 10 10 ns
Symbol Type Standard
Clock X2 Clock X Parameter for -
M Ran g e X Parameter for
-L Range Units
TLHLL Min 2 T - x T - x 15 15 ns
TAVLL Min T - x 0.5 T - x 20 20 ns
TLLAX M in T - x 0.5 T - x 20 20 ns
TLLIV Max 4 T - x 2 T - x 35 35 ns
TLLPL Min T - x 0.5 T - x 1 5 15 ns
TPLPH Min 3 T - x 1.5 T - x 25 25 ns
TPLIV Max 3 T - x 1.5 T - x 45 45 ns
TPXIX Min x x 0 0 ns
TPXIZ Max T - x 0.5 T - x 15 15 ns
TAVIV Max 5 T - x 2.5 T - x 45 45 ns
TPLAZ Max x x 10 10 ns
113
AT89C51RB2/RC2
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Ext ernal Prog ram Mem o ry
Read Cycle
Exte rnal Data M e mory
Characteristic s Table 78. Symbol Description
TPLIV
TPLAZ
ALE
PSEN
PORT 0
PORT 2
A0-A7A0-A7 INSTR ININSTR IN INSTR IN
ADDRESS
OR SFR-P2 ADDRESS A8-A15ADDRESS A8-A15
12 TCLCL
TAVIV
TLHLL
TAVLL
TLLIV
TLLPL
TPLPH
TPXAV
TPXIX
TPXIZ
TLLAX
Symbol Parameter
TRLRH RD Pulse Width
TWLWH WR Pulse Width
TRLDV RD to Valid Data In
TRHDX Data Hold After R D
TRHDZ Data Float After RD
TLLDV ALE to Valid Data In
TAVDV Address to Valid Data In
TLLWL ALE to WR or RD
TAVWL Address to WR or RD
TQVWX Data Valid to WR Tran s iti on
TQVWH Data set-up to WR High
TWHQX Data Hold After WR
TRLAZ RD Low to Ad dress Float
TWHLH RD or WR High to A LE high
114
AT89C51RB2/RC2
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Table 79. AC Parameters for a Fi x C l o c k
Symbol
-M -L
UnitsMin Max Min Max
TRLRH 125 125 ns
TWLWH 125 125 ns
TRLDV 95 95 ns
TRHDX 00ns
TRHDZ 25 25 ns
TLLDV 155 155 ns
TAVDV 160 160 ns
TLLWL 45 105 45 105 ns
TAVWL 70 70 ns
TQVWX 55ns
TQVWH 155 155 ns
TWHQX 10 10 ns
TRLAZ 00ns
TWHLH 545545ns
115
AT89C51RB2/RC2
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External Data Memo ry Write
Cycle
Symbol Type Standard
Clock X2 Clock X Parameter for -
M Range X Parameter for -
L Range Units
TRLRH Min 6 T - x 3 T - x 25 25 ns
TWLWH Min 6 T - x 3 T - x 25 25 ns
TRLDV Max 5 T - x 2.5 T - x 30 30 ns
TRHDX Min x x 0 0 ns
TRHDZ Max 2 T - x T - x 25 25 ns
TLLDV Max 8 T - x 4T -x 45 45 ns
TAVDV Ma x 9 T - x 4.5 T - x 6 5 65 ns
TLLWL Min 3 T - x 1 .5 T - x 30 30 ns
TLLWL Max 3 T + x 1.5 T + x 30 30 ns
TAVWL Min 4 T - x 2 T - x 30 30 ns
TQVWX Min T - x 0.5 T - x 20 20 ns
TQVWH Min 7 T - x 3.5 T - x 20 20 ns
TWHQX Min T - x 0.5 T - x 15 15 ns
TRLAZ Max x x 0 0 ns
TWHLH Min T - x 0.5 T - x 20 20 ns
TWHLH Max T + x 0.5 T + x 20 20 ns
TQVWH
TLLAX
ALE
PSEN
WR
PORT 0
PORT 2
A0-A7 DATA OUT
ADDRESS
OR SFR-P2
TAVWL
TLLWL
TQVWX
ADDRESS A8-A15 OR SFR P2
TWHQX
TWHLH
TWLWH
116
AT89C51RB2/RC2
4180E–8051–10/06
Externa l Data Mem o ry Read Cycle
Serial Port Timing - Shift
Register Mod e Table 80. Symbol Descr iption
Table 81. AC Parameters for a Fi x C l o c k
Table 82. AC Param eters for a Variable Clock
ALE
PSEN
RD
PORT 0
PORT 2
A0-A7 DATA IN
ADDRESS
OR SFR-P2
TAVWL
TLLWL
TRLAZ
ADDRESS A8-A 15 OR SFR P2
TRHDZ
TWHLH
TRLRH
TLLDV
TRHDX
TLLAX
TAVDV
Symbol Parameter
TXLXL Serial port clock cycle time
TQVHX Output data set-u p to cl ock ris in g edge
TXHQX Output data hold after clock rising edge
TXHDX Input data hold after clock rising edge
TXHDV Clock rising edge to input data v alid
Symbol
-M -L
UnitsMin Max Min Max
TXLXL 300 300 ns
TQVHX 200 200 ns
TXHQX 30 30 ns
TXHDX 00ns
TXHDV 117 117 ns
Symbol Type Standard
Clock X2 Clock X Parameter for -
M Range X Parameter for -L
Range Units
TXLXL Min 12 T 6 T ns
TQVHX Min 10 T - x 5 T - x 50 50 ns
TXHQX Min 2 T - x T - x 20 20 ns
TXHDX Min x x 0 0 ns
TXHDV Max 10 T - x 5 T- x 133 133 ns
117
AT89C51RB2/RC2
4180E–8051–10/06
Shi ft Regis te r Timi ng
Waveforms
Externa l Clock Drive
Waveforms
AC Testing Input/O utput
Waveforms
AC in puts during testin g are driven at VCC - 0.5 fo r a logic “1” and 0.45V for a logic “0”.
Timing m easurem ent are made at VIH min for a logi c “1” and VIL max for a logic “0”.
Float Wavefor ms
For t iming pu rposes a s port pi n is no lon ger float ing whe n a 100 m V chang e from loa d
voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL lev el
occurs. IOL/IOH ≥ ± 20mA.
Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
INPUT DATA VALIDVALID VALID VALID
0123456 87
ALE
CLOCK
OUTPUT DATA
WRI TE to SBUF
CLEAR RI
TXLXL
TQVXH TXHQX
TXHDV TXHDX SET TI
SET RI
INSTRUCTION
01234567
VALID VALID VALID VALID
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1
TCHCL TCLCX TCLCL
TCLCH
TCHCX
INPUT/OUTPUT 0.2 VCC + 0.9
0.2 VCC - 0.1
VCC -0.5V
0.45 V
FLOAT
VOH - 0.1 V
VOL + 0.1 V
VLOAD VLOAD + 0.1 V
VLOAD - 0.1 V
118
AT89C51RB2/RC2
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Figu re 50. Internal Clock Signals
This diagram indicates when signa ls are clocked intern ally. The time it takes the signals to propagate to the pins, ho wever,
ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propaga-
tion al so vari es from outpu t to out put and c om ponen t. Typica lly th ough (TA = 25°C fu lly loade d) RD and WR p ropag ation
delays are approxim ately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC
specifications.
DATA PCL OUT DATA PCL OUT DATA PCL OUT
SAMPLED SAMPLED SAMPLED
STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
FLOAT FLOAT FLOAT
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
INDICATES ADDRESS TRANSITIONS
EXTERNAL PROGRAM MEMORY FETCH
FLOAT
DATA
SAMPLED
DP L O R Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
PCL OUT (IF PROGRA
M
MEMORY IS EXTERNA
L)
OLD DATA NEW DATA P0 PINS SAMPLED
P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED
P0 PIN S SAM PLED
RXD SAMPLED
INTERNAL
CLOCK
XTAL2
ALE
PSEN
P0
P2 (EXT)
READ CYCLE
WRITE CYCLE
RD
P0
P2
WR
PO RT OPERATION
MOV PORT SRC
MOV DEST P0
MOV DEST PORT (P1. P2. P3)
(INCLUDES INTO. INT1. TO T1)
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
DATA OUT
DP L O R Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P0
P2
RXD SAMPL ED
119
AT89C51RB2/RC2
4180E–8051–10/06
Ordering Information
Tab le 83. Pos sible Orde r Entries
Part Number Memory Size Supply Voltage Temperature Range Package Packing Product Marking
AT89C51RB2-3CSIM
16 KBytes
5V Industrial PDIL40 Stick 89C51RB2-IM
AT89C51RB2-SLSCM 5V Commercial PLCC44 Stick 89C51RB2-CM
AT89C51RB2-SLSIM 5V Industrial PLCC44 Stick 89C51RB2-IM
AT89C51RB2-RLTCM 5V Commercial VQFP44 Tray 89C51RB2-CM
AT89C51RB2-RLTIM 5V Industrial VQFP44 Tray 89C51RB2-IM
AT89C51RB2-SLSIL 3V Industrial PLCC44 Stick 89C51RB2-IL
AT89C51RB2-RLTIL 3V Industrial VQFP44 Tray 89C51RB2-IL
AT89C51RC2-3CSCM
32 KBytes
5V Commercial PDIL40 Stick 89C51RC2-CM
AT89C51RC2-3CSIM 5V Industrial PDIL40 Stick 89C51RC2-IM
AT89C51RC2-SLSCM 5V Commercial PLCC44 Stick 89C51RC2-CM
AT89C51RC2-SLSIM 5V Industrial PLCC44 Stick 89C51RC2-IM
AT89C51RC2-RLTCM 5V Commercial VQFP44 Tray 89C51RC2-CM
AT89C51RC2-RLTIM 5V Industrial VQFP44 Tray 89C51RC2-IM
AT89C51RC2-SLSIL 3V Industrial PLCC44 Stick 89C51RC2-IL
AT89C51RC2-RLTIL 3V Industrial VQFP44 Tray 89C51RC2-IL
AT89C51RB2-3CSUM
16 KBytes
5V Ind us tr i al & Green PDI L4 0 St ic k 89C51 R B2 - UM
AT89 C 5 1R B2 - SLSU M 5V Ind us tr i al & Green PL C C44 St ic k 89C51 R B2-U M
AT89C51RB2-RLTUM 5V Industrial & Green VQFP44 Tr ay 89C51RB2-UM
AT 89C51 R B 2 -S LS U L 3V Ind us tr i al & Gre en P L C C44 Stic k 89C5 1R B2-U L
AT89 C 51 R B2 - R LTU L 3V Ind us tr i al & Green VQ FP44 Tr ay 89C 5 1R B2-U L
AT89C51RB2-RLTUM 5V Industrial & Green VQFP44 Tr ay 89C51RB2-UM
AT89C51RC2-3CSUM
32 KBytes
5V Ind us tr i al & Green PDI L4 0 St ic k 89 C51 R C 2- U M
AT89C51RC2-SLSUM 5V Industrial & Gre en PLCC44 St ick 89C51RC2-UM
AT89C51RC2-RLT UM 5V Industrial & Green VQFP44 Tr ay 89C51RC2-UM
AT 89C51RC2-SLS UL 3V Industrial & Gre en PLCC44 Stick 8 9C51RC 2-UL
AT89C51RC2-RLTUL 3V I ndustrial & Green VQFP44 Tr ay 89C51RC2-UL
120
AT89C51RB2/RC2
4180E–8051–10/06
Pac kag e Inf or m at io n
PDIL40
121
AT89C51RB2/RC2
4180E–8051–10/06
VQFP44
122
AT89C51RB2/RC2
4180E–8051–10/06
PLC44
123
AT89C51RB2/RC2
4180E–8051–10/06
Datasheet Change
Log
Changes from 4180A-
08/02 to 4180B-04/03 1. Changed the endurance of Flash to 100, 000 Write/Erase cycles.
2. Added note on Flash retention formula for VIH1, in Section “DC Parameter s for
Standard Voltage”, page 107.
Changes from 4180B-
04/03 to 4180C-12/03 1. Max frequency update for 4.5 to 5.5V range up to 60 MHz (internal code
execution).
Changes from 4180C-
12/03 - 4180D - 06/05 1. Added Green product ordering information. Page 119.
Changes from 4180D -
06/05 to 4180E - 10/06 1. Correction to PDIL40 figure on page 9.
Table of Contents
i
Table of Contents
Features .................................................................................................1
Description ............................................................................................ 1
Block Diagram .......................................................................................3
SFR Mapping .........................................................................................4
Pin Configura tions ..... ......... .......... ......... ............................ ......... ..........9
Port Types ...........................................................................................13
Oscillator .............................................................................................14
Registers ............................................................................................................ 14
Functional B lock Diagram .... .................. . ........................................................... 15
Enhanced Features .............................................................................16
X2 Feature .......................................................................................................... 16
Dual Data Pointer Register (DPTR) ...................................................20
Expanded RAM (XRAM) ......................................................................23
Registers ............................................................................................................ 25
Timer 2 .................................................................................................26
Auto- re load Mode... ............ ................. ............ ............ ........... ................. ........... 26
Programm able Clock-out Mode.......................................................................... 27
Registers ............................................................................................................ 29
Programmable Counter Array (PCA) .................................................31
Registers ............................................................................................................ 33
PCA Captu re Mode............................................................................................ 39
16-bit Software Timer/ Compare Mode .............................................................. 40
High-speed Out put Mode ............................................................... . ................... 41
Pulse Wi dth Modula tor Mode ............................................................................. 42
PCA Watch dog Timer....................................................... . ................................. 42
Serial I/O Port ......................................................................................44
Framing Error Detection..................................................................................... 44
Automatic Address Re cognition......................................................................... 45
ii
xxxxA–8051–10/06
Registers............................................................................................................. 47
Baud Rate Selection for UART for M ode 1 and 3. ................................. ............. 47
UART Registers .................................................................................................. 50
Interrupt System .................................................................................55
Registers............................................................................................................. 56
Interrupt Sources and Vector Addresses............................................................ 63
Keyboard Interface .............................................................................64
Registers............................................................................................................. 65
Serial Port Interface (SP I) ................................................................... 68
Features.............................................................................................................. 68
Signal Description........................ ............ ....... ....... ............ ....... ....... ............ ....... 68
Functional Description........................................................................................ 70
Hardware Watchdog Timer ................................................................ 77
Using th e WDT ................................................................................................... 77
WDT During Po wer - d own and Id l e... ............ ............ ........... ............ ............ ....... 78
ONCE™ Mode (ON Chip Emulation) ..................................................79
Power Management ............................................................................ 80
Reset.................................................................................................................. 80
Reset Recommendation to Prevent Flash Corruption..................... ....... .......... .. 82
Idle Mode............................................................................................................ 82
Power-down Mode.............................................................................................. 82
Power-off Flag .....................................................................................84
Reduced EMI Mode ............................................................................. 85
Flash EEPROM Memory ..................................................................... 86
Features.............................................................................................................. 86
Flash Programm ing and E rasure........................................................................ 86
Flash Registers and Memory Map..................................................................... . 87
Flash Memor y Sta tus............... ................ ............ ............ ................ ............ ....... 90
Memory Organizati on ......................................................................................... 90
Bootloader Architecture................ . ..................................................................... 91
ISP Protocol Description..................................................................................... 95
Functional Description........................................................................................ 96
Flow Des c ription..... ............ ............ ........... ............ ................. ............ ............ .... 97
API Call Description.......................................................................................... 105
Ele ctrical Char acte ris tics ..... ......... ......... .......... ......... ......... .......... ....107
Absolute Maximum Rat ing s . ............ ............ ............ ................ ............ ............ .107
iii xxxxA–8051–10/06
DC Parameters for Standard Voltage...... .. ..... ..... .. ..... .. ..... .. ..... ..... .. ..... .. ..... ..... 107
DC Parame te rs fo r Low Vo ltage.. ............ ............ ............ ................ ............ ..... 109
AC Para mete r s......... ............ ................. ............ ........... ................. ............ ....... 111
Ordering Information ........................................................................ 119
Package Information ........................................................................ 120
PDIL 40. ................. ........... ............ ................. ............ ........... ................. ............ 120
VQF P4 4........ ............ ................. ............ ............ ................ ............ ............ ....... 121
PLC44.............. ............ ............ ........... ................. ............ ............ ........... .......... 122
Datasheet Change Log .....................................................................123
Changes from 4180 A-08 /02 to 4180B-04/0 3.................................................... 123
Changes from 4180 B-04 /03 to 4180C-12/03. ................................... . ............... 123
Changes from 4180 C-12/03 - 4180D - 06/05 ....................... . ........................... 1 23
Changes from 4180 D - 06/05 to 4180E - 10/06................................................ 123
Table of Contents ..................................................................................i
Pr inted o n rec ycled paper.
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