4180E–8051–10/06
Reset Recomme nd ation
to Pr event Flash
Corruption
An example of bad initialization situation may occur in an instance where the bit
ENBOO T in AUXR1 register is initialized from the hardwa re bit BLJB upon res et. Since
this bit allows mapping of the bootloader in the code area, a reset failure can be critical.
If on e w ants th e EN BOO T cle ared i n orde r to u nmap the boo t from the code a rea (yet
due to a bad reset) the bit ENBOOT in SFRs m ay be set. If the value of Program
C ounter i s ac cidentl y in t he ran ge of the b oot m emory addres ses then a Flash acc ess
(write or erase) may corrupt the Flash on-chip memory.
It is recommended to use an ext ernal reset circuitry featuring power supply monitoring to
preve nt system malfunction during periods of ins uffici ent power su pply voltage (pow er
supp ly failure, power supply switched off).
Idle Mode An instruction that sets PCON.0 indic ates that it is the last instruction to be executed
before going into Idle mode. In Idle mode, the internal clock signal is gated off to the
C PU, b ut not t o the i nterr upt, Ti mer, a nd Seri al Po rt func tion s. The CPU status is p re-
served in its entirety: the Stack Pointer, Prog ram Counter, Program Status Word,
Accumulator and all other registers maintain their data during idle. The port pins hold the
logical state s they had at the time Idle was activated. AL E and PSEN hold at logic high
level.
The re are tw o ways to term inate t he Idle mode. A ctivation o f any en abled i nterru pt will
cau se PCON.0 to be cleared by hardware, te rminating the Idle mode . The interrupt will
be s erviced , and fol lowin g RETI th e nex t inst ruction t o be exec uted wi ll be the one fo l-
lowing the instruction that put the device into idle.
The flag bits GF0 and GF1 c an be used to give an indic ation if an interrupt occurred dur-
ing normal operation or during idle. For example, an instruction that activates idle can
also s et one or both f lag bits. When idle is terminat ed by an interrupt , the interrupt ser-
vice routine can exami ne the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycl es ( 24 osci ll ato r p e riod s) to complete the rese t.
Power-down Mode To sav e maximum pow er, a Power-down mo de can be invoked by softw are (se e Table
14, PCON register).
In Po wer-down mode, the os cillato r i s stopp ed a nd the instruc tion tha t invoke d Pow er-
down mode is the last instruction executed. The internal RAM and SFRs retain their
value until the Power-down mode is terminated. VCC can be lowered to save further
powe r. Eith er a ha rdwa re reset or an exte rnal int errupt ca n ca use an e xit fro m Powe r-
down . To p roperly te rminate P ower-do wn, the reset o r extern al interr upt sho uld no t be
executed before VCC is restored to its normal operating level and must be held active
long enough for the oscillat or to res ta rt and stabi lize.
Only external interrupts INT0, INT1 and Keyboard Interrupts are useful to exit from
Power-do wn. F or that, interrupt mus t be enabled and c onfigured as level or edge s ensi-
tive int errupt input. When K ey board Interrupt occurs after a power down mode, 1024
clocks are necessary to exit to power down mode and enter in operating mode.
Holding the p in low restarts the os cillator b ut bringing the pi n high com pl etes the exit as
det ailed in F igure 34. W hen b oth in terrupts are enable d, the osc illator restarts as soon
as one of the two inputs is held low and power down exit will be completed when the f irst
input will be released. In this case, the higher priorit y interrupt service routine is exe-
cuted. Onc e the interrupt is serviced, the next instruction to be executed after RETI will