Rev. 4180E–8051–10/06
Features
•80C52 Compatibl e
– 8051 Pin and I nstruction Compatible
– Four 8-bit I/O Ports
– Three 16-bit Timer/ Counters
– 256 Bytes Scratch Pad RAM
– 9 Interrupt Sources with 4 Priorit y Levels
– Dual Data Pointer
•Variable Lengt h MOVX for Slow RAM/Peripherals
•ISP (In-system Programming) Using Standard VCC Power Suppl y
•Boot ROM Contains Low Level Flash Progr am ming Routi nes and a Default Serial
Loader
•High-speed Architecture
– In Standard Mod e:
40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code executio n on ly)
– In X2 mode (6 Clocks/machine cycle)
20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code executio n on ly)
– 16K /32K Bytes On-chip Flash Program/Data Memory
– Byte and Page (128 Bytes) Erase and Write
– 100K Write Cycles
•On-chip 1024 Bytes Expanded RAM (XRAM)
– Software Selectable Size (0 , 256, 512, 768, 1024 Bytes)
– 256 Bytes Sel ected at Reset for TS87C51RB2/RC2 Comp atibility
•Keyboard Interrupt Interface on Port P1
•SPI Int erface (Master/Sl ave Mode)
•8-bit Clo ck Prescaler
•Improved X2 Mode with Inde pendent Selecti on for CPU and Each Periphe ral
•Programmable Counter Array 5 Channel s
– High-speed Output
– Compare/Capture
– Pulse Width Modulator
– W atchdog Timer Capabilities
•Asynchronous Port Reset
•Full Duplex Enhanced UART
•Dedicated Baud Rat e Generat or fo r UART
•Low EMI (Inhibit ALE)
•Hardware Watchdog Timer (One-time Enabl ed wit h Reset- out)
•Power Contr ol Modes
– Idle Mode
– Power-down Mode
– Power-off Flag
•Power Supply:
– 2.7 to 3.6 (3V Version)
– 2.7 to 5.5V (5V Version)
•Tem perature Ranges : Commercial (0 to +70°C) and Industri al ( -40°C to + 85 °C)
•Packages: PDIL40, PLCC44, VQFP44
Description
The AT89C51RB2/RC2 is a high-performance Flash version of the 80C51 8-bit micro-
controllers. It contains a 16K or 32K Bytes Flash memory block for program and data.
The F lash m em ory c an be p rogram med either in parallel mode or in seria l mo de with
the IS P c apability or wi th software . Th e prog ramm ing voltage i s int ernally gene rate d
from the standard V CC pin.
8-bit
Microcontroller
with 16K/
32K Bytes Flash
AT89C51RB2
AT89C51RC2
2
AT89C51RB2/RC2
4180E–8051–10/06
The AT89C51RB2/RC2 retains all features of the 80C52 with 256 Bytes of internal
RAM, a 9-source 4-level interrupt controller and three timer/coun ters.
In addition, the AT89C51RB2/RC2 has a Programmable Counter Array, an X RAM of
1024 Bytes, a Hardware Watchdog Timer, a Keyboard Interface, an SPI Interface, a
more versatile serial channel that facilitates multiproc essor communication (EUART)
and a speed improvement mechanism (X2 mode).
The Pinout is the standard 40/44 pins of the C52.
The fully static design reduces s ystem power con sumption of the AT89C51RB2/ RC2 by
allowing it to br ing the clock frequency down to any value, even DC, without loss of dat a.
Th e AT 89C5 1RB 2/RC 2 has 2 soft ware -sel ecta ble mo des of redu ced acti vity and 8 -bit
clock pr escaler for further reduc tion in power consumption. In Idle mode, the CPU is fro-
zen while the peripherals and the interrupt s ys tem are still operating. In power-down
mode, the RAM is saved and all other functions are inoperat ive.
The added features of the AT89C51RB2/RC2 make it more powerful for applicat ions
that need pulse width modulation, high sp eed I/O and counting capabilities such as
alarms, motor control , corded phones, and smart card readers.
Table 1. Memory Size
Par t Number Flash (Bytes) XR AM (Byt es) TOTA L RAM
(Bytes) I/O
AT89C51RB2 16K 1024 1280 32
AT89C51RC2 32K 1024 1280 32
AT89C51IC2 32K 1024 1280 32
3
AT89C51RB2/RC2
4180E–8051–10/06
Block Diagram
Figu re 1. Block Diagram
Notes: 1. Alter nate funct ion of Port 1.
2. Alter nate funct ion of Port 3.
Timer 0 INT
RAM
256x8
T0
T1 RxD
TxD
WR
RD
EA
PSEN
ALE/
XTAL2
XTAL1
EUART
CPU
Timer 1
INT1
Ctrl
INT0
(2)
(2)
C51
CORE
(2) (2) (2) (2)
Port 0
P0
Port 1 Port 2 Port 3
Parallel I/O Ports & Ext. Bus
P1
P2
P3
XRAM
1Kx8
IB-bus
PCA
RESET
PROG
Watch
Dog
PCA
ECI
Vss
VCC
(2)(2) (1)(1)
Timer2
T2EX
T2
(1) (1)
Flash
32Kx8 or
16Kx8
Key
Board
ROM
2Kx8
Boot
+
BRG
SPI
MISO
MOSI
SCK
(1)(1) (1)
SS
(1)
4
AT89C51RB2/RC2
4180E–8051–10/06
SFR Mapping The Specia l Function Registers (SFRs) o f the AT89C 51RB2 /RC2 fall into t he follo wing
categories:
• C51 core registers: ACC, B, DPH, DP L, PSW, SP
• I/O port registers: P0, P1, P2, P3
• T i m er registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
• Se rial I/O port registers: SADDR, SADEN, SBUF, SCON
• PCA (Programmable Count er Array) registers: CCON, CCAPMx, CL, CH, CCAPxH,
CCAPxL (x: 0 t o 4)
• Power and clock control regist ers: PCON
• Hardware Watchdog Timer registers: WDTRST, WDTPRG
• Interrupt system registers: IEN0, IPL0, IPH 0, IE N1, IPL1, IPH1
• Keyboard Interface registers: KBE, KBF, KBLS
• S PI r e gisters: SPCON , SPSTR, SPDAT
• BRG (Baud Rate Generator) registers: BRL, BDRCON
• Flash register: FCON
• Clock Prescaler register: CKRL
• Others: A UXR, AUXR1, CKCON0, CKCON1
5
AT89C51RB2/RC2
4180E–8051–10/06
Table 2. C51 Core SFRs
MnemonicAddName 76543210
ACC E0h Accumulator
B F0h B Register
PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P
SP 81h Stac k Pointe r
DPL 82h Data Pointer Low Byte
DPH 83h Data Pointer High Byte
Table 3. System Management SFRs
MnemonicAddName 76543210
PCON 87h Power Control SMOD1 SMOD0 - POF GF1 GF0 PD IDL
AUXR 8Eh Auxiliary Register 0 DPU - M0 XRS2 XRS1 XRS0 EXTRAM A O
AUXR1 A2h Auxiliary Register 1 - - ENBOOT - GF3 0 - DPS
CKRL 97 h Clock Reload Register CKRL7 CKRL6 CKRL5 CKRL4 CKRL3 CKRL2 CKRL1 CKRL0
CKCKON0 8Fh Clock Control Register 0 - WDTX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
CKCKON1AFhClock Control Register 1-------SPIX2
Table 4. Interrupt SFRs
MnemonicAddName 76543210
IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0
IEN1B1hInterrupt Enable Control 1 -----ESPI EI2C KBD
IPH0 B7h Interrupt Priority Control High 0 - PPCH PT2H PHS PT1H PX1H PT0H PX0H
IPL0 B8h Interrupt Priority Control Low 0 - PPCL PT2L PLS PT1L PX1L PT0L PX0L
IPH1B3hInterrupt Priority Control High 1-----SPIHIE2CHKBDH
IPL1B2hInterrupt Priority Control Low 1-----SPILIE2CLKBDL
Table 5. Port SFRs
MnemonicAddName 76543210
P0 80h 8-bit Port 0
P1 90h 8-bit Port 1
P2 A0h 8-bit Port 2
P3 B0h 8-bit Port 3
6
AT89C51RB2/RC2
4180E–8051–10/06
Table 6. Ti mer S FR s
MnemonicAddName 76543210
TCO N 88 h Time r/C o unte r 0 and 1 Co nt r ol T F1 TR1 TF0 TR 0 IE1 IT1 IE0 IT0
T MOD 89h Time r /Coun te r 0 and 1 Mo de s G AT E 1 C/ T1 # M11 M0 1 GATE 0 C/ T0 # M1 0 M0 0
TL0 8Ah Timer/Counter 0 Low Byte
TH0 8Ch Timer/Counter 0 High Byte
TL1 8Bh Timer/Counter 1 Low Byte
TH1 8Dh Timer/Counte r 1 High Byte
WD TRST A6h Watchdog Timer Reset
WDTPRGA7hWatchdog Timer Program -----WTO2WTO1WTO0
T2CON C8h Tim er/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
T2MODC9hTimer/Counter 2 Mode ------T2OEDCEN
RCAP2H CBh T imer/C ounter 2 Re load /Cap ture
High Byte
RCAP2L CAh T im er/Cou nter 2 Re load/C aptur e
Low Byte
TH2 CDh Ti mer/Counte r 2 High Byte
TL2 CCh Timer/Counter 2 Low Byte
Table 7. PCA SFRs
Mnemo-
nic AddName 76543210
CCON D8h PCA Ti mer/Counter Control CF CR - CCF4 CCF3 CCF2 CCF1 CCF0
CMOD D9h PCA Timer/Counter Mode CIDL WDTE - - - CPS1 CPS0 ECF
CL E9h P CA Timer/Counter Low Byte
CH F9h PCA Timer/Counter High Byte
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
DAh
DBh
DCh
DDh
DEh
PCA Timer/Counter Mode 0
PCA Timer/Counter Mode 1
PCA Timer/Counter Mode 2
PCA Timer/Counter Mode 3
PCA Timer/Counter Mode 4
-
ECOM0
ECOM1
ECOM2
ECOM3
ECOM4
CAPP0
CAPP1
CAPP2
CAPP3
CAPP4
CAPN0
CAPN1
CAPN2
CAPN3
CAPN4
MAT0
MAT1
MAT2
MAT3
MAT4
TOG0
TOG1
TOG2
TOG3
TOG4
PWM0
PWM1
PWM2
PWM3
PWM4
ECCF0
ECCF1
ECCF2
ECCF3
ECCF4
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
FAh
FBh
FCh
FDh
FEh
PC A Compare Captu re Module 0 H
PC A Compare Captu re Module 1 H
PC A Compare Captu re Module 2 H
PC A Compare Captu re Module 3 H
PC A Compare Captu re Module 4 H
CCAP0H7
CCAP1H7
CCAP2H7
CCAP3H7
CCAP4H7
CCAP0H6
CCAP1H6
CCAP2H6
CCAP3H6
CCAP4H6
CCAP0H5
CCAP1H5
CCAP2H5
CCAP3H5
CCAP4H5
CCAP0H4
CCAP1H4
CCAP2H4
CCAP3H4
CCAP4H4
CCAP0H3
CCAP1H3
CCAP2H3
CCAP3H3
CCAP4H3
CCAP0H2
CCAP1H2
CCAP2H2
CCAP3H2
CCAP4H2
CCAP0H1
CCAP1H1
CCAP2H1
CCAP3H1
CCAP4H1
CCAP0H0
CCAP1H0
CCAP2H0
CCAP3H0
CCAP4H0
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
EAh
EBh
ECh
EDh
EEh
PCA Compare Capture Module 0 L
PCA Compare Capture Module 1 L
PCA Compare Capture Module 2 L
PCA Compare Capture Module 3 L
PCA Compare Capture Module 4 L
CCAP0L7
CCAP1L7
CCAP2L7
CCAP3L7
CCAP4L7
CCAP0L6
CCAP1L6
CCAP2L6
CCAP3L6
CCAP4L6
CCAP0L5
CCAP1L5
CCAP2L5
CCAP3L5
CCAP4L5
CCAP0L4
CCAP1L4
CCAP2L4
CCAP3L4
CCAP4L4
CCAP0L3
CCAP1L3
CCAP2L3
CCAP3L3
CCAP4L3
CCAP0L2
CCAP1L2
CCAP2L2
CCAP3L2
CCAP4L2
CCAP0L1
CCAP1L1
CCAP2L1
CCAP3L1
CCAP4L1
CCAP0L0
CCAP1L0
CCAP2L0
CCAP3L0
CCAP4L0
7
AT89C51RB2/RC2
4180E–8051–10/06
Table 8. Serial I/O Port SFRs
MnemonicAddName 76543210
SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI
SBUF 99h Serial Data Buffer
SADE N B9h Slave Addre ss Mask
SADDR A9h Slave Addre ss
BDRCON 9Bh Baud Rate Control BRR TBCK RBCK SPD SRC
BRL 9Ah Baud Rate Reload
Table 9. SPI Controller SFRs
MnemonicAddName 76543210
SPCON C3h SPI Control SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPSTA C4h SPI Status SPIF WCOL SSERR MODF ----
SPDAT C5h SPI Data SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0
Table 10. Keyboard Interface SF Rs
MnemonicAddName 76543210
KBLS 9Ch Keyboard Level Selector KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
KBE 9Dh Keyboard Input Enable KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
KBF 9Eh Keyboard Flag Register KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
8
AT89C51RB2/RC2
4180E–8051–10/06
Table 11 shows all SFRs with their address and their res et va lue.
Table 1 1. SFR Mapping
Bit
addressable Non Bit addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h CH
0000 0000 CCAP0H
XXXX CCAP1H
XXXX CCAPL2H
XXXX CCAPL3H
XXXX CCAPL4H
XXXX FFh
F0h B
0000 0000 F7h
E8h CL
0000 0000 CCAP0L
XXXX XXXX CCAP1L
XXXX XXXX CCAPL2L
XXXX XXXX CCAPL3L
XXXX XXXX CCAPL4L
XXXX XXXX EFh
E0h ACC
0000 0000 E7h
D8h CCON
00X0 0000 CMOD
00XX X000 CCAPM0
X000 0000 CCAPM1
X000 0000 CCAPM2
X000 0000 CCAPM3
X000 0000 CCAPM4
X000 0000 DFh
D0h PSW
0000 0000 FCON (1)
XXXX 0000
1. FCON access is reserved for the Flash API and ISP softw are.
Reserved
D7h
C8h T2CON
0000 0000 T2MOD
XXXX XX00 RCAP2L
0000 0000 RCAP2H
0000 0000 TL2
0000 0000 TH2
0000 0000 CFh
C0h SPCON
0001 0100 SPSTA
0000 0000 SPDAT
XXXX XXXX C7h
B8h IPL0
X000 000 SADEN
0000 0000 BFh
B0h P3
1111 1111 IEN1
XXXXX 000 IPL1
XXXXX000 IPH1
XXXX X00 0 IPH0
X000 0000 B7h
A8h IEN0
0000 0000 SADDR
0000 0000 CKCON1
XXXX XXX0 AFh
A0h P2
1111 1111 AUXR1
XXXXX0X0 WDTRST
XXXX XXXX WDTPRG
XXXX X00 0 A7h
98h SCON
0000 0000 SBUF
XXXX XXXX BRL
0000 0000 BDRCON
XXX0 0000 KBLS
0000 0000 KBE
0000 0000 KBF
0000 0000 9Fh
90h P1
1111 1111 CKRL
1111 1111 97h
88h TCON
0000 0000 TMOD
0000 0000 TL0
0000 0000 TL1
0000 0000 TH0
0000 0000 TH1
0000 0000 AUXR
XX0X 0000 CKCON0
0000 0000 8Fh
80h P0
1111 1111 SP
0000 0111 DPL
0000 0000 DPH
0000 0000 PCON
00X1 0000 87h
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
9
AT89C51RB2/RC2
4180E–8051–10/06
Pin C onfigurations
Figu re 2. Pin Confi gurations
P1.7CEX4/MOSI
P1.4/CEX1
RST
P3.0/RxD
P3.1/TxD
P1.3CEX0
1
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
P2.7/A15
P2.5/A13
P2.6/A14
P1.0/T2
P1.2/ECI
P1.1/T2EX/SS VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
PDIL40
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
43 42 41 40 3944 38 37 36 35 34
P1.4/CEX1
P1.0/T2
P1.1/T2EX/SS
P1.3/CEX0
P1.2/ECI
NIC*
VCC
P0.0/AD0
P0.2/AD2
P0.3/AD3
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
NIC*
P2.7/A15
P2.5/A13
P2.6/A14
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
NIC*
1213 17161514 201918 2122
33
32
31
30
29
28
27
26
25
24
23
VQFP44 1.4
1
2
3
4
5
6
7
8
9
10
11
18 19 23222120 262524 27 28
5 4 3 2 1 6 44 43 42 41 40
P1.4/CEX1
P1.0/T2
P1.1/T2EX/SS
P1.3/CEX0
P1.2/ECI
NIC*
VCC
P0.0/AD0
P0.2/AD2
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE/PROG
PSEN
EA
NIC*
P2.7/A15
P2.5/A13
P2.6/A14
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEx4/MOSI
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P0.3/AD3
NIC*
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
PLCC44
*NIC: No Internal Connection
10
AT89C51RB2/RC2
4180E–8051–10/06
Tab le 12. Pin Descr iption for 40 - 44 Pin Packages
Mnemonic
Pin Number
Type Name and FunctionDIL LCC VQFP44 1.4
VSS 20 22 16 I Ground: 0V reference
VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle and power-down
operation
P0.0 - P0.7 39 - 32 43 - 36 37 - 30 I/O Po rt 0: Port 0 is an open-drain, bi -directional I/O port . Port 0 pins that have 1 s
written t o them float and can be used as high impedance inputs. Port 0 mu st be
pola r ize d to V CC or VSS in order to prevent any parasitic current consumption. Port 0
is also the multiplexed low-order address and da ta bus during ac cess to e xtern al
program and dat a memory. In this application, it uses strong internal pull-up when
emitting 1s. Por t 0 also input s the code Bytes duri ng F lash pr ogramming. External
pull-up s are required during program verificati on dur ing which P0 outputs t he code
Bytes.
P1.0 - P1.7 1 - 8 2 - 9 40 - 44
1 - 3 I/O Po r t 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 1 pins that are externally pulled low will source current
because of the internal pull-ups. Port 1 also receives the low-order address Byte
during mem ory programmi ng and verification.
A lter nate func tion s for AT89 C51 RB2 /R C2 Port 1 incl ude:
1 2 40 I/O P1.0: Input/Output
I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout
2 3 41 I/O P1.1: Input/Output
IT2EX: Timer/Counter 2 Reload/Capture/Direction Control
ISS: SPI Slave Se lect
3 4 42 I/O P1.2: Input/Output
IECI: Extern al Clock for th e PCA
4 5 43 I/O P1.3: Input/Output
I/O CEX0: Capture/Compare External I/O for PCA Module 0
5 6 44 I/O P1.4: Input/Output
I/O CEX1: Capture/Compare External I/O for PCA Module 1
6 7 1 I/O P1.5: Input/Output
I/O CEX2: Capture/Compare External I/O for PCA Module 2
I/O MISO: SPI Master Input Slave Output line
When SP I is in mast er mode, MISO receives data from the slave peripheral. When
SPI is in slave mode, MISO output s data to the master controller .
7 8 2 I/O P1.6: Input/Output
I/O CEX3: Capture/Compare External I/O for PCA Module 3
I/O SCK: SPI Ser ial Clock
SCK outputs clock to the slave peripheral
8 9 3 I/O P1.7: Input/Output:
11
AT89C51RB2/RC2
4180E–8051–10/06
I/O CEX4: Capture/Compare External I/O for PCA Module 4
P1.0 - P1.7 I/O MOSI: SPI Master Output Slave Input line
When SPI is in master mode , MOSI outputs data to the slave peripheral. When SPI
is in slave mode, MOSI receives data fr om the master controller.
XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generat or circuits.
XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier
P2.0 - P2.7 21 - 28 24 - 31 18 - 25 I/O Po rt 2 : Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 2 pins that are externally pulled low will source current
because of the internal pull-ups. Port 2 emits the high - order address Byte during
fetches f rom external program memory and during accesses to external da ta
mem ory tha t use 16- bit addresses (MOV X @DPTR). In this app lication, it uses
strong internal pull-ups emitting 1s. During accesses to external data memory that
use 8-bit addresses (MO VX @Ri), port 2 em its the contents of the P2 SFR. S ome
Port 2 pins receive the high order address bits during EPR OM programming a nd
verification:
P2.0 to P2.5 for 16 KB devices
P2.0 to P2.6 for 32KB devices
P3.0 - P3.7 10 - 17 11,
13 - 19 5,
7 - 13 I/O Po rt 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, Port 3 pins that are externally pulled low will source current
because of the internal pull-ups. Port 3 also serves the special features of the
80C51 fam ily, as listed below.
10 11 5 I RXD (P3.0): Seri al inpu t port
11 13 7 O TXD (P3.1): Serial output port
12 14 8 I INT0 (P3.2): Exte rna l in terr up t 0
13 15 9 I INT1 (P3.3): Exte rna l in terr up t 1
14 16 10 I T 0 (P3.4): Timer 0 external input
15 17 11 I T1 (P3.5): Timer 1 external input
16 18 12 O WR (P3.6): External dat a memory write strobe
17 19 13 O RD (P3.7): External data memory read strobe
RST 9 10 4 I/O
Reset: A high on this p in for two machine cycles whil e the oscilla tor is ru nning,
resets the device. An internal diffused resistor to VSS permits a power-on reset u sing
only an external capacitor to VCC. This pin is an outpu t when th e hardware
watchdog forces a system reset.
ALE/PROG 30 33 27 O (I) Add ress Latch Enable/Program Pu lse: Ou tp ut puls e for la tc hin g th e low Byte of
the addres s during an access to external m emory. In normal oper ation, A LE is
emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can
be us ed for external timing or clocking. Note t hat one ALE pulse is s kipped during
each access to external data memory. This pin is also the program pulse input
(PROG) d uri ng Flas h p rogr a mmi ng. ALE can be disa bl ed by s ett in g SF R’ s A UX R. 0
bit. With this bit set, ALE will be inactive during internal fetches.
Tab le 12. Pin Descr iption for 40 - 44 Pin Packages (Continued)
Mnemonic
Pin Number
Type Name and FunctionDIL LCC VQFP44 1.4
12
AT89C51RB2/RC2
4180E–8051–10/06
PSEN 29 32 26 O Program Strobe Enable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is acti vate d tw ic e ea ch
machine cycle, except that two PSEN activ at io ns are sk ip pe d dur i ng ea ch ac ces s t o
external data memory. PSEN is not activated during fetches from internal program
memory.
EA 31 35 29 I External Access Enable: EA must be externally held low to enable the device to
fetch code from external program memory locations 0000H to FFFFH (RD). If
sec urity level 1 is pro grammed, EA will be internally latched on Reset.
Tab le 12. Pin Descr iption for 40 - 44 Pin Packages (Continued)
Mnemonic
Pin Number
Type Name and FunctionDIL LCC VQFP44 1.4
13
AT89C51RB2/RC2
4180E–8051–10/06
Port Types AT 89C51RB 2/RC 2 I/O ports (P1, P2 , P3) implemen t the q uasi- bidirectio nal output th at
is c om mon on th e 80C 51 and mos t o f its d eriva tive s. Th is outp ut ty pe ca n b e used as
both an input an d outpu t w ithout the need to reconfigure the port. This is possible
because when the port outputs a logic high, it is weakly driven, allowing an external
device to pull t he pin low. When the pin i s pull ed low, i t is driven st rongly and able to sink
a fairly large current. These features are somewhat similar to an open drain output
except tha t there are three pull-up transistors in the quasi-bidirectional outpu t that serve
different purpo ses. One o f these pull-ups, c alled the "weak" pull-up, is turned on when-
ever the port latch for the pin contains a logic 1. The weak pull-up sources a very small
current that will pull the pin high if it is left f l oating. A second pull- up, called the "medium"
pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is
also at a logic 1 level. This pu ll-up provides t he primary source current for a quasi-bidi-
rectional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an
externa l device, the m edium pull-u p turns o ff, and only the we ak pull-up rem ains on. In
order to pull the pin low under these cond iti ons, the external device has to sink enou gh
cu rr ent to o verpow er the me dium pull -up and take the v oltage on the po rt pin bel ow its
input threshold.
The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up
low-to-high transit i ons on a quasi-bidirectional port pi n when the port latch changes from
a logic 0 to a lo gic 1. When this oc curs , the strong pull-up t urns on for a brief t ime, two
CPU clocks, in order to pull t he port pin high quickly. Then it turns off again.
The DP U bit (bit 7 in AUX R register) allows to disable the perman ent we ak pull up of all
ports when latch data is logical 0.
The quasi-bid irectional port configuration is shown in Figure 3.
Figu re 3. Quasi-B idire ctional Out put
2 CPU
Input
Pin
Strong Medium
N
Weak
P
Clock Delay
Port Latch
Data
Data
DPU
AUXR.7
PP
14
AT89C51RB2/RC2
4180E–8051–10/06
Oscillator To optim ize th e p ower co nsu mpti on an d ex ecut ion ti me n eede d fo r a speci fic task, a n
internal, pr escaler feature has been implemented between the oscillator and the CPU
and peripherals.
Registers Table 13. CK RL Register
CKRL – Clock Reload Register (97h)
Rese t Value = 1111 1111b
Not bit addressable
Table 14. PCO N Regist er
PCO N – Power Control Register (87h)
Rese t Value = 00X1 0000b Not bit addressable
76543210
CKRL7 CKRL6 CKRL5 CKRL4 CKRL3 CKRL2 CKRL1 CKRL0
Bit Number Mnemonic Description
7:0 CKRL Clo ck Reload Register
Prescaler valu e
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit Number Bit Mnemonic Description
7SMOD1
Serial Port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6SMOD0
Serial Port Mode bit 0
Cl ea red to selec t SM0 bit in SCON re gi ster.
Set to select FE bit in SCON register .
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4POF
Power-off Flag
Cleared to recognize next reset type.
Set by ha rdw ar e when VCC ris es from 0 to it s nomina l vo lt a ge. Can
also be set by software.
3GF1
Gen era l-pu r pos e Fla g
Cleared by software for general-purpose usage.
Set b y sof twa r e fo r ge ner al -pu rp os e usa ge .
2GF0
Gen era l-pu r pos e Fla g
Cleared by software for general-purpose usage.
Set b y sof twa r e fo r ge ner al -pu rp os e usa ge .
1PD
Power-down Mo de bit
Cleared by hardware when reset o ccurs.
Set to enter power-down mode.
0IDL
Idle Mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
15
AT89C51RB2/RC2
4180E–8051–10/06
Fu nct ional Block
Diagram
Figu re 4. Functional Oscillator Block Diagram
Prescaler Divid er • A hardwa re RESET puts the prescaler divider in the following state:
•CKRL = FFh: F
CLK CPU = FCLK PERIPH = FOSC/2 (S tandard C51 feature)
• Any value between FFh down to 00h can be written by software into CKR L register
in order to divide frequency of the sele cted os c illator:
• CKRL = 00h: minimum frequen cy
FCLK CPU = F CLK PERIPH = FOSC/1020 (Standard Mode )
FCLK CPU = F CLK PERIPH = FOSC/510 (X2 Mode)
• CKRL = FF h: maximum freque ncy
FCLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode)
FCLK CPU = FCLK PERIPH = FOSC (X2 Mode)
FCLK CPU and FCLK PERIPH
In X2 Mode, for CKRL<>0xFF:
In X1 Mode, for CKRL<>0xF F then:
Xtal2
Xtal1
Osc
CLK
Idle
CPU clock
CKRL
Reload
8-bit
Prescaler-Divider
Reset
Peripheral Clock
:2
X2
0
1
FOSC
CKCON0
CLK
PERIPH
CPU
CKRL = 0xFF?
0
1
F
CPU F=CLKPERIPH
F
OSC
2 255 CKRL
–
()×
--------------------------------------------
---
=
F
CPU F=CLKPERIPH
F
OSC
4 255 CKRL
–
()×
--------------------------------------------
---
=
16
AT89C51RB2/RC2
4180E–8051–10/06
Enhanced Features I n comp arison to the original 80C52, the AT 89C51RB2/ RC2 implem ents some new fea-
tures, which are:
• X2 option
• Dual Data Pointer
• Extended RAM
• Programmable Counter Array (PCA)
• Hardware Wa tchdog
• SPI interface
• 4-level interrupt prio rity system
• power-off f lag
• ONCE mode
• ALE disabling
• Some enha nced features are also located in the U ART and the timer 2
X2 Feature The AT89C51RB2/RC2 core needs only 6 clock periods per machine cycle. This feature
called ‘X2’ provides the following advantages :
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consum ption by dividing dynam ical ly the operating frequency by 2 in
operating and idle modes.
• Increase CPU power by 2 while keeping same crystal f requency.
In order to keep the original C51 com patibility, a divider by 2 is inserted between the
XT AL1 signal and the m ain clo ck input of t he core (phase gene rator). This divi der may
be disabled by software.
Description The c lo ck for the whole ci rcuit and peri pherals is first divided by 2 bef ore being used by
the CPU core and the peripherals.
This allows any cyclic ratio to be acc epted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 5 shows the clock generation block diagram. X2 bit is validated on the rising edge
of the XTAL1÷2 to avoid g litches whe n swi tchin g from X 2 to X1 mod e. Figure 6 show s
the switching mode waveforms.
Fi gure 5 . Clock Generation Diagram
XTAL1 2
CKCON0
X2
8 bit Prescaler
FOSC
FXTAL 0
1
XTAL1:2 FCLK CPU
FCL K PE RIPH
CKRL
17
AT89C51RB2/RC2
4180E–8051–10/06
Figu re 6. Mode Switching Waveforms
The X2 bit in the CKCON0 register (see Table 15) allows a switch from 12 clock periods
per instruc tion to 6 clo ck periods and vice versa. A t res et, the s pe ed is set ac cording t o
X2 bit of Hardware Security B yte (HSB). By default, Standard mode is act ive. Setting the
X2 bit activates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, UARTX2, PCAX2, and WDX2 bits in the CKCON0 register
(Table 15) and SPIX2 bit in the CKCON1 register (see Table 16) allow a switch from
sta ndard peri phera l s peed ( 12 clo ck p eriod s per p eriph eral clock cyc le) to fa st pe riph-
eral speed (6 clock periods p er peripheral clock cycle). These bits are active only in X2
mode.
XTAL1:2
XTAL1
CPU Clock
X2 Bit
X2 Modex1 Mode X1 Mode
FOSC
18
AT89C51RB2/RC2
4180E–8051–10/06
Table 15. CKC ON0 Register
CKCON0 - Clock Contro l Register (8Fh)
Rese t Value = 0000 000’HSB. X2’b (see Table 65 “Hardware Security Byte”)
Not bit addressable
76543210
- WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
Bit
Number Bit
Mnemonic Description
7 Reserved
6WDX2
Watchdog Cloc k
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, this bi t
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock per iods per peri pheral clock cycle.
5PCAX2
Programmable Counter Array Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, this bi t
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
4SIX2
Enhanced UART Clock (Mode 0 and 2)
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, this bi t
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
3T2X2
Timer 2 Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, this bi t
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock per iods per peri pheral clock cycle.
2T1X2
Timer 1 Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, this bi t
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
1T0X2
Timer0 Clock
(T h is con t rol bi t is vali da te d when the C PU clock X 2 i s s et; whe n X 2 is lo w, this bi t
has no effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
period s per pe ripheral clo c k cycle.
0X2
CPU Clock
Cleared to select 12 clock periods per machine cycle (STD, X1 mode) for CPU
and all the peripherals. Set to select 6 clock periods per machine cycle (X2
m ode) and to enable the individual peripher als’X2’ bits. Program m ed by
hardware after Power-up regarding Hardware Security Byte (HSB), Default
setting, X2 is cleared.
19
AT89C51RB2/RC2
4180E–8051–10/06
Table 16. CKC ON1 Register
CKCON1 - Clock Contro l Register (AFh)
Reset Value = XXXX XXX0b
Not bit addressable
76543210
-------SPIX2
Bit
Number Bit
Mnemonic Description
7-Reserved
6-Reserved
5-Reserved
4-Reserved
3-Reserved
2-Reserved
1-Reserved
0SPIX2
SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low,
this bit has no effect).
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock per iods per peri pheral clock cycle.
20
AT89C51RB2/RC2
4180E–8051–10/06
Dual Data Pointer
Register (DPTR) The ad dit ional data po int er can b e u sed to spe ed up c ode execut ion and red uce cod e
size.
T he du al D PT R st ru c tur e is a way by w hic h the c hip will s p ec ify the addre ss of an ext er -
nal data memor y l ocation. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = A UXR1.0 (see Table 17) that allows t he program
code to swi tch between them (see Figure 7).
Figu re 7. Use of Dual P ointer
Exte rna l Data Memory
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
07
DPTR0
DPTR1
21
AT89C51RB2/RC2
4180E–8051–10/06
Table 17. AUXR1 regist er
AUXR 1- Auxiliary Register 1(0A2h)
Reset Value = XXXX XX0X0b
Not bit addressable
Note: 1. Bit 2 stuck at 0; this allo ws using INC AUXR1 to toggle DPS withou t changing GF3.
ASSEM BLY LAN GUA GE
; Block move usin g dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DP S exits op posite of entry st ate
; unless an extra I NC AUXR1 i s added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,# SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DES T ; addre ss of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a Byte from SOURCE
000B A3 INC DPTR ; incr ement SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the Byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ L OOP ; ch eck for 0 terminator
0012 05A2 INC AU XR 1 ; (op tional) restore DPS
76543210
- - ENBOOT - GF3 0 - DPS
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 ENBOOT Enab le Boot Fla sh
Cle ared t o disa ble boot ROM .
Set to map the boot ROM between F800h - 0FFFFh.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3GF3This bit is a general-purpose user flag.(1)
20Always Cleared
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0DPS
Data Pointer Sel ec tion
Cleared to select DPTR0.
Set to select DPTR1.