M MCP6291/2/3/4 1.0 mA, 10 MHz Bandwidth, Rail-to-Rail Op Amp Features Description * * * * * * * The Microchip Technology Inc. MCP6291/2/3/4 family of operational amplifiers (op amps) provide wide bandwidth for the current. This family has a 10 MHz gain bandwidth product and 65 phase margin. This family also operates from a single supply voltage as low as 2.4V, while drawing 1 mA (typ.) quiescent current. In addition, the MCP6291/2/3/4 supports railto-rail input and output swing, with a common mode input voltage range of VDD + 300 mV to VSS - 300 mV. This family of operational amplifiers is designed with Microchip's advanced CMOS process. Gain Bandwidth Product: 10 MHz (typ.) Supply Current: IQ = 1.0 mA Supply Voltage: 2.4V to 5.5V Rail-to-Rail Input/Output Extended Temperature Range: -40C to +125C Available in Single, Dual and Quad Packages Single with Chip Select (CS) (MCP6293) Applications * * * * * * Automotive Portable Equipment Photodiode Pre-amps Analog Filters Notebooks and PDAs Battery-Powered Systems The MCP6291/2/3/4 family operates in the Extended Temperature Range of -40C to +125C. It also has a power supply range of 2.4V to 5.5V. Package Types MCP6291 Available Tools PDIP, SOIC, MSOP * SPICE Macro Model (at www.microchip.com) * FilterLab(R) Software (at www.microchip.com) NC 1 VIN R1 C1 + VSS 4 R2 R3 2 VIN+ 3 Typical Application VIN _ 8 NC R4 VOUT C3 VDD/2 Multiple Feedback Lowpass Filter 2003 Microchip Technology Inc. _ VINA 2 6 VOUT VINA + 3 5 NC NC 1 VIN _ 2 VSS 4 7 VOUTB +B - 6 VINB _ 5 VINB+ MCP6294 8 CS + 8 VDD A - + VSS 4 MCP6293 VIN + 3 MCP6291 PDIP, SOIC, MSOP VOUTA 1 7 VDD PDIP, SOIC, MSOP C4 MCP6292 PDIP, SOIC, TSSOP VOUTA 1 _ 7 VDD VINA 6 VOUT VINA+ 3 5 NC 2 VDD 4 VINB+ 5 VINB _ 6 VOUTB 7 14 VOUTD A D 13 VIND_ -+ + 12 VIND+ 11 VSS 10 VINC+ -+ +- 9 V _ INC B C 8 VOUTC DS21812B-page 1 MCP6291/2/3/4 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings VDD - VSS .........................................................................7.0V All Inputs and Outputs ...................... VSS -0.3V to V DD +0.3V Difference Input Voltage ....................................... |VDD - VSS| Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. PIN FUNCTION TABLE Output Short Circuit Current ..................................continuous Name Current at Input Pins ....................................................2 mA Current at Output and Supply Pins ............................30 mA Storage Temperature ....................................-65C to +150C Junction Temperature (TJ) ..........................................+150C ESD Protection On All Pins (HBM/MM) ................ 4 kV/200V Function VIN +, VINA+, VINB+, VINC+, VIND+ Non-inverting Inputs VIN _, VINA_, VINB_, VINC_, VIND _ Inverting Inputs VDD Positive Power Supply VSS Negative Power Supply VOUT, VOUTA, VOUTB, VOUTC , VOUTD Outputs NC No Internal Connection CS Chip Select DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD /2, RL = 10 k to VDD /2, and VOUT VDD/2. Parameters Sym Min Typ Max Units Conditions Input Offset Voltage VOS -3.0 -- +3.0 mV VCM = VSS Input Offset Voltage (Extended Temperature) VOS -5.0 -- +5.0 mV TA = -40C to +125C, VCM = VSS, VDD = 3.0V to 5.5V VOS/TA -- 1.7 -- V/C PSRR 70 90 -- dB Input Offset Input Offset Temperature Drift Power Supply Rejection TA = -40C to +125C, VDD =3.0V to 5.5V VCM = VSS Input Bias, Input Offset Current and Impedance IB -- 1.0 -- pA Overtemperature IB -- 50 200 pA TA = +85C Overtemperature IB -- 2 5 nA TA = +125C, VDD = 3.0V to 5.5V Input Offset Current IOS -- 1.0 -- pA Common Mode Input Impedance ZCM -- 1013||6 -- ||pF Differential Input Impedance ZDIFF -- 1013||3 -- ||pF Common Mode Input Range V CMR VSS-0.3 -- VDD+0.3 V Common Mode Rejection Ratio CMRR 70 85 -- dB VCM = -0.3V to 2.5V, VDD = 5V Common Mode Rejection Ratio CMRR 65 80 -- dB VCM = -0.3V to 5.3V, VDD = 5V AOL 90 110 -- dB VOUT = 0.2V to VDD - 0.2V, VCM = VSS VOL, VOH VSS+15 -- VDD -15 mV ISC -- 25 -- mA VDD 2.4 -- 5.5 V VDD 3.0 -- 5.5 V IQ 0.7 1.0 1.3 mA Input Bias Current Common Mode Open-Loop Gain DC Open-Loop Gain (large signal) Output Maximum Output Voltage Swing Output Short-Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier DS21812B-page 2 TA = -40C to +85C TA = +86C to +125C IO = 0 2003 Microchip Technology Inc. MCP6291/2/3/4 AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, R L = 10 k to VDD/2, and CL = 60 pF. Parameters Sym Min Typ Max Units GBWP -- 10.0 -- MHz Conditions AC Response Gain Bandwidth Product Phase Margin at Unity-Gain PM -- 65 -- Slew Rate SR -- 7 -- V/s Input Noise Voltage Eni -- 3.5 -- Vp-p Input Noise Voltage Density eni -- 8.7 -- nV/Hz f = 10 kHz Input Noise Current Density ini -- 3 -- fA/Hz f = 1 kHz Noise f = 0.1 Hz to 10 Hz TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +2.4V to +5.5V, and VSS = GND. Parameters Sym Min Typ Max Units Operating Temperature Range TA -40 -- +125 C Storage Temperature Range TA -65 -- +150 C Thermal Resistance, 8L-PDIP JA -- 85 -- C/W Thermal Resistance, 8L-SOIC JA -- 163 -- C/W Thermal Resistance, 8L-MSOP JA -- 206 -- C/W Thermal Resistance, 14L-PDIP JA -- 70 -- C/W Thermal Resistance, 14L-SOIC JA -- 120 -- C/W Thermal Resistance, 14L-TSSOP JA -- 100 -- C/W Conditions Temperature Ranges (Note) Thermal Package Resistances Note: The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150C. 2003 Microchip Technology Inc. DS21812B-page 3 MCP6291/2/3/4 MCP6293 CHIP SELECT (CS) SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, R L = 10 k to VDD/2, and CL = 60 pF. Parameters Sym Min Typ Max Units Conditions CS Logic Threshold, Low VIL VSS -- 0.2 VDD V CS Input Current, Low ICSL -- 0.01 -- A CS Logic Threshold, High VIH 0.8 V DD -- VDD V CS Input Current, High ICSH -- 0.7 2 A CS = VDD CS Input High, GND Current IQ -- -0.7 -- A CS = VDD Amplifier Output Leakage, CS High -- -- 0.01 -- A CS = VDD CS Low to Valid Amplifier Output, Turn-on Time tON -- 4 10 s CS Low 0.2 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.9 V DD/2, VDD = 5.0V CS High to Amplifier Output High-Z tOFF -- 0.01 -- s CS High 0.8 VDD, G = +1 V/V, VIN = VDD/2, VOUT = 0.1 V DD/2 VHYST -- 0.6 -- V VDD = 5V CS Low Specifications CS = VSS CS High Specifications Dynamic Specifications Hysteresis DS21812B-page 4 2003 Microchip Technology Inc. MCP6291/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 25% Percentage of Occurrences 840 Samples VCM = VSS TA = -40C to +125C 20% 15% 10% 5% Input Offset Voltage (mV) FIGURE 2-4: Voltage Drift. 30% 80 90 100 Input Offset Voltage (V) Input Offset Voltage (V) 400 VDD = 2.4 V 350 300 250 TA = -40C TA = +25C TA = +85C 150 100 50 10 8 6 VDD = 3.0 V 350 300 250 200 TA = -40C TA = +25C TA = +85C TA = +125C 150 100 50 0 0 -0.5 4 FIGURE 2-5: Histogram of Input Bias Current with TA = +125 C. FIGURE 2-2: Histogram of Input Bias Current with TA = +85 C. 200 2 Input Bias Current (pA) Input Bias Current (pA) 400 3000 70 2800 60 2600 50 2400 40 2200 30 2000 20 1800 10 0 0% 0% 0 -2 5% 1600 5% 1400 10% 10% 1200 15% 15% 1000 20% 20% 800 25% 600 30% 210 Samples TA = +125 C 25% 0 Percentage of Occurrences Percentage of Occurrences 210 Samples TA = 85 C Histogram of Input Offset 400 Histogram of Input Offset 40% 35% -4 Input Offset Voltage Drift (V/C) 200 FIGURE 2-1: Voltage. -6 -10 -8 0% 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0.0 -0.4 -0.8 -1.2 -1.6 -2.0 840 Samples VCM = VSS -2.4 12% 11% 10% 9% 8% 7% 6% 5% 4% 3% 2% 1% 0% -2.8 Percentage of Occurrences Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, V SS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2, and CL = 60 pF. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Common Mode Input Voltage (V) FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 2.4V. 2003 Microchip Technology Inc. -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Common Mode Input Voltage (V) FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 3.0V. DS21812B-page 5 MCP6291/2/3/4 800 750 700 650 600 550 500 450 400 350 300 250 200 VDD = 5.5 V Input Offset Voltage (V) Input Offset Voltage (V) Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, V SS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2, and CL = 60 pF. +125C +85C +25C -40C 700 650 600 550 500 450 400 350 300 250 200 150 100 VCM = VSS Representative Part VDD = 5.5V VDD = 3.0V VDD = 2.4V 0.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.5 1.0 1.5 Common Mode Input Voltage (V) FIGURE 2-7: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-10: Output Voltage. 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input Offset Voltage vs. 120 110 V DD = 5.0V 100 110 90 PSRR, CMRR (dB) CMRR, PSRR (dB) 2.0 Output Voltage (V) CMRR 80 PSRR- 70 PSRR+ 60 50 40 100 CMRR 90 PSRR VCM = VSS 80 70 30 20 60 1.E+00 1.E+01 1 1.E+02 10 1.E+03 100 1.E+04 1k 1.E+05 10k -50 1.E+06 100k 1M -25 Frequency (Hz) FIGURE 2-8: Frequency. FIGURE 2-11: Temperature. CMRR, PSRR vs. 2.5 45 Input Bias, Offset Currents (nA) Input Bias, Offset Currents (pA) 55 Input Bias Current 35 25 15 5 Input Offset Current -5 TA = +85C VDD = 5.5V -15 0 25 50 75 100 125 Ambient Temperature (C) -25 2.0 CMRR, PSRR vs. Ambient TA = +125 C VDD = 5.5V 1.5 Input Bias Current 1.0 0.5 0.0 Input Offset Current -0.5 -1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-9: Input Bias, Input Offset Currents vs. Common Mode Input Voltage with TA = +85C. DS21812B-page 6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-12: Input Bias, Input Offset Currents vs. Common Mode Input Voltage with TA = +125C. 2003 Microchip Technology Inc. MCP6291/2/3/4 Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, V SS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2, and CL = 60 pF. 1.4 V CM = VDD V DD = 5.5V 1.2 Quiescent Current (mA/channel) 1,000 Input Bias Current 100 Input Offset Current 10 1.0 0.8 TA = +125C TA = +85C TA = +25C TA = -40C 0.6 0.4 0.2 0.0 1 25 35 45 55 65 75 85 95 0.0 105 115 125 0.5 FIGURE 2-13: Input Bias, Input Offset Currents vs. Ambient Temperature VDD = 5.5V. 10k Ouput Voltage Headroom (mV) 100k 1M 10M -30 Gain 80 -60 Phase 60 -90 40 -120 20 -150 1.E+08 1.E+07 1.E+06 -210 10k 100k 1M 10M 100M 1.E+05 1k 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00 100 Frequency (Hz) FIGURE 2-15: Frequency. Open-Loop Gain, Phase vs. 2003 Microchip Technology Inc. 4.0 4.5 5.0 5.5 10 V OL - VSS VDD - V OH 1 0.01 16 -180 1.E-01 0 10 3.5 0.1 1 10 FIGURE 2-17: Output Voltage Headroom vs. Output Current Magnitude. Gain Bandwidth Product (MHz) 0 100 Open-Loop Phase () Open-Loop Gain (dB) 120 1 3.0 Output Current Magnitude (mA) FIGURE 2-14: Maximum Output Voltage Swing vs. Frequency. 0.1 2.5 100 Frequency (Hz) -20 2.0 1000 1.E+07 1k 1.E+06 1.E+04 1.E+03 0.1 1.E+05 Maximum Output Voltage Swing (VP-P) 1 1.5 FIGURE 2-16: Quiescent Current vs. Power Supply Voltage. 10 VDD = 5.5V VDD = 3.0V VDD = 2.4V 1.0 Power Supply Voltage (V) Ambient Temperature (C) 14 12 PM, VDD = 5.5V PM, VDD = 3.0V PM, VDD = 2.4V GBWP, VDD = 5.5V GBWP, VDD = 3.0V GBWP, VDD = 2.4V 100 95 90 10 85 8 80 6 75 4 70 2 65 0 Phase Margin () Input Bias, Offset Currents (pA) 10,000 60 -50 -25 0 25 50 75 100 125 Ambient Temperature (C) FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. DS21812B-page 7 MCP6291/2/3/4 12 Falling Edge, VDD = 5.5V VDD = 3.0V VDD = 2.4V 10 Slew Rate (V/s) Channel-to-Channel Separation (dB) Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, V SS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2, and CL = 60 pF. 8 6 4 Rising Edge, VDD = 5.5V VDD = 3.0V VDD = 2.4V 2 0 -50 -25 0 25 50 75 100 140 130 120 110 100 125 1 10 Ambient Temperature (C) FIGURE 2-19: Temperature. Slew Rate vs. Ambient FIGURE 2-22: Channel-to-Channel Separation vs. Frequency (MCP6292 and MCP6294). 11 VDD = 5.0V Input Noise Voltage Density (nV/Hz) Input Noise Voltage Density (nV/Hz) 1,000 100 10 1 1.E-01 1.E+00 0.1 1 1.E+01 1.E+02 10 100 1.E+03 1.E+04 1k 10k 1.E+05 9 8 f = 10 kHz VDD = 5.0V 7 6 5 4 3 2 1 0 1.E+06 100k 10 1M 0.0 Frequency (Hz) Input Noise Voltage Density Quiescent Current (mA) 1.2 1.0 0.8 Hysteresis 0.6 0.4 CS swept high to low 0.2 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FIGURE 2-23: Input Noise Voltage Density vs. Common Mode Input Voltage at 10 kHz. 1.6 V DD = 2.4V Op-Amp shuts off here Op-Amp turns on here 0.5 Common Mode Input Voltage (V) Quiescent Current (mA) FIGURE 2-20: vs. Frequency. 100 Frequency (kHz) CS swept low to high 0.0 VDD = 5.5V Op Amp shuts off Op Amp turns on 1.4 Hysteresis 1.2 1.0 0.8 CS swept high to low 0.6 CS swept low to high 0.4 0.2 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Chip Select Voltage (V) FIGURE 2-21: Quiescent Current vs. Chip Select (CS) Voltage with VDD = 2.4V (MCP6293 only). DS21812B-page 8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) FIGURE 2-24: Quiescent Current vs. Chip Select (CS) Voltage with VDD = 5.5V (MCP6293 only). 2003 Microchip Technology Inc. MCP6291/2/3/4 3.0 VDD = 2.4V G = +1V/V VIN = VSS CS Voltage 2.5 Chip Select, Output Voltage (V) Chip Select, Output Voltage (V) Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, V SS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2, and CL = 60 pF. 2.0 1.5 Output On VOUT 1.0 0.5 Output High-Z 0.0 0.E+00 5.E-06 1.E-05 2.E-05 2.E-05 3.E-05 3.E-05 4.E-05 4.E-05 5.E-05 6.0 CS Voltage 5.0 4.5 4.0 3.5 VOUT 3.0 2.5 2.0 1.5 1.0 Output High-Z 0.E+00 5.E-06 1.E-05 2.E-05 Time (5 s/div) 5.0 3.E-05 3.E-05 4.E-05 4.E-05 5.E-05 5.E-05 FIGURE 2-28: Chip Select (CS) to Amplifier Output Response Time with VDD = 5.5V (MCP6293 only). 5.0 G = +1V/V VDD = 5.0V 4.5 G = -1V/V VDD = 5.0V 4.5 4.0 Output Voltage (V) Output Voltage (V) 2.E-05 Time (5 s/div) FIGURE 2-25: Chip Select (CS) to Amplifier Output Response Time with VDD = 2.4V (MCP6293 only). 3.5 3.0 2.5 2.0 1.5 1.0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.5 0.0 Output On 0.5 0.0 5.E-05 V DD = 5.5V G = +1V/V V IN = VSS 5.5 0.E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 7.E-06 8.E-06 9.E-06 0.0 1.E-05 0.E+00 1.E-06 FIGURE 2-26: Pulse Response. 2.E-06 3.E-06 4.E-06 5.E-06 6.E-06 Large Signal Non-inverting FIGURE 2-29: Response. 8.E-06 9.E-06 1.E-05 Large Signal Inverting Pulse G = -1V/V Output Voltage (10 mV/div) Output Voltage (10 mV/div) G = +1V/V Time (200 ns/div) FIGURE 2-27: Pulse Response. 7.E-06 Time (1 s/div) Time (1 s/div) Small Signal Non-inverting 2003 Microchip Technology Inc. Time (200 ns/div) FIGURE 2-30: Response. Small Signal Inverting Pulse DS21812B-page 9 MCP6291/2/3/4 Note: Unless otherwise indicated, TA = +25C, VDD = +2.4V to +5.5V, V SS = GND, VCM = VDD/2, VOUT VDD/2, RL = 10 k to VDD/2, and CL = 60 pF. Ouptut Short Circuit Current (mA) 35 30 25 20 15 TA TA TA TA 10 5 = +125C = +85C = +25C = -40C 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-31: Output Short-Circuit Current vs. Power Supply Voltage. DS21812B-page 10 2003 Microchip Technology Inc. MCP6291/2/3/4 3.0 APPLICATION INFORMATION - The MCP6291/2/3/4 family of op amps is manufactured using Microchip's state-of-the-art CMOS process, specifically designed for low cost, low power and general-purpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP6291/2/3/4 ideal for battery-powered applications. 3.1 6 ( Maximum expected V IN ) - V DD R IN S -----------------------------------------------------------------------------------2 mA 3 VOUT 2 1 3.3 0 -1 FIGURE 3-2: Resistor (RIN). -15 -14 -13 -12 -11 -10 -9 Input Current Limiting Rail-to-Rail Output The output voltage range of the MCP6291/2/3/4 op amp is VDD - 15 mV (min.) and VSS + 15 mV (max.) when RL = 10 k is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-17 for more information. 4 VIN V SS - ( Minimum expected V IN ) R IN S ---------------------------------------------------------------------------------2 mA 3.2 VDD = 5.0V G = +2V/V 5 VOUT MCP6291 + VIN Rail-to-Rail Input The MCP6291/2/3/4 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 3-1 shows the input voltage exceeding the supply voltage without any phase reversal. Input, Output Voltage (V) RIN -8 -7 -6 -5 Time (1 ms/div) FIGURE 3-1: The MCP6291/2/3/4 Show No Phase Reversal. The input stage of the MCP6291/2/3/4 op amp uses two differential input stages in parallel. One operates at low common mode input voltage (VCM), while the other operates at high VCM. With this topology, the device operates with VCM up to 300 mV above VDD and 300 mV below VSS. The Input Offset Voltage is measured at VCM = V SS - 300 mV and V DD + 300 mV to ensure proper operation. Input voltages that exceed the input voltage range (VSS - 0.3V to VDD + 0.3V at 25C) can cause excessive current to flow into or out of the input pins. Current beyond 2 mA can cause reliability problems. Applications that exceed this rating must be externally limited with a resistor, as shown in Figure 3-2. MCP6293 Chip Select (CS) The MCP6293 is a single amplifier with Chip Select (CS). When CS is pulled high, the supply current drops to 0.7 A (typ) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled. If the CS pin is left floating, the amplifier may not operate properly. Figure 3-3 shows the output voltage and supply current response to a CS pulse. CS VIL VIH toff ton VOUT Hi-Z Hi-Z -1.0 mA, typ. IVSS ICS -0.7 A, typ. 0.7 A, typ. -0.7 A, typ. 10 nA, typ 0.7 A, typ. FIGURE 3-3: Timing Diagram for the Chip Select (CS) pin on the MCP6293. 2003 Microchip Technology Inc. DS21812B-page 11 MCP6291/2/3/4 3.4 Capacitive Loads 3.6 PCB Surface Leakage Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity-gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. In applications where low input bias current is critical, PCB (printer circuit board) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA, if current-to-flow, which is greater than the MCP6291/2/3/4 family's bias current at 25C (1 pA, typ). When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1), a small series resistor at the output (RISO in Figure 3-4) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. It does not, however, improve the bandwidth. The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 3-5. VIN- - + VOUT CL FIGURE 3-4: Output resistor, R ISO stabilizes large capacitive loads. To select RISO, check the frequency response peaking (or step response overshoot) on the bench (or with the MCP6291/2/3/4 SPICE Macro Model). If the response is reasonable, you do not need RISO. Otherwise, start RISO at 100 and modify its value until the response is reasonable. 3.5 Guard Ring FIGURE 3-5: for Inverting Gain. 1. Supply Bypass With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good high-frequency performance. It also needs a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other parts. DS21812B-page 12 VSS RISO MCP6291 VIN VIN+ 2. Example Guard Ring Layout For Inverting (Figure 3-5) and Transimpedance Amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b. Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the common mode input voltage. 2003 Microchip Technology Inc. MCP6291/2/3/4 3.7 3.7.1 Application Circuits 3.7.2 MULTIPLE FEEDBACK LOWPASS FILTER The MCP6291/2/3/4 op amp can be used in active-filter applications. Figure 3-6 shows an inverting, third-order, Multiple Feedback Lowpass filter that can be used as an anti-aliasing filter. PHOTO DIODE AMPLIFIER Figure 3-7 shows a photo diode biased in the photovoltaic mode for high precision. The resistor R converts the diode current ID to the voltage V OUT. The capacitor is used to limit the bandwidth or to stabilize the circuit against the diode's capacitance (it is not always needed). C VIN R1 C1 R2 R3 C3 R4 VOUT ID C4 R VOUT light MCP6291 MCP6291 VDD /2 VDD/2 FIGURE 3-7: FIGURE 3-6: Filter. Photo Diode Amplifier. Multiple Feedback Lowpass This filter, and others, can be designed using Microchip's FilterLab(R) software, which is available on our web site (www.microchip.com). 2003 Microchip Technology Inc. DS21812B-page 13 MCP6291/2/3/4 4.0 DESIGN TOOLS Microchip provides the basic design tools needed for the MCP6291/2/3/4 family of op amps. 4.1 SPICE Macro Model The latest SPICE Macro Model for the MCP6291/2/3/4 op amps is available on our web site at www.microchip.com. This model is intended as an initial design tool that works well in the op amp's linear region of operation at room temperature. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 4.2 FilterLab(R) Software Microchip's FilterLab software is an innovative tool that simplifies analog active-filter (using op amps) design. Available at no cost from our web site at www.microchip.com, the FilterLab active-filter software design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. DS21812B-page 14 2003 Microchip Technology Inc. MCP6291/2/3/4 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX XXXXXNNN YYWW MCP6291 E/P057 0309 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN 8-Lead MSOP Example: MCP6291 E/SN0309 057 Example: XXXXXX 6291 309057 YWWNNN Legend: Note: * XX...X YY WW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. 2003 Microchip Technology Inc. DS21812B-page 15 MCP6291/2/3/4 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6294) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) (MCP6294) XXXXXXXXXX XXXXXXXXXX YYWWNNN 14-Lead TSSOP (MCP6294) Example: MCP6294-E/P 0309057 Example: MCP6294ESL 0309057 Example: XXXXXX YYWW 6294ST 0309 NNN 057 DS21812B-page 16 2003 Microchip Technology Inc. MCP6291/2/3/4 8-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c A1 B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L c B1 B eB MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 2003 Microchip Technology Inc. DS21812B-page 17 MCP6291/2/3/4 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A2 A L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21812B-page 18 2003 Microchip Technology Inc. MCP6291/2/3/4 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 A2 A c A1 (F) L Units Dimension Limits n p MIN INCHES NOM MAX MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0 0.08 0.22 5 5 - MIN 8 Number of Pins .026 BSC Pitch A .043 Overall Height A2 .030 .033 .037 Molded Package Thickness A1 .006 .000 Standoff E .193 TYP. Overall Width E1 .118 BSC Molded Package Width D .118 BSC Overall Length L .016 .024 .031 Foot Length Footprint (Reference) F .037 REF Foot Angle 0 8 c Lead Thickness .003 .006 .009 B .009 .012 .016 Lead Width 5 15 Mold Draft Angle Top 5 15 Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. MAX 1.10 0.95 0.15 0.80 8 0.23 0.40 15 15 JEDEC Equivalent: MO-187 Drawing No. C04-111 2003 Microchip Technology Inc. DS21812B-page 19 MCP6291/2/3/4 14-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c A1 eB B1 p B Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 DS21812B-page 20 MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 2003 Microchip Technology Inc. MCP6291/2/3/4 14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A2 A A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D h L c B MIN .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 2003 Microchip Technology Inc. DS21812B-page 21 MCP6291/2/3/4 14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP) E E1 p D 2 1 n B A c A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L c B1 MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 A2 MAX .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS21812B-page 22 2003 Microchip Technology Inc. MCP6291/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Examples: a) b) c) Device: MCP6291: MCP6291T: MCP6292: MCP6292T: MCP6293: MCP6293T: MCP6294: MCP6294T: Single Operational Amplifier Single Operational Amplifier (Tape and Reel) (SOIC, MSOP) Dual Operational Amplifier Dual Operational Amplifier (Tape and Reel) (SOIC, MSOP) Single Operational Amplifier with Chip Select Single Operational Amplifier with Chip Select (Tape and Reel) (SOIC, MSOP) Quad Operational Amplifier Quad Operational Amplifier (Tape and Reel) (SOIC, TSSOP) d) e) a) b) c) d) Temperature Range: E = -40C to +125C Package: MS P SN SL ST = = = = = e) Plastic MSOP, 8-lead Plastic DIP (300 mil Body), 8-lead, 14-lead Plastic SOIC, (150 mil Body), 8-lead Plastic SOIC (150 mil Body), 14-lead Plastic TSSOP (4.4mm Body), 14-lead a) b) c) d) e) MCP6291-E/SN: Extended Temperature, 8LD SOIC package MCP6291-E/MS: Extended Temperature, 8LD MSOP package. MCP6291-E/P: Extended Temperature, 8LD PDIP package. MCP6291T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. MCP6291T-E/MS: Tape and Reel, Extended Temperature, 8LD MSOP package. MCP6292-E/SN: Extended Temperature, 8LD SOIC package MCP6292-E/MS: Extended Temperature, 8LD MSOP package. MCP6292-E/P: Extended Temperature, 8LD PDIP package. MCP6292T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. MCP6292T-E/MS: Tape and Reel, Extended Temperature, 8LD MSOP package. MCP6293-E/SN: Extended Temperature, 8LD SOIC package MCP6293-E/MS: Extended Temperature, 8LD MSOP package. MCP6293-E/P: Extended Temperature, 8LD PDIP package. MCP6293T-E/SN: Tape and Reel, Extended Temperature, 8LD SOIC package. MCP6293T-E/MS: Tape and Reel, Extended Temperature, 8LD MSOP package. a) MCP6294-E/P: b) MCP6294T-E/SL: c) MCP6294-E/SL: d) MCP6294-E/ST: e) MCP6294T-E/ST: Extended Temperature, 14LD PDIP package Tape and Reel, Extended Temperature, 14LD SOIC package. Extended Temperature, 14LD SOIC package. Extended Temperature, 14LD TSSOP package. Tape and Reel, Extended Temperature, 14LD TSSOP package. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2003 Microchip Technology Inc. DS21812B-page 23 MCP6291/2/3/4 NOTES: DS21812B-page 24 2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. 2003 Microchip Technology Inc. DS21812B-page 25 M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Atlanta Unit 915 Bei Hai Wan Tai Bldg. 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A. De Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 07/28/03 2003 Microchip Technology Inc.