2003 Microchip Technology Inc. DS21812B-page 1
MMCP6291/2/3/4
Features
• Gain Bandwidth Product: 10 MHz (typ.)
• Supply Current: IQ = 1.0 mA
• Supply Voltage: 2.4V to 5.5V
• Rail-to-Rail Input/Output
• Extended Temperature Range: -40°C to +125°C
• Available in Single, Dual and Quad Packages
• Single with Chip Select (CS) (MCP6293)
Applications
• Automotive
• Portable Equipment
• Photodiode Pre-amps
• Analog Filters
• Notebooks and PDAs
• Battery-Powered Systems
Available Tools
• SPICE Macro Model (at www.microchip.com)
• FilterLab® Software (at www.microchip.com)
Typical Application
Description
The Microchip Technology Inc. MCP6291/2/3/4 family
of operational amplifiers (op amps) provide wide
bandwidth for the current. This family has a 10 MHz
gain bandwidth product and 65° phase margin. This
family also operates from a single supply voltage as
low as 2.4V, while drawing 1 mA (typ.) quiescent
current. In addition, the MCP6291/2/3/4 supports rail-
to-rail input and output swing, with a common mode
input voltage range of VDD + 300 mV to VSS - 300 mV.
This family of operational amplifiers is designed with
Microchip’s advanced CMOS process.
The MCP6291/2/3/4 family operates in the Extended
Temperature Range of -40°C to +125°C. It also has a
power supply range of 2.4V to 5.5V.
Package Types
Multiple Feedback Lowpass Filter
MCP6291
VOUT
VIN
VDD/2
R3C3
C1
R1R2
C4
R4
8
7
6
5
VIN_
MCP6291
VDD
1
2
3
4
8
7
6
5
-
+
NC
NC
NC
VIN+
VSS
MCP6292
PDIP, SOIC, MSOP
MCP6294
1
2
3
4
14
13
12
11
-+-
+
AD
10
9
8
5
6
7
+
-BC
-
+
PDIP, SOIC, TSSOP
1
2
3
4
8
7
6
5
-
+-
+
A
B
VOUT
MCP6293
1
2
3
4
-
+
VINA_
VINA+
VSS
VOUTA
VOUTB
VDD
VINB_
VINB+
VSS
VIN+
VIN_
NC CS
VDD
VOUT
NC
VOUTA
VINA_
VINA+
VDD VSS
VOUTB
VINB_
VINB+
VOUTC
VINC_
VINC+
VOUTD
VIND_
VIND+
PDIP, SOIC, MSOP
PDIP, SOIC, MSOP
1.0 mA, 10 MHz Bandwidth, Rail-to-Rail Op Amp
MCP6291/2/3/4
DS21812B-page 2 2003 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD - VSS .........................................................................7.0V
All Inputs and Outputs ...................... VSS -0.3V to VDD +0.3V
Difference Input Voltage ....................................... |VDD - VSS|
Output Short Circuit Current ..................................continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ....................................-65°C to +150°C
Junction Temperature (TJ) ..........................................+150°C
ESD Protection On All Pins (HBM/MM) ................ ≥ 4 kV/200V
† Notice: Stresses above those listed under “Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
affect device reliability.
PIN FUNCTION TABLE
DC ELECTRICAL SPECIFICATIONS
Name Function
VIN+, VINA+, VINB+, VINC+, VIND+ Non-inverting Inputs
VIN_, VINA_, VINB_, VINC_, VIND_Inverting Inputs
VDD Positive Power Supply
VSS Negative Power Supply
VOUT
, VOUTA, VOUTB, VOUTC,
VOUTD
Outputs
NC No Internal Connection
CS Chip Select
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2,
RL = 10 kΩ to VDD/2, and VOUT ≈VDD/2.
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -3.0 — +3.0 mV VCM = VSS
Input Offset Voltage
(Extended Temperature)
VOS -5.0 — +5.0 mV TA = -40°C to +125°C,
VCM = VSS, VDD = 3.0V to 5.5V
Input Offset Temperature Drift ∆VOS/∆TA—±1.7—µV/°CT
A = -40°C to +125°C,
VDD =3.0V to 5.5V
Power Supply Rejection PSRR 70 90 — dB VCM = VSS
Input Bias, Input Offset Current and Impedance
Input Bias Current IB—±1.0— pA
Overtemperature IB— 50 200 pA TA = +85°C
Overtemperature IB—25nAT
A = +125°C,
VDD = 3.0V to 5.5V
Input Offset Current IOS —±1.0— pA
Common Mode Input Impedance ZCM —10
13||6 — Ω||pF
Differential Input Impedance ZDIFF —10
13||3 — Ω||pF
Common Mode
Common Mode Input Range VCMR VSS−0.3 — VDD+0.3 V
Common Mode Rejection Ratio CMRR 70 85 — dB VCM = -0.3V to 2.5V, VDD = 5V
Common Mode Rejection Ratio CMRR 65 80 — dB VCM = -0.3V to 5.3V, VDD = 5V
Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 90 110 — dB VOUT = 0.2V to VDD - 0.2V,
VCM =V
SS
Output
Maximum Output Voltage Swing VOL, VOH VSS+15 — VDD−15 mV
Output Short-Circuit Current ISC —±25—mA
Power Supply
Supply Voltage VDD 2.4 — 5.5 V TA = -40°C to +85°C
VDD 3.0 — 5.5 V TA = +86°C to +125°C
Quiescent Current per Amplifier IQ0.7 1.0 1.3 mA IO = 0
2003 Microchip Technology Inc. DS21812B-page 3
MCP6291/2/3/4
AC ELECTRICAL SPECIFICATIONS
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈VDD/2, RL = 10 kΩ to VDD/2, and CL = 60 pF.
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 10.0 — MHz
Phase Margin at Unity-Gain PM — 65 — °
Slew Rate SR — 7 — V/µs
Noise
Input Noise Voltage Eni — 3.5 — µVp-p f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —8.7—nV/√Hz f = 10 kHz
Input Noise Current Density ini —3—fA/√Hz f = 1 kHz
Electrical Characteristics: Unless otherwise indicated, VDD = +2.4V to +5.5V, and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Temperature Range TA-40 — +125 °C (Note)
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-PDIP θJA —85—°C/W
Thermal Resistance, 8L-SOIC θJA — 163 — °C/W
Thermal Resistance, 8L-MSOP θJA — 206 — °C/W
Thermal Resistance, 14L-PDIP θJA —70 —°C/W
Thermal Resistance, 14L-SOIC θJA —120 —°C/W
Thermal Resistance, 14L-TSSOP θJA —100 —°C/W
Note: The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
MCP6291/2/3/4
DS21812B-page 4 2003 Microchip Technology Inc.
MCP6293 CHIP SELECT (CS) SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT ≈VDD/2, RL = 10 kΩ to VDD/2, and CL = 60 pF.
Parameters Sym Min Typ Max Units Conditions
CS Low Specifications
CS Logic Threshold, Low VIL VSS —0.2V
DD V
CS Input Current, Low ICSL —0.01— µACS = VSS
CS High Specifications
CS Logic Threshold, High VIH 0.8 VDD —V
DD V
CS Input Current, High ICSH —0.7 2 µACS = VDD
CS Input High, GND Current IQ—-0.7— µACS = VDD
Amplifier Output Leakage,
CS High
— — 0.01 — µA CS = VDD
Dynamic Specifications
CS Low to Valid Amplifier
Output, Turn-on Time
tON —410µsCS Low ≤ 0.2 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.9 VDD/2,
VDD = 5.0V
CS High to Amplifier Output
High-Z
tOFF —0.01— µsCS High ≥ 0.8 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.1 VDD/2
Hysteresis VHYST —0.6— VV
DD = 5V
2003 Microchip Technology Inc. DS21812B-page 5
MCP6291/2/3/4
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2, and CL = 60 pF.
FIGURE 2-1: Histogram of Input Offset
Voltage.
FIGURE 2-2: Histogram of Input Bias
Current with TA = +85 °C.
FIGURE 2-3: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 2.4V.
FIGURE 2-4: Histogram of Input Offset
Voltage Drift.
FIGURE 2-5: Histogram of Input Bias
Current with TA = +125 °C.
FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 3.0V.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
1%
2%
3%
4%
5%
6%
7%
8%
9%
10%
11%
12%
-2.8
-2.4
-2.0
-1.6
-1.2
-0.8
-0.4
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
Input Offset Voltage (mV)
Percentage of Occurrences
840 Samples
VCM = VSS
0%
5%
10%
15%
20%
25%
30%
35%
40%
0 102030405060708090100
Input Bias Current (pA)
Percentage of Occurrences
210 Samples
TA = 85 °C
0
50
100
150
200
250
300
350
400
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 2.4 V
TA = -40°C
TA = +25°C
TA = +85°C
0%
5%
10%
15%
20%
25%
-10
-8
-6
-4
-2
0
2
4
6
8
10
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
840 Samples
VCM = VSS
TA = -40°C to +125°C
0%
5%
10%
15%
20%
25%
30%
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
3000
Input Bias Current (pA)
Percentage of Occurrences
210 Samples
TA = +125 °C
0
50
100
150
200
250
300
350
400
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 3.0 V
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
MCP6291/2/3/4
DS21812B-page 6 2003 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2, and CL = 60 pF.
FIGURE 2-7: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 5.5V.
FIGURE 2-8: CMRR, PSRR vs.
Frequency.
FIGURE 2-9: Input Bias, Input Offset
Currents vs. Common Mode Input Voltage with
TA = +85°C.
FIGURE 2-10: Input Offset Voltage vs.
Output Voltage.
FIGURE 2-11: CMRR, PSRR vs. Ambient
Temperature.
FIGURE 2-12: Input Bias, Input Offset
Currents vs. Common Mode Input Voltage with
TA = +125°C.
200
250
300
350
400
450
500
550
600
650
700
750
800
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5 V
+125°C
+85°C
+25°C
-40°C
20
30
40
50
60
70
80
90
100
110
1.E+00 1.E+01 1.E+02 1 .E+03 1 .E+04 1.E+05 1 .E+06
Frequency (Hz)
CMRR, PSRR (dB)
VDD = 5.0V
1 10k 100k 1M10010 1k
PSRR+
PSRR-
CMRR
-25
-15
-5
5
15
25
35
45
55
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents
(pA)
TA = +85°C
VDD = 5.5V
Input Bias Current
Input Offset Current
100
150
200
250
300
350
400
450
500
550
600
650
700
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Input Offset Voltage (µV)
VCM = VSS
Representative Part
VDD = 5.5V
VDD = 3.0V
VDD = 2.4V
60
70
80
90
100
110
120
-50-250 255075100125
Ambient Temperature (°C)
PSRR, CMRR (dB)
PSRR
VCM = VSS
CMRR
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents
(nA)
TA = +125 °C
VDD = 5.5V
Input Bias Current
Input Offset Current
2003 Microchip Technology Inc. DS21812B-page 7
MCP6291/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2, and CL = 60 pF.
FIGURE 2-13: Input Bias, Input Offset
Currents vs. Ambient Temperature VDD = 5.5V.
FIGURE 2-14: Maximum Output Voltage
Swing vs. Frequency.
FIGURE 2-15: Open-Loop Gain, Phase vs.
Frequency.
FIGURE 2-16: Quiescent Current vs.
Power Supply Voltage.
FIGURE 2-17: Output Voltage Headroom
vs. Output Current Magnitude.
FIGURE 2-18: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
1
10
100
1,000
10,000
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias, Offset Currents
(pA)
Input Bias Current
Input Offset Current
VCM = VDD
VDD = 5.5V
0.1
1
10
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequency (Hz)
Maximum Output Voltage
Swing (VP-P)
1k 10k 100k 1M 10M
VDD = 5.5V
VDD = 3.0V
VDD = 2.4V
-20
0
20
40
60
80
100
120
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Frequency (Hz)
Open-Loop Gain (dB)
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
Gain
Phase
0.1 1 10 100 1k 10k 100k 1M 10M 100M
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Quiescent Current
(mA/channel)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
1
10
100
1000
0.01 0.1 1 10
Output Current Magnitude (mA)
Ouput Voltage Headroom (mV)
VOL - VSS
VDD - VOH
0
2
4
6
8
10
12
14
16
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Gain Bandwidth Product
(MHz)
60
65
70
75
80
85
90
95
100
Phase Margin (°)
GBWP, VDD = 5.5V
GBWP, VDD = 3.0V
GBWP, VDD = 2.4V
PM, VDD = 5.5V
PM, VDD = 3.0V
PM, VDD = 2.4V
MCP6291/2/3/4
DS21812B-page 8 2003 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2, and CL = 60 pF.
FIGURE 2-19: Slew Rate vs. Ambient
Temperature.
FIGURE 2-20: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-21: Quiescent Current vs. Chip
Select (CS) Voltage with VDD = 2.4V (MCP6293
only).
FIGURE 2-22: Channel-to-Channel
Separation vs. Frequency (MCP6292 and
MCP6294).
FIGURE 2-23: Input Noise Voltage Density
vs. Common Mode Input Voltage at 10 kHz.
FIGURE 2-24: Quiescent Current vs. Chip
Select (CS) Voltage with VDD = 5.5V (MCP6293
only).
0
2
4
6
8
10
12
-50-250 255075100125
Ambient Temperature (°C)
Slew Rate (V/µs)
Rising Edge, VDD = 5.5V
VDD = 3.0V
VDD = 2.4V
Falling Edge, VDD = 5.5V
VDD = 3.0V
VDD = 2.4V
1
10
100
1,000
1.E-01 1.E+00 1.E+ 01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+ 06
Frequency (Hz)
Input Noise Voltage Density
(nV/√Hz)
V
DD
=5.0V
0.1 10010 1k 100k10k 1M1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Chip Select Voltage (V)
Quiescent Current (mA)
Hysteresis
Op-Amp shuts off here
Op-Amp turns on here
VDD = 2.4V
CS swept
high to low
CS swept
low to high
100
110
120
130
140
110100
Frequency (kHz)
Channel-to-Channel Separation
(dB)
0
1
2
3
4
5
6
7
8
9
10
11
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Input Voltage (V)
Input Noise Voltage Density
(nV/√Hz)
f = 10 kHz
V
DD
=5.0V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
Quiescent Current (mA)
Hysteresis
VDD = 5.5V
CS swept
low to high
CS swept
high to low
Op Amp shuts off
Op Amp turns on
2003 Microchip Technology Inc. DS21812B-page 9
MCP6291/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2, and CL = 60 pF.
FIGURE 2-25: Chip Select (CS) to
Amplifier Output Response Time with VDD = 2.4V
(MCP6293 only).
FIGURE 2-26: Large Signal Non-inverting
Pulse Response.
FIGURE 2-27: Small Signal Non-inverting
Pulse Response.
FIGURE 2-28: Chip Select (CS) to
Amplifier Output Response Time with VDD = 5.5V
(MCP6293 only).
FIGURE 2-29: Large Signal Inverting Pulse
Response.
FIGURE 2-30: Small Signal Inverting Pulse
Response.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.E+00 5.E- 06 1.E-05 2.E- 05 2.E-05 3.E- 05 3.E-05 4.E- 05 4.E-05 5.E-05 5.E- 05
Time (5 µs/div)
Chip Select, Output Voltage (V)
VOUT
Output On
Output High-Z
VDD = 2.4V
G = +1V/V
VIN = VSS
CS Voltage
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.E+00 1.E- 06 2.E-06 3.E- 06 4.E-06 5.E- 06 6.E-06 7.E- 06 8.E-06 9.E- 06 1.E-05
Time (1 µs/div)
Output Voltage (V)
G = +1V/V
VDD = 5.0V
Time (200 ns/div)
Output Voltage (10 mV/div)
G = +1V/V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0.E+00 5.E- 06 1 .E-05 2.E- 05 2.E-05 3.E-05 3.E-05 4 .E-05 4.E-05 5.E- 05 5.E-05
Time (5 µs/div)
Chip Select, Output Voltage (V)
VOUT
Output OnOutput High-Z
VDD = 5.5V
G = +1V/V
VIN = VSS
CS Voltage
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.E+00 1.E- 06 2 .E-06 3.E- 06 4.E-06 5 .E-06 6.E- 06 7.E- 06 8.E-06 9.E- 06 1.E- 05
Time (1 µs/div)
Output Voltage (V)
G = -1V/V
VDD = 5.0V
Time (200 ns/div)
Output Voltage (10 mV/div)
G = -1V/V
MCP6291/2/3/4
DS21812B-page 10 2003 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
RL = 10 kΩ to VDD/2, and CL = 60 pF.
FIGURE 2-31: Output Short-Circuit Current
vs. Power Supply Voltage.
0
5
10
15
20
25
30
35
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Ouptut Short Circuit Current
(mA)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
2003 Microchip Technology Inc. DS21812B-page 11
MCP6291/2/3/4
3.0 APPLICATION INFORMATION
The MCP6291/2/3/4 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process,
specifically designed for low cost, low power and
general-purpose applications. The low supply voltage,
low quiescent current and wide bandwidth makes the
MCP6291/2/3/4 ideal for battery-powered applications.
3.1 Rail-to-Rail Input
The MCP6291/2/3/4 op amps are designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 3-1 shows the input voltage exceeding
the supply voltage without any phase reversal.
FIGURE 3-1: The MCP6291/2/3/4 Show
No Phase Reversal.
The input stage of the MCP6291/2/3/4 op amp uses
two differential input stages in parallel. One operates at
low common mode input voltage (VCM), while the other
operates at high VCM. With this topology, the device
operates with VCM up to 300 mV above VDD and
300 mV below VSS. The Input Offset Voltage is
measured at VCM =V
SS - 300 mV and VDD + 300 mV
to ensure proper operation.
Input voltages that exceed the input voltage range
(VSS - 0.3V to VDD + 0.3V at 25°C) can cause
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally
limited with a resistor, as shown in Figure 3-2.
FIGURE 3-2: Input Current Limiting
Resistor (RIN).
3.2 Rail-to-Rail Output
The output voltage range of the MCP6291/2/3/4 op amp
is VDD - 15 mV (min.) and VSS + 15 mV (max.) when
RL=10kΩ is connected to VDD/2 and VDD =5.5V.
Refer to Figure 2-17 for more information.
3.3 MCP6293 Chip Select (CS)
The MCP6293 is a single amplifier with Chip Select
(CS). When CS is pulled high, the supply current drops
to 0.7 µA (typ) and flows through the CS pin to VSS.
When this happens, the amplifier output is put into a
high-impedance state. By pulling CS low, the amplifier
is enabled. If the CS pin is left floating, the amplifier
may not operate properly. Figure 3-3 shows the output
voltage and supply current response to a CS pulse.
FIGURE 3-3: Timing Diagram for the Chip
Select (CS) pin on the MCP6293.
-1
0
1
2
3
4
5
6
-15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5
Time (1 ms/div)
Input, Output Voltage (V)
VDD = 5.0V
G = +2V/V
VIN VOUT
RIN
VSS Minimum expected VIN
()–
2 mA
-----------------------------------------------------------------------------------Š
RIN
Maximum expected VIN
()VDD
–
2 mA
-------------------------------------------------------------------------------------Š
VIN
RIN VOUT
–
+
MCP6291
VIL
Hi-Z
ton
VIH
CS
toff
VOUT
-0.7 µA, typ.
Hi-Z
IVSS
ICS
0.7 µA, typ. 0.7 µA, typ.
-0.7 µA, typ.
-1.0 mA, typ.
10 nA, typ
MCP6291/2/3/4
DS21812B-page 12 2003 Microchip Technology Inc.
3.4 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 3-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. It does not,
however, improve the bandwidth.
FIGURE 3-4: Output resistor, RISO
stabilizes large capacitive loads.
To select RISO, check the frequency response peaking
(or step response overshoot) on the bench (or with the
MCP6291/2/3/4 SPICE Macro Model). If the response
is reasonable, you do not need RISO. Otherwise, start
RISO at 100Ω and modify its value until the response is
reasonable.
3.5 Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with other parts.
3.6 PCB Surface Leakage
In applications where low input bias current is critical,
PCB (printer circuit board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA, if current-to-flow, which is greater than the
MCP6291/2/3/4 family’s bias current at 25°C (1 pA,
typ).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 3-5.
FIGURE 3-5: Example Guard Ring Layout
for Inverting Gain.
1. For Inverting (Figure 3-5) and Transimpedance
Amplifiers (convert current to voltage, such as
photo detectors):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN-) to the input
with a wire that does not touch the PCB
surface.
2. Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input
pin (VIN-). This biases the guard ring to the
common mode input voltage.
VIN
RISO
VOUT
CL
–
+
MCP6291
Guard Ring
VSS
VIN-V
IN+
2003 Microchip Technology Inc. DS21812B-page 13
MCP6291/2/3/4
3.7 Application Circuits
3.7.1 MULTIPLE FEEDBACK LOWPASS
FILTER
The MCP6291/2/3/4 op amp can be used in active-filter
applications. Figure 3-6 shows an inverting, third-order,
Multiple Feedback Lowpass filter that can be used as
an anti-aliasing filter.
FIGURE 3-6: Multiple Feedback Lowpass
Filter.
This filter, and others, can be designed using
Microchip’s FilterLab® software, which is available on
our web site (www.microchip.com).
3.7.2 PHOTO DIODE AMPLIFIER
Figure 3-7 shows a photo diode biased in the photo-
voltaic mode for high precision. The resistor R
converts the diode current ID to the voltage VOUT. The
capacitor is used to limit the bandwidth or to stabilize
the circuit against the diode’s capacitance (it is not
always needed).
FIGURE 3-7: Photo Diode Amplifier.
MCP6291
VOUT
VIN
VDD/2
R3C3
C1
R1R2
C4
R4
MCP6291
VOUT
ID
VDD/2
R
C
light
MCP6291/2/3/4
DS21812B-page 14 2003 Microchip Technology Inc.
4.0 DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6291/2/3/4 family of op amps.
4.1 SPICE Macro Model
The latest SPICE Macro Model for the MCP6291/2/3/4
op amps is available on our web site at
www.microchip.com. This model is intended as an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. See the
model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
4.2 FilterLab® Software
Microchip’s FilterLab software is an innovative tool that
simplifies analog active-filter (using op amps) design.
Available at no cost from our web site at
www.microchip.com, the FilterLab active-filter software
design tool provides full schematic diagrams of the filter
circuit with component values. It also outputs the filter
circuit in SPICE format, which can be used with the
macro model to simulate actual filter performance.
2003 Microchip Technology Inc. DS21812B-page 15
MCP6291/2/3/4
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
Legend: XX...X Customer specific information*
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
MCP6291
E/P057
0309
MCP6291
E/SN0309
057
8-Lead MSOP Example:
XXXXXX
YWWNNN
6291
309057
MCP6291/2/3/4
DS21812B-page 16 2003 Microchip Technology Inc.
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6294) Example:
14-Lead TSSOP (MCP6294) Example:
14-Lead SOIC (150 mil) (MCP6294) Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXX
YYWWNNN
XXXXXX
YYWW
NNN
MCP6294-E/P
0309057
6294ST
0309
057
XXXXXXXXXX MCP6294ESL
0309057
2003 Microchip Technology Inc. DS21812B-page 17
MCP6291/2/3/4
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
MCP6291/2/3/4
DS21812B-page 18 2003 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom
1512015120
α
Mold Draft Angle Top
0.510.420.33.020.017.013BLead Width
0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length
0.510.380.25.020.015.010hChamfer Distance
5.004.904.80.197.193.189DOverall Length
3.993.913.71.157.154.146E1Molded Package Width
6.206.025.79.244.237.228EOverall Width
0.250.180.10.010.007.004A1Standoff §
1.551.421.32.061.056.052A2Molded Package Thickness
1.751.551.35.069.061.053AOverall Height
1.27.050
p
Pitch
88
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45°
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
2003 Microchip Technology Inc. DS21812B-page 19
MCP6291/2/3/4
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
D
A
A1
L
c
(F)
α
A2
E1
E
p
B
n 1
2
φ
β
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
.037 REFFFootprint (Reference)
exceed .010" (0.254mm) per side.
Notes:
Drawing No. C04-111
*Controlling Parameter
Mold Draft Angle Top
Mold Draft Angle Bottom
Foot Angle
Lead Width
Lead Thickness
β
α
c
B
φ
.003
.009
.006
.012
Dimension Limits
Overall Height
Molded Package Thickness
Molded Package Width
Overall Length
Foot Length
Standoff
Overall Width
Number of Pins
Pitch
A
L
E1
D
A1
E
A2
.016 .024
.118 BSC
.118 BSC
.000
.030
.193 TYP.
.033
MIN
p
n
Units
.026 BSC
NOM
8
INCHES
0.95 REF
-
-
.009
.016
0.08
0.22
0°
0.23
0.40
8°
MILLIMETERS*
0.65 BSC
0.85
3.00 BSC
3.00 BSC
0.60
4.90 BSC
.043
.031
.037
.006
0.40
0.00
0.75
MIN
MAX NOM
1.10
0.80
0.15
0.95
MAX
8
--
-
15°5° -
15°5° -
JEDEC Equivalent: MO-187
0° - 8°
5°
5° -
-
15°
15°
--
--
MCP6291/2/3/4
DS21812B-page 20 2003 Microchip Technology Inc.
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
n
D
1
2
eB
β
E
c
A
A1
B
B1
L
A2
p
α
Units INCHES* MILLIMETERS
Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n14 14
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .740 .750 .760 18.80 19.05 19.30
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α5 10 15 5 10 15
β5 10 15 5 10 15
Mold Draft Angle Bottom
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-005
§ Significant Characteristic
2003 Microchip Technology Inc. DS21812B-page 21
MCP6291/2/3/4
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom
1512015120
α
Mold Draft Angle Top
0.510.420.36.020.017.014BLead Width
0.250.230.20.010.009.008
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length
0.510.380.25.020.015.010hChamfer Distance
8.818.698.56.347.342.337DOverall Length
3.993.903.81.157.154.150E1Molded Package Width
6.205.995.79.244.236.228EOverall Width
0.250.180.10.010.007.004A1Standoff §
1.551.421.32.061.056.052A2Molded Package Thickness
1.751.551.35.069.061.053AOverall Height
1.27.050
p
Pitch
1414
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
h
L
c
β
45°
φ
α
A2
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065
§ Significant Characteristic
MCP6291/2/3/4
DS21812B-page 22 2003 Microchip Technology Inc.
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
840840
φ
Foot Angle
10501050
β
Mold Draft Angle Bottom
10501050
α
Mold Draft Angle Top
0.300.250.19.012.010.007B1Lead Width
0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Length
5.105.004.90.201.197.193DMolded Package Length
4.504.404.30.177.173.169E1Molded Package Width
6.506.386.25.256.251.246EOverall Width
0.150.100.05.006.004.002A1Standoff §
0.950.900.85.037.035.033A2Molded Package Thickness
1.10.043AOverall Height
0.65.026
p
Pitch
1414
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERS*INCHESUnits
L
β
c
φ
2
1
D
n
B
p
E1
E
α
A2A1
A
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087
§ Significant Characteristic
2003 Microchip Technology Inc. DS21812B-page 23
MCP6291/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
Device:MCP6291: Single Operational Amplifier
MCP6291T: Single Operational Amplifier
(Tape and Reel) (SOIC, MSOP)
MCP6292: Dual Operational Amplifier
MCP6292T: Dual Operational Amplifier
(Tape and Reel) (SOIC, MSOP)
MCP6293: Single Operational Amplifier with Chip
Select
MCP6293T: Single Operational Amplifier with Chip
Select (Tape and Reel) (SOIC, MSOP)
MCP6294: Quad Operational Amplifier
MCP6294T: Quad Operational Amplifier
(Tape and Reel) (SOIC, TSSOP)
Temperature Range: E = -40°C to +125°C
Package: MS = Plastic MSOP, 8-lead
P = Plastic DIP (300 mil Body), 8-lead, 14-lead
SN = Plastic SOIC, (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
ST = Plastic TSSOP (4.4mm Body), 14-lead
PAR T N O. X/XX
PackageTemperature
Range
Device
Examples:
a) MCP6291-E/SN: Extended Temperature,
8LD SOIC package
b) MCP6291-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6291-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6291T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
e) MCP6291T-E/MS: Tape and Reel,
Extended Temperature,
8LD MSOP package.
a) MCP6292-E/SN: Extended Temperature,
8LD SOIC package
b) MCP6292-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6292-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6292T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
e) MCP6292T-E/MS: Tape and Reel,
Extended Temperature,
8LD MSOP package.
a) MCP6293-E/SN: Extended Temperature,
8LD SOIC package
b) MCP6293-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6293-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6293T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
e) MCP6293T-E/MS: Tape and Reel,
Extended Temperature,
8LD MSOP package.
a) MCP6294-E/P: Extended Temperature,
14LD PDIP package
b) MCP6294T-E/SL: Tape and Reel,
Extended Temperature,
14LD SOIC package.
c) MCP6294-E/SL: Extended Temperature,
14LD SOIC package.
d) MCP6294-E/ST: Extended Temperature,
14LD TSSOP package.
e) MCP6294T-E/ST: Tape and Reel,
Extended Temperature,
14LD TSSOP package.
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
MCP6291/2/3/4
DS21812B-page 24 2003 Microchip Technology Inc.
NOTES:
2003 Microchip Technology Inc. DS21812B-page 25
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,
SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS21812B-page 26 2003 Microchip Technology Inc.
M
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support: 480-792-7627
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Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848
Fax: 978-692-3821
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
2767 S. Albright Road
Kokomo, IN 46902
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888
Fax: 949-263-1338
Phoenix
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966
Fax: 480-792-4338
San Jose
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950
Fax: 408-436-7955
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Australia
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Unit 915
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100
Fax: 86-10-85282104
China - Chengdu
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-86766200
Fax: 86-28-86766599
China - Fuzhou
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506
Fax: 86-591-7503521
China - Hong Kong SAR
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Shanghai
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700
Fax: 86-21-6275-5060
China - Shenzhen
Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
Shenzhen 518033, China
Tel: 86-755-82901380
Fax: 86-755-8295-1393
China - Shunde
Room 401, Hongjian Building
No. 2 Fengxiangnan Road, Ronggui Town
Shunde City, Guangdong 528303, China
Tel: 86-765-8395507 Fax: 86-765-8395571
China - Qingdao
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 86-532-5027355 Fax: 86-532-5027205
India
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
Singapore
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Kaohsiung Branch
30F - 1 No. 8
Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Austria
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45-4420-9895 Fax: 45-4420-9910
France
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy
Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
P. A. De Biesbosch 14
NL-5152 SC Drunen, Netherlands
Tel: 31-416-690399
Fax: 31-416-690340
United Kingdom
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
07/28/03
WORLDWIDE SALES AND SERVICE
