ispGDS22/18/14 in-system programmable Generic Digital Switch TM Functional Block Diagram (ispGDS22) * ELECTRONIC SIGNATURE FOR IDENTIFICATION I/O Cell B0 I/O Cell I/O Cell A10 B1 I/O Cell I/O Cell I/O Cell A9 B2 A8 I/O Cell I/O Cell B3 I/O Cell A7 I/O Cell A6 PROGRAMMABLE SWITCH MATRIX B4 I/O Cell I/O Cell A5 B5 I/O Cell I/O Cell A4 B6 I/O Cell I/O Cell I/O Cell A3 I/O Cell A2 B7 I/O Cell B8 * APPLICATIONS INCLUDE: -- Software-Driven Hardware Configuration -- Multiple DIP Switch Replacement -- Software Configuration of Add-In Boards -- Configurable Addressing of I/O Boards -- Multiple Clock Source Selection -- Cross-Matrix Switch A1 I/O Cell * E2 CELL TECHNOLOGY -- Non-Volatile Reprogrammable Cells -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100ms) -- 20 Year Data Retention I/O Cell B9 * IN-SYSTEM PROGRAMMABLE (5-VOLT ONLY) -- Programming Time of Less Than One Second -- 4-Wire Programming Interface -- Minimum 10,000 Program/Erase Cycles A0 I/O Cell * FLEXIBLE I/O MACROCELL -- Any I/O Pin Can be Input, Output, or Fixed TTL High or Low -- Programmable Output Polarity -- Multiple Outputs Can be Driven by One Input Bank A * HIGH-SPEED SWITCH MATRIX -- 7.5 ns Maximum Propagation Delay -- Typical Icc = 25 mA -- UltraMOS(R) Advanced CMOS Technology B10 Features Bank B I/O Cell Closed only when C0=1 and C1=0 4:1 MUX Vcc 01 10 Switch Matrix 11 C0 00 C2 C1 Description The Lattice Semiconductor ispGDSTM family is an ideal solution for reconfiguring system signal routing or replacing DIP switches used for feature selection. With today's demands for customer ease of use, there is a need for hardware which is easily reconfigured electronically without dismantling the system. The ispGDS devices address this challenge by replacing conventional switches with a software configurable solution. Since each I/O pin can be set to an independent logic level, the ispGDS devices can replace most DIP switch functions with about half the pin count, and without the need for additional pull-up resistors. In addition to DIP switch replacement, the ispGDS devices are useful as signal routing cross-matrix switches. This is the only non-volatile device on the market which can provide this flexibility. With a maximum tpd of 7.5ns, and a typical active Icc of only 25 mA, these devices provide maximum performance at very low power levels. The ispGDS devices may be programmed in-system, using 5 volt only signals, through a simple 4-wire programming interface. The ispGDS devices are manufactured using Lattice Semiconductor's advanced non-volatile E2CMOS process which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently. Each I/O macrocell can be configured as an input, an inverting or non-inverting output, or a fixed TTL high or low output. Any I/O pin can be driven by any other I/O pin in the opposite bank. A single input can drive one or more outputs in the opposite bank, allowing a signal (such as a clock) to be distributed to multiple destinations on the board, under software control. The I/Os accept and drive TTL voltage levels. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor is able to deliver 100% field programmability and functionality of all Lattice Semiconductor products. In addition, 10,000 erase/write cycles and data retention in excess of 20 years are specified. Copyright (c) 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268--8037; http://www.latticesemi.com ispgds_02 July 1997 Specifications ispGDS ispGDS Ordering Information Commercial Grade Specifications Matrix Size I/O Pins Tpd (ns) Isb (mA) Icc (mA) 11 x 11 22 7.5 25 40 9x9 18 7.5 25 40 7x7 14 7.5 25 40 Ordering # Package ispGDS22-7P 28-Pin Plastic DIP ispGDS22-7J 28-Lead PLCC ispGDS18-7P 24-Pin Plastic DIP ispGDS14-7P 20-Pin Plastic DIP ispGDS14-7J 20-Lead PLCC Part Number Description XXXXXXXX _ XX X X Grade ispGDS22 Device Name ispGDS18 ispGDS14 Blank = Commercial Package P = Plastic DIP J = PLCC Speed (ns) 2 Specifications ispGDS Pin Configuration 28-Pin DIP 24-Pin DIP A1 B1 A1 B1 A2 B2 A2 B2 A1 B1 A2 B2 28 SDI A3 A4 Vcc ispGDS 22 7 A5 21 B3 A3 B4 Vcc B5 A4 GND A5 24 SDO SDI SDO ispGDS 18 6 18 Vcc B4 A3 GND B5 A6 B6 SCLK A7 B7 A8 B8 A8 A9 B9 B2 B1 B0 A0 A1 SDI A2 2 28 26 25 5 7 A6 23 ispGDS22 A5 9 21 A7 11 SDO SDI B3 Vcc B4 A3 B5 B8 B9 A0 MODE B0 B1 20 18 4 A4 ispGDS14 6 16 3 B3 GND 14 8 10 A5 B7 B2 SDO GND SCLK 19 18 16 B10 A10 14 A9 12 A1 2 B6 A8 MODE B6 20-Pin PLCC A4 Vcc 11 B10 A2 A3 10 B8 28-Pin PLCC 4 SCLK MODE A5 A6 15 GND 15 SCLK B7 14 B3 B4 A7 A10 SDO ispGDS 5 14 A4 MODE 13 B0 B5 B6 12 20 SDI B3 A6 MODE 1 A0 A0 1 1 B0 B0 A0 20-Pin DIP A6 12 B6 B5 B4 SCLK Specifications ispGDS ispGDS Family Overview Device Programming There are three members of the ispGDS family, the ispGDS22, ispGDS18, and ispGSD14. The numerical portion of the part name indicates the number of I/O cells available. All of the devices are available in a DIP package, with the ispGDS22 and ispGDS14 also available in a PLCC package. Each of the devices operate identically, with the only difference being the number of I/O cells available. The ispGDS family of devices uses a standard JEDEC file, as used for programmable logic devices, to describe device programming information. Popular logic compilers, such as ABEL and CUPL, can produce the JEDEC files for these devices. The JEDEC files can be used to program the ispGDS devices in a number of ways, which are shown in the section titled ISP Architecture and Programming. The ispGDS devices are all programmed through a four-pin interface, using TTL level signals. The four dedicated programming pins are named MODE, SDI, SDO, and SCLK. No highvoltage is needed, as the voltages needed for programming are generated internally. Programming of the entire device, including erasure, can be done in less than one second. During the programming operation, all I/O pins will be tri-stated. Further details of the programming process can be found in the InSystem Programming section later in this datasheet. Electronic Signature An electronic signature word is provided with every ispGDS device. It contains 32 bits of reprogrammable memory that can contain user defined data. Some uses include user ID codes, revision numbers, or inventory control. NOTE: The electronic signature is included in checksum calculations. Changing the electronic signature will alter the fuse checksum in the JEDEC fusemap. The I/O cells in each device are divided equally into two banks (Bank A and Bank B). Each I/O cell can be configured as an input, an inverting output, a non-inverting output, or set to a fixed TTL high or low. A switch matrix connects the I/O banks, allowing an I/O cell in one bank to be connected to any of the I/ O cells in the other bank. A single I/O cell configured as an input can drive one or more I/O cells in the other bank. The full I/O macrocell, which is identical for each of the I/O pins, is shown below. The allowable configurations are shown on the following page. In-System Programmability The ispGDS family of devices feature In-System Programmable technology. By integrating all the high voltage programming circuitry on-chip, programming can be accomplished by simply shifting data into the device. Once the function is programmed, the non-volatile E2CMOS cells will not lose the pattern even when the power is turned off. All necessary programming is done via four TTL level logic interface signals. These four signals are fed into the on-chip programming circuitry where a state machine controls the programming. The interface signals are Serial Data In (SDI), Serial Data Out (SDO), Serial Clock (SCLK) and Mode (MODE) control. For details on the operation of the internal state machine and programming of ispGDS devices please refer to the ISP Architecture and Programming section in this Data Book. 4 Specifications ispGDS I/O Macrocell Closed only when C0=1 and C1=0 4:1 MUX Vcc 01 10 Switch Matrix 11 C0 00 C1 C2 I/O Macrocell Configurations Configuration for Active High Output From Switch Matrix - C0 = 0. - C1 = 1. - C2 = 1. Configuration for Active Low Output From Switch Matrix - C0 = 0. - C1 = 0. - C2 = 1. Configuration for Fixed TTL High Output Vcc - C0 = 0. - C1 = 1. - C2 = 0. Configuration for Fixed TTL Low Output - C0 = 0. - C1 = 0. - C2 = 0. Configuration for Dedicated Input To Switch Matrix - C0 = 1. - C1 = 0. - C2 = 1. Note 1: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Note 2: The default configuration for unused pins is for all configuration bits set to one, which produces a tri-stated output. 5 Specifications ispGDS Absolute Maximum Ratings(1) Recommended Operating Cond. Supply voltage VCC ........................................ -.5 to +7V Input voltage applied .......................... -2.5 to VCC +1.0V Off-state output voltage applied ......... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Ambient Temperature with Power Applied ........................................... -55 to 125C Commercial Devices: Ambient Temperature (TA) ............................... 0 to 75C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V 1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL VIL VIH IIL IIH VOL VOH IOL IOH IOS1 MIN. TYP.2 MAX. UNITS Input Low Voltage Vss - 0.5 -- 0.8 V Input High Voltage 2.0 -- Vcc+1 V PARAMETER CONDITION Input or I/O Low Leakage Current 0V VIN VIL (MAX.) -- -- -10 A Input or I/O High Leakage Current 3.5V VIN VCC -- -- 10 A Output Low Voltage IOL = MAX. Vin = VIL or VIH -- -- 0.5 V Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 -- -- V Low Level Output Current -- -- 8 mA High Level Output Current -- -- -3.2 mA -30 -- -130 mA L-7 -- 15 25 mA L -7 -- 25 40 mA Output Short Circuit Current COMMERCIAL ISB Standby Power Inputs = 0V VCC = 5V VOUT = 0.5V Outputs open TA = 25C Supply Current ICC Operating Power VIL = 0.5V VIH = 3.0V Supply Current ftoggle = 15MHz Outputs Open 1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 2) Typical values are at Vcc = 5V and TA = 25 C Capacitance (TA = 25C, f = 1.0 MHz) SYMBOL CI/O PARAMETER I/O Capacitance (as input or output) *Characterized but not 100% tested. 6 MAXIMUM* UNITS TEST CONDITIONS 8 pF VCC = 5.0V, VI = 2.0V Specifications ispGDS AC Switching Characteristics Over Recommended Operating Conditions COM PARAMETER tpd fmax twh twl TEST COND. DESCRIPTION MIN. MAX. UNITS A Input to Output Delay One Input Driving One Output 1 7.5 ns A Maximum Input Frequency One Output Switching -- 50 MHz A Input Pulse Duration, High 10 -- ns A Input Pulse Duration, Low 10 -- ns Switching Waveforms VALID INPUT INP UT tw h tpd twl INP UT 1/ fmax OU TP U T Input Pulse Width/ Fmax Input to Output Delay Switching Test Conditions Input Pulse Levels +5V GND to 3.0V Input Rise and Fall Times 2ns 10% - 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels R1 1.5V Output Load See Figure FROM OUTPUT (O/Q) UNDER TEST 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure) Test Condition A TEST POINT R2 R1 R2 CL 470 390 50pF C L* *C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE 7 Specifications ispGDS Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc Delta Tpd vs # of Outputs Switching Input Clamp (Vik) 0 2.25 PT H->L 2 PT L->H 1.1 1 0.9 FALL 1.25 1 4.75 5.00 5.25 80 70 90 1 5.50 2 3 4 6 7 8 9 10 11 -2.00 0.8 RISE 10 FALL 8 6 4 2 0 25 50 75 100 0 125 50 Temperature (deg. C) 100 150 200 250 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 300 Vin (V) Voh vs Ioh Voh (V) 2 1.5 1 5 4.25 4 4 Voh (V) 3 3 2 0 80.00 0.00 10.00 20.00 Iol (mA) 30.00 40.00 0.00 50.00 60.00 0.90 0.80 1.1 1 0.9 5.25 Supply Voltage (V) 5.50 1.20 1.10 1.00 0.90 0.8 5.00 4.00 1.30 Normalized Icc Normalized Icc 1.00 3.00 Normalized Icc vs Freq. 1.2 1.10 2.00 Ioh(mA) Normalized Icc vs Temp 1.20 4.75 1.00 Ioh(mA) Normalized Icc vs Vcc 4.50 3.5 3 0 60.00 3.75 3.25 1 0.5 40.00 2 Voh vs Ioh 2.5 20.00 3 Output Loading (pF) Vol vs Iol 0.00 4 0 -4 0 5 1 -2 0.7 0.00 6 Delta Icc (mA) Delta Tpd (ns) 0.9 -0.50 7 12 PT L->H -1.00 Delta Icc vs Vin (1 input) 14 PT H->L -25 -1.50 Vik (V) Delta Tpd vs Output Loading 1 Vol (V) 5 Number of Outputs Switching 1.3 -55 50 0.25 Normalized Tpd vs Temp 1.1 40 60 Supply Voltage (V) 1.2 30 0.75 0.5 0 4.50 Normalized Icc 20 RISE 1.75 1.5 0.8 Normalized Tpd 10 Iik (mA) 1.2 Delta Tpd (ns) Normalized Tpd 1.3 -55 -25 0 25 50 75 100 Temperature (deg. C) 8 125 0 25 50 75 Frequency (MHz) 100