CS4349-CZZ - Cirrus Logic, Inc. - Datasheet.Directory

http://www.cirrus.com

192 kHz DAC w/ Volume Control and 1 Vrms @ 3.3 V

Features

Advanced Multi-bit Delta-Sigma Architecture

101 dB Dynamic Range

-91 dB THD+N at 5.0 V

-84 dB THD+N at 3.3 V

24-Bit Conversion

Supports Audio Sample Rates Up to 192 kHz

Low-Latency Digital Filtering

Single-Ended Analog Output Architecture

Automatic Sample-Rate Range Detection

Popguard® Technology for Control of Clicks

and Pops

– Hardware Popguard Disable for Fast

Startups

Supports All Standard Serial Audio Formats

Including Time-Division Multiplexed (TDM)

+3.3 V or +5.0 V Analog Supply

+1.5 V to +5.0 V Logic Supplies for Serial Port

+3.3 V to +5.0 V Control Port Interface

Control Port Mode Features

SPI™ and I²C® Modes

ATAPI Mixing

Mute Control for Individual Channels

Digital Volume Control with Soft Ramp

– 127.5 dB Attenuation

– 1/2 dB Step Size

– Zero Crossing Click-Free Transitions

PCM

Serial

Interface

Serial Audio Input

Right

Channel

Output

Left

Channel

Output

Reset

3.3 V to 5 V

Hardware

Configuration

Hardware or I2C/

SPI Control Data

1.5 V to 5 V

Internal Voltage

Reference

and Regulation

Interpolation

Filter with

Volume

Control

Interpolation

Filter with

Volume

Control

Multibit ΔΣ

Modulator

Multibit ΔΣ

Modulator

Level Translator Level Translator

Amp

Filter

Amp

Filter

Left and

Right Mute

Controls

External

Mute

Control

DAC

3.3 V to 5 V

AUGUST '07

DS782F1

CS4349

2DS782F1

CS4349

Description

The CS4349 is a complete stereo digital-to-analog system including digital interpolation, 5th-order multi-bit delta-

sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing, and analog filtering. The

advantages of this architecture include ideal linearity, no distortion mechanisms due to resistor matching errors, no

linearity drift over time and temperature, tolerance to clock jitter, and a minimal set of external components.

The CS4349 supports all standard digital audio interface formats, including TDM.

The CS4349 is available in a 24-pin TSSOP package in both Commercial (-40° to +85°C) and Automotive grades

(-40° to +105°C). The CDB4349 Customer Demonstration board is also available for device evaluation and imple-

mentation suggestions. Please refer to “Ordering Information” on page 40 for complete ordering information.

These features are ideal for cost-sensitive, two-channel audio systems, including DVD players and recorders, set-

top boxes, digital TVs, mini-component systems, musical instruments and automotive audio systems.

DS782F1 3
CS4349
TABLE OF CONTENTS
PIN DESCRIPTION.................................................................................................................................. 6
CHARACTERISTICS AND SPECIFICATIONS....................................................................................... 8
RECOMMENDED OPERATING CONDITIONS .......................................................................................... 8
ABSOLUTE MAXIMUM RATINGS............................................................................................................... 8
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ) ................................................................... 9
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DZZ) .................................................................. 10
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE............................................ 12
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE.............................................................. 13
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT.................................................... 14
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT................................................... 15
DIGITAL CHARACTERISTICS .................................................................................................................. 16
POWER AND THERMAL CHARACTERISTICS........................................................................................ 16
TYPICAL CONNECTION DIAGRAM   .................................................................................................. 17
APPLICATIONS .................................................................................................................................... 18
1 Sample Rate Range and Oversampling Mode Detect................................................................... 18
1.1 Sample Rate Auto-Detect .................................................................................................... 18
2 System Clocking ............................................................................................................................ 18
3 Digital Interface Format ................................................................................................................. 19
3.1 Time-Division Multiplex (TDM) Mode ................................................................................... 20
4 De-Emphasis ................................................................................................................................. 21
5 Mute Control .................................................................................................................................. 21
6 Recommended Power-Up Sequence ............................................................................................ 21
6.1 Stand-Alone Mode ............................................................................................................... 21
6.2 Control Port Mode ................................................................................................................ 22
7 Popguard Transient Control .......................................................................................................... 22
7.1 Power-Up ............................................................................................................................. 22
7.2 Power-Down......................................................................................................................... 22
7.3 Discharge Time .................................................................................................................... 22
8 Analog Output and Filtering........................................................................................................... 23
9 Grounding and Power Supply Arrangements ................................................................................ 23
9.1 Capacitor Placement............................................................................................................ 23
STAND-ALONE OPERATION............................................................................................................... 24
1 Serial Port Format Selection.......................................................................................................... 24
2 De-Emphasis Control .................................................................................................................... 24
3 Popguard Transient Control .......................................................................................................... 24
CONTROL PORT OPERATION ............................................................................................................ 25
1 MAP Auto Increment ..................................................................................................................... 25
2 I²C Mode........................................................................................................................................ 25
2.1 I²C Write ............................................................................................................................... 25
2.2 I²C Read............................................................................................................................... 25
3 SPI Mode....................................................................................................................................... 26
3.1 SPI Write .............................................................................................................................. 26
3.2 SPI Read.............................................................................................................................. 27
4 Memory Address Pointer (MAP) ................................................................................................... 27
4.1 INCR (Auto Map Increment Enable) .................................................................................... 27
4.2 MAP (Memory Address Pointer) .......................................................................................... 27
REGISTER QUICK REFERENCE ......................................................................................................... 28
REGISTER DESCRIPTION ................................................................................................................... 29
1 Device and Revision ID - Register 01h.......................................................................................... 29
2 Mode Control - Register 02h ......................................................................................................... 29
2.1 Digital Interface Format (DIF[2:0]) Bits 6-4 .......................................................................... 29
2.2 De-Emphasis Control (DEM[1:0]) Bits 3-2 ........................................................................... 30

4DS782F1
CS4349
2.3 Functional Mode (FM[1:0]) Bits 1-0...................................................................................... 30
3 Volume Mixing and Inversion Control - Register 03h .................................................................... 30
3.1 Channel A Volume = Channel B Volume (VOLB=A) Bit 7 ................................................... 30
3.2 Invert Signal Polarity (INVERT_A) Bit 6 ............................................................................... 30
3.3 Invert Signal Polarity (INVERT_B) Bit 5 ............................................................................... 31
3.4 ATAPI Channel Mixing and Muting (ATAPI[3:0]) Bits 3-0 .................................................... 31
4  Mute Control - Register 04h ......................................................................................................... 32
4.1 Auto-Mute (AMUTE) Bit 7 .................................................................................................... 32
4.2 AMUTEC = BMUTEC (MUTEC A=B) Bit 5 .......................................................................... 32
4.3 Channel A Mute (MUTE_A) Bit 4 & Channel B Mute (MUTE_B) Bit 3................................. 32
5 Channel A & B Volume Control - Register 05h & 06h ................................................................... 33
6 Ramp and Filter Control - Register 07h......................................................................................... 33
6.1 Soft Ramp and Zero Cross Control (SZC[1:0]) Bits 7-6 ....................................................... 33
6.2 Soft Volume Ramp-Up After Error (RMP_UP) Bit 5 ............................................................. 34
6.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) Bit 4........................................... 34
6.4 Interpolation Filter Select (FILT_SEL) Bit 2.......................................................................... 34
7 Misc. Control - Register 08h .......................................................................................................... 35
7.1 Power Down (PDN) Bit 7...................................................................................................... 35
7.2 Freeze Controls (FREEZE) Bit 5.......................................................................................... 35
7.3 Popguard Enable (POPG_EN) Bit 4 .................................................................................... 35
FILTER PLOTS    .................................................................................................................................. 36
PARAMETER DEFINITIONS............................................................................................................... 38
PACKAGE DIMENSIONS ................................................................................................................... 39
THERMAL CHARACTERISTICS ............................................................................................................... 39
ORDERING INFORMATION ............................................................................................................... 40
REVISION HISTORY  .......................................................................................................................... 40

DS782F1 5
CS4349
LIST OF FIGURES
Figure 1. Output Test Load ........................................................................................................................ 11
Figure 2. Maximum Loading....................................................................................................................... 11
Figure 3. THD+N vs Output Amplitude for VA = 5.0 V ............................................................................... 11
Figure 4. THD+N vs Output Amplitude for VA = 3.3 V ............................................................................... 11
Figure 5. THD+N vs Output Amplitude for VA = 3.14 V ............................................................................. 11
Figure 6. Serial Port Timing, Non-TDM Mode............................................................................................ 14
Figure 7. Serial Port Timing, TDM Mode.................................................................................................... 14
Figure 8. Control Port Timing - I²C Format................................................................................................. 14
Figure 9. Control Port Timing - SPI Mode .................................................................................................. 15
Figure 10. Typical Connection Diagram..................................................................................................... 17
Figure 11. Left-Justified up to 24-Bit Data.................................................................................................. 19
Figure 12. I²S, up to 24-Bit Data ................................................................................................................ 19
Figure 13. Right-Justified Data................................................................................................................... 19
Figure 14. TDM Mode Connection Diagram .............................................................................................. 20
Figure 15. TDM Mode Timing .................................................................................................................... 20
Figure 16. De-Emphasis Curve.................................................................................................................. 21
Figure 17. Passive Single-Ended Output Filter .......................................................................................... 23
Figure 18. Control Port Timing, I²C Mode .................................................................................................. 26
Figure 19. Control Port Timing, SPI Mode ................................................................................................. 27
Figure 20. De-Emphasis Curve.................................................................................................................. 30
Figure 21. ATAPI Block Diagram ............................................................................................................... 31
Figure 22. Stopband Rejection (fast), all Modes ........................................................................................ 36
Figure 23. Stopband Rejection (slow), all Modes....................................................................................... 36
Figure 24. Single-Speed (fast) Passband Detail ........................................................................................ 36
Figure 25. Single-Speed (slow) Passband Detail....................................................................................... 36
Figure 26. Double-Speed (fast) Passband Detail....................................................................................... 36
Figure 27. Double-Speed (slow) Passband Detail ..................................................................................... 36
Figure 28. Quad-Speed (fast) Passband Detail ......................................................................................... 37
Figure 29. Quad-Speed (slow) Passband Detail........................................................................................ 37
LIST OF TABLES
Table 1. CS4349 Auto-Detect .................................................................................................................... 18
Table 2. Digital Interface Format - Stand-Alone Mode............................................................................... 24
Table 3. Digital Interface Formats .............................................................................................................. 29
Table 4. ATAPI Decode ............................................................................................................................. 31
Table 5. Example Digital Volume Settings ................................................................................................. 33

6DS782F1

CS4349

1. PIN DESCRIPTION

Pin Name #Pin Description

VLC 5 Control Interface Power (Input) - Positive power for the hardware/software control interface

VD_FILT 6 Regulator Voltage (Output) - Filter connection for internal voltage regulator

GND 7, 19 Ground (Input) - Ground reference

VLS 9 Serial Audio Interface Power (Input) - Positive power for the serial audio interface

SCLK 10 Serial Clock (Input) - Serial bit-clock for the serial audio interface

SDIN 11 Serial Audio Data Input (Input) - Input for two’s complement serial audio data

LRCK 12 Left/Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial

audio data line

TSTO 13 Test Output (Output) - This pin needs to be floating and not connected to any trace or plane.

TSTO 14

23 Test Output (Output) - These pins need to be floating and not connected to any trace or plane.

AOUTA

AOUTB

Analog Outputs (Output) - The full-scale output level is specified in “DAC Analog Characteristics -

Commercial (-CZZ)” on page 9.

AMUTEC

BMUTEC

21 Mute Control (Output) - Control signals for optional mute circuit

VBIAS 17 Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC

VA 18 Analog Power (Input) - Positive power supply for the analog section

VQ 20 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage

RST 24 Reset (Input) - When pulled low, device will power down and reset all internal registers to their default

settings.

DIF2(AD1/CDOUT) RST

DEM(AD0/CS)TSTO

DIF0(SDA/CDIN) AOUTB

DIF1(SCL/CCLK) BMUTEC

VLC VQ

VD_FILT GND

GND VA

POPGUARD(TSTO) VBIAS

VLS AMUTEC

SCLK AOUTA

SDIN TSTO

LRCK TSTO

817

12 13

DS782F1 7

CS4349

Control Port Definitions

AD1/CDOUT 1 Address Bit 1 / Serial Control Data Out (I/O) - Chip address bit 1 in I²C Mode or data output in SPI Mode

AD0/CS 2Address Bit 0 / Chip Select (Input) - Chip address bit 0 in I²C Mode or Chip Select in SPI Mode

SDA/CDIN 3 Serial Control Data In (I/O) - Input/Output for I²C data. Input for SPI data

SCL/CCLK 4 Serial Control Port Clock (Input) - Serial clock for the control port interface

TSTO 8 Test Output (Output) - This pin needs to be floating and not connected to any trace or plane.

Stand-Alone Definitions

DIF0

DIF1

DIF2

Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial

Clock, and Serial Audio Data

DEM 2De-emphasis (Input) - Selects the standard 15 μs/50 μs digital de-emphasis filter response for

44.1 kHz sample rates

POPGUARD 8Popguard Disable (Input/Output) - At RST this pin is an input to disable PopGuard when pulled high;

Otherwise leave floating. After RST is released this pin becomes TSTO.

8DS782F1

CS4349

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

GND = 0 V; all voltages with respect to ground.

ABSOLUTE MAXIMUM RATINGS

GND = 0 V; all voltages with respect to ground.(Note 1)

Notes: 1. Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

2. Any pin except supplies.

Parameters Symbol Min Typ Max Units

DC Power Supply Analog power VA 4.75 5.0 5.25 V

VA 3.14 3.3 3.46 V

Serial Audio Interface power VLS 1.35 3.3 5.25 V

Control Interface power VLC 3.14 3.3 5.25 V

Ambient Operating Temperature (Power Applied)

Commercial (-CZZ) TA-40 - +85 °C

Automotive (-DZZ) TA-40 - +105 °C

Parameters Symbol Min Max Units

DC Power Supply Analog power VA -0.3 6.0 V

Serial Audio Interface power VLS -0.3 6.0 V

Control Interface power VLC -0.3 6.0 V

Input Current (Note 2) Iin -±10mA

Digital Input Voltage Serial Audio Interface VIN-LS -0.3 VLS+ 0.4 V

Control Interface VIN-LC -0.3 VLC+ 0.4 V

Ambient Operating Temperature (power applied) TA-55 125 °C

Storage Temperature Tstg -65 150 °C

DS782F1 9
CS4349
DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CZZ)
Test conditions (unless otherwise specified): VLS = VLC = 3.3 V; TA = 25° C; input test signal is a 997 Hz sine 
wave; Valid with the recommended capacitor values on VFILT, VQ, and VBIAS and output circuit as shown in the typical con-
nection diagram in Figure 10 and Figure 17; Fs = 48 kHz, 96 kHz, and 192 kHz; measurement bandwidth 10 Hz to 
20 kHz.  
Notes: 3. One-half LSB of triangular PDF dither is added to data. See Figure 3, Figure 4, and Figure 5 for details
on THD+N performance.
4. RL and CL represent the minimum resistance and maximum capacitance required for the CS4349’s in-
ternal op-amp to remain stable. See Figure 1 and Figure 2 for more details.
Parameter Symbol Min Typ Max Unit
VA = 5.0 V 
Dynamic Range (Note 3)  24-bit    A-Weighted
unweighted
16-bit    A-Weighted
 unweighted
98
95
-
-
101
98
95
92
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 3)
 24-bit               0 dB
-20 dB
-60 dB
16-bit               0 dB
         -20 dB
-60 dB
THD+N
-
-
-
-
-
-
-
-91
-78
-38
-90
-72
-32
-85
-
-35
-
-
-
dB
dB
dB
dB
dB
dB
VA = 3.3 V 
Dynamic Range (Note 3)  24-bit    A-Weighted
unweighted
16-bit    A-Weighted
 unweighted
98
95
-
-
101
98
95
92
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 3)
 24-bit               0 dB
-2 dB
-20 dB
-60 dB
16-bit               0 dB
         -20 dB
-60 dB
THD+N
-
-
-
-
-
-
-
-86
-91
-78
-38
-83
-72
-32
-79
-
-
-35
-
-
-
dB
dB
dB
dB
dB
dB
dB
VA = 5.0 to 3.3 V   
Interchannel Isolation (1 kHz) - 100 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 0.25 dB
Gain Drift - -400 - ppm/°C
Analog Output
Full Scale Output Voltage  2.70 2.78 2.97 Vpp
Quiescent Voltage VQ-0.5•VA-VDC
Max DC Current draw from an AOUT pin IOUTmax -10-μA
Max Current draw from VQ IQmax - 100 - μA
Max AC-Load Resistance (Note 4) RL-3-kΩ
Max Load Capacitance  (Note 4) CL- 100 - pF
Output Impedance ZOUT - 100 - Ω

10 DS782F1
CS4349
DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DZZ)
Test conditions (unless otherwise specified): VLS = 1.35 V to 5.25 V, VLC = 3.14 V to 5.25 V, TA = -40° C to 85° C, 
input test signal is a 997 Hz sine wave; Valid with the recommended capacitor values on VFILT, VQ, and VBIAS and output 
circuit as shown in the typical connection diagram in Figure 10and Figure 17; Fs = 48 kHz, 96 kHz, and 192 kHz; mea-
surement bandwidth 10 Hz to 20 kHz.  
Parameter Symbol Min Typ Max Unit
VA = 4.75 V to 5.25 V
Dynamic Range (Note 3)  24-bit    A-Weighted
unweighted
16-bit    A-Weighted
 unweighted
95
92
-
-
101
98
95
92
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 3)
 24-bit               0 dB
-20 dB
-60 dB
16-bit               0 dB
         -20 dB
-60 dB
THD+N
-
-
-
-
-
-
-91
-78
-38
-90
-72
-32
-85
-
-32
-
-
-
dB
dB
dB
dB
dB
dB
VA = 3.14 V to 3.46 V
Dynamic Range (Note 3)  24-bit    A-Weighted
unweighted
16-bit    A-Weighted
 unweighted
95
91
-
-
101
98
95
92
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion + Noise (Note 3)
 24-bit               0 dB
-2 dB
-20 dB
-60 dB
16-bit               0 dB
         -20 dB
-60 dB
THD+N
-
-
-
-
-
-
-
-81
-91
-78
-38
-83
-72
-32
-50
-
-
-31
-
-
-
dB
dB
dB
dB
dB
dB
VA = 3.14 to 5.25 V  
Interchannel Isolation (1 kHz) - 100 - dB
DC Accuracy
Interchannel Gain Mismatch - 0.1 0.25 dB
Gain Drift - -400 - ppm/°C
Analog Output
Full Scale Output Voltage  2.63 2.78 3.05 Vpp
Quiescent Voltage VQ-0.5•VA-VDC
Max DC Current draw from an AOUT pin IOUTmax -10-μA
Max Current draw from VQ IQmax -100-μA
Max AC-Load Resistance (Note 4) RL-3-kΩ
Max Load Capacitance  (Note 4) CL-100-pF
Output Impedance ZOUT -100-Ω

DS782F1 11

CS4349

Figures 3 through 5 show typical THD+N performance for CS4349 devices that exhibit the maximum full scale out-

put voltages as specified in the DAC Analog Characteristics tables (see page 9 and 10). With decreasing VA,

THD+N performance is increasingly affected by the full scale output voltage and temperature, with higher full scale

output voltage and lower temperatures corresponding to lower THD+N performance.

AOUTx +

3.3 µF

Analog

Output

GND

RLCL

100

2.5

51015

Safe Operating

Region

Capacitive Load -- C (pF)

Resistive Load -- R (k

)

125

Figure 1. Output Test Load Figure 2. Maximum Loading

CS4349

-3-2.5-2-1.5-1-0.50

-100

-90

-80

-70

-60

-50

-40

-30

Output Amplitude(dB)

THD+N (dB)

TA = -40° C

TA = 25° C

TA = 85° C

-3-2.5-2-1.5-1-0.50

-100

-90

-80

-70

-60

-50

-40

-30

Output Amplitude(dB)

THD+N (dB)

TA = -40° C

TA = 25° C

TA = 85° C

Figure 3. THD+N vs Output Amplitude for VA = 5.0 V Figure 4. THD+N vs Output Amplitude for VA = 3.3 V

-3-2.5-2-1.5-1-0.50

-100

-90

-80

-70

-60

-50

-40

-30

Output Amplitude(dB)

THD+N (dB)

TA = -40° C

TA = 25° C

TA = 85° C

Figure 5. THD+N vs Output Amplitude for VA = 3.14 V

12 DS782F1
CS4349
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam-
ple rate by multiplying the given characteristic by Fs. Amplitude vs. Frequency plots of this data are available in the 
“Filter Plots” on page 36.
Notes: 5. Response is clock dependent.
6. The Measurement Bandwidth is from stopband to 3 Fs.
7. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in Stand-
Alone Mode.
8. Slow Roll-off interpolation filter is only available in Control Port Mode.
Parameter Min Typ Max Unit
Fast Roll-Off
Passband (Note 5) -0.01 dB corner (Single Speed) 0 - .454 Fs
-0.1 dB corner (Double Speed) 0 - .42 Fs
-0.2 dB corner (Quad Speed) 0 - .27 Fs
-3 dB corner (All Speed Modes) 0 - .499 Fs
Frequency Response 10 Hz to 20 kHz Single Speed -0.01 - +0.01 dB
Double Speed, Quad Speed -0.02 - +0.02 dB
StopBand 0.547 - - Fs
Stop-Band Attenuation (Note 6) 102 - - dB
Total Group Delay (Fs = Output Sample Rate) - 9.4/Fs - s
Intra-channel Phase Deviation - - ±0.56/Fs s
Inter-channel Phase Deviation - - 0 s
De-emphasis Error (Note 7) Fs = 32 kHz - - ±0.23 dB
(Relative to 1 kHz) Fs = 44.1 kHz - - ±0.14 dB
Fs = 48 kHz --±0.09dB
Slow Roll-Off (Note 8)
Passband (Note 5) -0.01 dB corner (Single Speed) 0 - 0.417 Fs
-0.1 dB corner (Double Speed) 0 - .37 Fs
-0.2 dB corner (Quad Speed) 0 - .27 Fs
-3 dB corner (All Speed Modes) 0 - .499 Fs
Frequency Response 10 Hz to 20 kHz Single Speed -0.01 - +0.01 dB
Double Speed, Quad Speed -0.02 - +0.02 dB
StopBand .583 - - Fs
Stop-Band Attenuation (Note 6) 64 - - dB
Total Group Delay (Fs = Output Sample Rate) - 6.5/Fs - s
Intra-channel Phase Deviation - - ±0.14/Fs s
Inter-channel Phase Deviation - - 0 s
De-emphasis Error (Note 7) Fs = 32 kHz - - ±0.23 dB
(Relative to 1 kHz) Fs = 44.1 kHz - - ±0.14 dB
Fs = 48 kHz --±0.09dB

DS782F1 13

CS4349

SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE

Inputs: Logic 0 = GND; Logic 1 = VLS; CL=20pF.

Parameters Symbol Min Max Units

3.14 V

≤

5.25 V and 1.35 V

≤

VLS

≤

5.25 V

RMCK Output Frequency (Note ) 7.680 55.3 MHz

RMCK Output Duty Cycle 45 55 %

Input Sample Rate Single-Speed Mode 30 54

Double-Speed Mode Fs 60 108 kHz

Quad-Speed Mode 120 216

LRCK Duty Cycle (Non-TDM Mode) 40 60 %

SDIN Setup Time Before SCLK Rising Edge tds 1-ns

SDIN Hold Time After SCLK Rising Edge tdh 1-ns

4.75 V

≤

5.25 V and 3.14 V

≤

VLS

≤

5.25 V

SCLK Frequency -55.3MHz

SCLK High Time tsckh 6-ns

SCLK Low Time tsckl 6-ns

Non-TDM Mode (refer to Figure 6)

LRCK Edge to SCLK Rising Edge tlcks 11 - ns

SCLK Rising Edge to LRCK Edge tlckd 1-ns

TDM Mode (refer to Figure 7)

LRCK High Time tlrckh 6-ns

SCLK Rising to LRCK Falling Edge tfsh 3-ns

LRCK Rising Edge to SCLK Rising Edge tfss 1-ns

3.14 V

≤

VA < 4.75 V or 1.35 V

≤

VLS < 3.14 V

SCLK Frequency -27.7MHz

SCLK High Time tsckh 11 - ns

SCLK Low Time tsckl 11 - ns

Non-TDM Mode (refer to Figure 6)

LRCK Edge to SCLK Rising Edge tlcks 16 - ns

SCLK Rising Edge to LRCK Edge tlckd 1-ns

TDM Mode (refer to Figure 7)

LRCK High Time tlrckh 25 - ns

SCLK Rising to LRCK Falling Edge tfsh 8-ns

LRCK Rising Edge to SCLK Rising Edge tfss 1-ns

14 DS782F1

CS4349

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT

Inputs: Logic 0 = GND; Logic 1 = VLC; CL=20pF.

Note: 9. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

Parameter Symbol Min Max Unit

SCL Clock Frequency fscl - 100 kHz

RST Rising Edge to Start tirs 500 - ns

Bus Free Time Between Transmissions tbuf 4.7 - µs

Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs

Clock Low time tlow 4.7 - µs

Clock High Time thigh 4.0 - µs

Setup Time for Repeated Start Condition tsust 4.7 - µs

SDA Hold Time from SCL Falling (Note 9) thdd 0-µs

SDA Setup time to SCL Rising tsud 250 - ns

Rise Time of SCL and SDA trc, trc -1µs

Fall Time SCL and SDA tfc, tfc - 300 ns

Setup Time for Stop Condition tsusp 4.7 - µs

Acknowledge Delay from SCL Falling tack 300 1000 ns

tds

LRCK

(Input)

tdh

tsckh tsckl

tfsh

tfss

SCLK

(Input)

SDIN

(Input) MSB MSB-1

tlrckh

tds

MSB

tdh

MSB-1

LRCK

(input)

SCLK

(input)

SDIN

(input)

tsckh tsckl

tlcks

tlckd

Figure 6. Serial Port Timing, Non-TDM Mode Figure 7. Serial Port Timing, TDM Mode

tbuf thdst

tlow thdd

thigh

tsud

Stop Sta rt

SDA

SCL

tirs

RST

thdst

trc

tfc

tsust

tsus

Start Stop

Repeated

trd tfd

tack

Figure 8. Control Port Timing - I²C Format

DS782F1 15

CS4349

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

Inputs: Logic 0 = GND; Logic 1 = VLC; CL=20pF.

Notes: 10. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

11. Data must be held for sufficient time to bridge the transition time of CCLK.

12. For FSCK < 1 MHz.

13. CDOUT should not be sampled during this time.

Figure 9. Control Port Timing - SPI Mode

Parameter Symbol Min Max Unit

CCLK Clock Frequency fsclk -6MHz

RST Rising Edge to CS Falling tsrs 500 - ns

CCLK Edge to CS Falling (Note 10) tspi 500 - ns

CS High Time Between Transmissions tcsh 1.0 - µs

CS Falling to CCLK Edge tcss 20 - ns

CCLK Low Time tscl 66 - ns

CCLK High Time tsch 66 - ns

CDIN to CCLK Rising Setup Time tdsu 40 - ns

CCLK Rising to DATA Hold Time (Note 11) tdh 15 - ns

Rise Time of CCLK and CDIN (Note 12) tr2 -100ns

Fall Time of CCLK and CDIN (Note 12) tf2 -100ns

Transition Time from CCLK to CDOUT Valid (Note 13) tscdov -100ns

Time from CS rising to CDOUT High-Z tcscdo -100ns

tr2 tf2

tdsu tdh

tsch

tscl

CCLK

CDIN

tcss tcsh

tspi

tsrs

RST

CDOUT

tscdov tscdov tcscdo

Hi-Impedance

16 DS782F1
CS4349
DIGITAL CHARACTERISTICS
POWER AND THERMAL CHARACTERISTICS 
Notes: 14. Current consumption increases with increasing Fs within the range of a speed mode. Variance between
speed modes is small. Typ and Max values are based on Fs = 48 kHz.  
15. ILC measured with no external loading on pin 2 (SDA).
16. Power-down mode is defined as RST pin = Low with all clock and data lines held static. 
17. Valid with the recommended capacitor values on VFILT, VQ, and VBIAS+ as shown in the typical con-
nection diagram in Figure 10.
Parameters Symbol Min  Typ Max Units
High-Level Input Voltage VLC or VLS = 5.0 V VIH 0.7•VL-- V
VLC or VLS = 3.3 V VIH 2.0 - - V
VLS = 2.5 V VIH 1.7 - - V
VLS = 1.5 V VIH 0.75•VL-- V
High-Level Input Voltage VLC or VLS = 5.0 V VIL --0.35•V
LV
VLC or VLS = 3.3 V VIL --0.8V
VLS = 2.5 V VIL --0.7V
VLS = 1.5 V VIL --0.25•V
LV
Input Leakage Current Iin --±10μA
Input Capacitance - 8 - pF
Maximum MUTEC Drive Current - 2 - mA
MUTEC High-Level Output Voltage VOH -VA- V
MUTEC Low-Level Output Voltage VOL -0- V
Parameters Symbol Min Typ Max Units
Power Supply Current - Normal Operation (Note 14) VA= 5.0 V IA-2834mA
VA= 3.3 V IA-2429mA
VLS = VLC =5.0 V (Note 15) ILS -46mA
VLS = VLC =3.3 V (Note 15) ILS -25mA
VLS = VLC = 5.0 V (Note 15) ILC -1418mA
VLS = VLC = 3.3 V (Note 15) ILC -1418mA
Power Supply Current - Power-Down State (Note 16)
VA, VLS, VLC Ipd -100- μA
Power Dissipation - Normal Operation (Note 14)
VA = VLC= VLS = 5.0 V - 230 290 mW
VA = VLC= VLS = 3.3 V - 132 171 mW
Power Dissipation - Power-Down State (Note 16)
VA = VLC= VLS = 5.0 V - 0.5 - mW
VA = VLC= VLS = 3.3 V - 0.33 - mW
Power Supply Rejection Ratio (Note 17) (1 kHz) PSRR - 60 - dB
(60 Hz) PSRR - 50 - dB

DS782F1 17

CS4349

3. TYPICAL CONNECTION DIAGRAM

Digital

Audio

Source

VLS

GND

AOUTA+

0.1 µF +10 µF

µ C/

Mode

Configuration

SDIN

DIF1(SCL/CCLK)

DIF0(SDA/CDIN) 3.3 µF

AOUTA

VBIAS+

LRCK

SCLK

AOUTB+

10 µF

VD_FILT

GND

0.1 µF

+1.5 V to +3.3 V

0.1 µF

10 µF

+3.3 V

VLC

0.1 µF

+3.3 V

VLS

*Optional for PopGuard

Disable

*47 kΩ

TSTO

DIF2(AD1/CDOUT)

Single-ended Output

Filter

AOUTB

Single-ended Output

Filter

24 RST

2DEM(AD0/CS)

719

BMUTEC

AMUTEC

N.C.

8POPGUARD(TSTO)

TSTO N.C.

Figure 10. Typical Connection Diagram

CS4349

18 DS782F1

CS4349

4. APPLICATIONS

4.1 Sample Rate Range and Oversampling Mode Detect

The device operates in one of three oversampling modes based on the input sample rate. In Control Port

Mode, the allowed sample rate range in each mode will depend on how the FM[1:0] bits are configured. In

Stand-Alone Mode, the sample rate range will be according to Table 1.

4.1.1 Sample Rate Auto-Detect

The Auto-Detect feature is enabled by default. In this state, the CS4349 will auto-detect the correct mode

when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges shown in

Table 1. Sample rates outside the specified range for each mode are not supported when Auto-Detect is

enabled.

In Control Port Mode, the Auto-Detect feature can be disabled by the Functional Mode (FM[1:0]) bits in

the control port register 02h. In this state, the CS4349 will not auto-detect the correct mode based on the

input sample rate (Fs). The operational mode must then be set manually according to one of the ranges

referred to in Section 8.2.3. Sample rates outside the specified range for each mode are not supported.

In Stand-Alone Mode, it is not possible to disable auto-detect of sample rates.

4.2 System Clocking

The device requires external generation of the left/right (LRCK) and serial (SCLK) clocks. The left/right

clock, defined also as the input sample rate (Fs).

Refer to Section 4.3 for the required SCLK-to-LRCK timing associated with the selected digital interface for-

mat, and “Switching Specifications - Serial Audio Interface” on page 13 for the maximum allowed clock fre-

quencies.

Input Sample Rate (Fs) Mode

30 kHz - 54 kHz Single-Speed Mode

60 kHz - 108 kHz Double-Speed Mode

120 kHz - 216 kHz Quad-Speed Mode

Table 1. CS4349 Auto-Detect

DS782F1 19

CS4349

4.3 Digital Interface Format

The device will accept audio samples in 1 of 8 digital interface formats, as shown in Table 2 on page 24 for

Stand-Alone Mode and Table 3 on page 29 for Control Port Mode.

The desired serial audio interface format is selected via the DIF[2:0] bits in Control Port Mode (see

Section 8.2.1), or the DIF[2:0] pins in Stand-Alone Mode (see Section 5.1). For illustrations of the required

relationship between LRCK, SCLK and SDIN, see Figures 11-13. For all formats, SDIN is valid on the rising

edge of SCLK.

For more information about serial audio formats, refer to the Cirrus Logic Application Note AN282,

The 2-Channel Serial Audio Interface: A Tutorial, available at www.cirrus.com.

+3 +2 +1+5 +4

MSB -1 -2 -3 -4 -5 +3 +2 +1+5 +4

-1 -2 -3 -4

LSB MSB LSB

Left Channel Right Channel

LRCK

SCLK

SDIN

Figure 11. Left-Justified up to 24-Bit Data

+3 +2 +1+5 +4

MSB -1 -2 -3 -4 -5 +3 +2 +1+5 +4

-1 -2 -3 -4

MSB

LSB LSB

Left Channel Right Channel

LRCK

SCLK

SDIN

Figure 12. I²S, up to 24-Bit Data

SDIN +6 +5 +4 +3 +2 +1+7

-1 -2 -3 -4 -5

LSB LSBMSB -1 -2 -3 -4 -5 LSB

+6 +5 +4 +3 +2 +1+7

MSB

Left Channel Right Channel

LRCK

SCLK

Figure 13. Right-Justified Data

20 DS782F1

CS4349

4.3.1 Time-Division Multiplex (TDM) Mode

Four TDM interface modes are available that allow the CS4349 to input stereo PCM data in one of 4 time

“slots”. Figure 14 shows the serial port connections necessary to input 8-channel TDM data into four

CS4349 devices and the corresponding DIF[2:0] pin or register-bit settings required for each CS4349.

Figure 15 shows the TDM data format for each of the four CS4349 devices shown in Figure 14.

Figure 14. TDM Mode Connection Diagram

LRCK

SCLK

SDIN

ILRCK

ISCLK

SDIN

LRCK

SCLK

SDIN

LRCK SCLK TDM_OUT

TDM Source

LRCK

SCLK

SDIN

DIF[2:0] = 100 DIF[2:0] = 101 DIF[2:0] = 110 DIF[2:0] = 111

CS43494

CS43491CS43493

CS43492

Slot 2, ch B

LRCK

SCLK

MSB MSB MSB MSB MSB

SDIN1

Slot 4, ch A Slot 4, ch B

Slot 2, ch ASlot 1, ch A

256 clks

32 clks 32 clks 32 clks 32 clks 32 clks

MSB

Slot 3, ch A

32 clks

MSB

Slot 1, ch B

32 clks

MSB

Slot 3, ch B

32 clks

LSBMSB zero

Data

Figure 15. TDM Mode Timing

DS782F1 21

CS4349

4.4 De-Emphasis

The device includes on-chip digital de-emphasis. Figure 16 shows the de-emphasis curve for Fs equal to

44.1 kHz. The frequency response of the de-emphasis curve scales proportionally with changes in sample

rate, Fs.

Note: De-emphasis is only available in Single-Speed Mode.

4.5 Mute Control

The mute control pins (AMUTEC and BMUTEC) go active during power-up initialization, reset, muting (see

Section 8.4.3), and loss of LRCK. These pins are intended to be used as control for external mute circuits

to prevent the clicks and pops that can occur in any single-ended single-supply system.

Use of the mute control function is not mandatory but recommended for designs requiring the absolute min-

imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer

to achieve idle-channel noise and signal-to-noise ratios which are only limited by the external mute circuit.

4.6 Recommended Power-Up Sequence

4.6.1 Stand-Alone Mode

1. Hold RST low until the power supplies and configuration pins are stable, and the serial and left/right

clocks are fixed to the appropriate frequencies, as discussed in Section 4.2. In this state, the control

port registers are reset to their default settings, VQ will remain low, and VBIAS will be connected to

VA.

2. Bring RST high. The device will remain in a low power state with VQ low for approximately 512 LRCK

cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in

Quad-Speed Mode).

3. The device will then initiate the power up sequence which lasts approximately 50 µs when the

Popguard is disabled. If the Popguard is enabled, see Section 4.7 for a complete description of

power-up timing.

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1 F2

3.183 kHz 10.61 kHz

Figure 16. De-Emphasis Curve

22 DS782F1

CS4349

4.6.2 Control Port Mode

1. Hold RST low until the power supply is stable and the left/right clock is fixed to the appropriate

frequency, as discussed in Section 4.2. In this state, the control port is reset to its default settings, VQ

will remain low, and VBIAS will be connected to VA.

2. Bring RST high. The device will remain in a low-power state with VQ low.

3. Perform a control port write to a valid register prior to the completion of approximately 512 LRCK

cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in

Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1.

4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs when

the Popguard is disabled. If the Popguard is enabled, see Section 4.7 for a complete description of

power-up timing.

4.7 Popguard Transient Control

The CS4349 uses a novel technique to minimize the effects of output transients during power-up and power-

down. This technology, when used with external DC-blocking capacitors in series with the audio outputs,

minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated

inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing the

appropriate DC-blocking capacitors.

4.7.1 Power-Up

When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to GND.

Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quies-

cent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins.

This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quies-

cent voltage, minimizing audible power-up transients.

4.7.2 Power-Down

To prevent audible transients at power-down, the device must first enter its power-down state. When this

occurs, audio output ceases and the internal output buffers are disconnected from AOUTA and AOUTB.

In their place, a soft-start current sink is substituted that allows the DC-blocking capacitors to slowly dis-

charge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready

for the next power-on.

4.7.3 Discharge Time

To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge be-

fore turning on the power or exiting the power-down state. If full discharge does not occur, a transient will

occur when the audio outputs are initially clamped to GND. The time that the device must remain in the

power-down state is related to the value of the DC-blocking capacitance and the output load. For example,

with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.

DS782F1 23

CS4349

4.8 Analog Output and Filtering

The CS4349 requires a simple single-ended passive output design as shown in Figure 17.

4.9 Grounding and Power Supply Arrangements

As with any high-resolution converter, the CS4349 requires careful attention to power supply and grounding

arrangements if its potential performance is to be realized. Figure 10 shows the recommended power ar-

rangements, with VA, VLC, and VLS connected to clean supplies. The use of split analog and digital ground

planes is not recommended. However, if planes are split between digital ground and analog ground the

GND pins of the CS4349 should be connected to the analog ground plane.

All signals, especially clocks, should be kept away from the VBIAS, VFILT, and VQ pins in order to avoid

unwanted coupling into the DAC.

4.9.1 Capacitor Placement

Decoupling capacitors should be placed as close to the DAC as possible, with the low-value ceramic ca-

pacitor being the closest. To further minimize impedance, these capacitors should be located on the same

layer as the DAC. If desired, all supply pins may be connected to the same supply, but a decoupling ca-

pacitor should still be placed on each supply pin.

Note: All decoupling capacitors should be referenced to GND.

The CDB4349 evaluation board demonstrates the optimum layout and power supply arrangements.

AOUTx +

3.3 µF

Analog

Output

2200 pF

10 kΩ

GND

560 Ω

* See section 4.9 for ground connection details

Figure 17. Passive Single-Ended Output Filter

CS4349

24 DS782F1
CS4349
5. STAND-ALONE OPERATION
5.1 Serial Port Format Selection
The desired serial audio format is selected with the DIF2, DIF1 and DIF0 pins. For an explanation of the
required relationship between the LRCK, SCLK and SDIN, see Figures 11-13. For all formats, SDIN is valid
on the rising edge of SCLK. TDM Mode requires the selection of which stereo pair time “slot” is used to out-
put data as shown in Table 2 and Figure 15.
 
5.2 De-Emphasis Control
When pulled to VLC, the DEM pin activates the 44.1 kHz de-emphasis filter. When pulled to GND, the DEM
pin turns off the de-emphasis filter.
5.3 Popguard Transient Control
In Stand-Alone Mode, Popguard is enabled by default. Popguard can be defeated in Stand-Alone Mode by
placing a 47 kΩ resistor between POPGUARD(TSTO) and VLS.
DIF2 DIF1 DIF0 DESCRIPTION FORMAT FIGURE
000
Left-Justified, up to 24-bit data 012
001
I²S, up to 24-bit data  111
010
Right-Justified, 16-bit data 213
011
Right-Justified, 24-bit data 313
100
TDM slot 0 415
101
TDM slot 1 515
110
TDM slot 2 615
111
TDM slot 3 715
Table 2. Digital Interface Format - Stand-Alone Mode 

DS782F1 25

CS4349

6. CONTROL PORT OPERATION

The control port is used to load all the internal register settings (see ”Register Description” on page 29). The oper-

ation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential

interference problems, the control port pins should remain static if no operation is required.

The control port can operate in I²C or SPI mode.

6.1 MAP Auto Increment

The device has a MAP (memory address pointer) auto-increment capability enabled by the INCR bit (also

the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for consecutive writes or reads. If INCR is

set to 1, MAP will auto increment after each byte is read or written, allowing block reads or writes of con-

secutive registers.

6.2 I²C Mode

In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial

control port clock, SCL (see Figure 18 for the clock to data relationship). There is no CS pin. AD1 and AD0

enable the user to alter the chip address (10010[AD1][AD0][R/W]) and should be tied to VLC or GND as

required before powering-up the device. SPI Mode will be selected if the device ever detects a high-to-low

transition on the AD0/CS pin after power-up.

6.2.1 I²C Write

To write to the device, follow the procedure below while adhering to the control port Switching Specifica-

tions in ”Switching Characteristics - Control Port - I²C Format” on page 14.

1. Initiate a START condition to the I²C bus followed by the address byte. The upper five bits must be

10010. The sixth and seventh bit must match the settings of the AD1 and AD0 pins respectively, and

the eighth must be 0 (the eighth bit of the address byte is the R/W bit).

2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This

byte points to the register to be written.

3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by

the MAP.

4. If the INCR bit (see Section 6.1) is set to 1, repeat the previous step until all the desired registers are

written, then initiate a STOP condition to the bus.

5. If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to initiate

a repeated START condition and follow the procedure detailed from step 1. If no further writes to other

registers are desired, initiate a STOP condition to the bus.

6.2.2 I²C Read

To read from the device, follow the procedure below while adhering to the control port switching specifi-

cations in ”Switching Characteristics - Control Port - I²C Format” on page 14.

1. Initiate a START condition to the I²C bus followed by the address byte. The upper 5 bits must be

10010. The sixth and seventh bits must match the setting of the AD1 and AD0 pins, respectively, and

the eighth must be 1. The eighth bit of the address byte is the R/W bit.

2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register

pointed to by the MAP. The MAP register will contain the address of the last register written to the

26 DS782F1

CS4349

MAP or the default address (see Section 6.4.2) if an I²C read is the first operation performed on the

device.

3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.

4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.

Continue providing a clock and issue an ACK after each byte until all the desired registers are read;

then initiate a STOP condition to the bus.

5. If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to

initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I²C

Write instructions, followed by step 1 of the I²C Read section. If no further reads from other registers

are desired, initiate a STOP condition to the bus.

6.3 SPI Mode

In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK

(see Figure 19 for the clock to data relationship). There are no AD0 or AD1 pins. Pin CS is the chip select

signal and is used to control SPI writes to the control port. When the device detects a high-to-low transition

on the AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in

on the rising edge of CCLK.

6.3.1 SPI Write

To write to the device, follow the procedure below while adhering to the control port switching specifica-

tions in ”Switching Characteristics - Control Port - SPI Format” on page 15.

1. Bring CS low.

2. The address byte on the CDIN pin must then be 10011110 (R/W =0).

3. Write to the memory address pointer, MAP. This byte points to the register to be written.

4. Write the desired data to the register pointed to by the MAP.

5. If the INCR bit (see Section 6.1) is set to 1, repeat the previous step until all the desired registers are

written, then bring CS high.

6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring

CS high, and follow the procedure detailed from step 1. If no further writes to other registers are

desired, bring CS high

4 5 6 7 24 25

SCL

CHIP ADDRESS MAP BYTE DATA DATA +1

START

ACK

STOP

ACKACKACK

1 0 0 1 0 AD1 AD0 R/W

SDA 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0

0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28

DATA +n

INC

Figure 18. Control Port Timing, I²C Mode

DS782F1 27

CS4349

6.3.2 SPI Read

To read from the device, follow the procedure below while adhering to the values specified in ”Switching

Characteristics - Control Port - SPI Format” on page 15.

1. Bring CS low.

2. The address byte on the CDIN pin must then be 10011111 (R/W =1).

3. CDOUT pin will then output the data from the register pointed to by the MAP, which is set during the

SPI write operation.

4. If the INCR bit (see Section 6.1) is set to 1, keep CS low and continue providing clocks on CCLK to

read from multiple consecutive registers. Bring CS high when reading is complete.

5. If the INCR bit is set to 0 and further SPI reads from other registers are desired, it is necessary to bring

CS high, and follow the procedure detailed from step 1. If no further reads from other registers are

desired, bring CS high.

6.4 Memory Address Pointer (MAP)

6.4.1 INCR (Auto Map Increment Enable)

Default = ‘0’

0 - Disabled

1 - Enabled

6.4.2 MAP (Memory Address Pointer)

Default = ‘0000’

76543210

INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0

00000000

MAP

MSB LSB

DATA

byte 1 byte n

R/W R/W

ADDRESS

CHIP

ADDRESS

CHIP

MSB LSB MSB LSB

MAP = Memory Address Pointer, 8 bits, MSB first

High Impedance

1001111 1001111

CCLK

CDIN

CDOUT

Figure 19. Control Port Timing, SPI Mode

28 DS782F1

CS4349

7. REGISTER QUICK REFERENCE

Addr Function 7 6 5 4 3 2 1 0

1h Device and RevID DeviceID4 DeviceID3 DeviceID2 DeviceID1 DeviceID0 RevID2 RevID1 RevID0

default 1 1 1 1 - - - -

2h Mode Control Reserved DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0

default000 0 0 000

3h Volume, Mixing,

and Inversion

Control

VOLB=A INVERTA INVERTB Reserved ATAPI3 ATAPI2 ATAPI1 ATAPI0

default000 0 1 001

4h Mute Control AMUTE Reserved MUTEC

A=B

MUTE_A MUTE_B Reserved Reserved Reserved

default100 0 0 001

5h Channel A Volume

Control

VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0

default000 0 0 000

6h Channel B Volume

Control

VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0

default000 0 0 000

7h Ramp and Filter

Control

SZC1 SZC0 RMP_UP RMP_DN Reserved FILT_SEL Reserved Reserved

default101 1 0 001

8h Misc. Control PDN Reserved FREEZE POPG_EN Reserved Reserved Reserved Reserved

default000 1 1 100

DS782F1 29
CS4349
8. REGISTER DESCRIPTION
** All register access is R/W unless specified otherwise**
8.1 Device and Revision ID - Register 01h 
Function:
This register is Read-Only. It is decoded as follows:
8.2 Mode Control - Register 02h 
8.2.1 Digital Interface Format (DIF[2:0]) Bits 6-4
Function:
These bits select the interface format for the serial audio input. 
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 11-13.    
76543210
Device4 Device3 Device2 Device1 Device0 Rev2 Rev1 Rev0
1111 - - - -
Rev Register 01h contents
A 1111,0000
B 1111,0001
C2 1111,1111
76543210
Reserved DIF2 DIF1 DIF0 DEM1 DEM0 FM1 FM0
00000000
DIF2 DIF1 DIF0 Description Format Figure
000
Left-Justified, up to 24-bit data 0 (Default) 11
001
I²S, up to 24-bit data  112
010
Right-Justified, 16-bit data 213
011
Right-Justified, 24-bit data 313
100
TDM slot 0 415
101
TDM slot 1 515
110
TDM slot 2 615
111
TDM slot 3 715
Table 3. Digital Interface Formats

30 DS782F1

CS4349

8.2.2 De-Emphasis Control (DEM[1:0]) Bits 3-2

Default = 0

00 - No De-emphasis

01 - 44.1 kHz De-emphasis

10 - 48 kHz De-emphasis

11 - 32 kHz De-emphasis

Function:

Selects the appropriate digital filter to maintain the standard

15 μs/50 μs digital de-emphasis filter response at 32, 44.1

or 48 kHz sample rates. (See Figure 20)

Note: De-emphasis is only available in Single-Speed

Mode

8.2.3 Functional Mode (FM[1:0]) Bits 1-0

Default = 00

00 - Auto speed mode detect

01 - Single-Speed Mode (30 to 54 kHz sample rates)

10 - Double-Speed Mode (50 to 108 kHz sample rates)

11 - Quad-Speed Mode (100 to 216 kHz sample rates)

Function:

Selects the required range of input sample rates or auto speed mode.

8.3 Volume Mixing and Inversion Control - Register 03h

8.3.1 Channel A Volume = Channel B Volume (VOLB=A) Bit 7

Function:

When set to 0 (default), the AOUTA and AOUTB volume levels are independently controlled by the A and

the B Channel Volume Control Bytes.

When set to 1, the volume on both AOUTA and AOUTB are determined by the A Channel Attenuation and

Volume Control Bytes, and the B Channel Bytes are ignored.

8.3.2 Invert Signal Polarity (INVERT_A) Bit 6

Function:

When set to 1, this bit inverts the signal polarity of channel A.

When set to 0 (default), this function is disabled.

This function is only available for Left Justified, Right Justified 16, and Right Justified 24 data formats.

76543210

VOLB=A INVERT_A INVERT_B Reserved ATAPI3 ATAPI2 ATAPI1 ATAPI0

00001001

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1 F2

3.183 kHz 10.61 kHz

Figure 20. De-Emphasis Curve

DS782F1 31

CS4349

8.3.3 Invert Signal Polarity (INVERT_B) Bit 5

Function:

When set to 1, this bit inverts the signal polarity of channel B.

When set to 0 (default), this function is disabled.

This function is only available for Left Justified, Right Justified 16, and Right Justified 24 data formats.

8.3.4 ATAPI Channel Mixing and Muting (ATAPI[3:0]) Bits 3-0

Default = 1001 - AOUTA = aL, AOUTB = bR (Stereo)

Function:

The CS4349 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to

Table 4 and Figure 21 for additional information.

ATAPI_A1 ATAPI_A0 ATAPI_B1 ATAPI_B0 AOUTA AOUTB

0000 MUTE MUTE

0001 MUTE bR

0010 MUTE bL

0 0 1 1 MUTE b[(L+R)/2]

0100 aR MUTE

0 1 0 1 aR bR

0110 aR bL

0 1 1 1 aR b[(L+R)/2]

Table 4. ATAPI Decode

ΣΣ

A Channel

Volume

Control AoutA

AoutB

Left Channel

Audio Data

Right Channel

Audio Data

B Channel

Volume

Control

MUTE

Figure 21. ATAPI Block Diagram

32 DS782F1

CS4349

8.4 Mute Control - Register 04h

8.4.1 Auto-Mute (AMUTE) Bit 7

Function:

When set to 1 (default), the Digital-to-Analog converter output will mute following the reception of 8192

consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. De-

tection and muting is done independently for each channel. The quiescent voltage on the output will be

retained, and the Mute Control pin will go active during the mute period.

When set to 0, this function is disabled

8.4.2 AMUTEC = BMUTEC (MUTEC A=B) Bit 5

Function:

When set to 0 (default), the AMUTEC and BMUTEC pins operate independently.

When set to 1, the individual controls for AMUTEC and BMUTEC are internally connected through an

AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins go active only

when the requirements for both AMUTEC and BMUTEC are valid.

8.4.3 Channel A Mute (MUTE_A) Bit 4 & Channel B Mute (MUTE_B) Bit 3

Function:

When set to 1, the Digital-to-Analog converter output will mute. The quiescent voltage on the output will

be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero Cross

bits in the Volume and Mixing Control register. The corresponding MUTEC pin will go active following any

ramping due to the soft and zero cross function.

When set to 0 (default), this function is disabled.

1000 aL MUTE

1001 aL bR

1 0 1 0 aL bL

1 0 1 1 aL b[(L+R)/2]

1 1 0 0 a[(L+R)/2] MUTE

1 1 0 1 a[(L+R)/2] bR

1 1 1 0 a[(L+R)/2] bL

1 1 1 1 a[(L+R)/2] b[(L+R)/2]

76543210

AMUTE Reserved MUTEC A=B MUTE_A MUTE_B Reserved Reserved Reserved

10000000

ATAPI_A1 ATAPI_A0 ATAPI_B1 ATAPI_B0 AOUTA AOUTB

Table 4. ATAPI Decode

DS782F1 33

CS4349

8.5 Channel A & B Volume Control - Register 05h & 06h

Digital Volume Control (VOL[7:0]) Bits 7-0

Default = 00h (0 dB)

Function:

The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments

from 0 to -127.5 dB. Volume settings are decoded as shown in Table 5. The volume changes are imple-

mented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register. The actual

attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/12.

8.6 Ramp and Filter Control - Register 07h

8.6.1 Soft Ramp and Zero Cross Control (SZC[1:0]) Bits 7-6

Default = 10

Function:

Immediate Change

When Immediate Change is selected all level changes will take effect immediately in one step.

Zero Cross

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur

on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-

out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal

does not encounter a zero crossing. The zero cross function is independently monitored and implemented

for each channel.

Soft Ramp PCM

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-

ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.

76543210

VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0

00000000

Binary Code Decimal Value Volume Setting

00000000 0 0 dB

00000001 1 -0.5 dB

00000110 6 -3.0 dB

11111111 255 -127.5 dB

Table 5. Example Digital Volume Settings

76543210

SZC1 SZC0 RMP_UP RMP_DN Reserved FILT_SEL Reserved Reserved

10110001

SZC1 SZC0 Description

0 0 Immediate Change

0 1 Zero Cross

1 0 Soft Ramp

1 1 Soft Ramp on Zero Crossings

34 DS782F1

CS4349

Soft Ramp and Zero Cross

Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut-

ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will

occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample

rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored

and implemented for each channel.

8.6.2 Soft Volume Ramp-Up After Error (RMP_UP) Bit 5

Function:

When set to 1 (default), an un-mute will be performed after executing a filter mode change, after LRCK is

lost, and after changing the Functional Mode. This un-mute is affected, similar to attenuation changes, by

the Soft and Zero Cross bits in the Volume and Mixing Control register.

When set to 0, an immediate un-mute is performed in these instances.

Note: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.

8.6.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) Bit 4

Function:

When set to 1 (default), a mute will be performed prior to executing a filter mode change. This mute is

affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control

When set to 0, an immediate mute is performed prior to executing a filter mode change.

Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.

8.6.4 Interpolation Filter Select (FILT_SEL) Bit 2

Function:

When set to 0 (default), the Interpolation Filter has a fast roll-off.

When set to 1, the Interpolation Filter has a slow roll-off.

The specifications for each filter can be found in the ”Combined Interpolation & On-Chip Analog Filter Re-

sponse” on page 12, and response plots can be found in Figures 24 through 29.

DS782F1 35

CS4349

8.7 Misc. Control - Register 08h

8.7.1 Power Down (PDN) Bit 7

Function:

When set to 1, the entire device enters a low-power state, and the contents of the control registers is re-

tained. The power-down bit defaults to ‘0’ on power-up.

8.7.2 Freeze Controls (FREEZE) Bit 5

Function:

When set to 1, this function allows modifications to be made to the registers without the changes taking

effect until FREEZE is set back to 0. To make multiple changes in the Control Port registers take effect

simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.

When set to 0 (default), register changes take effect immediately.

8.7.3 Popguard Enable (POPG_EN) Bit 4

Function:

When set to 1, (default) the Device initiates a ramping function as outlined in Section 4.7 on page 22.

When set to 0, the outputs step to VQ upon release of PDN.

76543210

PDN Reserved FREEZE POPG_EN Reserved Reserved Reserved Reserved

00011100

36 DS782F1

CS4349

9. FILTER PLOTS

0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 22. Stopband Rejection (fast), all Modes Figure 23. Stopband Rejection (slow), all Modes

0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 24. Single-Speed (fast) Passband Detail Figure 25. Single-Speed (slow) Passband Detail

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.

−0.5

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0.5

Frequency (normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.

−0.5

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0.5

Frequency (normalized to Fs)

Amplitude (dB)

Figure 26. Double-Speed (fast) Passband Detail Figure 27. Double-Speed (slow) Passband Detail

DS782F1 37

CS4349

0 0.05 0.1 0.15 0.2 0.25 0.

−0.5

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0.5

Frequency (normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.

−0.5

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0.5

Frequency (normalized to Fs)

Amplitude (dB)

Figure 28. Quad-Speed (fast) Passband Detail Figure 29. Quad-Speed (slow) Passband Detail

38 DS782F1

CS4349

10.PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified

bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the

specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made

with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full

scale. This technique ensures that the distortion components are below the noise level and do not effect the

measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-

1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's

output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in deci-

bels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Intra-Channel Phase Deviation

The deviation from linear phase within a given channel.

Inter-Channel Phase Deviation

The difference in phase between channels.

DS782F1 39

CS4349

11.PACKAGE DIMENSIONS

1. D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per

side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not re-

duce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

THERMAL CHARACTERISTICS

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.043 -- -- 1.10

A1 0.002 0.004 0.006 0.05 -- 0.15

A2 0.03346 0.0354 0.037 0.85 0.90 0.95

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3

D 0.303 0.307 0.311 7.70 7.80 7.90 1

E 0.248 0.2519 0.256 6.30 6.40 6.50

E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- 0.026 BSC -- -- 0.65 BSC --

L 0.020 0.024 0.028 0.50 0.60 0.70

µ0°4°8°0°4°8°

JEDEC #: MO-153

Controlling Dimension is Millimeters.

Parameters Symbol Min Typ Max Units

Package Thermal Resistance Single-Layer PCB

Multi-Layer PCB θJA -70

105 -°C/Watt

24L TSSOP (4.4 mm BODY) PACKAGE DRAWING

123

eb2A1

A2 A

SEATING

PLANE

E11

SIDE VIEW

END VIEW

TOP VIEW

∝

40 DS782F1
CS4349
12.ORDERING INFORMATION
13.REVISION HISTORY  
 
Product Description Package Pb-Free Grade Temp Range Container Order#
CS4349
192 kHz Stereo DAC 
with 1 Vrms Single 
Ended Output
24-TSSOP YES
Commercial -40° to +85°C Rail CS4349-CZZ
Tape and Reel CS4349-CZZR
Automotive -40° to +105°C Rail CS4349-DZZ
Tape and Reel CS4349-DZZR
CDB4349 Evaluation Board for CS4349 - - - - CDB4349
Release Changes
F1
Updated “DAC Analog Characteristics - Commercial (-CZZ)” on page 9.
Updated “DAC Analog Characteristics - Automotive (-DZZ)” on page 10.
Added Figure 3, Figure 4, and Figure 5 on page 11.
Updated “Switching Specifications - Serial Audio Interface” on page 13.
Updated “Digital Characteristics” on page 16.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. 
To find the one nearest you, go to www.cirrus.com.
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