LM27403EVM-POL600 30A Ultra-Compact DC/DC Regulator Evaluation Module User's Guide Literature Number: SNVU330 October 2013 Contents 1 .................................................................................................................. 4 ..................................................................................................... 4 1.2 EVM Features and Electrical Performance .......................................................................... 5 ELECTRICAL PERFORMANCE .............................................................................................. 6 CIRCUIT DIAGRAM .............................................................................................................. 7 PHOTOS ............................................................................................................................. 8 4.1 Module .................................................................................................................... 8 4.2 Sub-Assembly ........................................................................................................... 8 DESIGN CONSIDERATIONS .................................................................................................. 9 5.1 Current Sensing in DC/DC Regulators ............................................................................... 9 5.2 Thermal Design .......................................................................................................... 9 5.3 Components ............................................................................................................ 10 5.4 Output Voltage Setpoint and Rempote Sensing ................................................................... 10 SIGNAL CONNECTIONS AND TEST POINTS ......................................................................... 11 6.1 Test Point Descriptions ................................................................................................ 11 6.2 Signal Connections .................................................................................................... 11 6.3 Remote Sense Configuration ......................................................................................... 11 TEST SETUP ..................................................................................................................... 12 7.1 Test Equipment ........................................................................................................ 12 7.2 Recommended Test Setup ........................................................................................... 13 7.3 Test Procedure ......................................................................................................... 13 TEST DATA AND PERFORMANCE CURVES ......................................................................... 14 8.1 Efficiency ................................................................................................................ 14 8.2 Load Regulation ........................................................................................................ 14 8.3 Line Regulation ......................................................................................................... 15 8.4 Current Limit Hiccup Mode ........................................................................................... 15 8.5 Load Transient Response ............................................................................................ 16 8.6 Output Ripple ........................................................................................................... 16 8.7 Startup and Shutdown - VIN ......................................................................................... 17 8.8 Startup and Shutdown - Enable ..................................................................................... 18 8.9 Pre-Bias Startup ........................................................................................................ 19 8.10 Switch Node ............................................................................................................ 19 8.11 Switch Deadtimes ...................................................................................................... 20 EVM DOCUMENTATION ..................................................................................................... 21 9.1 Schematics ............................................................................................................. 21 9.2 Module PCB Layout ................................................................................................... 22 9.3 Motherboard PCB Layout ............................................................................................. 24 9.4 Assembly Drawings .................................................................................................... 26 9.5 Bill of Materials ......................................................................................................... 27 INTRODUCTION 1.1 2 3 4 5 6 7 8 9 2 Typical Applications Table of Contents SNVU330 - October 2013 Submit Documentation Feedback Copyright (c) 2013, Texas Instruments Incorporated www.ti.com List of Figures 1 Regulator Circuit Diagram ................................................................................................. 7 2 Photo of Module ............................................................................................................. 8 3 Photo of Module SMT Connected to Host PCB......................................................................... 8 4 Connection Diagram ...................................................................................................... 12 5 Efficiency ................................................................................................................... Load Regulation .......................................................................................................... Line Regulation ............................................................................................................ Current Limit Hiccup Mode ............................................................................................... Load Transient Response; VIN = 12 V, VOUT = 1.8 V, 0 A to 10 A at 2 A/s ....................................... Output Voltage Ripple; VIN = 12 V, VOUT = 1.8 V, IOUT = 20 A ........................................................ Startup with VIN Stepped to 12 V; VOUT = 1.8 V, 30-A Resistive Load ............................................. Shutdown After VIN Disconnected; VIN = 12 V, VOUT = 1.8 V, 22-A Resistive Load .............................. Startup with EN Stepped to 3 V; VIN = 12 V, VOUT = 1.8 V, 30-A Resistive Load .................................. Shutdown with EN Pulled To GND; VIN = 12 V, VOUT = 1.8 V, 20-A Resistive Load .............................. Pre-bias Startup; VIN = 12 V, No Load, 0.6-V Pre-bias ............................................................... Switch Node Voltage; VIN = 12 V, VOUT = 1.8 V ........................................................................ Deadtime Prior To High-side MOSFET Turn-on; VIN = 12 V, VOUT = 1.8 V, 120-m Load ....................... Deadtime Prior To High-side MOSFET Turn-off; VIN = 12 V, VOUT = 1.8 V, 120-m Load ....................... Module Schematic ......................................................................................................... Motherboard Schematic .................................................................................................. Top Copper and Paste Layers ........................................................................................... Internal Layer 2 (Top view) ............................................................................................... Internal Layer 3 (Top view) ............................................................................................... Bottom Copper and Paste Layers (Bottom view) ..................................................................... Top Copper and Paste Layers ........................................................................................... Internal Layer 2 (Top view) ............................................................................................... Internal Layer 3 (Top view) ............................................................................................... Bottom Copper and Paste Layers (Bottom view) ..................................................................... Module Assembly Drawing ............................................................................................... Motherboard Assembly Drawing ........................................................................................ 14 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SNVU330 - October 2013 Submit Documentation Feedback List of Figures Copyright (c) 2013, Texas Instruments Incorporated 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 3 User's Guide SNVU330 - October 2013 LM27403EVM-POL600 Evaluation Module This user's guide offers perspective regarding point-of-load (POL) DC/DC regulation circuit design and implementation. Specifically, it describes a cost-effective solution to address the challenges a system designer can encounter when a high density and efficient POL regulator is required and PC board real estate is at a premium. Using the LM27403 voltage-mode PWM controller and a Power Block NexFETTM in an embedded module style solution, the LM27403EVM-POL600 synchronous buck regulator delivers an output current up to 30 A. High conversion efficiency is a key parameter in this design--translating into lower power loss, less package temperature rise for a given power throughput, and enabling a higher power density form factor. PCB source and gerber files, as well as component views and fabrication drawings, are available in PowerLabTM for this design. spacer to force list of Figures title to next page spacer to force list of Figures title to next page 1 INTRODUCTION The LM27403EVM-POL600 represents a standalone POL module with benchmark power density surfacemounted on a host board as a mother-daughter configuration. The POL module itself is an independent sub-assembly that is ultra-compact, versatile, tailored to high-volume SMT manufacturing, and fully proven and tested before SMT placement on the host board. In practice, a POL module such as this is typically parallel stacked onto the system motherboard wherein power and signal connections are realized using SMT connections. As such, the module can be flexibly deployed across multiple systems and applications, greatly easing the design burden of a system engineer. Alternatively, the design is realized as a voltage-regulator-down (VRD) implementation with the components placed directly on the motherboard. High density and small footprint are the main design tenets, with efficiency as a key performance metric. An output voltage with better than 1% setpoint accuracy is adjustable between 0.6 V and 5.5 V simply by changing a trim resistor. With an output current up to 30 A, the switching frequency is 600 kHz and synchronizable to a higher frequency if required. Nominal input voltage is 12 V but can vary from 3 V to 20 V with suitable adjustment of the programmable UVLO. The LM27403EVM-POL600 is designed specifically to demonstrate the LM27403 PWM controller in a typical 12-V bus to low output voltage, low duty-cycle application. 1.1 Typical Applications * * * * 4 Synchronous buck regulators in distributed power architectures High current density POL modules Communications, cloud, server, storage, graphics Embedded computing, FPGAs, ASICs, DSPs LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated SNVU330 - October 2013 Submit Documentation Feedback INTRODUCTION www.ti.com 1.2 EVM Features and Electrical Performance * * * * * * * * * * * * * * * * * * * * High conversion efficiency: 91% at 1.8 V, 30 A High current and power per unit volume, 200A/in3 Tiny converter footprint of 20 mm x 15 mm (0.8" x 0.6") Low profile of 8.4 mm (0.33") Wide input voltage operating range of 3 V to 20 V Nominal output voltage of 1.8 V with 1% feedback accuracy Adjustable output voltage from 0.6 V to 5.5 V by changing "trim" resistance 600-kHz free-running switching frequency Synchronizable to an external clock signal up to 1.2 MHz Single supply rail--no additional bias voltage required Overcurrent protection via inductor DCR current sensing with thermal compensation Programmable thermal shutdown based on remote-sensed BJT temperature Soft-start time of 8 ms Monotonic pre-bias output voltage startup Programmable input UVLO set to turn on and off at 4.4 V and 3.7 V, respectively Voltage-mode PWM control supporting all-ceramic or ceramic/electrolytic output capacitor implementations Configurable remote output voltage sensing for optimal load regulation performance Power Good indicator Input circuit damping with optional electrolytic capacitor Easy access to key features including PGOOD, Enable, SYNC, and output remote sense SNVU330 - October 2013 Submit Documentation Feedback LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated 5 ELECTRICAL PERFORMANCE 2 www.ti.com ELECTRICAL PERFORMANCE Table 1. Electrical Performance Specifications Symbol Parameter Notes and Conditions Min Nom Max 12 20 Units INPUT CHARACTERISTICS VIN Input voltage range VIN(ON) Input voltage turn on 4.5 VIN(OFF) Input voltage turn off IIN(MAX) Input current, full load (1) IIN(NL) Input current, no load VIN = 12 V, IOUT = 0 A IIN(OFF) Input current, disabled VIN = 12 V, VUVLO/EN = 0 V Set by UVLO/EN resistors VIN = 7 V VIN = 12 V IOUT = 30 A V 4.4 V 3.7 V 8.48 A 4.95 A 40 mA 1 mA OUTPUT CHARACTERISTICS VOUT Output voltage IOUT Output current VOUT Output voltage regulation 1.782 1.800 1.818 (2) V VOUT 1.8 V 0 30 A VOUT > 1.8 V 0 25 A Load Regulation: IOUT = 0 A to 30 A 0.5% Line Regulation: VIN = 4.5 V to 20 V 0.5% VO(RIPPLE) Output voltage ripple VIN = 12 V, IOUT = 20 A 10 mVpp VO(PKDEV) Output voltage transient response IOUT = 0 A to 10 A, 2 A/s slew rate 50 mV ILIM Output overcurrent protection 33 A tSS Soft-start time 8 ms 600 kHz SYSTEMS CHARACTERISTICS FSW(NOM) Switching frequency (free running) FSW Switching frequency range (using SYNC) PK Peak efficiency (1) (3) FULL Full load efficiency fc Loop bandwidth M Phase margin (1) (3) FSW(NOM) 93% VIN = 5 V 91% VIN = 12 V IOUT = 30 A Ambient temperature TOTP System-level thermal shutdown (1) (2) (3) (4) 6 89% VIN = 12 V, IOUT = 15 A (4) kHz 91% VIN = 20 V TA 1200 VIN = 12 V, IOUT = 12 A 75 kHz 55 -40 85 110 C C The default output voltage and switching frequency are 1.8 V and 600 kHz, respectively. Efficiency and other parameters will change based on the chosen output voltage, load current, and frequency. This is equivalent to an output voltage tolerance of 1%. Input and output voltage measurements are taken local to the module. The ambient temperature range is provided with the implicit caveat of appropriate output current derating to assure recommended maximum component operating temperatures are not exceeded. LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated SNVU330 - October 2013 Submit Documentation Feedback CIRCUIT DIAGRAM www.ti.com 3 CIRCUIT DIAGRAM VOUT SENSE+ VDD DBOOT CC3 470 pF SENSE- U1 CRS 1 F 1 CSS 47 nF SS/TRACK 23 CBOOT 18 CBT 0.1 F 2 RS HG 17 3 FB SW 16 TGR 4 COMP 5 FADJ LM27403SQ D+ D PGOOD VIN 6 OTP RF 15 k 7 8 9 10 11 12 SYNC SYNC RUV2 3.48 k PGND VIN COTP 0.1 F ROTP 84.5 k CIN 22 F Q1 3904 VOUT 100 F GND CVDD 4.7 F CD 2.2 nF D PGOOD RUV1 10 k BG CO1-3 GND 13 EN VIN 0.3 H 0.29 m VDD 14 47 pF SENSE+ RS+ 10 L1 VSW LG 15 UVLO /EN CC1 3.3 nF CC2 VIN TG CS 0.1 F RS 2.32 k Q2 TRIM RC1 10 k RSET 4.02 k VIN 40V 0.2A 24 CS+ 200 RFB1 20 k CS RC2 CCS 100 pF CIN 1 F D+ RVIN 2.2 Figure 1. Regulator Circuit Diagram SNVU330 - October 2013 Submit Documentation Feedback LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated 7 PHOTOS 4 PHOTOS 4.1 Module www.ti.com Figure 2. Photo of Module 4.2 Sub-Assembly Figure 3. Photo of Module SMT Connected to Host PCB 8 LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated SNVU330 - October 2013 Submit Documentation Feedback DESIGN CONSIDERATIONS www.ti.com 5 DESIGN CONSIDERATIONS 5.1 Current Sensing in DC/DC Regulators Availing of intrinsic circuit parasitic elements, such as inductor DCR or MOSFET on-state resistance, for lossless current sensing is quite common as it enables high power density and low-cost circuit implementations. But merely sensing the voltage across the low-side MOSFET in a buck converter is inaccurate given the large initial tolerance of the RDS(ON) (as high as 30%) and the variation with temperature inherent with the MOSFET die. Also, sensing occurs only when the low-side MOSFET is conducting. By contrast, the tolerance of an inductor's DCR is typically specified at 8%, sometimes even lower. The inductor DCR current sense technique, achieved by connecting an RC filter network in parallel with the inductor, is widely adopted in DC/DC regulators for high-current applications. With the trend towards higher switching frequencies coupled with the need for fast load transient response, a relatively low inductance is required. At high output currents, ultra-low DCR ferrite inductors offer reduced copper and core losses. Unfortunately, the current sense signal amplitude derived from subm inductor DCR is adversely affected. For example, a 30-A full load current and 0.3-m DCR produces an average voltage signal of only 9 mV (at room temperature), driving the need for low offset circuits to meet accuracy specifications. Also, a design is typically captive to the hard saturation characteristic of ferrite-cored inductors, and the imperative is to never exceed the inductor's saturation current threshold. 5.1.1 Leveraging MOSFET Vertically-Stacked Construction An increased effective sense resistance (and resultant voltage signal amplitude) is realized by advantageously employing the package structure copper resistance in the vertically-integrated MOSFET device, e.g. TI Power Block NexFETTM. Here, the inductor DCR current sensing method is reconfigured to include the copper resistance of the MOSFET's switch clip connecting high-side source and low-side drain. This is shown in the schematic of Figure 19. The return to the high-side gate drive, designated TGR, is a kelvin connection attached to the low-side MOSFET's drain. The voltage drop across the SW copper plate is now easily sensed and incorporated with the sensed voltage from the inductor DCR. The cumulative signal derived from the DCR and SW clip offers a continuous signal at higher amplitude, thus enabling more accurate current sensing performance. The effective sense resistance on an average basis is the DCR plus the clip resistance weighted by a (1-D) factor, where D is the PWM duty cycle. The sense network time constant is then chosen based on this effective sense resistance. 5.2 Thermal Design It is critical to minimize power dissipation to reduce component operating temperature, particularly with small footprint implementations. MOSFET switch on-state resistance has a positive temperature coefficient, which means an increase of junction temperature compounds upon itself to increase even further until a steady state thermal equilibrium is obtained. Also, the local ambient and PCB temperatures in high-density PCB layouts can become elevated quickly due to the mutual heating effect inherent with high power dissipation from immediately adjacent power components. The power and ground planes common to and layered beneath the devices act as heat spreaders throughout the PCB. It's important to bear in mind that the motherboard provides conductive thermal dissipation and heatsinking through the module's surface-mount terminal connections. The power terminals of the module PCB are also edge-plated to connect the inner and outer PCB current-carrying planes as well as increase the surface contact area to the host PCB. A general design recommendation is to position the major power dissipating components--the MOSFETs and inductor--on the top side of the module to purposely capitalize on whatever natural or forced convection is available in the application environment. Moreover, a low thermal impedance MOSFET package (from junction to soldered pin) serves to conduct a large portion of the heat flux through the device pins and utilize the PCB substrate as a heatsinking element. SNVU330 - October 2013 Submit Documentation Feedback LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated 9 DESIGN CONSIDERATIONS 5.3 5.3.1 www.ti.com Components PWM Controller The LM27403EVM-POL600 uses the LM27403 high performance, synchronous buck PWM controller with voltage-mode control loop, integrated MOSFET gate drivers with adaptively-controlled deadtime, inductor DCR current sensing, and 30-ns minimum on-time for low duty-cycle operation. Remote BJT temperature measurement enables (a) DCR sense voltage compensation for accurate current limit across the operating temperature range, and (b) board-level thermal shutdown for increased reliability. The LM27403 is available in a 4-mm x 4-mm WQFN-24 PowerPADTM package. Please consult the LM27403 datasheet for more details. In addition to WEBENCH(R) Power Designer, the reader is also encouraged to avail of the LM27403 Design Tool, particularly for quick-start guidance with power train and compensation circuit component selection. 5.3.2 MOSFETs A CSD87350Q5D Power Block NexFETTM from TI is an optimized MOSFET design for synchronous buck applications offering high current, high efficiency, and high frequency capability in a small SON 5-mm x 6mm package. Optimized for 5-V gate drive applications, it offers a flexible solution when paired with any 5V gate drive PWM control stage. Using a system-optimized grounded leadframe, thick copper clips and vertical die stacking, the asymmetric MOSFETs are optimized for low duty cycle, high power density and efficient operation in high switching frequency applications. The low-side synchronous and high-side control MOSFETs have 1.2-m and 5.0-m effective AC on-impedances at 25C, and gate charges of 20 nC and 8.4 nC, respectively. With the common source inductance of the high-side MOSFET essentially eliminated by kelvin gate connections, these low charge parameters enable very low switching losses. Leveraging the heat spreading advantages of the grounded tab, total MOSFET power dissipation at 1.8-V and 25-A output in this application, including conduction and switching loss contributions at 100C junction temperature, is 2.5W. 5.3.3 Filter Inductor Off-the-shelf component options for low-DCR ferrite inductors with single-turn "staple" winding are widely available; a few examples are given in Table 4. Inductor power dissipation at 30 A, including copper and core loss at 75C operating temperature, is 0.6 W. 5.4 Output Voltage Setpoint and Rempote Sensing The module's output voltage is easily changing by appropriate selection of lower feedback resistance. This is designated as Rtrim on the motherboard, see schematic in Figure 20. The appropriate trim resistance for various output voltages is provided in Table 2. Table 2. Output Voltage Trim Resistance 10 VOUT (V) TRIM RESISTANCE (k) 0.6 OPEN 0.8 60 0.9 40 1.0 30 1.2 20 1.5 13.3 1.8 10 3.3 4.42 5.0 2.8 LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated SNVU330 - October 2013 Submit Documentation Feedback SIGNAL CONNECTIONS AND TEST POINTS www.ti.com 6 SIGNAL CONNECTIONS AND TEST POINTS 6.1 Test Point Descriptions Table 3. Test Point Descriptions 6.2 6.2.1 LABEL DESCRIPTION VIN Input voltage connection GND GND connection for input and output VOUT Output voltage connection SYNC SYNC input EN UVLO/Enable input, pull to ground to disable converter PGOOD Power Good output VCC Pullup voltage supply connection for PGOOD Signal Connections Power Good Output The LM27403EVM-POL600 provides a test point for measuring the Power Good voltage. A 20-k resistor pull-up to an externally provided voltage source, designated VCC, is included. For true open-drain operation with no pullup, remove Rpg or the pullup voltage rail. Then, PGOOD can be connected to the EN terminal of a downstream regulator to provide sequential startup of two LM27403-based regulators. 6.2.2 EN Input The LM27403EVM-POL600 provides a test point for measuring the LM27403's UVLO/EN pin voltage. Shorting this test point to GND disables the regulator. 6.2.3 SYNC Input The LM27403EVM-POL600 provides a test point for applying a synchronization (SYNC) input signal. The free-running switching frequency is set at 600 kHz. However, the regulator can align in frequency and phase with that of the applied SYNC signal up to 1.2 MHz. The applied SYNC voltage should not exceed 5.5 V. CAUTION Proper control loop compensation, as related to the installed output capacitance appropriately derated for DC bias voltage, is imperative. Consult the LM27403 datasheet, LM27403 design tool, or WEBENCH(R) Designer for guidance with component selection. 6.3 Remote Sense Configuration Two switches on the motherboard, designated SENSE+ and SENSE-, are used to configure output voltage remote sensing. For local voltage sensing at the module's VOUT and SGND terminals, move the switch sliders to their respective inside positions (i.e. towards the module). Conversely, to achieve remote voltage sensing at the VOUT and GND banana plug connectors, move the switch sliders to their respective outer positions (i.e. away from the module). SNVU330 - October 2013 Submit Documentation Feedback LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated 11 TEST SETUP 7 www.ti.com TEST SETUP Figure 4 shows the recommended test setup to evaluate the LM27403EVM-POL600. Working at an ESD workstation, make sure that any wrist straps, boot straps or mats are connected referencing the user to earth ground before power is applied to the EVM. Oscilloscope Ammeter 1 Electronic Load + COM V COM Voltmeter 2 COM A Power Supply + -S +S V Voltmeter 1 Figure 4. Connection Diagram 7.1 Test Equipment Voltage Source: The input voltage source VIN should be a 0-20-V variable dc source capable of supplying 10 A. Multimeters: * Voltmeter 1: Input voltage at VIN to GND * Voltmeter 2: Output voltage at the output connector lugs (or locally at the module, depending on the remote sense configuration) * Ammeter 1: Input current (or use the power supply readout if its accuracy is deemed acceptable) Electronic Load: The output load should be an electronic constant-resistance or constant-current mode load capable of 0 Adc to 30 Adc at 1.8 V. Oscilloscope: A digital or analog oscilloscope can be used to measure pertinent converter waveforms. With the scope set to 20-MHz bandwidth and AC coupling, the output voltage ripple can be measured directly across an output capacitor with a short ground lead normally provided with the scope probe. Place the oscilloscope probe tip on the positive terminal of the output capacitor, holding the probe's ground barrel through the ground lead to the capacitor's negative terminal. It is not recommended to use a long leaded ground connection because this may induce additional noise given a large ground loop. To measure other waveforms, adjust the oscilloscope as needed. 12 LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated SNVU330 - October 2013 Submit Documentation Feedback TEST SETUP www.ti.com Fan: Some of this EVM's components may exceed temperatures of 60C during operation. Although not mandatory, a small fan capable of 200-400 LFM can be used to reduce component temperatures while the EVM is operating. Exercise care when touching the EVM while the fan is not running. Always exercise caution when touching any circuits that may be live or energized. Recommended Wire Gauge: * Input Source to VIN and GND: The recommended wire size is 1 x AWG #14 per input connection, with the total length of wire less than 4 feet (2 feet input, 2 feet return). * VOUT to LOAD: The minimum recommended wire size is 2 x AWG #14, with the total length of wire less than 4 feet (2 feet input, 2 feet return). 7.2 Recommended Test Setup 7.2.1 Input Connections * Prior to connecting the DC input source, it is advisable to limit the source current to 10 A maximum. Make sure the input source is initially set to 0 V and connected to VIN and GND banana connections as shown in Figure 4. An additional high-ESR electrolytic input capacitor may be required if long input lines are used. * Connect voltmeter 1 at VIN and GND connector lugs to measure the input voltage. * Connect ammeter 1 to measure the input current. 7.2.2 Output Connections Connect an electronic load to VOUT and GND connections. Set the load to constant-resistance mode or constant-current mode at 0 Adc before input voltage is applied. Use short load lines to minimize voltage drop to the load. * Connect voltmeter 2 at the output connectors' solder lugs to measure the output voltage. * The output current level is taken from the electronic load readout (if its accuracy is deemed acceptable). * 7.2.3 Local or Remote Output Voltage Sensing Slider switches designated SENSE+ and SENSE- on the host PCB are used to select local or remote output voltage sensing as follows: * Move the switches to their respective inner positions (i.e. towards the module) for local sensing at the VOUT and SGND module terminals. * Move the switches to their respective outer positions (i.e. away from the module) for remote sensing at the VOUT and GND banana power connectors. 7.3 Test Procedure 7.3.1 * * * * * * * Load, Line Regulation and Efficiency Set up the EVM as described above. Set load to constant resistance or constant current mode and to sink 0 Adc. Increase input source from 0 V to 12 V, using voltmeter 1 to measure input voltage. Use voltmeter 2 to measure output voltage, VOUT. Vary load from 0 to 30 Adc, VOUT should remain within load regulation specification. Vary input source voltage from 4.5 V to 20 V, VOUT should remain within line regulation specification. Decrease load to 0 A. Decrease input source voltage to 0 V. SNVU330 - October 2013 Submit Documentation Feedback LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated 13 TEST DATA AND PERFORMANCE CURVES 8 www.ti.com TEST DATA AND PERFORMANCE CURVES Figure 5 through Figure 18 present typical performance curves for the LM27403EVM-POL600. Since actual performance data can be affected by measurement techniques and environmental variables, these curves are presented for reference and may differ from actual field measurements. 8.1 Efficiency 100 Efficiency (%) 95 90 VOUT = 1.8V 85 VOUT = 3.3V VOUT = 1.2V 80 75 VIN = 12V 70 0 5 10 15 20 25 Output Current (A) 30 C008 Figure 5. Efficiency 8.2 Load Regulation Output Voltage (V) 1.84 1.82 1.8 1.78 VIN = 12V 1.76 0 5 10 15 20 Output Current (A) 25 30 C009 Figure 6. Load Regulation 14 LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated SNVU330 - October 2013 Submit Documentation Feedback TEST DATA AND PERFORMANCE CURVES www.ti.com 8.3 Line Regulation Output Voltage (V) 1.84 1.82 1.80 1.78 IOUT = 0A 1.76 0 4 8 12 16 Input Voltage (V) 20 C010 Figure 7. Line Regulation 8.4 Current Limit Hiccup Mode IOUT VOUT Figure 8. Current Limit Hiccup Mode SNVU330 - October 2013 Submit Documentation Feedback LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated 15 TEST DATA AND PERFORMANCE CURVES 8.5 www.ti.com Load Transient Response IOUT VOUT Figure 9. Load Transient Response; VIN = 12 V, VOUT = 1.8 V, 0 A to 10 A at 2 A/s 8.6 Output Ripple VOUT Figure 10. Output Voltage Ripple; VIN = 12 V, VOUT = 1.8 V, IOUT = 20 A 16 LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated SNVU330 - October 2013 Submit Documentation Feedback TEST DATA AND PERFORMANCE CURVES www.ti.com 8.7 Startup and Shutdown - VIN IOUT VIN VOUT Figure 11. Startup with VIN Stepped to 12 V; VOUT = 1.8 V, 30-A Resistive Load VIN IOUT VOUT Figure 12. Shutdown After VIN Disconnected; VIN = 12 V, VOUT = 1.8 V, 22-A Resistive Load SNVU330 - October 2013 Submit Documentation Feedback LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated 17 TEST DATA AND PERFORMANCE CURVES 8.8 www.ti.com Startup and Shutdown - Enable IOUT VIN EN VOUT Figure 13. Startup with EN Stepped to 3 V; VIN = 12 V, VOUT = 1.8 V, 30-A Resistive Load VIN EN IOUT VOUT Figure 14. Shutdown with EN Pulled To GND; VIN = 12 V, VOUT = 1.8 V, 20-A Resistive Load 18 LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated SNVU330 - October 2013 Submit Documentation Feedback TEST DATA AND PERFORMANCE CURVES www.ti.com 8.9 Pre-Bias Startup VIN VOUT Figure 15. Pre-bias Startup; VIN = 12 V, No Load, 0.6-V Pre-bias 8.10 Switch Node SW Figure 16. Switch Node Voltage; VIN = 12 V, VOUT = 1.8 V SNVU330 - October 2013 Submit Documentation Feedback LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated 19 TEST DATA AND PERFORMANCE CURVES www.ti.com 8.11 Switch Deadtimes LG SW Figure 17. Deadtime Prior To High-side MOSFET Turn-on; VIN = 12 V, VOUT = 1.8 V, 120-m Load SW LG BOOT-SW Figure 18. Deadtime Prior To High-side MOSFET Turn-off; VIN = 12 V, VOUT = 1.8 V, 120-m Load 20 LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated SNVU330 - October 2013 Submit Documentation Feedback EVM DOCUMENTATION www.ti.com 9 EVM DOCUMENTATION 9.1 Schematics Figure 19. Module Schematic Figure 20. Motherboard Schematic SNVU330 - October 2013 Submit Documentation Feedback LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated 21 EVM DOCUMENTATION 9.2 www.ti.com Module PCB Layout Figure 21 through Figure 24 show the LM27403EVM-POL600 4-layer module PCB (2-oz copper). This is a single-sided design with bottom-side SMT pads for power and signal connections to the host PCB. Figure 21. Top Copper and Paste Layers Figure 22. Internal Layer 2 (Top view) 22 LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated SNVU330 - October 2013 Submit Documentation Feedback EVM DOCUMENTATION www.ti.com Figure 23. Internal Layer 3 (Top view) Figure 24. Bottom Copper and Paste Layers (Bottom view) SNVU330 - October 2013 Submit Documentation Feedback LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated 23 EVM DOCUMENTATION 9.3 www.ti.com Motherboard PCB Layout Figure 25 through Figure 28 show the motherboard PCB (2-oz copper). Figure 25. Top Copper and Paste Layers Figure 26. Internal Layer 2 (Top view) 24 LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated SNVU330 - October 2013 Submit Documentation Feedback EVM DOCUMENTATION www.ti.com Figure 27. Internal Layer 3 (Top view) Figure 28. Bottom Copper and Paste Layers (Bottom view) SNVU330 - October 2013 Submit Documentation Feedback LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated 25 EVM DOCUMENTATION 9.4 www.ti.com Assembly Drawings Figure 29. Module Assembly Drawing Figure 30. Motherboard Assembly Drawing 26 LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated SNVU330 - October 2013 Submit Documentation Feedback EVM DOCUMENTATION www.ti.com 9.5 Bill of Materials Table 4. Bill of Materials - Module Count Ref Des Description Part Number Manufacturer 1 C1 Capacitor, Ceramic, 47nF, 25V, X7R, 10%, 0402 Generic Multi-sourced 1 C2 Capacitor, Ceramic, 47pF, 50V, C0G/NPO, 5%, 0402 Generic Multi-sourced 1 C3 Capacitor, Ceramic, 3300pF, 50V, X7R, 10%, 0402 Generic Multi-sourced 1 C4 Capacitor, Ceramic, 470pF, 50V, C0G/NPO, 5%, 0402 Generic Multi-sourced 1 C5 Capacitor, Ceramic, 1F, 25V, X5R, 10%, 0603 Generic Multi-sourced 1 C6 Capacitor, Ceramic, 4.7F, 10V, X5R, 10%, 0603 C0603C475K8PACTU Kemet 3 C7, C8, C10 Capacitor, Ceramic, 0.1F, 50V, X7R, 10%, 0402 Generic Multi-sourced 1 C9 Capacitor, Ceramic, 1F, 10V, X5R, 20%, 0402 Generic Multi-sourced 1 C11 Capacitor, Ceramic, 100pF, 50V, X7R, 10%, 0402 Generic Multi-sourced 1 C12 Capacitor, Ceramic, 22F, 25V, X5R, 10%, 1210 12103D226KAT2A AVX 3 C20, C21, C22 Capacitor, Ceramic, 100F, 6.3V, X5R, 20%, 1206 C1206C107M9PACTU Kemet 1 C31 Capacitor, Ceramic, 2200pF, 50V, X7R, 10%, 0402 Generic Multi-sourced 1 D1 Diode Schottky, 40V, 200mA, SOD-882 PMEG4002EL NXP FP1107R1-R30-R Coiltronics 744308025 Wurth Electronik SLC1175-301MEC Coilcraft PCDC1107-R30EMO Cyntec 1 L1 Inductor, 300nH, 0.29m DCR, 34A Isat 1 PCB PCB, FR4, 4 layer, 20 mm x 15 mm PCB1 Multi-sourced 1 Q1 Transistor, NPN, 40V, 0.2A, SOT-923 MMBT3904LP Diodes Inc. 1 Q2 Synchronous Buck NexFETTM Power Block, N-Channel, 30V CSD87350Q5D TI 1 R1 Resistor, Chip, 84.5k, 1/16W, 1%, 0402 Generic Multi-sourced 1 R2 Resistor, Chip, 15k, 1/16W, 1%, 0402 Generic Multi-sourced 2 R5, R11 Resistor, Chip, 10k, 1/16W, 1%, 0402 Generic Multi-sourced 1 R6 Resistor, Chip, 200, 1/16W, 1%, 0402 Generic Multi-sourced 1 R7 Resistor, Chip, 20k, 1/16W, 1%, 0402 Generic Multi-sourced 1 R8 Resistor, Chip, 2.32k, 1/16W, 1%, 0402 Generic Multi-sourced 1 R9 Resistor, Chip, 4.02k, 1/16W, 1%, 0402 Generic Multi-sourced 1 R10 Resistor, Chip, 2.2, 1/16W, 5%, 0402 Generic Multi-sourced 1 R16 Resistor, Chip, 10, 1/16W, 1%, 0402 Generic Multi-sourced 1 R26 Resistor, Chip, 3.48k, 1/16W, 1%, 0402 Generic Multi-sourced U1 IC, Synchronous Buck Controller with DCR Current Sensing and Thermal Compensation, 4-mm x 4-mm WQFN-24 PowerPADTM package LM27403SQ TI 1 SNVU330 - October 2013 Submit Documentation Feedback LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated 27 EVM DOCUMENTATION www.ti.com Table 5. Bill of Materials - Motherboard Count Ref Des 28 Description Part Number Manufacturer 4 Cin1, Cin2, Cin4, Cin5 Capacitor, Ceramic, 22F, 25V, X5R, 10%, 1210 12103D226KAT2A AVX 1 Cin3 Capacitor, Oscon, 33F, 25V, 20%, 80m, SMD EEHZA1E330R Panasonic 4 Co1, Co2, Co4, Co5 Capacitor, Ceramic, 100F, 6.3V, X5R, 20%, 1210 GRM32ER60J107ME20L Murata 4 H1, H2, H3, H4 Machine Screw, Round, #4-40 x 1/4, Nylon, Philips panhead NY PMS 440 0025 PH B&F Fastener Supply 4 H5, H6, H7, H8 Standoff, Hex, 0.5"L #4-40 Nylon 1902C Keystone 1 MOD1 POL Module, 20 mm x 15 mm - - 1 RS- Resistor, Chip, 10, 1/10W, 1%, 0603 Generic Multi-sourced 1 Rpg Resistor, Chip, 100k, 1/10W, 1%, 0603 Generic Multi-sourced 1 Rtrim Resistor, Chip, 10k, 1/10W, 1%, 0603 Generic Multi-sourced 1 PCB PCB, FR4, 6 layer, 50 mm x 50 mm PCB2 Multi-sourced 3 VIN, VOUT, GND Banana Jack Power Terminal 108-0740-001 Emerson 4 VCC, EN, PGOOD, SYNC Test Point, SMT, Miniature 5015 Keystone 2 SENSE+, SENSE- Switch, slide, SPDT, 100mA, SMT CAS-210TA Copal Electronics LM27403EVM-POL600 Evaluation Module Copyright (c) 2013, Texas Instruments Incorporated SNVU330 - October 2013 Submit Documentation Feedback EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Should this evaluation board/kit not meet the specifications indicated in the User's Guide, the board/kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. 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For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable protection against radio frequency interference. Operation of the equipment may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. General Statement for EVMs including a radio User Power/Frequency Use Obligations: This radio is intended for development/professional use only in legally allocated frequency and power limits. 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Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Concerning EVMs including detachable antennas Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device. Cet appareil numerique de la classe A ou B est conforme a la norme NMB-003 du Canada. Les changements ou les modifications pas expressement approuves par la partie responsable de la conformite ont pu vider l'autorite de l'utilisateur pour actionner l'equipement. Concernant les EVMs avec appareils radio Le present appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisee aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioelectrique subi, meme si le brouillage est susceptible d'en compromettre le fonctionnement. Concernant les EVMs avec antennes detachables Conformement a la reglementation d'Industrie Canada, le present emetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inferieur) approuve pour l'emetteur par Industrie Canada. Dans le but de reduire les risques de brouillage radioelectrique a l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnee equivalente (p.i.r.e.) ne depasse pas l'intensite necessaire a l'etablissement d'une communication satisfaisante. Le present emetteur radio a ete approuve par Industrie Canada pour fonctionner avec les types d'antenne enumeres dans le manuel d'usage et ayant un gain admissible maximal et l'impedance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est superieur au gain maximal indique, sont strictement interdits pour l'exploitation de l'emetteur. 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