PL671-02
PicoEMITM Spread Spectrum Clock Generator
Micrel Inc. • 2180 Fortune Dr ive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 07/24/09 Page 3
FUNCTIONAL DESCRIPTION
PL671-02 is a highly featured, very flexible, advanced programmable PLL design for hi gh performance, low-power
Spread Spectrum modulation applications. The PL671-02 accepts a reference clock input of 1MHz to 200MHz and
is capable of producing three SST modulated outputs up to 200MHz. This flexible design allows the PL671 -02 to
deliver any PLL generated frequency, FREF (Ref Clk) frequency or FREF /2 to CLK0, CLK1 and/or CLK2. Alternate
programming using CSEL allows the device to choose from 2 different pre -programmed settings providing a range
of spread settings and outputs to choose from. Some of the design features of the PL671-02 are mentioned below.
PLL Programming
The PLL in the PL671-02 is fully programmable. The
PLL is equipped with a 9-bit input frequency divider
(R-Counter), and an 11-bit VCO frequency feedback
loop divider (M-Counter). The output of the PLL is
transferred to a 6-bit post VCO Odd/Even divider (P -
Counter). The output frequency is determined by the
following formula [FOUT = (FREF * M)/(R*P).
Modulation Magnitude and Type
The PL671-02 provides the following programmable
capabilities for Modulation Type and Modulation
Magnitude (Spread Percentage):
Modulation Rate
The PL671-02 modulation rate is defined as FREF (Ref
Clk Frequency) divided by 8 times the R-counter, i.e.
Modulation Rate = (FREF / 8R). The rate can be
changed by choosing alternate R-Counter settings.
Clock Outputs (CLK[0:2])
CLK0 is the main clock output. The PL671-02 can
also be programmed with additional clock outputs
CLK1 and CLK2. The outputs of CLK[0:2] can be
configured as described below:
CLK0= FREF, FREF/2 or FVCO/P*
CLK1= FREF, FREF/2 or FVCO/P*
CLK2= FREF, CLK0, CLK0/2 or CLK0/4
Where
FREF - Reference (Ref Clk) Frequency
FOUT = FREF * M / (R * P)
The output drive level of each output can be
independently programmed to Low Drive (4mA),
Standard Drive (8mA) or High Drive (16mA). The
output frequency can be programmed up to 200MHz
at 3.3V (166MHz at 2.5V).
Power-Down Control (PDB)
When activated (logic ‘0’), PDB ‘Disables the PLL,
the oscillator circuitry, counters, and all other active
circuitry. In Power Down mode the IC consumes
<10µA of power. The PDB input incorporates a
60kΩ pull up resistor giving a default condition of
logic “1”.
Configuration Select (CSEL)
The PL671-02 has the capability to be programmed
with 2 distinct configurations and to toggle “On the
Fly” between these configurations using the selector
pin CSEL. CSEL incorporates a 60kΩ pull up
resistor giving a default condition of logic “1”.