Rev 0; 5/05 Full Laser Control with Fault Management Features The DS1861 is a laser-driver control IC designed to reduce the production cost of fiber optics circuits by eliminating multiple temperature tests. It works with nearly all laser-driver ICs to provide automatic power control (APC) and automatic extinction ratio control (AERC), which improves the performance of the system over temperature and aging. It also has built-in monitoring capability to provide early fault detection, which can be configured to latch the IC into a shutdown condition. Settings programmed into the DS1861 are stored in password-protected EEPROM memory, which writeprotects calibration data. Programming is accomplished through an I2C-compatible interface, which can also be used to read diagnostic information. Automatic Power Control (APC) Automatic Extinction Ratio Control (AERC) Across Temperature and Laser Aging Works in AC-Coupled Laser Systems Configurable Latched Automatic Shutdown with Tx-Fault and Tx-Disable Programmable Fast Alarm Conditions I2C-Compatible Serial Interface Allows Up to Eight Devices on the Same Serial Bus Operates Over Wide Supply-Voltage Range Nonvolatile Memory for Device Settings Small, 14-Pin TSSOP Package -40C to +95C Operating Temperature Range Applications Ordering Information Optical Transceivers Optical Transponders PART TEMP RANGE PIN-PACKAGE DS1861E -40C to +95C 14 TSSOP (173 mils) DS1861E+ -40C to +95C 14 TSSOP (173 mils) +Denotes lead free. Pin Configuration appears at end of data sheet. Typical Operating Circuit VCC 30k 4.7k VCC 4.7k VCC VCC 4.7k MAX3736 DS1861 SCL SDA LASER DRIVER BIASSET TX-F BIAS OUT MOD BIAS IBIASSET TX-D MODSET IMODSET N.C. N.C. A2 A1 A0 GND BMD IBMD 1nF ______________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 DS1861 General Description DS1861 Full Laser Control with Fault Management ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC, SDA, and SCL Pins Relative to Ground.....................................-0.5V to +6.0V Voltage Range on A0, A1, A2, Tx-Fault, Tx-Disable, BIASSET, MODSET, and BMD Relative to Ground.................-0.5V to (VCC + 0.5V), not to exceed +6.0V Operating Temperature Range ...........................-40C to +95C EEPROM Programming Temperature Range .........0C to +70C Storage Temperature Range .............................-55C to +125C Soldering Temperature .......................................See IPC/JEDEC J-STD-020 Specification Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (VCC = +2.85V to 5.5V, TA = -40C to +95C.) PARAMETER SYMBOL MAX UNITS 2.85 5.50 V VIH1 0.7 x VCC VCC + 0.3 V Input Logic 0 (SDA, SCL, A2, A1, A0) VIL1 -0.3 +0.3 x VCC V Input Logic 1 (TX-D) VIH2 1.5 Input Logic 0 (TX-D) VIL2 Supply Voltage VCC Input Logic 1 (SDA, SCL, A2, A1, A0) CONDITIONS (Note 1) Voltage at BIASSET and MODSET MIN TYP V 0.6 ITH/IAPC Ratio (Note 2) 0.9 V 3.0 V 7:1 DC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to 5.5V, TA = -40C to +95C.) PARAMETER SYMBOL Supply Current ICC Input Leakage ILI Output Leakage (TX-F, SDA) CONDITIONS MIN (Note 3) -1 TYP MAX UNITS 5 7 mA +1 A A ILO High impedance -1 +1 Low-Level Output Voltage (TX-F, SDA) VOL1 3mA sink current 0 0.4 VOL2 6mA sink current 0 0.6 I/O Capacitance CI/O 10 pF -10 +10 A Input Current Each I/O Pin 2 0.4 < VI/O < 0.9 x VDD _____________________________________________________________________ V Full Laser Control with Fault Management DS1861 ANALOG OUTPUT CHARACTERISTICS (VCC = +2.85V to 5.5V; TA = -40C to +95C.) PARAMETER SYMBOL BIASSET Current Range IBIASSET CONDITIONS MIN BIASSET Shutdown Current MODSET Current Range TYP 0.01 10 IMODSET 0.01 MODSET Shutdown Current 10 MAX UNITS 1.50 mA 100 nA 1.20 mA 100 nA 3 % % APC Calibration Accuracy (Error in Setting IBMD) (Note 4) APC Temp Drift (% Drift in IBMD) (Note 5) 2 4 40A < IMODSET < 100A at +25oC (Note 6) 1 4 100A < IMODSET < 400A at +25oC (Note 6) 1 3 1 2.75 N Temp Drift o IMODSET > 400A at +25 C (Note 6) Extinction Ratio Calibration Accuracy At 10dB extinction ratio Loop Transient Settling Error IBIASSET and IMODSET after 300ms Extinction Ratio Update Frequency fERU Peak BMD Disturbance Current IDIST 0.22 dB 3 % 25 Hz 3.33 3.60 % TYP MAX UNITS 1.50 mA V 5 Percent increase above IBMD % ANALOG INPUT CHARACTERISTICS (VCC = +2.85V to 5.5V, TA = -40C to +95C.) PARAMETER SYMBOL BMD Current--Source or Sink () ISET BMD Voltage BMD Input Resistance Reference Voltage VBMD RBMD VREF CONDITIONS MIN (Note 7) 0.05 IBMD = 0.5x to 2x ISET 1.0 1.24 1.5 Gain = 16 175 265 350 Gain = 8 350 530 700 IBMD = ISET 10% (ISET) Gain = 4 700 1060 1400 Gain = 2 1400 2120 2800 Gain = 1 2800 4240 5600 1.24 V _____________________________________________________________________ 3 DS1861 Full Laser Control with Fault Management FAST ALARMS AND VCC MONITOR CHARACTERISTICS (VCC = +2.85V to 5.5V, TA = -40C to +95C.) PARAMETER SYMBOL CONDITIONS High Bias Alarm LSB 255 settings (includes off) High Bias Alarm Threshold Accuracy High bias settings > 100A MIN TYP MAX 8.2 UNITS A 10 % LTXP_Thres (bin) LTXP Alarm Threshold Multiplier (ISET Multiplier Shown, Note 8) XXXXX000 LTXP Alarm OFF XXXXX001 Do not use XXXXX010 0.81 XXXXX011 0.76 XXXXX100 0.54 XXXXX101 0.41 XXXXX110 0.28 XXXXX111 0.14 mA/mA HTXP_Thres (bin) HTXP Alarm Threshold Multiplier (ISET Multiplier Shown, Note 8) XXXXX000 HTXP Alarm OFF XXXXX001 Do not use XXXXX010 1.30 XXXXX011 1.43 XXXXX100 1.56 XXXXX101 1.69 XXXXX110 1.82 XXXXX111 1.95 mA/mA VCC Power Good VPOA 2.15 2.70 V Vcc Fault Deassert Delay tPOAR 360 700 s Digital Power-On Reset Voltage VPOD 1.0 2.2 V MAX UNITS 400 kHz I2C AC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to 5.5V, TA = -40C to +95C, timing referenced to VIL(MAX) and VIH(MIN).) (Figure 14) PARAMETER SYMBOL CONDITIONS fSCL Bus Free Time Between Stop and Start Conditions tBUF 1.3 s tHD:STA 0.6 s tLOW 1.3 s tHIGH 0.6 tHD:DAT 0 Low Period of SCL High Period of SCL Data Hold Time 4 _____________________________________________________________________ 0 TYP SCL Clock Frequency Hold Time (Repeated) Start Condition (Note 9) MIN s 0.9 s Full Laser Control with Fault Management DS1861 I2C AC ELECTRICAL CHARACTERISTICS (continued) (VCC = +2.85V to 5.5V, TA = -40C to +95C, timing referenced to VIL(MAX) and VIH(MIN).) (Figure 14) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Data Setup Time tSU:DAT 100 ns Start Setup Time tSU:STA 0.6 s SDA and SCL Rise Time tR (Note 10) 20 + 0.1CB 300 ns SDA and SCL Fall Time tF (Note 10) 20 + 0.1CB 300 ns Stop Setup Time tSU:STO 0.6 SDA and SCL Capacitive Loading CB (Note 10) EEPROM Write Time tW (Note 11) s 400 pF 10 20 ms TYP MAX UNITS 30 V/ms MAX UNITS 5 s POWER-SUPPLY AC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to 5.5V, TA = -40C to +95C.) PARAMETER Supply Slew Rate SYMBOL dV/dt Vcc CONDITIONS MIN VCC = 0 to 5.5 (Note 12) SHUTDOWN AND FAULT AC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to 5.5V, TA = -40C to +95C.) PARAMETER SYMBOL CONDITIONS MIN TYP BIASSET and MODSET Disable (10% of Active Level) tOFF From rising edge of TX-D APC Recovery From Normal Disable (to IBMD 90% Level) tON:B From falling edge of TX-D (Note 13) 0.8 ms Modulation Recovery From Normal Disable (to IMODDRIVER 90% Level) tON:M From falling edge of TX-D (Note 14) 0.2 ms APC Recovery After Power-Up or Shutdown (to IBMD 90% Level) tINIT:B (Note 13) 0.8 ms Modulation Recovery After Power-Up or Shutdown (to IMODDRIVER 90% Level) tINIT:M 100 ms Fault Reset Time (to TX-Fault = 0) tINIT:F 150 ms Shutdown Time (to 10% IBIASSET, 10% IMODSET, TX-F High) tFAULT 50 s Minimum Reset Pulse Width tRESET 100 IBMD > HTXP Threshold, or IBIAS HBIAS Threshold, or IBMD < LTXP Threshold 1 s _____________________________________________________________________ 5 DS1861 Full Laser Control with Fault Management NONVOLATILE MEMORY CHARACTERISTICS (VCC = +2.85V to 5.5V, TA = 0C to +70C.) PARAMETER Writes Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: 6 SYMBOL CONDITIONS +70C (Note 15) MIN TYP MAX UNITS 50,000 All voltages are referenced to ground. Currents into the IC are positive, out of the IC negative. The threshold current (ITH) to light producing current (IAPC) ratio should remain below 7:1. This limits overshoot to under 10% and ensures the data sheet accuracies are met. Max ICC is dependent on SCL clock rates. Calibration accuracy refers to the accuracy achieved at the end of calibration. This specification refers to the error contribution due to this chip, and does not include the error due to the drift of the monitor-diode responsivity with temperature. The N Temperature Drift specification includes error caused by changes in modulation current due to system temperature variation. After the part is calibrated at +25C, this spec allows for modulation current changes of up to +65% with increasing temperature and -25% with decreasing temperature. Larger modulation current variations would have increased drift, but this range accommodates a reasonable change (up to 2x across temperature) in laser diode slope efficiency. Calibration is assumed to take place at +25C for the purposes of this spec. This does not imply that the system must be calibrated at +25C. Within the APC calibration accuracy. Values in the table are multiplied times the IBMD set point (set by APC register) to determine the threshold limits. I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing. CB--total capacitance of one bus line in pF. EEPROM write begins after a stop condition occurs. If the supply ramps up at slew rates within the specification, the device will be functional after VCC exceeds VPOA and the power-up time (tPOAR) elapses. On power-up and when TX-D is deasserted, IBIASSET ramps up from zero current to its final value with 10% APC overshoot during the transient. Modulation is applied at the level it was at before disable. If the time from disable is so long that the laser has cooled down, then meeting ER accuracy is contingent upon completion of the first ER update. The MODLOAD enable bit and MODLOAD register can be used to load a predetermined IMODSET value if desired. See the Detailed Register Descriptions section for more information. This parameter is guaranteed by design. _____________________________________________________________________ Full Laser Control with Fault Management VCC > VPOA tPOAR TX-D TX-F tINIT:F tINIT:B IBIASSET IMODSET tINIT:M Figure 1. Power-Up Timing with TX-D Not Asserted (Including Hotplug) VCC > VPOA TX-D TX-F tINIT:F tINIT:B IBIASSET tINIT:M IMODSET Figure 2. Power-Up Timing with TX-D Asserted _____________________________________________________________________ 7 DS1861 Timing Diagrams Full Laser Control with Fault Management DS1861 Timing Diagrams (continued) TX-D TX-F* IBIASSET tON:B tOFF tINIT:M IMODSET tOFF tON:M FIRST CONTROL LOOP ADJUSTMENT OF IMODSET AFTER TX-D IS DEASSERTED *TX-F WILL ASSERT IF THE HTXP ALARM IS TRIGGERED WHILE THE BIAS CURRENTS ARE DISABLED. THE LTXP ALARM IS MASKED WHILE TX-D IS ASSERTED. Figure 3. TX-D Timing During Normal Operation OCCURENCE OF FAULT TX-D TX-F tFAULT IBIASSET tFAULT IMODSET tFAULT Figure 4. Detection of Transmitter Safety Fault Condition 8 _____________________________________________________________________ Full Laser Control with Fault Management OCCURENCE OF FAULT TX-D tRESET tINIT:F TX-F IBIASSET tINIT:B IMODSET tINIT:M Figure 5. Successful Recovery from Transmitter Safety Fault Condition OCCURENCE OF FAULT tRESET TX-D TX-F TX-F REMAINS HIGH DURING AN UNSUCCESSFUL RECOVERY DUE TO THE INTERNAL TIMER. IBIASSET tINIT:M IBIASSET AND IMODSET MAY HAVE TO BIAS THE PART TO RECREATE THE SHUTDOWN CONDITION. IMODSET Figure 6. Unsuccessful Recovery from Transmitter Safety Fault Condition _____________________________________________________________________ 9 DS1861 Timing Diagrams (continued) Typical Operating Characteristics (VCC = +5.0V, TA = +25C, unless otherwise noted.) GAIN = 4, APC = 16, EXT. LOOP GAIN = 1 DPOL = 1 6.5 6.4 3.35 3.85 4.35 4.85 6.2 -0.6 -0.8 VCC = 5.0V, APC = 4, GAIN = 16 -1.0 -40 -15 10 35 60 85 2.85 4.85 N DRIFT vs. TEMPERATURE -1.2 -1.4 IMODSET = 40A 20 15 10 35 60 IMODSET = 100A -2 0 85 IMODSET = 400A 0 VCC = 2.85V VCC = 5.0V, APC = 16, GAIN = 4 10 1 -1 5 TEMPERATURE (C) DS1861 toc06 2 N DRIFT (%) OUTPUT CURRENT (mA) 25 5.35 3 DS1861 toc05 30 DS1861 toc04 DPOL = 1 -1.0 -15 4.35 TX-F OUTPUT CURRENT vs. OUTPUT VOLTAGE -0.6 -40 3.85 IBMD DRIFT vs. TEMPERATURE -0.4 -1.8 3.35 SUPPLY VOLTAGE (V) DPOL = 0 -1.6 DPOL = 1 TEMPERATURE (C) -0.2 -0.8 0 -0.2 -0.4 5.35 DPOL = 0 0.2 SUPPLY VOLTAGE (V) 0.2 0 0.4 6.3 6.0 2.85 10 6.6 6.1 4.9 0.6 DPOL = 0 6.7 TA = 25C, APC = 16, GAIN = 4 0.8 IBMD DRIFT (%) DPOL = 1, TA = +25C DPOL = 1, TA = +85C DPOL = 1, TA = -40C 5.4 6.9 6.8 6.4 1.0 DS1861 toc02 DS1861 toc01 DPOL = 0, TA = +85C DPOL = 0, TA = +25C DPOL = 0, TA = -40C 5.9 7.0 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 6.9 IBMD DRIFT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE DS1861 toc03 SUPPLY CURRENT vs. SUPPLY VOLTAGE IBMD DRIFT (%) DS1861 Full Laser Control with Fault Management VCC = 2.85V, DPOL = 0, N = 30 -3 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OUTPUT VOLTAGE ____________________________________________________________________ -40 -15 10 35 TEMPERATURE (C) 60 85 Full Laser Control with Fault Management PIN 11 NAME FUNCTION 1 SDA Serial Data Input/Output. I2C bidirectional data pin, which requires a pullup resistor to realize high logic levels. 2 SCL Serial Clock Input. I2C clock input. 3 TX-F Transmit Fault Output. Open-collector output that indicates an alarm condition has occurred. A pullup resistor is required on this pin to realize high logic levels. 4 TX-D Transmit Disable Input 5, 8 N.C. No Connection 6 BMD Photodiode Current Input 7 GND 9 BIASSET 10 A0 11 A1 12 A2 13 MODSET 14 VCC Ground Bias Current Output I2C Address Inputs. These inputs determine the slave address of the device. The slave address in binary is 1010A2A1A0. Modulation Current Ouput Power Supply ___________________________________________________________________________________________________ ____________________________________________________________________ 11 DS1861 Pin Description Full Laser Control with Fault Management DS1861 Functional Diagram VCC VCC SDA USER EEPROM (8 BYTES) I2C-COMPATIBLE INTERFACE SCL AUTOMATIC POWER CONTROL WITH SETTINGS PASSWORD PROTECTION A2 IDIST DISTURBANCE CURRENT BIASSET IB IBMD NONVOLATILE MODSET AUTOMATIC EXTINCTION RATIO CONTROL A1 A0 IBMD NONVOLATILE VREF TX-D RBMD TX-F QUICK TRIP FAULT MONITOR NONVOLATILE IB BMD IBMD VCC ISET CURRENT SENSE GND DS1861 Detailed Description Automatic Power Control The DS1861 APC is accomplished by adjusting the bias current (IBIAS) until the feedback current (IBMD) from a photodiode matches the value determined by the APC register. The relationship between the APC register and IBMD is given by: ISET = 1.525A Gain (APC<4:0> + 32) where APC<4:0> is the numerical value determined by the five least significant bits of the APC register, and the gain value is determined by the upper three bits of the APC register, as shown in the truth table below. See Figure 7 for a graph of the BMD current-set point vs. the APC register value. 12 APC<7:5> GAIN 000 1 001 2 010 4 011 8 1xx 16 CURRENT SINK/SOURCE The BMD pin appears to the photodiode as a voltage source (VREF) with an output resistance equal to RBMD in parallel with a current source (ISET) equal to the IBMD setpoint. When the control loop is at its steady state value, the voltage at the BMD pin (VBMD) is equal to VREF, and the BMD current will all be sourced by ISET. When an imbalance causes the feedback current to differ from the set current, the difference in the currents causes the DS1861 to adjust the BIASSET and the MODSET currents to new settings so the input current matches the set current. During transient periods, the difference in the ISET and IBMD currents causes a small current to pass through RBMD. This causes a slight increase or decrease in the VBMD voltage. The current source can sink and source current, which must be configured using the DPOL bit in the control byte for proper operation. This allows the photodiode to be referenced to either V CC or GND. See the Memory Map and Detailed Register Descriptions sections for more detail. ____________________________________________________________________ Full Laser Control with Fault Management Automatic Extinction Ratio Control The DS1861 injects a small disturbance current to measure the gain (light/mA) of the laser driver and laser diode pairing. This control methodology makes the extinction ratio insensitive to changes in the photodiode's responsivity due to temperature and aging effects, as long as the ratio of the laser driver's bias current gain (AD) and modulation current gain (A M) remains constant (Figure 8). The IBIASSET and IMODSET currents are generated by embedded 18-bit and 12-bit DACs, respectively, and their output currents can be read when the DS1861 has been halted using the halt bit, and the password has been entered. See the Detailed Register Descriptions section for information on calculating the output current from the register's value. DS1861 fig07 The disturbance current is automatically scaled as the BMD current-set point is adjusted, so the peak disturbance current always increases IBMD by approximately 3.3%. See Figure 9 for details. 1.500 To understand how the MODSET and BIASSET currents control the extinction ratio, the extinction ratio equation (extinction ratio = P1/P0) must first be expressed in terms of the modulation power (PMOD) and average power (PAVG). Figure 10 shows the current and power levels that correspond to the optical logic 1 (P1) and logic 0 (P0) levels. ISET (mA) 1.125 0.750 0.375 1 PAVG + PMOD P1 2 Extinction Ratio = = 1 P0 P PMOD - AVG 2 0 0 64 128 192 255 APC REGISTER SETTING (DECIMAL) Figure 7. BMD Current Setpoint vs. APC Register Setting LASER DRIVER BIASSET MODSET IBIASSET IMODSET BIASREF MODREF AD AM BIAS MOD IBIAS IMOD AC-COUPLING ID* CIRCUITRY LASER DIODE DS1861 BMD IBMD PHOTODIODE LIGHT *ID = IBIAS 1 IMOD 2 Figure 8. AERC Block Diagram ____________________________________________________________________ 13 DS1861 Reading the BIASSET and MODSET Registers Once the extinction ratio is expressed as a function of the average power and the modulation power, the equation can then be written in terms of the modulation and average power currents. The modulation current (IMOD) is defined as the difference between the I1 and I0 currents (IMOD = I1 - I0). The average power current (IAPC) is the arithmetic mean of the I1 and I0 currents referenced to the threshold current (I APC = 1/2 I1 + 1/2 I0 - ITH). After defining these currents, the equation can now be rewritten as the following equations. BMD CURRENT DS1861 fig09 DS1861 Full Laser Control with Fault Management IDIST 1 fERU 1 IMOD 1 IAPC + IMOD 1 + x 2 IAPC 2 Extinction Ratio = = 1 IMOD 1 IAPC - IMOD 1 - x 2 IAPC 2 TIME DS1861 fig10 Figure 9. BMD Disturbance Current I1 IMOD 2 P1 IMOD 2 AVERAGE POWER PMOD IMOD N A x M = 30 IAPC AD Substituting into the previous extinction ratio equation yields the extinction ratio as a function of N. I0 P0 ITH The APC loop is already controlling IAPC to keep the average power at a constant value, so the DS1861 outputs IMODSET so that IMOD/IAPC remains constant to control the extinction ratio. The DS1861 determines the I MOD /I APC ratio according to the following formula, where N is a variable gain that can be used to adjust the extinction ratio. IMOD IAPC CURRENT (mA) A 1 N AM 60 + N M x x AD 2 30 AD Extinction Ratio = = AM 1 N AM 60 - N 1- x x AD 2 30 AD Figure 10. Laser Diode Bias Current Definitions 14 ____________________________________________________________________ 1+ Full Laser Control with Fault Management The ER<6:0> value should be programmed to values between 28 and 104 (decimal), regardless if the high or low range is selected, to ensure that the N value remains accurate and constant as intended. These limits allow the N values of the high and low range to overlap to ensure that all N values can be attained, but prevents potential errors that can be caused by using the extremes of each RSEL range. Figure 12 shows the N values as a function of the ER register setting. EXTINCTION RATIO (AM/AD = 1.2) vs. ER SETTING DS1861 fig11a 25 EXTINCTION RATIO (dB) 20 15 RSEL = 0 10 5 0 16 48 64 80 96 112 EXTINCTION RATIO (AM/AD = 0.8) vs. ER SETTING DS1861 fig11b 25 20 RSEL = 1 15 10 RSEL = 0 5 0 16 32 48 64 80 96 112 ER SETTING (DECIMAL) The Convergence Algorithm and Overshoot Control EXTINCTION RATIO (AM/AD = 0.4) vs. ER SETTING DS1861 fig11c 25 20 EXTINCTION RATIO (dB) The DS1861 uses a tiered slew-rate control system that adjusts the DAC update rate and the number of LSBs it increases/decreases per update cycle when the control loop is seeking to converge to its steady state value. For the APC loop, it makes its decision on the required convergence rate based on the percent error between the present BMD current and the BMD current-set point. The modulation current slew rate is adjusted based solely on the difference between its present code and the code-set point that is determined by the AERC circuitry. Both update rates are designed to prevent any overshoot during large set-point changes in excess of 10%, which assumes (see the following) the ratio of the laser diode's threshold current (I TH) to the average power current (IAPC) is below 7:1. Most systems do not exhibit any overshoot when using the DS1861. 32 ER SETTING (DECIMAL) EXTINCTION RATIO (dB) ER < 6 : 0 > +32 when RSEL = 0 N= 2 ER < 6 : 0 > +32 when RSEL = 1 DS1861 Figure 11 shows the extinction ratios (expressed in decibels) as a function of N for several AM/AD ratios. Note the actual extinction ratio value is determined by the ratio A M/A D in addition to N. If the A M/A D ratio varies due to voltage, temperature, or aging effects, it becomes an additional error source when determining the overall extinction ratio variance. The DS1861 is meant to be used with a monolithic laser driver, where A M and A D are generated on the same chip, so changes in the ratio of AM to AD are minimal. The N value itself is determined by the extinction ratio register. There are two components of the ER register used to calculate N. The range select bit (RSEL), which selects the high (RSEL = 1) or low (RSEL = 0) range of N, is the MSB of the register. The lower seven bits of the register (ER<6:0>) determine the value of N within the selected range. The value of N is given by: 15 RSEL = 1 10 RSEL = 0 5 0 16 32 48 64 80 96 112 ER SETTING (DECIMAL) Figure 11. Typical Extinction Ratios vs. N Codes ____________________________________________________________________ 15 DS1861 Full Laser Control with Fault Management INVALID ER SETTINGS SHADED 128 112 L= INVALID 1) INVALID E RS 96 ( GE N 80 N DS1861 fig12 144 The average power current is defined as the difference between the current required to reach the average power output and the threshold current of the laser diode. The average power output is defined as the mean of the power used to transmit a high logic level (P1) and the power used to transmit a low power level (P0). Figure 10 graphically shows the threshold and average power currents as they relate to the light output of a laser diode. H IG RA H EL = 64 S E (R 0) Fault Monitors and Shutdown G AN WR 48 The DS1861 has a VCC monitor plus three programmable quick-trip (QT) fault monitors (Figure 13) that can trigger the TX-F output. The QTs monitor for high transmit power (HTXP), low transmit power (LTXP), and for high bias current (HBIAS). All the QTs feature programmable trip levels, an alarm disable, and a shutdown enable to determine if the enabled QT alarm shuts off the IBIASSET and IMODSET outputs. VCC is monitored against two internal voltage levels to ensure that VCC is at an adequate level for the part to LO 32 16 0 27 28 127 104 105 ER REGISTER SETTING (DECIMAL) Figure 12. Setting N Using the ER Register TX-F LTXP ALARM SHUTDOWN FLAG BIASSET LTXP ENABLE QUICKSTART HTXP ALARM MODLOAD ENABLE HTXP ENABLE CONTROL LOGIC RST HBIAS ALARM HBIAS ENABLE HTXP SHUTDOWN HBIAS SHUTDOWN S TX-D SOFT TX-D S Q D LTXP SHUTDOWN Q D Q Q R S Q D R Q R POA NOTE: POA IS HIGH WHEN VCC < VPOA. Figure 13. Quick Trip Logic Diagram 16 ____________________________________________________________________ IN FAULT RESET TIMER (130ms) OUT IN OUT MODSET Full Laser Control with Fault Management The high and low transmit power quick-trip thresholds are each programmed by 3 bits that select one of seven different levels as a function of the expected IBMD current. Each QT monitor can be disabled by programming all three bits to zero. Disabling a QT by programming its control bits to zero prevents the QT alarm flags from ever being set, which consequently prevents that monitor from asserting the TX-F output, latching the device into a shutdown condition, or setting the alarm bits in the Status register. The HTXP and LTXP enable bits can be used to prevent the transmit power level QTs from causing shutdown while allowing the TX-F output to be set to flag the system of a transmit power fault condition. Figure 13 shows the shutdown logic. Tables 1 and 2 show the QT thresholds as a function of IBMD current-set point. The high-bias, quick-trip alarm features an 8-bit threshold setting with an LSB of 8.2A. Programming the HBIAS threshold to zero inhibits the HBIAS alarm flag, preventing TX-F from being asserted, the HBIAS alarm from causing a shutdown, and the HBIAS alarm bit in Status from being set. The HBIAS enable bit can be used to prevent shutdown from occurring while allowing the HBIAS alarm flag to trigger TX-F. Password Protection The DS1861 has two 16-bit password entry registers (used as a 32-bit value) and two 16-bit password registers (used as 32-bit value) that can be used to write-protect all the configuration settings. The password entry registers, PWE High and PWE Low, are the locations where the user enters the password to disable the write protection and change the device settings. The password bytes, PW High and PW Low, set the password to a new value. When the device is write-protected, the only bytes that can be written are the password entry bytes. To secure the password, the PW bytes always read as 0s when the PWE bytes do not match the PW bytes. Once the correct password has been entered into the DS1861 communicate over the I2C bus and for the analog circuitry to function properly. The first monitoring level, the power-on digital voltage (VPOD), inhibits the part's I2C functionality when V CC is below V POD. The second monitoring level is the power-on analog voltage (VPOA). The DS1861 disables I BIASSET and I MODSET and asserts the TX-F output whenever VCC is below VPOA. Both VCC monitors are nonmaskable, so there is no way to force the chip to function when VCC is not at an adequate level to assure the DS1861 operates properly. Table 1. HTXP Threshold Settings HTXP_Thresh<2:0> HIGH-TRANSMIT POWER THRESHOLD (ISET) 000 Disabled* 001 Do not use 010 1.30 011 1.43 100 1.56 101 1.69 110 1.82 111 1.95 *Disabled inhibits the HTXP QT from causing a shutdown or asserting TX-F. Table 2. LTXP Threshold Settings LTXP_Thresh<2:0> LOW-TRANSMIT POWER THRESHOLD (ISET) 000 Disabled* 001 Do not use 010 0.81 011 0.76 100 0.54 101 0.41 110 0.28 111 0.14 *Disabled inhibits the LTXP QT from causing a shutdown or asserting TX-F. PWE bytes, the password can also be read from the PW registers. Because the PWE bytes can be read all the time, it is recommended that the PWE bytes are written to all 1s once the desired settings are modified to prevent anyone from simply reading PWE to attain the password. The PWE bytes are SRAM, so they reset themselves to 1s if VCC drops below VPOA. In addition to write protection, the password must also be entered and the DS1861 must be HALTed to read the I BIASSET and I MODSET DAC codes. See the Reading the BIASSET and MODSET Registers section for more information about reading the DAC codes. ____________________________________________________________________ 17 DS1861 Full Laser Control with Fault Management DS1861 Memory Map BASE ADDR ROW NAME 78h WORD 0 WORD 1 WORD 2 BYTE 0/8 BYTE 1/9 BYTE 2/A Password Entry Status SRAM SRAM B0h APC Config User EE User EE APC User EE ER (N) B8h Fast Comp HTXP Threshold LTXP Threshold HBIAS Threshold User EE User EE C0h Password Reserved Reserved Reserved D0h DAC Codes Reserved IBIASSET Code Reserved SRAM KEY: BYTE 3/B BYTE 4/C WORD 3 BYTE 5/D PWE High BYTE 7/F PWE Low Reserved MODLOAD Control User EE PW High Reserved BYTE 6/E User EE User EE PW Low Reserved Reserved Reserved IMODSET Code EEPROM EXPANDED BYTES BYTE ADDR BYTE NAME 78h Status 7Bh 7Dh BIT 7 bit15 bit14 BIT 6 bit13 BIT 5 bit12 bit11 bit10 BIT 4 bit9 bit8 Shutdown Flag HTXP Shutdown LTXP Shutdown HBIAS Shutdown PWE High 231 230 229 228 227 226 225 PWE Low 215 214 213 212 211 210 29 APC GAIN2 GAIN1 GAIN0 2 B4h ER (N) RSEL 26 25 24 B5h MODLOAD 210 29 28 27 26 25 bit6 POA 224 223 28 27 4 B2h 211 BIT 3 bit7 2 BIT 2 bit5 HTXP Alarm 222 221 26 25 3 2 23 24 220 219 24 23 2 2 21 BIT 0 bit1 bit0 HBIAS Alarm 218 217 22 21 1 EE 20 2 21 20 216 0 20 EE EE EE Control B8h High TX-P Alarm Threshold EE EE EE EE EE 22 21 20 B9h Low TX-P Alarm Threshold EE EE EE EE EE 22 21 20 BAh High BIAS Alarm Threshold 27 26 25 24 23 22 21 20 C3h PW High 231 C5h PW Low 215 2 211 HBIAS Enable LTXP Alarm 22 22 bit2 B7h IBIASSET Code IMODSET Code LTXP Enable BIT 1 bit3 MODLOAD Enable D1h D6h HTXP Enable 23 bit4 230 229 214 213 7 2 210 29 228 227 212 211 6 2 28 27 226 225 210 29 5 2 26 25 DPOL Soft TX-D Excite Disable HALT 224 223 28 27 4 2 24 221 26 25 3 23 Note: 0 indicates an unused bit that reads as 0. 18 222 ____________________________________________________________________ 2 22 21 220 219 24 23 2 2 20 0 218 217 22 21 1 216 20 2 0 0 0 0 Full Laser Control with Fault Management Volatility: V is volatile (SRAM), NV is nonvolatile (EEPROM). Power-Up/Factory Default Value: For SRAM registers, this value is always the power-up value. For EEPROM registers, this is the factory default value. These can be permanently modified by entering the password and writing the register. N/A is used for hardware-dependent values, such as alarm flags. Password Entry * Status <R><V><N/A, depends on power-up condition> 0. HBIAS Alarm.....High Bias-Current Alarm. This flag is high when I BIASSET HBIAS Alarm Threshold. This flag is updated every 4s or 16s depending on the state of the convergence algorithm. Programming HBIAS threshold byte to zero disables the HBIAS Alarm. 1. LTXP Alarm.....Low Transmitted Power Alarm. This flag is high when the IBMD current drops below the value set by the LTXP threshold. This flag is updated every 16s. Programming LTXP threshold to zero disables this flag. This flag willl be high when TX-D = 1 unless the alarm has been disabled. 2. HTXP Alarm....High Transmitted Power Alarm. This flag is high when the IBMD current rises above the value set by the HTXP threshold. This flag is updated every 16s. Programming HTXP Threshold to zero disables this flag. 3. POA....Analog Power-On Reset Alarm (V CC Power Good). This flag is set when VCC < VPOA. 4. HBIAS Shutdown....This flag goes high when a HBIAS safety fault is generated and HBIAS Enable is high. HBIAS Shutdown goes low with POA or a falling edge of the TX-D pin, providing the safety fault is no longer present. 5. LTXP Shutdown....This flag goes high when a LTXP safety fault is generated and LTXP Enable is high. LTXP Shutdown goes low with POA or a falling edge of TX-D, providing the safety fault is no longer present. 6. HTXP Shutdown....This flag goes high when a HTXP safety fault is generated and HTXP Enable is high. HTXP Shutdown goes low with POA or a falling edge of TX-D, providing the safety fault is no longer present. 7. Shutdown Flag....This flag is high when any of the three latched safety faults are high (HBIAS Shutdown, LTXP Shutdown, or HTXP Shutdown), and it remains high after the individual flag's are reset until fault reset time has elapsed. * PWE High & Low....<R/W><V><FFFFh> Until the correct 32-bit password is written to PWE, the PWE bytes are the only locations that can be written. PWE should be written to a value other than the password once the device's configuration has been updated to prevent the password from being read from PWE. After a power cycle these locations will each be reset to FFFFh. APC Config * APC....<R/W><NV><00h> Sets the desired value of the feedback current into the IBMD pin. The 3 MSB's determine the input GAIN value according to this table: APC<7:5> GAIN 000 1 001 2 010 4 011 8 1xx 16 The remaining 5 LSBs determine the IBMD current setpoint (ISET) assuming a GAIN of 1. The formula for the IBMD current setpoint with the gain is then given by: ISET = 1.525A GAIN (APC<4:0> + 32) If values greater than 10011111b (9Fh) are programmed into the APC register, the DS1861 will clamp ISET to its maximum value, equivalent to if the register was set to 10011111b. * ER (N)....<R/W><NV><1Ch> Sets the gain (N) on the measured excitation current used to generate IMODSET. This sets the extinction ratio of the system. Higher N values increase the excitation ratio. The MSB of this register (RSEL) is a flag that selects a high (RSEL = 1) or low (RSEL = 0) range for N. The 7 LSBs of the register determine the actual N code. The value of N can be calculated by the following equation: ____________________________________________________________________ 19 DS1861 Detailed Register Description Conventions Name of Row * Name of Byte...<Write Access><Volatility><PowerUp/Factory Default Value> 0. Name of bit 0.....Bit 0 Description 1. Name of bit 1.....Bit 1 Description 2 to 7. Bit names.....Bit 2 to 7 Descriptions Write Access: W is write-only access, R is read-only access, and R/W is read/write access. A password may be required for write access on R/W registers. See the memory map for complete access code descriptions. DS1861 Full Laser Control with Fault Management ER < 6 : 0 > +32 RSEL = 0 N= 2 ER < 6 : 0 > +32 RSEL = 1 The default setting of ER = 1Ch corresponds to N = 30, which is the minimum useable value. The maximum useable value is N = 136 (ER = E8h). For more information refer to the Automatic Extinction Ration Control section. * MODLOAD.....<R/W><NV><0000h> This register determines the startup value of I MODSET following a falling edge of TX-D when MODLOAD_Enable = 1 and no fault condition has occurred. This 12-bit register value is left justified in a 16-bit register. The 4 LSBs default to 0s. * Control.....<R/W><NV><70h> This byte is used to enable/disnable the shutdown alarms and configure several other settings. Writing to this byte causes an EEPROM write cycle, even if only the HALT bit (SRAM) is changed. It should not be modified more than the specified number of write cycles. 0. HALT.....Setting this bit high stops the control loop and freezes the outputs at their present state. Once the control loop is stopped the IBIASSET and I MODSET output registers can be read. This bit is SRAM and resets to zero when VCC drops below VPOAF. 1. Excite_Disable.....Setting this bit high prevents the DS1861 from entering the excitation state (it does not add the disturbance current), which disables automatic extinction ratio control. IMODSET will remain at its last value until reset by a fault or set to MODLOAD. 2. Soft_TX-Disable.....This bit is ORed with the TX-D pin to create the internal TX-Disable signal. So asserting either Soft_TX-Disable or the TX-D pin will disable the outputs. Both Soft_TX-Disable and TX-D must be deasserted for the outputs to operate. 3. DPOL.....Diode Polarity. Set to 0 to have the BMD pin source current. Set to 1 to have BMD sink current. 4. HBIAS_Enable.....Set high to allow a safety fault caused by high bias alarm shut the part down. 20 5. LTXP_Enable.....Set high to allow a safety fault caused by low transmitted power alarm shut the part down. 6. HTXP_Enable.....Set high to allow a safety faultl caused by high transmitted power alarm shut the part down. 7. MODLOAD_Enable.....If high, IMODSET loads the value in MODLOAD on the falling edge of TX-D when no fault condition is present. Otherwise, IMODSET will return to operation with its value prior to when TX-D was asserted. Quick-Trip Monitors * HTXP Threshold.....<R/W><NV><00h> Sets the threshold current for the HTXP alarm. The alarm trips when I BMD > I BMD SETPOINT * [1 + (HTXP Threshold<2:0>) 0.125]. Set to 00h to disable the alarm. * LTXP Threshold.....<R/W><NV><00h> Sets the threshold current for the LTXP alarm. The alarm trips when I BMD < I BMD SETPOINT * [1 - (LTXP Threshold<2:0>) 0.125]. Set to 00h to disable the alarm. * HBIAS Threshold.....<R/W><NV><00h> Sets the threshold current for the high bias current alarm. The alarm trips when BIAS current is 7.625A x (HBIAS Threshold). This register value is compared directly against the I BIASSET code value in register D1h to determine if an alarm condition has occurred. Set HBIAS threshold to 00h to disable this alarm. Password * PW High and Low.....<R/W><NV><0000h> The PWE value is compared against the value written to these locations to determine if the user has write access to password-protected memory locations. These locations read as zeros unless the password has been entered into PWE to ensure the password remains secure. DAC Codes * IBIASSET Code.....<R/W><V><00h> This is the most signicant byte of the 18-bit IBIASSET DAC code. IBIASSET = 7.625A x (IBIASSET code). The part must be halted and the password must be entered to read this value. * IMODSET Code.....<R/W><V><0000h> The IMODSET DAC code. The LSB weight of the IMODSET DAC code is 477nA. Thus, IMODSET = 477nA x (IMODSET code). The part must be halted and the password entered to read this value. The four least significant bytes of this register read as 0s. ____________________________________________________________________ Full Laser Control with Fault Management Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses, and start and stop conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between stop and start conditions when both SDA and SCL are inactive and in their logic-high states. Start Condition: A start condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a start condition. See the timing diagram for applicable timing. Stop Condition: A stop condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a stop condition. See the timing diagram for applicable timing. Repeated Start Condition: The master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a normal start condition. See the timing diagram for applicable timing. Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements (Figure 14). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time (Figure 14) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 14) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. SDA tBUF tHD:STA tLOW tR tSP tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START REPEATED START tSU:STO tHD:DAT NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN). Figure 14. I2C Timing Diagram ____________________________________________________________________ 21 DS1861 I2C Definitions The following terminology is commonly used to describe I2C data transfers. DS1861 Full Laser Control with Fault Management Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminated communication so the slave returns control of SDA to the master. Slave Address Byte: Each slave on the I 2 C bus responds to a slave addressing byte sent immediately following a start condition. The slave address byte (Figure 15) contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS1861's slave address is 1010A2A1A0 (binary), where A2, A1, and A0 are the values of the address pins. The address pins allow the device to respond to one of eight possible slave addresses. By writing the correct slave address with R/W = 0, the master indicates it will write data to the slave. If R/W = 1, the master will read data from the slave. If an incorrect slave address is written, the DS1861 assumes the master is communicating with another I2C device and ignore the communications until the next start condition is sent. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. I2C Communication Writing a Single Byte to a Slave: The master must generate a start condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data and generate a stop condition. Remember the master must read the slave's acknowledgement during all byte write operations. Writing Multiple Bytes to a Slave: To write multiple bytes to a slave the master generates a start condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 8 data bytes and generates a stop condition. 22 7-BIT SLAVE ADDRESS 1 MOST SIGNIFICANT BIT 0 1 0 A2 A1 A0 A2, A1 AND A0 PIN VALUES R/W DETERMINES READ OR WRITE Figure 15. Slave Address Byte The DS1861 can write 1 to 8 bytes (referred to as 1 row) with a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one row of the memory map. Attempts to write to additional memory rows without sending a stop condition between rows will result in the address counter wrapping around to the beginning address of the present row. Example: A 3-byte write starts at address BEh and writes three data bytes (11h, 22h, and 33h) to three "consecutive" addresses. The result would be addresses BEh and BFh would contain 11h and 22h, respectively, and the third data byte, 33h, would be written to address B8h. To prevent address wrapping from occurring, the master must send a stop condition at the end of the row, and then wait for the bus free or EEPROM write time to elapse. Then the master can generate a new start condition, write the slave address byte (R/W = 0), and the first memory address of the next memory row before continuing to write data. Acknowledge Polling: Any time EEPROM is written, the DS1861 requires the EEPROM write time (tW) after the stop condition to write the contents of the row to EEPROM. During the EEPROM write time, the DS1861 does not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS1861, which allows the next row to be written as soon as the DS1861 is ready to receive the data. The alternative to acknowledge polling is to wait for maximum period of tW to elapse before attempting to write again to the DS1861. EEPROM Write Cycles: When EEPROM writes occur, the DS1861 will write the whole EEPROM memory row even if only a single byte on the row was modified. Writes that do not modify all 8 bytes on the row are allowed and do not corrupt the remaining bytes of memory on the same row. Because the whole row is written, bytes on the row that were not modified during the transaction are still subject to a write cycle. This ____________________________________________________________________ Full Laser Control with Fault Management counter to a particular value. To do this the master generates a start condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a stop condition. Figure 16 shows a read example using the repeated start condition to specify the starting memory location. Reading Multiple Bytes from a Slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte, it NACKs to indicate the end of the transfer and generates a stop condition. This can be done with or without modifying the address counter's location before the read cycle. NOTES COMMUNICATIONS KEY S START A ACK WHITE BOXES INDICATED THE MASTER IS CONTROLLING SDA P STOP N NOT ACK SHADED BOXES INDICATED THE SLAVE IS CONTROLLING SDA SR REPEATED START X X X X X X X X 1) ALL BYTES ARE SENT MOST SIGNIFICANT BIT FIRST. 2) THE FIRST BYTE SENT AFTER A START CONDITION IS ALWAYS THE SLAVE ADDRESS FOLLOWED BY THE READ/WRITE BIT. 8-BITS ADDRESS OR DATA WRITE A SINGLE BYTE S 1 0 1 0 A2 A1 A0 0 A MEMORY ADDRESS A DATA A A DATA A P WRITE UP TO AN 8-BYTE PAGE WITH A SINGLE TRANSACTION S 1 0 1 0 A2 A1 A0 0 A MEMORY ADDRESS A DATA P READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER S 1 0 1 0 A2 A1 A0 0 MEMORY ADDRESS A A SR 1 0 1 0 A2 A1 A0 0 A DATA N 1 0 1 0 A2 A1 A0 0 A DATA A P READ MULTIPLE BYTES WITH A DUMMY WRITE CYCLE TO SET THE ADDRESS COUNTER S 1 0 1 0 A2 A1 A0 0 DATA A MEMORY ADDRESS A A DATA SR A DATA N P Figure 16. I2C Communications Examples ____________________________________________________________________ 23 DS1861 can result in a whole row being worn out over time by writing a single byte repeatedly. Writing a row one byte at a time will wear out the EEPROM eight times faster than writing the entire row at once. The DS1861's EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. Reading a Single Byte from a Slave: Unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave at the location currently in the address counter; the master generates a start condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address DS1861 Full Laser Control with Fault Management Applications Information Calibrating APC and Extinction Ratio Before calibrating, the APC register should be set to a low value to ensure the laser's maximum power level is not exceeded before the power level is calibrated. Additionally, the ER register should be set to its minimum value (28 decimal) to ensure that a data test pattern does not cause the laser to shut off. Once the APC and ER registers are at minimal values, enable a data pattern and calibrate the average power level first. Calibrating the Average Power Level While sending data through the laser diode, increase the value in the APC register until the light output matches the desired average power level. The average power level is the arithmetic average of the 1 and 0 power levels. Calibrating the Extinction Ratio While sending data through the laser diode, begin increasing the ER register from its minimum value of 28 decimal (1Ch), until the proper extinction ratio is reached or the maximum setting (104 decimal or 68h) of the low range is reached. If the maximum low range value is reached, write the ER register to 156 decimal (9Ch), which switches the extinction ratio value to the minimum value of the high range. Continue increasing the ER setting until the proper extinction ratio is reached. If the maximum value of the high range setting is reached (232 decimal or E8h) without reaching the proper extinction ratio, then either the desired extinction ratio cannot be reached or a problem is preventing the system from operating properly. 24 Addressing Multiple DS1861s on a Common I2C Bus Up to eight DS1861s can be addressed on a single I2C bus by using the device's address inputs (A2, A1, A0) to change its slave address. For information about device addressing, see the I2C Communications section. Power-Supply Decoupling To achieve best results, it is recommended that the power supply is decoupled with a 0.01F or a 0.1F capacitor. Use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the VCC and GND pins to minimize lead inductance. BMD Shunt Capacitor The BMD shunt capacitor works with the internal resistance of the BMD input to provide a lowpass filter that reduces the effects of noise on the APC loop. Its capacitance value must be chosen carefully to ensure that it is both large enough to provide good filtering of high-frequency noise and small enough that it does not cause the control loop to become unstable. A 1nF, 10% tolerant, X7R ceramic capacitor is recommended. SDA and SCL Pullup Resistors SDA is an open-collector bidirectional data pin on the DS1861 that requires a pullup resistor to realize high logic levels. Either an open-collector output with a pullup resistor or a push-pull output driver can be used for the SCL input. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the AC Electrical Characteristics table are within specification. ____________________________________________________________________ Full Laser Control with Fault Management Chip Information TRANSISTOR COUNT: 55,677 SUBSTRATE CONNECTED TO GROUND TOP VIEW SDA 1 14 VCC SCL 2 13 MODSET TX-F 3 12 A2 TX-D 4 DS1861 11 A1 N.C. 5 10 A0 BMD 6 9 BIASSET GND 7 8 N.C. Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation. DS1861 Pin Configuration